1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18 #undef DEBUG
19
20 #include <linux/clk.h>
21 #include <linux/console.h>
22 #include <linux/ctype.h>
23 #include <linux/cpufreq.h>
24 #include <linux/delay.h>
25 #include <linux/dmaengine.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/err.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/ioport.h>
32 #include <linux/ktime.h>
33 #include <linux/major.h>
34 #include <linux/minmax.h>
35 #include <linux/module.h>
36 #include <linux/mm.h>
37 #include <linux/of.h>
38 #include <linux/platform_device.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/reset.h>
41 #include <linux/scatterlist.h>
42 #include <linux/serial.h>
43 #include <linux/serial_sci.h>
44 #include <linux/sh_dma.h>
45 #include <linux/slab.h>
46 #include <linux/string.h>
47 #include <linux/sysrq.h>
48 #include <linux/timer.h>
49 #include <linux/tty.h>
50 #include <linux/tty_flip.h>
51
52 #ifdef CONFIG_SUPERH
53 #include <asm/sh_bios.h>
54 #include <asm/platform_early.h>
55 #endif
56
57 #include "rsci.h"
58 #include "serial_mctrl_gpio.h"
59 #include "sh-sci.h"
60 #include "sh-sci-common.h"
61
62 #define SCIx_IRQ_IS_MUXED(port) \
63 ((port)->irqs[SCIx_ERI_IRQ] == \
64 (port)->irqs[SCIx_RXI_IRQ]) || \
65 ((port)->irqs[SCIx_ERI_IRQ] && \
66 ((port)->irqs[SCIx_RXI_IRQ] < 0))
67
68 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
69 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
70 SCI_SR(19) | SCI_SR(27)
71
72 /* Iterate over all supported sampling rates, from high to low */
73 #define for_each_sr(_sr, _port) \
74 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
75 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
76
77 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
78
79 #define SCI_PUBLIC_PORT_ID(port) (((port) & BIT(7)) ? PORT_GENERIC : (port))
80
81 static struct sci_port sci_ports[SCI_NPORTS];
82 static unsigned long sci_ports_in_use;
83 static struct uart_driver sci_uart_driver;
84 static bool sci_uart_earlycon;
85 static bool sci_uart_earlycon_dev_probing;
86
87 static const struct sci_port_params_bits sci_sci_port_params_bits = {
88 .rxtx_enable = SCSCR_RE | SCSCR_TE,
89 .te_clear = SCSCR_TE | SCSCR_TEIE,
90 .poll_sent_bits = SCI_TDRE | SCI_TEND
91 };
92
93 static const struct sci_port_params_bits sci_scif_port_params_bits = {
94 .rxtx_enable = SCSCR_RE | SCSCR_TE,
95 .te_clear = SCSCR_TE | SCSCR_TEIE,
96 .poll_sent_bits = SCIF_TDFE | SCIF_TEND
97 };
98
99 static const struct sci_common_regs sci_common_regs = {
100 .status = SCxSR,
101 .control = SCSCR,
102 };
103
104 struct sci_suspend_regs {
105 u16 scdl;
106 u16 sccks;
107 u16 scsmr;
108 u16 scscr;
109 u16 scfcr;
110 u16 scsptr;
111 u16 hssrr;
112 u16 scpcr;
113 u16 scpdr;
114 u8 scbrr;
115 u8 semr;
116 };
117
sci_suspend_regs_size(void)118 static size_t sci_suspend_regs_size(void)
119 {
120 return sizeof(struct sci_suspend_regs);
121 }
122
123 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
124 /*
125 * Common SCI definitions, dependent on the port's regshift
126 * value.
127 */
128 [SCIx_SCI_REGTYPE] = {
129 .regs = {
130 [SCSMR] = { 0x00, 8 },
131 [SCBRR] = { 0x01, 8 },
132 [SCSCR] = { 0x02, 8 },
133 [SCxTDR] = { 0x03, 8 },
134 [SCxSR] = { 0x04, 8 },
135 [SCxRDR] = { 0x05, 8 },
136 },
137 .fifosize = 1,
138 .overrun_reg = SCxSR,
139 .overrun_mask = SCI_ORER,
140 .sampling_rate_mask = SCI_SR(32),
141 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
142 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
143 .param_bits = &sci_sci_port_params_bits,
144 .common_regs = &sci_common_regs,
145 },
146
147 /*
148 * Common definitions for legacy IrDA ports.
149 */
150 [SCIx_IRDA_REGTYPE] = {
151 .regs = {
152 [SCSMR] = { 0x00, 8 },
153 [SCBRR] = { 0x02, 8 },
154 [SCSCR] = { 0x04, 8 },
155 [SCxTDR] = { 0x06, 8 },
156 [SCxSR] = { 0x08, 16 },
157 [SCxRDR] = { 0x0a, 8 },
158 [SCFCR] = { 0x0c, 8 },
159 [SCFDR] = { 0x0e, 16 },
160 },
161 .fifosize = 1,
162 .overrun_reg = SCxSR,
163 .overrun_mask = SCI_ORER,
164 .sampling_rate_mask = SCI_SR(32),
165 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
166 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
167 .param_bits = &sci_scif_port_params_bits,
168 .common_regs = &sci_common_regs,
169 },
170
171 /*
172 * Common SCIFA definitions.
173 */
174 [SCIx_SCIFA_REGTYPE] = {
175 .regs = {
176 [SCSMR] = { 0x00, 16 },
177 [SCBRR] = { 0x04, 8 },
178 [SCSCR] = { 0x08, 16 },
179 [SCxTDR] = { 0x20, 8 },
180 [SCxSR] = { 0x14, 16 },
181 [SCxRDR] = { 0x24, 8 },
182 [SCFCR] = { 0x18, 16 },
183 [SCFDR] = { 0x1c, 16 },
184 [SCPCR] = { 0x30, 16 },
185 [SCPDR] = { 0x34, 16 },
186 },
187 .fifosize = 64,
188 .overrun_reg = SCxSR,
189 .overrun_mask = SCIFA_ORER,
190 .sampling_rate_mask = SCI_SR_SCIFAB,
191 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
192 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
193 .param_bits = &sci_scif_port_params_bits,
194 .common_regs = &sci_common_regs,
195 },
196
197 /*
198 * Common SCIFB definitions.
199 */
200 [SCIx_SCIFB_REGTYPE] = {
201 .regs = {
202 [SCSMR] = { 0x00, 16 },
203 [SCBRR] = { 0x04, 8 },
204 [SCSCR] = { 0x08, 16 },
205 [SCxTDR] = { 0x40, 8 },
206 [SCxSR] = { 0x14, 16 },
207 [SCxRDR] = { 0x60, 8 },
208 [SCFCR] = { 0x18, 16 },
209 [SCTFDR] = { 0x38, 16 },
210 [SCRFDR] = { 0x3c, 16 },
211 [SCPCR] = { 0x30, 16 },
212 [SCPDR] = { 0x34, 16 },
213 },
214 .fifosize = 256,
215 .overrun_reg = SCxSR,
216 .overrun_mask = SCIFA_ORER,
217 .sampling_rate_mask = SCI_SR_SCIFAB,
218 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
219 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
220 .param_bits = &sci_scif_port_params_bits,
221 .common_regs = &sci_common_regs,
222 },
223
224 /*
225 * Common SH-2(A) SCIF definitions for ports with FIFO data
226 * count registers.
227 */
228 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
229 .regs = {
230 [SCSMR] = { 0x00, 16 },
231 [SCBRR] = { 0x04, 8 },
232 [SCSCR] = { 0x08, 16 },
233 [SCxTDR] = { 0x0c, 8 },
234 [SCxSR] = { 0x10, 16 },
235 [SCxRDR] = { 0x14, 8 },
236 [SCFCR] = { 0x18, 16 },
237 [SCFDR] = { 0x1c, 16 },
238 [SCSPTR] = { 0x20, 16 },
239 [SCLSR] = { 0x24, 16 },
240 },
241 .fifosize = 16,
242 .overrun_reg = SCLSR,
243 .overrun_mask = SCLSR_ORER,
244 .sampling_rate_mask = SCI_SR(32),
245 .error_mask = SCIF_DEFAULT_ERROR_MASK,
246 .error_clear = SCIF_ERROR_CLEAR,
247 .param_bits = &sci_scif_port_params_bits,
248 .common_regs = &sci_common_regs,
249 },
250
251 /*
252 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T1.
253 * It looks like a normal SCIF with FIFO data, but with a
254 * compressed address space. Also, the break out of interrupts
255 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
256 */
257 [SCIx_RZ_SCIFA_REGTYPE] = {
258 .regs = {
259 [SCSMR] = { 0x00, 16 },
260 [SCBRR] = { 0x02, 8 },
261 [SCSCR] = { 0x04, 16 },
262 [SCxTDR] = { 0x06, 8 },
263 [SCxSR] = { 0x08, 16 },
264 [SCxRDR] = { 0x0A, 8 },
265 [SCFCR] = { 0x0C, 16 },
266 [SCFDR] = { 0x0E, 16 },
267 [SCSPTR] = { 0x10, 16 },
268 [SCLSR] = { 0x12, 16 },
269 [SEMR] = { 0x14, 8 },
270 },
271 .fifosize = 16,
272 .overrun_reg = SCLSR,
273 .overrun_mask = SCLSR_ORER,
274 .sampling_rate_mask = SCI_SR(32),
275 .error_mask = SCIF_DEFAULT_ERROR_MASK,
276 .error_clear = SCIF_ERROR_CLEAR,
277 .param_bits = &sci_scif_port_params_bits,
278 .common_regs = &sci_common_regs,
279 },
280
281 /*
282 * The "SCIF" that is in RZ/V2H(P) SoC is similar to one found on RZ/G2L SoC
283 * with below differences,
284 * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI,
285 * TEI-DRI, RXI-EDGE and TXI-EDGE.
286 * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode.
287 * - SCFCR register does not have SCFCR_MCE bit.
288 * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO.
289 */
290 [SCIx_RZV2H_SCIF_REGTYPE] = {
291 .regs = {
292 [SCSMR] = { 0x00, 16 },
293 [SCBRR] = { 0x02, 8 },
294 [SCSCR] = { 0x04, 16 },
295 [SCxTDR] = { 0x06, 8 },
296 [SCxSR] = { 0x08, 16 },
297 [SCxRDR] = { 0x0a, 8 },
298 [SCFCR] = { 0x0c, 16 },
299 [SCFDR] = { 0x0e, 16 },
300 [SCSPTR] = { 0x10, 16 },
301 [SCLSR] = { 0x12, 16 },
302 [SEMR] = { 0x14, 8 },
303 },
304 .fifosize = 16,
305 .overrun_reg = SCLSR,
306 .overrun_mask = SCLSR_ORER,
307 .sampling_rate_mask = SCI_SR(32),
308 .error_mask = SCIF_DEFAULT_ERROR_MASK,
309 .error_clear = SCIF_ERROR_CLEAR,
310 .param_bits = &sci_scif_port_params_bits,
311 .common_regs = &sci_common_regs,
312 },
313
314 /*
315 * Common SH-3 SCIF definitions.
316 */
317 [SCIx_SH3_SCIF_REGTYPE] = {
318 .regs = {
319 [SCSMR] = { 0x00, 8 },
320 [SCBRR] = { 0x02, 8 },
321 [SCSCR] = { 0x04, 8 },
322 [SCxTDR] = { 0x06, 8 },
323 [SCxSR] = { 0x08, 16 },
324 [SCxRDR] = { 0x0a, 8 },
325 [SCFCR] = { 0x0c, 8 },
326 [SCFDR] = { 0x0e, 16 },
327 },
328 .fifosize = 16,
329 .overrun_reg = SCLSR,
330 .overrun_mask = SCLSR_ORER,
331 .sampling_rate_mask = SCI_SR(32),
332 .error_mask = SCIF_DEFAULT_ERROR_MASK,
333 .error_clear = SCIF_ERROR_CLEAR,
334 .param_bits = &sci_scif_port_params_bits,
335 .common_regs = &sci_common_regs,
336 },
337
338 /*
339 * Common SH-4(A) SCIF(B) definitions.
340 */
341 [SCIx_SH4_SCIF_REGTYPE] = {
342 .regs = {
343 [SCSMR] = { 0x00, 16 },
344 [SCBRR] = { 0x04, 8 },
345 [SCSCR] = { 0x08, 16 },
346 [SCxTDR] = { 0x0c, 8 },
347 [SCxSR] = { 0x10, 16 },
348 [SCxRDR] = { 0x14, 8 },
349 [SCFCR] = { 0x18, 16 },
350 [SCFDR] = { 0x1c, 16 },
351 [SCSPTR] = { 0x20, 16 },
352 [SCLSR] = { 0x24, 16 },
353 },
354 .fifosize = 16,
355 .overrun_reg = SCLSR,
356 .overrun_mask = SCLSR_ORER,
357 .sampling_rate_mask = SCI_SR(32),
358 .error_mask = SCIF_DEFAULT_ERROR_MASK,
359 .error_clear = SCIF_ERROR_CLEAR,
360 .param_bits = &sci_scif_port_params_bits,
361 .common_regs = &sci_common_regs,
362 },
363
364 /*
365 * Common SCIF definitions for ports with a Baud Rate Generator for
366 * External Clock (BRG).
367 */
368 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
369 .regs = {
370 [SCSMR] = { 0x00, 16 },
371 [SCBRR] = { 0x04, 8 },
372 [SCSCR] = { 0x08, 16 },
373 [SCxTDR] = { 0x0c, 8 },
374 [SCxSR] = { 0x10, 16 },
375 [SCxRDR] = { 0x14, 8 },
376 [SCFCR] = { 0x18, 16 },
377 [SCFDR] = { 0x1c, 16 },
378 [SCSPTR] = { 0x20, 16 },
379 [SCLSR] = { 0x24, 16 },
380 [SCDL] = { 0x30, 16 },
381 [SCCKS] = { 0x34, 16 },
382 },
383 .fifosize = 16,
384 .overrun_reg = SCLSR,
385 .overrun_mask = SCLSR_ORER,
386 .sampling_rate_mask = SCI_SR(32),
387 .error_mask = SCIF_DEFAULT_ERROR_MASK,
388 .error_clear = SCIF_ERROR_CLEAR,
389 .param_bits = &sci_scif_port_params_bits,
390 .common_regs = &sci_common_regs,
391 },
392
393 /*
394 * Common HSCIF definitions.
395 */
396 [SCIx_HSCIF_REGTYPE] = {
397 .regs = {
398 [SCSMR] = { 0x00, 16 },
399 [SCBRR] = { 0x04, 8 },
400 [SCSCR] = { 0x08, 16 },
401 [SCxTDR] = { 0x0c, 8 },
402 [SCxSR] = { 0x10, 16 },
403 [SCxRDR] = { 0x14, 8 },
404 [SCFCR] = { 0x18, 16 },
405 [SCFDR] = { 0x1c, 16 },
406 [SCSPTR] = { 0x20, 16 },
407 [SCLSR] = { 0x24, 16 },
408 [HSSRR] = { 0x40, 16 },
409 [SCDL] = { 0x30, 16 },
410 [SCCKS] = { 0x34, 16 },
411 [HSRTRGR] = { 0x54, 16 },
412 [HSTTRGR] = { 0x58, 16 },
413 },
414 .fifosize = 128,
415 .overrun_reg = SCLSR,
416 .overrun_mask = SCLSR_ORER,
417 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
418 .error_mask = SCIF_DEFAULT_ERROR_MASK,
419 .error_clear = SCIF_ERROR_CLEAR,
420 .param_bits = &sci_scif_port_params_bits,
421 .common_regs = &sci_common_regs,
422 },
423
424 /*
425 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
426 * register.
427 */
428 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
429 .regs = {
430 [SCSMR] = { 0x00, 16 },
431 [SCBRR] = { 0x04, 8 },
432 [SCSCR] = { 0x08, 16 },
433 [SCxTDR] = { 0x0c, 8 },
434 [SCxSR] = { 0x10, 16 },
435 [SCxRDR] = { 0x14, 8 },
436 [SCFCR] = { 0x18, 16 },
437 [SCFDR] = { 0x1c, 16 },
438 [SCLSR] = { 0x24, 16 },
439 },
440 .fifosize = 16,
441 .overrun_reg = SCLSR,
442 .overrun_mask = SCLSR_ORER,
443 .sampling_rate_mask = SCI_SR(32),
444 .error_mask = SCIF_DEFAULT_ERROR_MASK,
445 .error_clear = SCIF_ERROR_CLEAR,
446 .param_bits = &sci_scif_port_params_bits,
447 .common_regs = &sci_common_regs,
448 },
449
450 /*
451 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
452 * count registers.
453 */
454 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
455 .regs = {
456 [SCSMR] = { 0x00, 16 },
457 [SCBRR] = { 0x04, 8 },
458 [SCSCR] = { 0x08, 16 },
459 [SCxTDR] = { 0x0c, 8 },
460 [SCxSR] = { 0x10, 16 },
461 [SCxRDR] = { 0x14, 8 },
462 [SCFCR] = { 0x18, 16 },
463 [SCFDR] = { 0x1c, 16 },
464 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
465 [SCRFDR] = { 0x20, 16 },
466 [SCSPTR] = { 0x24, 16 },
467 [SCLSR] = { 0x28, 16 },
468 },
469 .fifosize = 16,
470 .overrun_reg = SCLSR,
471 .overrun_mask = SCLSR_ORER,
472 .sampling_rate_mask = SCI_SR(32),
473 .error_mask = SCIF_DEFAULT_ERROR_MASK,
474 .error_clear = SCIF_ERROR_CLEAR,
475 .param_bits = &sci_scif_port_params_bits,
476 .common_regs = &sci_common_regs,
477 },
478
479 /*
480 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
481 * registers.
482 */
483 [SCIx_SH7705_SCIF_REGTYPE] = {
484 .regs = {
485 [SCSMR] = { 0x00, 16 },
486 [SCBRR] = { 0x04, 8 },
487 [SCSCR] = { 0x08, 16 },
488 [SCxTDR] = { 0x20, 8 },
489 [SCxSR] = { 0x14, 16 },
490 [SCxRDR] = { 0x24, 8 },
491 [SCFCR] = { 0x18, 16 },
492 [SCFDR] = { 0x1c, 16 },
493 },
494 .fifosize = 64,
495 .overrun_reg = SCxSR,
496 .overrun_mask = SCIFA_ORER,
497 .sampling_rate_mask = SCI_SR(16),
498 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
499 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
500 .param_bits = &sci_scif_port_params_bits,
501 .common_regs = &sci_common_regs,
502 },
503 };
504
505 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
506
507 /*
508 * The "offset" here is rather misleading, in that it refers to an enum
509 * value relative to the port mapping rather than the fixed offset
510 * itself, which needs to be manually retrieved from the platform's
511 * register map for the given port.
512 */
sci_serial_in(struct uart_port * p,int offset)513 static unsigned int sci_serial_in(struct uart_port *p, int offset)
514 {
515 const struct plat_sci_reg *reg = sci_getreg(p, offset);
516
517 if (reg->size == 8)
518 return ioread8(p->membase + (reg->offset << p->regshift));
519 else if (reg->size == 16)
520 return ioread16(p->membase + (reg->offset << p->regshift));
521 else
522 WARN(1, "Invalid register access\n");
523
524 return 0;
525 }
526
sci_serial_out(struct uart_port * p,int offset,int value)527 static void sci_serial_out(struct uart_port *p, int offset, int value)
528 {
529 const struct plat_sci_reg *reg = sci_getreg(p, offset);
530
531 if (reg->size == 8)
532 iowrite8(value, p->membase + (reg->offset << p->regshift));
533 else if (reg->size == 16)
534 iowrite16(value, p->membase + (reg->offset << p->regshift));
535 else
536 WARN(1, "Invalid register access\n");
537 }
538
sci_port_enable(struct sci_port * sci_port)539 void sci_port_enable(struct sci_port *sci_port)
540 {
541 unsigned int i;
542
543 if (!sci_port->port.dev)
544 return;
545
546 pm_runtime_get_sync(sci_port->port.dev);
547
548 for (i = 0; i < SCI_NUM_CLKS; i++) {
549 clk_prepare_enable(sci_port->clks[i]);
550 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
551 }
552 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
553 }
554 EXPORT_SYMBOL_NS_GPL(sci_port_enable, "SH_SCI");
555
sci_port_disable(struct sci_port * sci_port)556 void sci_port_disable(struct sci_port *sci_port)
557 {
558 unsigned int i;
559
560 if (!sci_port->port.dev)
561 return;
562
563 for (i = SCI_NUM_CLKS; i-- > 0; )
564 clk_disable_unprepare(sci_port->clks[i]);
565
566 pm_runtime_put_sync(sci_port->port.dev);
567 }
568 EXPORT_SYMBOL_NS_GPL(sci_port_disable, "SH_SCI");
569
port_rx_irq_mask(struct uart_port * port)570 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
571 {
572 /*
573 * Not all ports (such as SCIFA) will support REIE. Rather than
574 * special-casing the port type, we check the port initialization
575 * IRQ enable mask to see whether the IRQ is desired at all. If
576 * it's unset, it's logically inferred that there's no point in
577 * testing for it.
578 */
579 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
580 }
581
sci_start_tx(struct uart_port * port)582 static void sci_start_tx(struct uart_port *port)
583 {
584 struct sci_port *s = to_sci_port(port);
585 unsigned short ctrl;
586
587 #ifdef CONFIG_SERIAL_SH_SCI_DMA
588 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
589 u16 new, scr = sci_serial_in(port, SCSCR);
590 if (s->chan_tx)
591 new = scr | SCSCR_TDRQE;
592 else
593 new = scr & ~SCSCR_TDRQE;
594 if (new != scr)
595 sci_serial_out(port, SCSCR, new);
596 }
597
598 if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) &&
599 dma_submit_error(s->cookie_tx)) {
600 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE)
601 /* Switch irq from SCIF to DMA */
602 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]);
603
604 s->cookie_tx = 0;
605 schedule_work(&s->work_tx);
606 }
607 #endif
608
609 if (!s->chan_tx || s->regtype == SCIx_RZ_SCIFA_REGTYPE ||
610 s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
611 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
612 ctrl = sci_serial_in(port, SCSCR);
613
614 /*
615 * For SCI, TE (transmit enable) must be set after setting TIE
616 * (transmit interrupt enable) or in the same instruction to start
617 * the transmit process.
618 */
619 if (s->type == PORT_SCI)
620 ctrl |= SCSCR_TE;
621
622 sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE);
623 }
624 }
625
sci_stop_tx(struct uart_port * port)626 static void sci_stop_tx(struct uart_port *port)
627 {
628 struct sci_port *s = to_sci_port(port);
629 unsigned short ctrl;
630
631 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
632 ctrl = sci_serial_in(port, SCSCR);
633
634 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)
635 ctrl &= ~SCSCR_TDRQE;
636
637 ctrl &= ~SCSCR_TIE;
638
639 sci_serial_out(port, SCSCR, ctrl);
640
641 #ifdef CONFIG_SERIAL_SH_SCI_DMA
642 if (s->chan_tx &&
643 !dma_submit_error(s->cookie_tx)) {
644 dmaengine_terminate_async(s->chan_tx);
645 s->cookie_tx = -EINVAL;
646 }
647 #endif
648 }
649
sci_start_rx(struct uart_port * port)650 static void sci_start_rx(struct uart_port *port)
651 {
652 struct sci_port *s = to_sci_port(port);
653 unsigned short ctrl;
654
655 ctrl = sci_serial_in(port, SCSCR) | port_rx_irq_mask(port);
656
657 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)
658 ctrl &= ~SCSCR_RDRQE;
659
660 sci_serial_out(port, SCSCR, ctrl);
661 }
662
sci_stop_rx(struct uart_port * port)663 static void sci_stop_rx(struct uart_port *port)
664 {
665 struct sci_port *s = to_sci_port(port);
666 unsigned short ctrl;
667
668 ctrl = sci_serial_in(port, SCSCR);
669
670 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)
671 ctrl &= ~SCSCR_RDRQE;
672
673 ctrl &= ~port_rx_irq_mask(port);
674
675 sci_serial_out(port, SCSCR, ctrl);
676 }
677
sci_clear_SCxSR(struct uart_port * port,unsigned int mask)678 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
679 {
680 struct sci_port *s = to_sci_port(port);
681
682 if (s->type == PORT_SCI) {
683 /* Just store the mask */
684 sci_serial_out(port, SCxSR, mask);
685 } else if (s->params->overrun_mask == SCIFA_ORER) {
686 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
687 /* Only clear the status bits we want to clear */
688 sci_serial_out(port, SCxSR, sci_serial_in(port, SCxSR) & mask);
689 } else {
690 /* Store the mask, clear parity/framing errors */
691 sci_serial_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
692 }
693 }
694
695 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
696 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
697
698 #ifdef CONFIG_CONSOLE_POLL
sci_poll_get_char(struct uart_port * port)699 static int sci_poll_get_char(struct uart_port *port)
700 {
701 unsigned short status;
702 struct sci_port *s = to_sci_port(port);
703 int c;
704
705 do {
706 status = sci_serial_in(port, SCxSR);
707 if (status & SCxSR_ERRORS(port)) {
708 s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
709 continue;
710 }
711 break;
712 } while (1);
713
714 if (!(status & SCxSR_RDxF(port)))
715 return NO_POLL_CHAR;
716
717 c = sci_serial_in(port, SCxRDR);
718
719 /* Dummy read */
720 sci_serial_in(port, SCxSR);
721 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
722
723 return c;
724 }
725 #endif
726
sci_poll_put_char(struct uart_port * port,unsigned char c)727 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
728 {
729 struct sci_port *s = to_sci_port(port);
730 const struct sci_common_regs *regs = s->params->common_regs;
731 unsigned int status;
732
733 do {
734 status = s->ops->read_reg(port, regs->status);
735 } while (!(status & SCxSR_TDxE(port)));
736
737 sci_serial_out(port, SCxTDR, c);
738 s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
739 }
740 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
741 CONFIG_SERIAL_SH_SCI_EARLYCON */
742
sci_init_pins(struct uart_port * port,unsigned int cflag)743 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
744 {
745 struct sci_port *s = to_sci_port(port);
746
747 /*
748 * Use port-specific handler if provided.
749 */
750 if (s->cfg->ops && s->cfg->ops->init_pins) {
751 s->cfg->ops->init_pins(port, cflag);
752 return;
753 }
754
755 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
756 u16 data = sci_serial_in(port, SCPDR);
757 u16 ctrl = sci_serial_in(port, SCPCR);
758
759 /* Enable RXD and TXD pin functions */
760 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
761 if (s->has_rtscts) {
762 /* RTS# is output, active low, unless autorts */
763 if (!(port->mctrl & TIOCM_RTS)) {
764 ctrl |= SCPCR_RTSC;
765 data |= SCPDR_RTSD;
766 } else if (!s->autorts) {
767 ctrl |= SCPCR_RTSC;
768 data &= ~SCPDR_RTSD;
769 } else {
770 /* Enable RTS# pin function */
771 ctrl &= ~SCPCR_RTSC;
772 }
773 /* Enable CTS# pin function */
774 ctrl &= ~SCPCR_CTSC;
775 }
776 sci_serial_out(port, SCPDR, data);
777 sci_serial_out(port, SCPCR, ctrl);
778 } else if (sci_getreg(port, SCSPTR)->size && s->regtype != SCIx_RZV2H_SCIF_REGTYPE) {
779 u16 status = sci_serial_in(port, SCSPTR);
780
781 /* RTS# is always output; and active low, unless autorts */
782 status |= SCSPTR_RTSIO;
783 if (!(port->mctrl & TIOCM_RTS))
784 status |= SCSPTR_RTSDT;
785 else if (!s->autorts)
786 status &= ~SCSPTR_RTSDT;
787 /* CTS# and SCK are inputs */
788 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
789 sci_serial_out(port, SCSPTR, status);
790 }
791 }
792
sci_txfill(struct uart_port * port)793 static int sci_txfill(struct uart_port *port)
794 {
795 struct sci_port *s = to_sci_port(port);
796 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
797 const struct plat_sci_reg *reg;
798
799 reg = sci_getreg(port, SCTFDR);
800 if (reg->size)
801 return sci_serial_in(port, SCTFDR) & fifo_mask;
802
803 reg = sci_getreg(port, SCFDR);
804 if (reg->size)
805 return sci_serial_in(port, SCFDR) >> 8;
806
807 return !(sci_serial_in(port, SCxSR) & SCI_TDRE);
808 }
809
sci_txroom(struct uart_port * port)810 static int sci_txroom(struct uart_port *port)
811 {
812 return port->fifosize - sci_txfill(port);
813 }
814
sci_rxfill(struct uart_port * port)815 static int sci_rxfill(struct uart_port *port)
816 {
817 struct sci_port *s = to_sci_port(port);
818 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
819 const struct plat_sci_reg *reg;
820
821 reg = sci_getreg(port, SCRFDR);
822 if (reg->size)
823 return sci_serial_in(port, SCRFDR) & fifo_mask;
824
825 reg = sci_getreg(port, SCFDR);
826 if (reg->size)
827 return sci_serial_in(port, SCFDR) & fifo_mask;
828
829 return (sci_serial_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
830 }
831
832 /* ********************************************************************** *
833 * the interrupt related routines *
834 * ********************************************************************** */
835
sci_transmit_chars(struct uart_port * port)836 static void sci_transmit_chars(struct uart_port *port)
837 {
838 struct tty_port *tport = &port->state->port;
839 unsigned int stopped = uart_tx_stopped(port);
840 struct sci_port *s = to_sci_port(port);
841 unsigned short status;
842 unsigned short ctrl;
843 int count;
844
845 status = sci_serial_in(port, SCxSR);
846 if (!(status & SCxSR_TDxE(port))) {
847 ctrl = sci_serial_in(port, SCSCR);
848 if (kfifo_is_empty(&tport->xmit_fifo))
849 ctrl &= ~SCSCR_TIE;
850 else
851 ctrl |= SCSCR_TIE;
852 sci_serial_out(port, SCSCR, ctrl);
853 return;
854 }
855
856 count = sci_txroom(port);
857
858 do {
859 unsigned char c;
860
861 if (port->x_char) {
862 c = port->x_char;
863 port->x_char = 0;
864 } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) {
865 if (s->type == PORT_SCI &&
866 kfifo_is_empty(&tport->xmit_fifo)) {
867 ctrl = sci_serial_in(port, SCSCR);
868 ctrl &= ~SCSCR_TE;
869 sci_serial_out(port, SCSCR, ctrl);
870 return;
871 }
872 break;
873 }
874
875 sci_serial_out(port, SCxTDR, c);
876 s->tx_occurred = true;
877
878 port->icount.tx++;
879 } while (--count > 0);
880
881 s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
882
883 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
884 uart_write_wakeup(port);
885 if (kfifo_is_empty(&tport->xmit_fifo)) {
886 if (s->type == PORT_SCI) {
887 ctrl = sci_serial_in(port, SCSCR);
888 ctrl &= ~SCSCR_TIE;
889 ctrl |= SCSCR_TEIE;
890 sci_serial_out(port, SCSCR, ctrl);
891 }
892
893 sci_stop_tx(port);
894 }
895 }
896
sci_receive_chars(struct uart_port * port)897 static void sci_receive_chars(struct uart_port *port)
898 {
899 struct tty_port *tport = &port->state->port;
900 struct sci_port *s = to_sci_port(port);
901 int i, count, copied = 0;
902 unsigned short status;
903 unsigned char flag;
904
905 status = sci_serial_in(port, SCxSR);
906 if (!(status & SCxSR_RDxF(port)))
907 return;
908
909 while (1) {
910 /* Don't copy more bytes than there is room for in the buffer */
911 count = tty_buffer_request_room(tport, sci_rxfill(port));
912
913 /* If for any reason we can't copy more data, we're done! */
914 if (count == 0)
915 break;
916
917 if (s->type == PORT_SCI) {
918 char c = sci_serial_in(port, SCxRDR);
919 if (uart_handle_sysrq_char(port, c))
920 count = 0;
921 else
922 tty_insert_flip_char(tport, c, TTY_NORMAL);
923 } else {
924 for (i = 0; i < count; i++) {
925 char c;
926
927 if (s->type == PORT_SCIF ||
928 s->type == PORT_HSCIF) {
929 status = sci_serial_in(port, SCxSR);
930 c = sci_serial_in(port, SCxRDR);
931 } else {
932 c = sci_serial_in(port, SCxRDR);
933 status = sci_serial_in(port, SCxSR);
934 }
935 if (uart_handle_sysrq_char(port, c)) {
936 count--; i--;
937 continue;
938 }
939
940 /* Store data and status */
941 if (status & SCxSR_FER(port)) {
942 flag = TTY_FRAME;
943 port->icount.frame++;
944 } else if (status & SCxSR_PER(port)) {
945 flag = TTY_PARITY;
946 port->icount.parity++;
947 } else
948 flag = TTY_NORMAL;
949
950 tty_insert_flip_char(tport, c, flag);
951 }
952 }
953
954 sci_serial_in(port, SCxSR); /* dummy read */
955 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
956
957 copied += count;
958 port->icount.rx += count;
959 }
960
961 if (copied) {
962 /* Tell the rest of the system the news. New characters! */
963 tty_flip_buffer_push(tport);
964 } else {
965 /* TTY buffers full; read from RX reg to prevent lockup */
966 sci_serial_in(port, SCxRDR);
967 sci_serial_in(port, SCxSR); /* dummy read */
968 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
969 }
970 }
971
sci_handle_errors(struct uart_port * port)972 static int sci_handle_errors(struct uart_port *port)
973 {
974 int copied = 0;
975 struct sci_port *s = to_sci_port(port);
976 const struct sci_common_regs *regs = s->params->common_regs;
977 unsigned int status = s->ops->read_reg(port, regs->status);
978 struct tty_port *tport = &port->state->port;
979
980 /* Handle overruns */
981 if (status & s->params->overrun_mask) {
982 port->icount.overrun++;
983
984 /* overrun error */
985 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
986 copied++;
987 }
988
989 if (status & SCxSR_FER(port)) {
990 /* frame error */
991 port->icount.frame++;
992
993 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
994 copied++;
995 }
996
997 if (status & SCxSR_PER(port)) {
998 /* parity error */
999 port->icount.parity++;
1000
1001 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
1002 copied++;
1003 }
1004
1005 if (copied)
1006 tty_flip_buffer_push(tport);
1007
1008 return copied;
1009 }
1010
sci_handle_fifo_overrun(struct uart_port * port)1011 static int sci_handle_fifo_overrun(struct uart_port *port)
1012 {
1013 struct tty_port *tport = &port->state->port;
1014 struct sci_port *s = to_sci_port(port);
1015 const struct plat_sci_reg *reg;
1016 int copied = 0;
1017 u32 status;
1018
1019 if (s->type != SCI_PORT_RSCI) {
1020 reg = sci_getreg(port, s->params->overrun_reg);
1021 if (!reg->size)
1022 return 0;
1023 }
1024
1025 status = s->ops->read_reg(port, s->params->overrun_reg);
1026 if (status & s->params->overrun_mask) {
1027 status &= ~s->params->overrun_mask;
1028 s->ops->write_reg(port, s->params->overrun_reg, status);
1029
1030 port->icount.overrun++;
1031
1032 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1033 tty_flip_buffer_push(tport);
1034 copied++;
1035 }
1036
1037 return copied;
1038 }
1039
sci_handle_breaks(struct uart_port * port)1040 static int sci_handle_breaks(struct uart_port *port)
1041 {
1042 int copied = 0;
1043 unsigned short status = sci_serial_in(port, SCxSR);
1044 struct tty_port *tport = &port->state->port;
1045
1046 if (uart_handle_break(port))
1047 return 0;
1048
1049 if (status & SCxSR_BRK(port)) {
1050 port->icount.brk++;
1051
1052 /* Notify of BREAK */
1053 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1054 copied++;
1055 }
1056
1057 if (copied)
1058 tty_flip_buffer_push(tport);
1059
1060 copied += sci_handle_fifo_overrun(port);
1061
1062 return copied;
1063 }
1064
scif_set_rtrg(struct uart_port * port,int rx_trig)1065 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1066 {
1067 struct sci_port *s = to_sci_port(port);
1068 unsigned int bits;
1069
1070 if (rx_trig >= port->fifosize)
1071 rx_trig = port->fifosize - 1;
1072 if (rx_trig < 1)
1073 rx_trig = 1;
1074
1075 /* HSCIF can be set to an arbitrary level. */
1076 if (sci_getreg(port, HSRTRGR)->size) {
1077 sci_serial_out(port, HSRTRGR, rx_trig);
1078 return rx_trig;
1079 }
1080
1081 switch (s->type) {
1082 case PORT_SCIF:
1083 if (rx_trig < 4) {
1084 bits = 0;
1085 rx_trig = 1;
1086 } else if (rx_trig < 8) {
1087 bits = SCFCR_RTRG0;
1088 rx_trig = 4;
1089 } else if (rx_trig < 14) {
1090 bits = SCFCR_RTRG1;
1091 rx_trig = 8;
1092 } else {
1093 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1094 rx_trig = 14;
1095 }
1096 break;
1097 case PORT_SCIFA:
1098 case PORT_SCIFB:
1099 if (rx_trig < 16) {
1100 bits = 0;
1101 rx_trig = 1;
1102 } else if (rx_trig < 32) {
1103 bits = SCFCR_RTRG0;
1104 rx_trig = 16;
1105 } else if (rx_trig < 48) {
1106 bits = SCFCR_RTRG1;
1107 rx_trig = 32;
1108 } else {
1109 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1110 rx_trig = 48;
1111 }
1112 break;
1113 default:
1114 WARN(1, "unknown FIFO configuration");
1115 return 1;
1116 }
1117
1118 sci_serial_out(port, SCFCR,
1119 (sci_serial_in(port, SCFCR) &
1120 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1121
1122 return rx_trig;
1123 }
1124
scif_rtrg_enabled(struct uart_port * port)1125 static int scif_rtrg_enabled(struct uart_port *port)
1126 {
1127 if (sci_getreg(port, HSRTRGR)->size)
1128 return sci_serial_in(port, HSRTRGR) != 0;
1129 else
1130 return (sci_serial_in(port, SCFCR) &
1131 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1132 }
1133
rx_fifo_timer_fn(struct timer_list * t)1134 static void rx_fifo_timer_fn(struct timer_list *t)
1135 {
1136 struct sci_port *s = timer_container_of(s, t, rx_fifo_timer);
1137 struct uart_port *port = &s->port;
1138
1139 dev_dbg(port->dev, "Rx timed out\n");
1140 s->ops->set_rtrg(port, 1);
1141 }
1142
rx_fifo_trigger_show(struct device * dev,struct device_attribute * attr,char * buf)1143 static ssize_t rx_fifo_trigger_show(struct device *dev,
1144 struct device_attribute *attr, char *buf)
1145 {
1146 struct uart_port *port = dev_get_drvdata(dev);
1147 struct sci_port *sci = to_sci_port(port);
1148
1149 return sprintf(buf, "%d\n", sci->rx_trigger);
1150 }
1151
rx_fifo_trigger_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1152 static ssize_t rx_fifo_trigger_store(struct device *dev,
1153 struct device_attribute *attr,
1154 const char *buf, size_t count)
1155 {
1156 struct uart_port *port = dev_get_drvdata(dev);
1157 struct sci_port *sci = to_sci_port(port);
1158 int ret;
1159 long r;
1160
1161 ret = kstrtol(buf, 0, &r);
1162 if (ret)
1163 return ret;
1164
1165 sci->rx_trigger = sci->ops->set_rtrg(port, r);
1166 if (sci->type == PORT_SCIFA || sci->type == PORT_SCIFB)
1167 sci->ops->set_rtrg(port, 1);
1168
1169 return count;
1170 }
1171
1172 static DEVICE_ATTR_RW(rx_fifo_trigger);
1173
rx_fifo_timeout_show(struct device * dev,struct device_attribute * attr,char * buf)1174 static ssize_t rx_fifo_timeout_show(struct device *dev,
1175 struct device_attribute *attr,
1176 char *buf)
1177 {
1178 struct uart_port *port = dev_get_drvdata(dev);
1179 struct sci_port *sci = to_sci_port(port);
1180 int v;
1181
1182 if (sci->type == PORT_HSCIF)
1183 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1184 else
1185 v = sci->rx_fifo_timeout;
1186
1187 return sprintf(buf, "%d\n", v);
1188 }
1189
rx_fifo_timeout_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1190 static ssize_t rx_fifo_timeout_store(struct device *dev,
1191 struct device_attribute *attr,
1192 const char *buf,
1193 size_t count)
1194 {
1195 struct uart_port *port = dev_get_drvdata(dev);
1196 struct sci_port *sci = to_sci_port(port);
1197 int ret;
1198 long r;
1199
1200 ret = kstrtol(buf, 0, &r);
1201 if (ret)
1202 return ret;
1203
1204 if (sci->type == PORT_HSCIF) {
1205 if (r < 0 || r > 3)
1206 return -EINVAL;
1207 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1208 } else {
1209 sci->rx_fifo_timeout = r;
1210 sci->ops->set_rtrg(port, 1);
1211 if (r > 0)
1212 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1213 }
1214
1215 return count;
1216 }
1217
1218 static DEVICE_ATTR_RW(rx_fifo_timeout);
1219
1220
1221 #ifdef CONFIG_SERIAL_SH_SCI_DMA
sci_dma_tx_complete(void * arg)1222 static void sci_dma_tx_complete(void *arg)
1223 {
1224 struct sci_port *s = arg;
1225 struct uart_port *port = &s->port;
1226 struct tty_port *tport = &port->state->port;
1227 unsigned long flags;
1228
1229 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1230
1231 uart_port_lock_irqsave(port, &flags);
1232
1233 uart_xmit_advance(port, s->tx_dma_len);
1234
1235 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
1236 uart_write_wakeup(port);
1237
1238 s->tx_occurred = true;
1239
1240 if (!kfifo_is_empty(&tport->xmit_fifo)) {
1241 s->cookie_tx = 0;
1242 schedule_work(&s->work_tx);
1243 } else {
1244 s->cookie_tx = -EINVAL;
1245 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1246 s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1247 u16 ctrl = sci_serial_in(port, SCSCR);
1248 sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1249 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1250 /* Switch irq from DMA to SCIF */
1251 dmaengine_pause(s->chan_tx_saved);
1252 enable_irq(s->irqs[SCIx_TXI_IRQ]);
1253 }
1254 }
1255 }
1256
1257 uart_port_unlock_irqrestore(port, flags);
1258 }
1259
1260 /* Locking: called with port lock held */
sci_dma_rx_push(struct sci_port * s,void * buf,size_t count)1261 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1262 {
1263 struct uart_port *port = &s->port;
1264 struct tty_port *tport = &port->state->port;
1265 int copied;
1266
1267 copied = tty_insert_flip_string(tport, buf, count);
1268 if (copied < count)
1269 port->icount.buf_overrun++;
1270
1271 port->icount.rx += copied;
1272
1273 return copied;
1274 }
1275
sci_dma_rx_find_active(struct sci_port * s)1276 static int sci_dma_rx_find_active(struct sci_port *s)
1277 {
1278 unsigned int i;
1279
1280 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1281 if (s->active_rx == s->cookie_rx[i])
1282 return i;
1283
1284 return -1;
1285 }
1286
1287 /* Must only be called with uart_port_lock taken */
sci_dma_rx_chan_invalidate(struct sci_port * s)1288 static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1289 {
1290 unsigned int i;
1291
1292 s->chan_rx = NULL;
1293 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1294 s->cookie_rx[i] = -EINVAL;
1295 s->active_rx = 0;
1296 }
1297
sci_dma_rx_release(struct sci_port * s)1298 static void sci_dma_rx_release(struct sci_port *s)
1299 {
1300 struct dma_chan *chan = s->chan_rx_saved;
1301 struct uart_port *port = &s->port;
1302 unsigned long flags;
1303
1304 uart_port_lock_irqsave(port, &flags);
1305 s->chan_rx_saved = NULL;
1306 sci_dma_rx_chan_invalidate(s);
1307 uart_port_unlock_irqrestore(port, flags);
1308
1309 dmaengine_terminate_sync(chan);
1310 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1311 sg_dma_address(&s->sg_rx[0]));
1312 dma_release_channel(chan);
1313 }
1314
start_hrtimer_us(struct hrtimer * hrt,unsigned long usec)1315 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1316 {
1317 long sec = usec / 1000000;
1318 long nsec = (usec % 1000000) * 1000;
1319 ktime_t t = ktime_set(sec, nsec);
1320
1321 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1322 }
1323
sci_dma_rx_reenable_irq(struct sci_port * s)1324 static void sci_dma_rx_reenable_irq(struct sci_port *s)
1325 {
1326 struct uart_port *port = &s->port;
1327 u16 scr;
1328
1329 /* Direct new serial port interrupts back to CPU */
1330 scr = sci_serial_in(port, SCSCR);
1331 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1332 s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1333 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1334 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE)
1335 s->ops->set_rtrg(port, s->rx_trigger);
1336 else
1337 scr &= ~SCSCR_RDRQE;
1338 }
1339 sci_serial_out(port, SCSCR, scr | SCSCR_RIE);
1340 }
1341
sci_dma_rx_complete(void * arg)1342 static void sci_dma_rx_complete(void *arg)
1343 {
1344 struct sci_port *s = arg;
1345 struct dma_chan *chan = s->chan_rx;
1346 struct uart_port *port = &s->port;
1347 struct dma_async_tx_descriptor *desc;
1348 unsigned long flags;
1349 int active, count = 0;
1350
1351 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1352 s->active_rx);
1353
1354 hrtimer_cancel(&s->rx_timer);
1355
1356 uart_port_lock_irqsave(port, &flags);
1357
1358 active = sci_dma_rx_find_active(s);
1359 if (active >= 0)
1360 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1361
1362 if (count)
1363 tty_flip_buffer_push(&port->state->port);
1364
1365 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1366 DMA_DEV_TO_MEM,
1367 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1368 if (!desc)
1369 goto fail;
1370
1371 desc->callback = sci_dma_rx_complete;
1372 desc->callback_param = s;
1373 s->cookie_rx[active] = dmaengine_submit(desc);
1374 if (dma_submit_error(s->cookie_rx[active]))
1375 goto fail;
1376
1377 s->active_rx = s->cookie_rx[!active];
1378
1379 dma_async_issue_pending(chan);
1380
1381 uart_port_unlock_irqrestore(port, flags);
1382 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1383 __func__, s->cookie_rx[active], active, s->active_rx);
1384
1385 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1386
1387 return;
1388
1389 fail:
1390 /* Switch to PIO */
1391 dmaengine_terminate_async(chan);
1392 sci_dma_rx_chan_invalidate(s);
1393 sci_dma_rx_reenable_irq(s);
1394 uart_port_unlock_irqrestore(port, flags);
1395 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1396 }
1397
sci_dma_tx_release(struct sci_port * s)1398 static void sci_dma_tx_release(struct sci_port *s)
1399 {
1400 struct dma_chan *chan = s->chan_tx_saved;
1401
1402 cancel_work_sync(&s->work_tx);
1403 s->chan_tx_saved = s->chan_tx = NULL;
1404 s->cookie_tx = -EINVAL;
1405 dmaengine_terminate_sync(chan);
1406 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1407 DMA_TO_DEVICE);
1408 dma_release_channel(chan);
1409 }
1410
sci_dma_rx_submit(struct sci_port * s,bool port_lock_held)1411 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1412 {
1413 struct dma_chan *chan = s->chan_rx;
1414 struct uart_port *port = &s->port;
1415 unsigned long flags;
1416 int i;
1417
1418 for (i = 0; i < 2; i++) {
1419 struct scatterlist *sg = &s->sg_rx[i];
1420 struct dma_async_tx_descriptor *desc;
1421
1422 desc = dmaengine_prep_slave_sg(chan,
1423 sg, 1, DMA_DEV_TO_MEM,
1424 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1425 if (!desc)
1426 goto fail;
1427
1428 desc->callback = sci_dma_rx_complete;
1429 desc->callback_param = s;
1430 s->cookie_rx[i] = dmaengine_submit(desc);
1431 if (dma_submit_error(s->cookie_rx[i]))
1432 goto fail;
1433
1434 }
1435
1436 s->active_rx = s->cookie_rx[0];
1437
1438 dma_async_issue_pending(chan);
1439 return 0;
1440
1441 fail:
1442 /* Switch to PIO */
1443 if (!port_lock_held)
1444 uart_port_lock_irqsave(port, &flags);
1445 if (i)
1446 dmaengine_terminate_async(chan);
1447 sci_dma_rx_chan_invalidate(s);
1448 sci_start_rx(port);
1449 if (!port_lock_held)
1450 uart_port_unlock_irqrestore(port, flags);
1451 return -EAGAIN;
1452 }
1453
sci_dma_tx_work_fn(struct work_struct * work)1454 static void sci_dma_tx_work_fn(struct work_struct *work)
1455 {
1456 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1457 struct dma_async_tx_descriptor *desc;
1458 struct dma_chan *chan = s->chan_tx;
1459 struct uart_port *port = &s->port;
1460 struct tty_port *tport = &port->state->port;
1461 unsigned long flags;
1462 unsigned int tail;
1463 dma_addr_t buf;
1464
1465 /*
1466 * DMA is idle now.
1467 * Port xmit buffer is already mapped, and it is one page... Just adjust
1468 * offsets and lengths. Since it is a circular buffer, we have to
1469 * transmit till the end, and then the rest. Take the port lock to get a
1470 * consistent xmit buffer state.
1471 */
1472 uart_port_lock_irq(port);
1473 s->tx_dma_len = kfifo_out_linear(&tport->xmit_fifo, &tail,
1474 UART_XMIT_SIZE);
1475 buf = s->tx_dma_addr + tail;
1476 if (!s->tx_dma_len) {
1477 /* Transmit buffer has been flushed */
1478 uart_port_unlock_irq(port);
1479 return;
1480 }
1481
1482 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1483 DMA_MEM_TO_DEV,
1484 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1485 if (!desc) {
1486 uart_port_unlock_irq(port);
1487 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1488 goto switch_to_pio;
1489 }
1490
1491 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1492 DMA_TO_DEVICE);
1493
1494 desc->callback = sci_dma_tx_complete;
1495 desc->callback_param = s;
1496 s->cookie_tx = dmaengine_submit(desc);
1497 if (dma_submit_error(s->cookie_tx)) {
1498 uart_port_unlock_irq(port);
1499 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1500 goto switch_to_pio;
1501 }
1502
1503 uart_port_unlock_irq(port);
1504 dev_dbg(port->dev, "%s: %p: %u, cookie %d\n",
1505 __func__, tport->xmit_buf, tail, s->cookie_tx);
1506
1507 dma_async_issue_pending(chan);
1508 return;
1509
1510 switch_to_pio:
1511 uart_port_lock_irqsave(port, &flags);
1512 s->chan_tx = NULL;
1513 sci_start_tx(port);
1514 uart_port_unlock_irqrestore(port, flags);
1515 return;
1516 }
1517
sci_dma_rx_timer_fn(struct hrtimer * t)1518 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1519 {
1520 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1521 struct dma_chan *chan = s->chan_rx;
1522 struct uart_port *port = &s->port;
1523 struct dma_tx_state state;
1524 enum dma_status status;
1525 unsigned long flags;
1526 unsigned int read;
1527 int active, count;
1528
1529 dev_dbg(port->dev, "DMA Rx timed out\n");
1530
1531 uart_port_lock_irqsave(port, &flags);
1532
1533 active = sci_dma_rx_find_active(s);
1534 if (active < 0) {
1535 uart_port_unlock_irqrestore(port, flags);
1536 return HRTIMER_NORESTART;
1537 }
1538
1539 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1540 if (status == DMA_COMPLETE) {
1541 uart_port_unlock_irqrestore(port, flags);
1542 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1543 s->active_rx, active);
1544
1545 /* Let packet complete handler take care of the packet */
1546 return HRTIMER_NORESTART;
1547 }
1548
1549 dmaengine_pause(chan);
1550
1551 /*
1552 * sometimes DMA transfer doesn't stop even if it is stopped and
1553 * data keeps on coming until transaction is complete so check
1554 * for DMA_COMPLETE again
1555 * Let packet complete handler take care of the packet
1556 */
1557 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1558 if (status == DMA_COMPLETE) {
1559 uart_port_unlock_irqrestore(port, flags);
1560 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1561 return HRTIMER_NORESTART;
1562 }
1563
1564 /* Handle incomplete DMA receive */
1565 dmaengine_terminate_async(s->chan_rx);
1566 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1567
1568 if (read) {
1569 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1570 if (count)
1571 tty_flip_buffer_push(&port->state->port);
1572 }
1573
1574 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1575 s->regtype == SCIx_RZ_SCIFA_REGTYPE)
1576 sci_dma_rx_submit(s, true);
1577
1578 sci_dma_rx_reenable_irq(s);
1579
1580 uart_port_unlock_irqrestore(port, flags);
1581
1582 return HRTIMER_NORESTART;
1583 }
1584
sci_request_dma_chan(struct uart_port * port,enum dma_transfer_direction dir)1585 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1586 enum dma_transfer_direction dir)
1587 {
1588 struct dma_chan *chan;
1589 struct dma_slave_config cfg;
1590 int ret;
1591
1592 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1593 if (IS_ERR(chan)) {
1594 dev_dbg(port->dev, "dma_request_chan failed\n");
1595 return NULL;
1596 }
1597
1598 memset(&cfg, 0, sizeof(cfg));
1599 cfg.direction = dir;
1600 cfg.dst_addr = port->mapbase +
1601 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1602 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1603 cfg.src_addr = port->mapbase +
1604 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1605 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1606
1607 ret = dmaengine_slave_config(chan, &cfg);
1608 if (ret) {
1609 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1610 dma_release_channel(chan);
1611 return NULL;
1612 }
1613
1614 return chan;
1615 }
1616
sci_request_dma(struct uart_port * port)1617 static void sci_request_dma(struct uart_port *port)
1618 {
1619 struct sci_port *s = to_sci_port(port);
1620 struct tty_port *tport = &port->state->port;
1621 struct dma_chan *chan;
1622
1623 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1624
1625 /*
1626 * DMA on console may interfere with Kernel log messages which use
1627 * plain putchar(). So, simply don't use it with a console.
1628 */
1629 if (uart_console(port))
1630 return;
1631
1632 if (!port->dev->of_node)
1633 return;
1634
1635 s->cookie_tx = -EINVAL;
1636
1637 /*
1638 * Don't request a dma channel if no channel was specified
1639 * in the device tree.
1640 */
1641 if (!of_property_present(port->dev->of_node, "dmas"))
1642 return;
1643
1644 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1645 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1646 if (chan) {
1647 /* UART circular tx buffer is an aligned page. */
1648 s->tx_dma_addr = dma_map_single(chan->device->dev,
1649 tport->xmit_buf,
1650 UART_XMIT_SIZE,
1651 DMA_TO_DEVICE);
1652 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1653 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1654 dma_release_channel(chan);
1655 } else {
1656 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1657 __func__, UART_XMIT_SIZE,
1658 tport->xmit_buf, &s->tx_dma_addr);
1659
1660 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1661 s->chan_tx_saved = s->chan_tx = chan;
1662 }
1663 }
1664
1665 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1666 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1667 if (chan) {
1668 unsigned int i;
1669 dma_addr_t dma;
1670 void *buf;
1671
1672 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1673 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1674 &dma, GFP_KERNEL);
1675 if (!buf) {
1676 dev_warn(port->dev,
1677 "Failed to allocate Rx dma buffer, using PIO\n");
1678 dma_release_channel(chan);
1679 return;
1680 }
1681
1682 for (i = 0; i < 2; i++) {
1683 struct scatterlist *sg = &s->sg_rx[i];
1684
1685 sg_init_table(sg, 1);
1686 s->rx_buf[i] = buf;
1687 sg_dma_address(sg) = dma;
1688 sg_dma_len(sg) = s->buf_len_rx;
1689
1690 buf += s->buf_len_rx;
1691 dma += s->buf_len_rx;
1692 }
1693
1694 hrtimer_setup(&s->rx_timer, sci_dma_rx_timer_fn, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1695
1696 s->chan_rx_saved = s->chan_rx = chan;
1697
1698 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1699 s->regtype == SCIx_RZ_SCIFA_REGTYPE)
1700 sci_dma_rx_submit(s, false);
1701 }
1702 }
1703
sci_free_dma(struct uart_port * port)1704 static void sci_free_dma(struct uart_port *port)
1705 {
1706 struct sci_port *s = to_sci_port(port);
1707
1708 if (s->chan_tx_saved)
1709 sci_dma_tx_release(s);
1710 if (s->chan_rx_saved)
1711 sci_dma_rx_release(s);
1712 }
1713
sci_flush_buffer(struct uart_port * port)1714 static void sci_flush_buffer(struct uart_port *port)
1715 {
1716 struct sci_port *s = to_sci_port(port);
1717
1718 /*
1719 * In uart_flush_buffer(), the xmit circular buffer has just been
1720 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1721 * pending transfers
1722 */
1723 s->tx_dma_len = 0;
1724 if (s->chan_tx) {
1725 dmaengine_terminate_async(s->chan_tx);
1726 s->cookie_tx = -EINVAL;
1727 }
1728 }
1729
sci_dma_check_tx_occurred(struct sci_port * s)1730 static void sci_dma_check_tx_occurred(struct sci_port *s)
1731 {
1732 struct dma_tx_state state;
1733 enum dma_status status;
1734
1735 if (!s->chan_tx)
1736 return;
1737
1738 status = dmaengine_tx_status(s->chan_tx, s->cookie_tx, &state);
1739 if (status == DMA_COMPLETE || status == DMA_IN_PROGRESS)
1740 s->tx_occurred = true;
1741 }
1742 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
sci_request_dma(struct uart_port * port)1743 static inline void sci_request_dma(struct uart_port *port)
1744 {
1745 }
1746
sci_free_dma(struct uart_port * port)1747 static inline void sci_free_dma(struct uart_port *port)
1748 {
1749 }
1750
sci_dma_check_tx_occurred(struct sci_port * s)1751 static void sci_dma_check_tx_occurred(struct sci_port *s)
1752 {
1753 }
1754
1755 #define sci_flush_buffer NULL
1756 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1757
sci_rx_interrupt(int irq,void * ptr)1758 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1759 {
1760 struct uart_port *port = ptr;
1761 struct sci_port *s = to_sci_port(port);
1762
1763 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1764 if (s->chan_rx) {
1765 u16 scr = sci_serial_in(port, SCSCR);
1766 u16 ssr = sci_serial_in(port, SCxSR);
1767
1768 /* Disable future Rx interrupts */
1769 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1770 s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1771 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]);
1772 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1773 s->ops->set_rtrg(port, 1);
1774 scr |= SCSCR_RIE;
1775 } else {
1776 scr |= SCSCR_RDRQE;
1777 }
1778 } else {
1779 if (sci_dma_rx_submit(s, false) < 0)
1780 goto handle_pio;
1781
1782 scr &= ~SCSCR_RIE;
1783 }
1784 sci_serial_out(port, SCSCR, scr);
1785 /* Clear current interrupt */
1786 sci_serial_out(port, SCxSR,
1787 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1788 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1789 jiffies, s->rx_timeout);
1790 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1791
1792 return IRQ_HANDLED;
1793 }
1794
1795 handle_pio:
1796 #endif
1797
1798 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1799 if (!s->ops->rtrg_enabled(port))
1800 s->ops->set_rtrg(port, s->rx_trigger);
1801
1802 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1803 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1804 }
1805
1806 /* I think sci_receive_chars has to be called irrespective
1807 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1808 * to be disabled?
1809 */
1810 s->ops->receive_chars(port);
1811
1812 return IRQ_HANDLED;
1813 }
1814
sci_tx_interrupt(int irq,void * ptr)1815 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1816 {
1817 struct uart_port *port = ptr;
1818 unsigned long flags;
1819 struct sci_port *s = to_sci_port(port);
1820
1821 uart_port_lock_irqsave(port, &flags);
1822 s->ops->transmit_chars(port);
1823 uart_port_unlock_irqrestore(port, flags);
1824
1825 return IRQ_HANDLED;
1826 }
1827
sci_tx_end_interrupt(int irq,void * ptr)1828 static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
1829 {
1830 struct uart_port *port = ptr;
1831 struct sci_port *s = to_sci_port(port);
1832 const struct sci_common_regs *regs = s->params->common_regs;
1833 unsigned long flags;
1834 u32 ctrl;
1835
1836 if (s->type != PORT_SCI && s->type != SCI_PORT_RSCI)
1837 return sci_tx_interrupt(irq, ptr);
1838
1839 uart_port_lock_irqsave(port, &flags);
1840 ctrl = s->ops->read_reg(port, regs->control) &
1841 ~(s->params->param_bits->te_clear);
1842 s->ops->write_reg(port, regs->control, ctrl);
1843 uart_port_unlock_irqrestore(port, flags);
1844
1845 return IRQ_HANDLED;
1846 }
1847
sci_br_interrupt(int irq,void * ptr)1848 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1849 {
1850 struct uart_port *port = ptr;
1851 struct sci_port *s = to_sci_port(port);
1852
1853 /* Handle BREAKs */
1854 sci_handle_breaks(port);
1855
1856 /* drop invalid character received before break was detected */
1857 sci_serial_in(port, SCxRDR);
1858
1859 s->ops->clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1860
1861 return IRQ_HANDLED;
1862 }
1863
sci_er_interrupt(int irq,void * ptr)1864 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1865 {
1866 struct uart_port *port = ptr;
1867 struct sci_port *s = to_sci_port(port);
1868
1869 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1870 /* Break and Error interrupts are muxed */
1871 unsigned short ssr_status = sci_serial_in(port, SCxSR);
1872
1873 /* Break Interrupt */
1874 if (ssr_status & SCxSR_BRK(port))
1875 sci_br_interrupt(irq, ptr);
1876
1877 /* Break only? */
1878 if (!(ssr_status & SCxSR_ERRORS(port)))
1879 return IRQ_HANDLED;
1880 }
1881
1882 /* Handle errors */
1883 if (s->type == PORT_SCI) {
1884 if (sci_handle_errors(port)) {
1885 /* discard character in rx buffer */
1886 sci_serial_in(port, SCxSR);
1887 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1888 }
1889 } else {
1890 sci_handle_fifo_overrun(port);
1891 if (!s->chan_rx)
1892 s->ops->receive_chars(port);
1893 }
1894
1895 s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1896
1897 /* Kick the transmission */
1898 if (!s->chan_tx)
1899 sci_tx_interrupt(irq, ptr);
1900
1901 return IRQ_HANDLED;
1902 }
1903
sci_mpxed_interrupt(int irq,void * ptr)1904 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1905 {
1906 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1907 struct uart_port *port = ptr;
1908 struct sci_port *s = to_sci_port(port);
1909 irqreturn_t ret = IRQ_NONE;
1910
1911 ssr_status = sci_serial_in(port, SCxSR);
1912 scr_status = sci_serial_in(port, SCSCR);
1913 if (s->params->overrun_reg == SCxSR)
1914 orer_status = ssr_status;
1915 else if (sci_getreg(port, s->params->overrun_reg)->size)
1916 orer_status = sci_serial_in(port, s->params->overrun_reg);
1917
1918 err_enabled = scr_status & port_rx_irq_mask(port);
1919
1920 /* Tx Interrupt */
1921 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1922 !s->chan_tx)
1923 ret = sci_tx_interrupt(irq, ptr);
1924
1925 /*
1926 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1927 * DR flags
1928 */
1929 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1930 (scr_status & SCSCR_RIE))
1931 ret = sci_rx_interrupt(irq, ptr);
1932
1933 /* Error Interrupt */
1934 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1935 ret = sci_er_interrupt(irq, ptr);
1936
1937 /* Break Interrupt */
1938 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
1939 (ssr_status & SCxSR_BRK(port)) && err_enabled)
1940 ret = sci_br_interrupt(irq, ptr);
1941
1942 /* Overrun Interrupt */
1943 if (orer_status & s->params->overrun_mask) {
1944 sci_handle_fifo_overrun(port);
1945 ret = IRQ_HANDLED;
1946 }
1947
1948 return ret;
1949 }
1950
1951 static const struct sci_irq_desc {
1952 const char *desc;
1953 irq_handler_t handler;
1954 } sci_irq_desc[] = {
1955 /*
1956 * Split out handlers, the default case.
1957 */
1958 [SCIx_ERI_IRQ] = {
1959 .desc = "rx err",
1960 .handler = sci_er_interrupt,
1961 },
1962
1963 [SCIx_RXI_IRQ] = {
1964 .desc = "rx full",
1965 .handler = sci_rx_interrupt,
1966 },
1967
1968 [SCIx_TXI_IRQ] = {
1969 .desc = "tx empty",
1970 .handler = sci_tx_interrupt,
1971 },
1972
1973 [SCIx_BRI_IRQ] = {
1974 .desc = "break",
1975 .handler = sci_br_interrupt,
1976 },
1977
1978 [SCIx_DRI_IRQ] = {
1979 .desc = "rx ready",
1980 .handler = sci_rx_interrupt,
1981 },
1982
1983 [SCIx_TEI_IRQ] = {
1984 .desc = "tx end",
1985 .handler = sci_tx_end_interrupt,
1986 },
1987
1988 /*
1989 * Special muxed handler.
1990 */
1991 [SCIx_MUX_IRQ] = {
1992 .desc = "mux",
1993 .handler = sci_mpxed_interrupt,
1994 },
1995 };
1996
sci_request_irq(struct sci_port * port)1997 static int sci_request_irq(struct sci_port *port)
1998 {
1999 struct uart_port *up = &port->port;
2000 int i, j, w, ret = 0;
2001
2002 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
2003 const struct sci_irq_desc *desc;
2004 int irq;
2005
2006 /* Check if already registered (muxed) */
2007 for (w = 0; w < i; w++)
2008 if (port->irqs[w] == port->irqs[i])
2009 w = i + 1;
2010 if (w > i)
2011 continue;
2012
2013 if (SCIx_IRQ_IS_MUXED(port)) {
2014 i = SCIx_MUX_IRQ;
2015 irq = up->irq;
2016 } else {
2017 irq = port->irqs[i];
2018
2019 /*
2020 * Certain port types won't support all of the
2021 * available interrupt sources.
2022 */
2023 if (unlikely(irq < 0))
2024 continue;
2025 }
2026
2027 desc = sci_irq_desc + i;
2028 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
2029 dev_name(up->dev), desc->desc);
2030 if (!port->irqstr[j]) {
2031 ret = -ENOMEM;
2032 goto out_nomem;
2033 }
2034
2035 ret = request_irq(irq, desc->handler, up->irqflags,
2036 port->irqstr[j], port);
2037 if (unlikely(ret)) {
2038 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
2039 goto out_noirq;
2040 }
2041 }
2042
2043 return 0;
2044
2045 out_noirq:
2046 while (--i >= 0)
2047 free_irq(port->irqs[i], port);
2048
2049 out_nomem:
2050 while (--j >= 0)
2051 kfree(port->irqstr[j]);
2052
2053 return ret;
2054 }
2055
sci_free_irq(struct sci_port * port)2056 static void sci_free_irq(struct sci_port *port)
2057 {
2058 int i, j;
2059
2060 /*
2061 * Intentionally in reverse order so we iterate over the muxed
2062 * IRQ first.
2063 */
2064 for (i = 0; i < SCIx_NR_IRQS; i++) {
2065 int irq = port->irqs[i];
2066
2067 /*
2068 * Certain port types won't support all of the available
2069 * interrupt sources.
2070 */
2071 if (unlikely(irq < 0))
2072 continue;
2073
2074 /* Check if already freed (irq was muxed) */
2075 for (j = 0; j < i; j++)
2076 if (port->irqs[j] == irq)
2077 j = i + 1;
2078 if (j > i)
2079 continue;
2080
2081 free_irq(port->irqs[i], port);
2082 kfree(port->irqstr[i]);
2083
2084 if (SCIx_IRQ_IS_MUXED(port)) {
2085 /* If there's only one IRQ, we're done. */
2086 return;
2087 }
2088 }
2089 }
2090
sci_tx_empty(struct uart_port * port)2091 static unsigned int sci_tx_empty(struct uart_port *port)
2092 {
2093 unsigned short status = sci_serial_in(port, SCxSR);
2094 unsigned short in_tx_fifo = sci_txfill(port);
2095 struct sci_port *s = to_sci_port(port);
2096
2097 sci_dma_check_tx_occurred(s);
2098
2099 if (!s->tx_occurred)
2100 return TIOCSER_TEMT;
2101
2102 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
2103 }
2104
sci_set_rts(struct uart_port * port,bool state)2105 static void sci_set_rts(struct uart_port *port, bool state)
2106 {
2107 struct sci_port *s = to_sci_port(port);
2108
2109 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
2110 u16 data = sci_serial_in(port, SCPDR);
2111
2112 /* Active low */
2113 if (state)
2114 data &= ~SCPDR_RTSD;
2115 else
2116 data |= SCPDR_RTSD;
2117 sci_serial_out(port, SCPDR, data);
2118
2119 /* RTS# is output */
2120 sci_serial_out(port, SCPCR,
2121 sci_serial_in(port, SCPCR) | SCPCR_RTSC);
2122 } else if (sci_getreg(port, SCSPTR)->size) {
2123 u16 ctrl = sci_serial_in(port, SCSPTR);
2124
2125 /* Active low */
2126 if (state)
2127 ctrl &= ~SCSPTR_RTSDT;
2128 else
2129 ctrl |= SCSPTR_RTSDT;
2130 sci_serial_out(port, SCSPTR, ctrl);
2131 }
2132 }
2133
sci_get_cts(struct uart_port * port)2134 static bool sci_get_cts(struct uart_port *port)
2135 {
2136 struct sci_port *s = to_sci_port(port);
2137
2138 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
2139 /* Active low */
2140 return !(sci_serial_in(port, SCPDR) & SCPDR_CTSD);
2141 } else if (sci_getreg(port, SCSPTR)->size) {
2142 /* Active low */
2143 return !(sci_serial_in(port, SCSPTR) & SCSPTR_CTSDT);
2144 }
2145
2146 return true;
2147 }
2148
2149 /*
2150 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2151 * CTS/RTS is supported in hardware by at least one port and controlled
2152 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2153 * handled via the ->init_pins() op, which is a bit of a one-way street,
2154 * lacking any ability to defer pin control -- this will later be
2155 * converted over to the GPIO framework).
2156 *
2157 * Other modes (such as loopback) are supported generically on certain
2158 * port types, but not others. For these it's sufficient to test for the
2159 * existence of the support register and simply ignore the port type.
2160 */
sci_set_mctrl(struct uart_port * port,unsigned int mctrl)2161 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2162 {
2163 struct sci_port *s = to_sci_port(port);
2164
2165 if (mctrl & TIOCM_LOOP) {
2166 const struct plat_sci_reg *reg;
2167
2168 /*
2169 * Standard loopback mode for SCFCR ports.
2170 */
2171 reg = sci_getreg(port, SCFCR);
2172 if (reg->size)
2173 sci_serial_out(port, SCFCR,
2174 sci_serial_in(port, SCFCR) | SCFCR_LOOP);
2175 }
2176
2177 mctrl_gpio_set(s->gpios, mctrl);
2178
2179 if (!s->has_rtscts)
2180 return;
2181
2182 if (!(mctrl & TIOCM_RTS)) {
2183 /* Disable Auto RTS */
2184 if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE)
2185 sci_serial_out(port, SCFCR,
2186 sci_serial_in(port, SCFCR) & ~SCFCR_MCE);
2187
2188 /* Clear RTS */
2189 sci_set_rts(port, 0);
2190 } else if (s->autorts) {
2191 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
2192 /* Enable RTS# pin function */
2193 sci_serial_out(port, SCPCR,
2194 sci_serial_in(port, SCPCR) & ~SCPCR_RTSC);
2195 }
2196
2197 /* Enable Auto RTS */
2198 if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE)
2199 sci_serial_out(port, SCFCR,
2200 sci_serial_in(port, SCFCR) | SCFCR_MCE);
2201 } else {
2202 /* Set RTS */
2203 sci_set_rts(port, 1);
2204 }
2205 }
2206
sci_get_mctrl(struct uart_port * port)2207 static unsigned int sci_get_mctrl(struct uart_port *port)
2208 {
2209 struct sci_port *s = to_sci_port(port);
2210 struct mctrl_gpios *gpios = s->gpios;
2211 unsigned int mctrl = 0;
2212
2213 mctrl_gpio_get(gpios, &mctrl);
2214
2215 /*
2216 * CTS/RTS is handled in hardware when supported, while nothing
2217 * else is wired up.
2218 */
2219 if (s->autorts) {
2220 if (sci_get_cts(port))
2221 mctrl |= TIOCM_CTS;
2222 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2223 mctrl |= TIOCM_CTS;
2224 }
2225 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2226 mctrl |= TIOCM_DSR;
2227 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2228 mctrl |= TIOCM_CAR;
2229
2230 return mctrl;
2231 }
2232
sci_enable_ms(struct uart_port * port)2233 static void sci_enable_ms(struct uart_port *port)
2234 {
2235 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2236 }
2237
sci_break_ctl(struct uart_port * port,int break_state)2238 static void sci_break_ctl(struct uart_port *port, int break_state)
2239 {
2240 unsigned short scscr, scsptr;
2241 unsigned long flags;
2242
2243 /* check whether the port has SCSPTR */
2244 if (!sci_getreg(port, SCSPTR)->size) {
2245 /*
2246 * Not supported by hardware. Most parts couple break and rx
2247 * interrupts together, with break detection always enabled.
2248 */
2249 return;
2250 }
2251
2252 uart_port_lock_irqsave(port, &flags);
2253 scsptr = sci_serial_in(port, SCSPTR);
2254 scscr = sci_serial_in(port, SCSCR);
2255
2256 if (break_state == -1) {
2257 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2258 scscr &= ~SCSCR_TE;
2259 } else {
2260 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2261 scscr |= SCSCR_TE;
2262 }
2263
2264 sci_serial_out(port, SCSPTR, scsptr);
2265 sci_serial_out(port, SCSCR, scscr);
2266 uart_port_unlock_irqrestore(port, flags);
2267 }
2268
sci_shutdown_complete(struct uart_port * port)2269 static void sci_shutdown_complete(struct uart_port *port)
2270 {
2271 struct sci_port *s = to_sci_port(port);
2272 u16 scr;
2273
2274 scr = sci_serial_in(port, SCSCR);
2275 sci_serial_out(port, SCSCR,
2276 scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2277 }
2278
sci_startup(struct uart_port * port)2279 int sci_startup(struct uart_port *port)
2280 {
2281 struct sci_port *s = to_sci_port(port);
2282 int ret;
2283
2284 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2285
2286 s->tx_occurred = false;
2287 sci_request_dma(port);
2288
2289 ret = sci_request_irq(s);
2290 if (unlikely(ret < 0)) {
2291 sci_free_dma(port);
2292 return ret;
2293 }
2294
2295 return 0;
2296 }
2297 EXPORT_SYMBOL_NS_GPL(sci_startup, "SH_SCI");
2298
sci_shutdown(struct uart_port * port)2299 void sci_shutdown(struct uart_port *port)
2300 {
2301 struct sci_port *s = to_sci_port(port);
2302 unsigned long flags;
2303
2304 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2305
2306 s->autorts = false;
2307 mctrl_gpio_disable_ms_sync(to_sci_port(port)->gpios);
2308
2309 uart_port_lock_irqsave(port, &flags);
2310 s->port.ops->stop_rx(port);
2311 s->port.ops->stop_tx(port);
2312 s->ops->shutdown_complete(port);
2313 uart_port_unlock_irqrestore(port, flags);
2314
2315 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2316 if (s->chan_rx_saved) {
2317 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2318 port->line);
2319 hrtimer_cancel(&s->rx_timer);
2320 }
2321 #endif
2322
2323 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2324 timer_delete_sync(&s->rx_fifo_timer);
2325 sci_free_irq(s);
2326 sci_free_dma(port);
2327 }
2328 EXPORT_SYMBOL_NS_GPL(sci_shutdown, "SH_SCI");
2329
sci_sck_calc(struct sci_port * s,unsigned int bps,unsigned int * srr)2330 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2331 unsigned int *srr)
2332 {
2333 unsigned long freq = s->clk_rates[SCI_SCK];
2334 int err, min_err = INT_MAX;
2335 unsigned int sr;
2336
2337 if (s->type != PORT_HSCIF)
2338 freq *= 2;
2339
2340 for_each_sr(sr, s) {
2341 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2342 if (abs(err) >= abs(min_err))
2343 continue;
2344
2345 min_err = err;
2346 *srr = sr - 1;
2347
2348 if (!err)
2349 break;
2350 }
2351
2352 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2353 *srr + 1);
2354 return min_err;
2355 }
2356
sci_brg_calc(struct sci_port * s,unsigned int bps,unsigned long freq,unsigned int * dlr,unsigned int * srr)2357 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2358 unsigned long freq, unsigned int *dlr,
2359 unsigned int *srr)
2360 {
2361 int err, min_err = INT_MAX;
2362 unsigned int sr, dl;
2363
2364 if (s->type != PORT_HSCIF)
2365 freq *= 2;
2366
2367 for_each_sr(sr, s) {
2368 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2369 dl = clamp(dl, 1U, 65535U);
2370
2371 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2372 if (abs(err) >= abs(min_err))
2373 continue;
2374
2375 min_err = err;
2376 *dlr = dl;
2377 *srr = sr - 1;
2378
2379 if (!err)
2380 break;
2381 }
2382
2383 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2384 min_err, *dlr, *srr + 1);
2385 return min_err;
2386 }
2387
2388 /* calculate sample rate, BRR, and clock select */
sci_scbrr_calc(struct sci_port * s,unsigned int bps,unsigned int * brr,unsigned int * srr,unsigned int * cks)2389 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2390 unsigned int *brr, unsigned int *srr,
2391 unsigned int *cks)
2392 {
2393 unsigned long freq = s->clk_rates[SCI_FCK];
2394 unsigned int sr, br, prediv, scrate, c;
2395 int err, min_err = INT_MAX;
2396
2397 if (s->type != PORT_HSCIF)
2398 freq *= 2;
2399
2400 /*
2401 * Find the combination of sample rate and clock select with the
2402 * smallest deviation from the desired baud rate.
2403 * Prefer high sample rates to maximise the receive margin.
2404 *
2405 * M: Receive margin (%)
2406 * N: Ratio of bit rate to clock (N = sampling rate)
2407 * D: Clock duty (D = 0 to 1.0)
2408 * L: Frame length (L = 9 to 12)
2409 * F: Absolute value of clock frequency deviation
2410 *
2411 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2412 * (|D - 0.5| / N * (1 + F))|
2413 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2414 */
2415 for_each_sr(sr, s) {
2416 for (c = 0; c <= 3; c++) {
2417 /* integerized formulas from HSCIF documentation */
2418 prediv = sr << (2 * c + 1);
2419
2420 /*
2421 * We need to calculate:
2422 *
2423 * br = freq / (prediv * bps) clamped to [1..256]
2424 * err = freq / (br * prediv) - bps
2425 *
2426 * Watch out for overflow when calculating the desired
2427 * sampling clock rate!
2428 */
2429 if (bps > UINT_MAX / prediv)
2430 break;
2431
2432 scrate = prediv * bps;
2433 br = DIV_ROUND_CLOSEST(freq, scrate);
2434 br = clamp(br, 1U, 256U);
2435
2436 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2437 if (abs(err) >= abs(min_err))
2438 continue;
2439
2440 min_err = err;
2441 *brr = br - 1;
2442 *srr = sr - 1;
2443 *cks = c;
2444
2445 if (!err)
2446 goto found;
2447 }
2448 }
2449
2450 found:
2451 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2452 min_err, *brr, *srr + 1, *cks);
2453 return min_err;
2454 }
2455
sci_reset(struct uart_port * port)2456 static void sci_reset(struct uart_port *port)
2457 {
2458 const struct plat_sci_reg *reg;
2459 unsigned int status;
2460 struct sci_port *s = to_sci_port(port);
2461
2462 sci_serial_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2463
2464 reg = sci_getreg(port, SCFCR);
2465 if (reg->size)
2466 sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2467
2468 s->ops->clear_SCxSR(port,
2469 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2470 SCxSR_BREAK_CLEAR(port));
2471 if (sci_getreg(port, SCLSR)->size) {
2472 status = sci_serial_in(port, SCLSR);
2473 status &= ~(SCLSR_TO | SCLSR_ORER);
2474 sci_serial_out(port, SCLSR, status);
2475 }
2476
2477 if (s->rx_trigger > 1) {
2478 if (s->rx_fifo_timeout) {
2479 s->ops->set_rtrg(port, 1);
2480 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2481 } else {
2482 if (s->type == PORT_SCIFA ||
2483 s->type == PORT_SCIFB)
2484 s->ops->set_rtrg(port, 1);
2485 else
2486 s->ops->set_rtrg(port, s->rx_trigger);
2487 }
2488 }
2489 }
2490
sci_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)2491 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2492 const struct ktermios *old)
2493 {
2494 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2495 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2496 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2497 struct sci_port *s = to_sci_port(port);
2498 const struct plat_sci_reg *reg;
2499 int min_err = INT_MAX, err;
2500 unsigned long max_freq = 0;
2501 int best_clk = -1;
2502 unsigned long flags;
2503
2504 if ((termios->c_cflag & CSIZE) == CS7) {
2505 smr_val |= SCSMR_CHR;
2506 } else {
2507 termios->c_cflag &= ~CSIZE;
2508 termios->c_cflag |= CS8;
2509 }
2510 if (termios->c_cflag & PARENB)
2511 smr_val |= SCSMR_PE;
2512 if (termios->c_cflag & PARODD)
2513 smr_val |= SCSMR_PE | SCSMR_ODD;
2514 if (termios->c_cflag & CSTOPB)
2515 smr_val |= SCSMR_STOP;
2516
2517 /*
2518 * earlyprintk comes here early on with port->uartclk set to zero.
2519 * the clock framework is not up and running at this point so here
2520 * we assume that 115200 is the maximum baud rate. please note that
2521 * the baud rate is not programmed during earlyprintk - it is assumed
2522 * that the previous boot loader has enabled required clocks and
2523 * setup the baud rate generator hardware for us already.
2524 */
2525 if (!port->uartclk) {
2526 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2527 goto done;
2528 }
2529
2530 for (i = 0; i < SCI_NUM_CLKS; i++)
2531 max_freq = max(max_freq, s->clk_rates[i]);
2532
2533 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2534 if (!baud)
2535 goto done;
2536
2537 /*
2538 * There can be multiple sources for the sampling clock. Find the one
2539 * that gives us the smallest deviation from the desired baud rate.
2540 */
2541
2542 /* Optional Undivided External Clock */
2543 if (s->clk_rates[SCI_SCK] && s->type != PORT_SCIFA &&
2544 s->type != PORT_SCIFB) {
2545 err = sci_sck_calc(s, baud, &srr1);
2546 if (abs(err) < abs(min_err)) {
2547 best_clk = SCI_SCK;
2548 scr_val = SCSCR_CKE1;
2549 sccks = SCCKS_CKS;
2550 min_err = err;
2551 srr = srr1;
2552 if (!err)
2553 goto done;
2554 }
2555 }
2556
2557 /* Optional BRG Frequency Divided External Clock */
2558 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2559 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2560 &srr1);
2561 if (abs(err) < abs(min_err)) {
2562 best_clk = SCI_SCIF_CLK;
2563 scr_val = SCSCR_CKE1;
2564 sccks = 0;
2565 min_err = err;
2566 dl = dl1;
2567 srr = srr1;
2568 if (!err)
2569 goto done;
2570 }
2571 }
2572
2573 /* Optional BRG Frequency Divided Internal Clock */
2574 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2575 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2576 &srr1);
2577 if (abs(err) < abs(min_err)) {
2578 best_clk = SCI_BRG_INT;
2579 scr_val = SCSCR_CKE1;
2580 sccks = SCCKS_XIN;
2581 min_err = err;
2582 dl = dl1;
2583 srr = srr1;
2584 if (!min_err)
2585 goto done;
2586 }
2587 }
2588
2589 /* Divided Functional Clock using standard Bit Rate Register */
2590 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2591 if (abs(err) < abs(min_err)) {
2592 best_clk = SCI_FCK;
2593 scr_val = 0;
2594 min_err = err;
2595 brr = brr1;
2596 srr = srr1;
2597 cks = cks1;
2598 }
2599
2600 done:
2601 if (best_clk >= 0)
2602 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2603 s->clks[best_clk], baud, min_err);
2604
2605 sci_port_enable(s);
2606
2607 /*
2608 * Program the optional External Baud Rate Generator (BRG) first.
2609 * It controls the mux to select (H)SCK or frequency divided clock.
2610 */
2611 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2612 sci_serial_out(port, SCDL, dl);
2613 sci_serial_out(port, SCCKS, sccks);
2614 }
2615
2616 uart_port_lock_irqsave(port, &flags);
2617
2618 sci_reset(port);
2619
2620 uart_update_timeout(port, termios->c_cflag, baud);
2621
2622 /* byte size and parity */
2623 bits = tty_get_frame_size(termios->c_cflag);
2624
2625 if (sci_getreg(port, SEMR)->size)
2626 sci_serial_out(port, SEMR, 0);
2627
2628 if (best_clk >= 0) {
2629 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)
2630 switch (srr + 1) {
2631 case 5: smr_val |= SCSMR_SRC_5; break;
2632 case 7: smr_val |= SCSMR_SRC_7; break;
2633 case 11: smr_val |= SCSMR_SRC_11; break;
2634 case 13: smr_val |= SCSMR_SRC_13; break;
2635 case 16: smr_val |= SCSMR_SRC_16; break;
2636 case 17: smr_val |= SCSMR_SRC_17; break;
2637 case 19: smr_val |= SCSMR_SRC_19; break;
2638 case 27: smr_val |= SCSMR_SRC_27; break;
2639 }
2640 smr_val |= cks;
2641 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2642 sci_serial_out(port, SCSMR, smr_val);
2643 sci_serial_out(port, SCBRR, brr);
2644 if (sci_getreg(port, HSSRR)->size) {
2645 unsigned int hssrr = srr | HSCIF_SRE;
2646 /* Calculate deviation from intended rate at the
2647 * center of the last stop bit in sampling clocks.
2648 */
2649 int last_stop = bits * 2 - 1;
2650 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2651 (int)(srr + 1),
2652 2 * (int)baud);
2653
2654 if (abs(deviation) >= 2) {
2655 /* At least two sampling clocks off at the
2656 * last stop bit; we can increase the error
2657 * margin by shifting the sampling point.
2658 */
2659 int shift = clamp(deviation / 2, -8, 7);
2660
2661 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2662 HSCIF_SRHP_MASK;
2663 hssrr |= HSCIF_SRDE;
2664 }
2665 sci_serial_out(port, HSSRR, hssrr);
2666 }
2667
2668 /* Wait one bit interval */
2669 udelay((1000000 + (baud - 1)) / baud);
2670 } else {
2671 /* Don't touch the bit rate configuration */
2672 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2673 smr_val |= sci_serial_in(port, SCSMR) &
2674 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2675 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2676 sci_serial_out(port, SCSMR, smr_val);
2677 }
2678
2679 sci_init_pins(port, termios->c_cflag);
2680
2681 port->status &= ~UPSTAT_AUTOCTS;
2682 s->autorts = false;
2683 reg = sci_getreg(port, SCFCR);
2684 if (reg->size) {
2685 unsigned short ctrl = sci_serial_in(port, SCFCR);
2686
2687 if ((port->flags & UPF_HARD_FLOW) &&
2688 (termios->c_cflag & CRTSCTS)) {
2689 /* There is no CTS interrupt to restart the hardware */
2690 port->status |= UPSTAT_AUTOCTS;
2691 /* MCE is enabled when RTS is raised */
2692 s->autorts = true;
2693 }
2694
2695 /*
2696 * As we've done a sci_reset() above, ensure we don't
2697 * interfere with the FIFOs while toggling MCE. As the
2698 * reset values could still be set, simply mask them out.
2699 */
2700 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2701
2702 sci_serial_out(port, SCFCR, ctrl);
2703 }
2704 if (port->flags & UPF_HARD_FLOW) {
2705 /* Refresh (Auto) RTS */
2706 sci_set_mctrl(port, port->mctrl);
2707 }
2708
2709 /*
2710 * For SCI, TE (transmit enable) must be set after setting TIE
2711 * (transmit interrupt enable) or in the same instruction to
2712 * start the transmitting process. So skip setting TE here for SCI.
2713 */
2714 if (s->type != PORT_SCI)
2715 scr_val |= SCSCR_TE;
2716 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2717 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2718 if ((srr + 1 == 5) &&
2719 (s->type == PORT_SCIFA || s->type == PORT_SCIFB)) {
2720 /*
2721 * In asynchronous mode, when the sampling rate is 1/5, first
2722 * received data may become invalid on some SCIFA and SCIFB.
2723 * To avoid this problem wait more than 1 serial data time (1
2724 * bit time x serial data number) after setting SCSCR.RE = 1.
2725 */
2726 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2727 }
2728
2729 /* Calculate delay for 2 DMA buffers (4 FIFO). */
2730 s->rx_frame = (10000 * bits) / (baud / 100);
2731 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2732 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2733 #endif
2734
2735 if ((termios->c_cflag & CREAD) != 0)
2736 sci_start_rx(port);
2737
2738 uart_port_unlock_irqrestore(port, flags);
2739
2740 sci_port_disable(s);
2741
2742 if (UART_ENABLE_MS(port, termios->c_cflag))
2743 sci_enable_ms(port);
2744 }
2745
sci_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)2746 void sci_pm(struct uart_port *port, unsigned int state,
2747 unsigned int oldstate)
2748 {
2749 struct sci_port *sci_port = to_sci_port(port);
2750
2751 switch (state) {
2752 case UART_PM_STATE_OFF:
2753 sci_port_disable(sci_port);
2754 break;
2755 default:
2756 sci_port_enable(sci_port);
2757 break;
2758 }
2759 }
2760 EXPORT_SYMBOL_NS_GPL(sci_pm, "SH_SCI");
2761
sci_type(struct uart_port * port)2762 static const char *sci_type(struct uart_port *port)
2763 {
2764 struct sci_port *s = to_sci_port(port);
2765
2766 switch (s->type) {
2767 case PORT_IRDA:
2768 return "irda";
2769 case PORT_SCI:
2770 return "sci";
2771 case PORT_SCIF:
2772 return "scif";
2773 case PORT_SCIFA:
2774 return "scifa";
2775 case PORT_SCIFB:
2776 return "scifb";
2777 case PORT_HSCIF:
2778 return "hscif";
2779 }
2780
2781 return NULL;
2782 }
2783
sci_remap_port(struct uart_port * port)2784 static int sci_remap_port(struct uart_port *port)
2785 {
2786 struct sci_port *sport = to_sci_port(port);
2787
2788 /*
2789 * Nothing to do if there's already an established membase.
2790 */
2791 if (port->membase)
2792 return 0;
2793
2794 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2795 port->membase = ioremap(port->mapbase, sport->reg_size);
2796 if (unlikely(!port->membase)) {
2797 dev_err(port->dev, "can't remap port#%d\n", port->line);
2798 return -ENXIO;
2799 }
2800 } else {
2801 /*
2802 * For the simple (and majority of) cases where we don't
2803 * need to do any remapping, just cast the cookie
2804 * directly.
2805 */
2806 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2807 }
2808
2809 return 0;
2810 }
2811
sci_release_port(struct uart_port * port)2812 void sci_release_port(struct uart_port *port)
2813 {
2814 struct sci_port *sport = to_sci_port(port);
2815
2816 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2817 iounmap(port->membase);
2818 port->membase = NULL;
2819 }
2820
2821 release_mem_region(port->mapbase, sport->reg_size);
2822 }
2823 EXPORT_SYMBOL_NS_GPL(sci_release_port, "SH_SCI");
2824
sci_request_port(struct uart_port * port)2825 int sci_request_port(struct uart_port *port)
2826 {
2827 struct resource *res;
2828 struct sci_port *sport = to_sci_port(port);
2829 int ret;
2830
2831 res = request_mem_region(port->mapbase, sport->reg_size,
2832 dev_name(port->dev));
2833 if (unlikely(res == NULL)) {
2834 dev_err(port->dev, "request_mem_region failed.");
2835 return -EBUSY;
2836 }
2837
2838 ret = sci_remap_port(port);
2839 if (unlikely(ret != 0)) {
2840 release_resource(res);
2841 return ret;
2842 }
2843
2844 return 0;
2845 }
2846 EXPORT_SYMBOL_NS_GPL(sci_request_port, "SH_SCI");
2847
sci_config_port(struct uart_port * port,int flags)2848 void sci_config_port(struct uart_port *port, int flags)
2849 {
2850 if (flags & UART_CONFIG_TYPE) {
2851 struct sci_port *sport = to_sci_port(port);
2852 port->type = SCI_PUBLIC_PORT_ID(sport->type);
2853 sci_request_port(port);
2854 }
2855 }
2856 EXPORT_SYMBOL_NS_GPL(sci_config_port, "SH_SCI");
2857
sci_verify_port(struct uart_port * port,struct serial_struct * ser)2858 int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2859 {
2860 if (ser->baud_base < 2400)
2861 /* No paper tape reader for Mitch.. */
2862 return -EINVAL;
2863
2864 return 0;
2865 }
2866 EXPORT_SYMBOL_NS_GPL(sci_verify_port, "SH_SCI");
2867
sci_prepare_console_write(struct uart_port * port,u32 ctrl)2868 static void sci_prepare_console_write(struct uart_port *port, u32 ctrl)
2869 {
2870 struct sci_port *s = to_sci_port(port);
2871 u32 ctrl_temp =
2872 s->params->param_bits->rxtx_enable |
2873 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2874 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)) |
2875 s->hscif_tot;
2876 sci_serial_out(port, SCSCR, ctrl_temp);
2877 }
2878
sci_console_save(struct uart_port * port)2879 static void sci_console_save(struct uart_port *port)
2880 {
2881 struct sci_port *s = to_sci_port(port);
2882 struct sci_suspend_regs *regs = s->suspend_regs;
2883
2884 if (sci_getreg(port, SCDL)->size)
2885 regs->scdl = sci_serial_in(port, SCDL);
2886 if (sci_getreg(port, SCCKS)->size)
2887 regs->sccks = sci_serial_in(port, SCCKS);
2888 if (sci_getreg(port, SCSMR)->size)
2889 regs->scsmr = sci_serial_in(port, SCSMR);
2890 if (sci_getreg(port, SCSCR)->size)
2891 regs->scscr = sci_serial_in(port, SCSCR);
2892 if (sci_getreg(port, SCFCR)->size)
2893 regs->scfcr = sci_serial_in(port, SCFCR);
2894 if (sci_getreg(port, SCSPTR)->size)
2895 regs->scsptr = sci_serial_in(port, SCSPTR);
2896 if (sci_getreg(port, SCBRR)->size)
2897 regs->scbrr = sci_serial_in(port, SCBRR);
2898 if (sci_getreg(port, HSSRR)->size)
2899 regs->hssrr = sci_serial_in(port, HSSRR);
2900 if (sci_getreg(port, SCPCR)->size)
2901 regs->scpcr = sci_serial_in(port, SCPCR);
2902 if (sci_getreg(port, SCPDR)->size)
2903 regs->scpdr = sci_serial_in(port, SCPDR);
2904 if (sci_getreg(port, SEMR)->size)
2905 regs->semr = sci_serial_in(port, SEMR);
2906 }
2907
sci_console_restore(struct uart_port * port)2908 static void sci_console_restore(struct uart_port *port)
2909 {
2910 struct sci_port *s = to_sci_port(port);
2911 struct sci_suspend_regs *regs = s->suspend_regs;
2912
2913 if (sci_getreg(port, SCDL)->size)
2914 sci_serial_out(port, SCDL, regs->scdl);
2915 if (sci_getreg(port, SCCKS)->size)
2916 sci_serial_out(port, SCCKS, regs->sccks);
2917 if (sci_getreg(port, SCSMR)->size)
2918 sci_serial_out(port, SCSMR, regs->scsmr);
2919 if (sci_getreg(port, SCSCR)->size)
2920 sci_serial_out(port, SCSCR, regs->scscr);
2921 if (sci_getreg(port, SCFCR)->size)
2922 sci_serial_out(port, SCFCR, regs->scfcr);
2923 if (sci_getreg(port, SCSPTR)->size)
2924 sci_serial_out(port, SCSPTR, regs->scsptr);
2925 if (sci_getreg(port, SCBRR)->size)
2926 sci_serial_out(port, SCBRR, regs->scbrr);
2927 if (sci_getreg(port, HSSRR)->size)
2928 sci_serial_out(port, HSSRR, regs->hssrr);
2929 if (sci_getreg(port, SCPCR)->size)
2930 sci_serial_out(port, SCPCR, regs->scpcr);
2931 if (sci_getreg(port, SCPDR)->size)
2932 sci_serial_out(port, SCPDR, regs->scpdr);
2933 if (sci_getreg(port, SEMR)->size)
2934 sci_serial_out(port, SEMR, regs->semr);
2935 }
2936
2937 static const struct uart_ops sci_uart_ops = {
2938 .tx_empty = sci_tx_empty,
2939 .set_mctrl = sci_set_mctrl,
2940 .get_mctrl = sci_get_mctrl,
2941 .start_tx = sci_start_tx,
2942 .stop_tx = sci_stop_tx,
2943 .stop_rx = sci_stop_rx,
2944 .enable_ms = sci_enable_ms,
2945 .break_ctl = sci_break_ctl,
2946 .startup = sci_startup,
2947 .shutdown = sci_shutdown,
2948 .flush_buffer = sci_flush_buffer,
2949 .set_termios = sci_set_termios,
2950 .pm = sci_pm,
2951 .type = sci_type,
2952 .release_port = sci_release_port,
2953 .request_port = sci_request_port,
2954 .config_port = sci_config_port,
2955 .verify_port = sci_verify_port,
2956 #ifdef CONFIG_CONSOLE_POLL
2957 .poll_get_char = sci_poll_get_char,
2958 .poll_put_char = sci_poll_put_char,
2959 #endif
2960 };
2961
2962 static const struct sci_port_ops sci_port_ops = {
2963 .read_reg = sci_serial_in,
2964 .write_reg = sci_serial_out,
2965 .clear_SCxSR = sci_clear_SCxSR,
2966 .transmit_chars = sci_transmit_chars,
2967 .receive_chars = sci_receive_chars,
2968 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2969 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2970 .poll_put_char = sci_poll_put_char,
2971 #endif
2972 .set_rtrg = scif_set_rtrg,
2973 .rtrg_enabled = scif_rtrg_enabled,
2974 .shutdown_complete = sci_shutdown_complete,
2975 .prepare_console_write = sci_prepare_console_write,
2976 .console_save = sci_console_save,
2977 .console_restore = sci_console_restore,
2978 .suspend_regs_size = sci_suspend_regs_size,
2979 };
2980
sci_init_clocks(struct sci_port * sci_port,struct device * dev)2981 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2982 {
2983 const char *clk_names[] = {
2984 [SCI_FCK] = "fck",
2985 [SCI_SCK] = "sck",
2986 [SCI_BRG_INT] = "brg_int",
2987 [SCI_SCIF_CLK] = "scif_clk",
2988 };
2989 struct clk *clk;
2990 unsigned int i;
2991
2992 if (sci_port->type == PORT_HSCIF) {
2993 clk_names[SCI_SCK] = "hsck";
2994 } else if (sci_port->type == SCI_PORT_RSCI) {
2995 clk_names[SCI_FCK] = "operation";
2996 clk_names[SCI_BRG_INT] = "bus";
2997 }
2998
2999 for (i = 0; i < SCI_NUM_CLKS; i++) {
3000 const char *name = clk_names[i];
3001
3002 clk = devm_clk_get_optional(dev, name);
3003 if (IS_ERR(clk))
3004 return PTR_ERR(clk);
3005
3006 if (!clk && sci_port->type == SCI_PORT_RSCI &&
3007 (i == SCI_FCK || i == SCI_BRG_INT)) {
3008 return dev_err_probe(dev, -ENODEV,
3009 "failed to get %s\n",
3010 name);
3011 }
3012
3013 if (!clk && i == SCI_FCK) {
3014 /*
3015 * Not all SH platforms declare a clock lookup entry
3016 * for SCI devices, in which case we need to get the
3017 * global "peripheral_clk" clock.
3018 */
3019 clk = devm_clk_get(dev, "peripheral_clk");
3020 if (IS_ERR(clk))
3021 return dev_err_probe(dev, PTR_ERR(clk),
3022 "failed to get %s\n",
3023 name);
3024 }
3025
3026 if (!clk)
3027 dev_dbg(dev, "failed to get %s\n", name);
3028 else
3029 dev_dbg(dev, "clk %s is %pC rate %lu\n", name,
3030 clk, clk_get_rate(clk));
3031 sci_port->clks[i] = clk;
3032 }
3033 return 0;
3034 }
3035
3036 static const struct sci_port_params *
sci_probe_regmap(const struct plat_sci_port * cfg,struct sci_port * sci_port)3037 sci_probe_regmap(const struct plat_sci_port *cfg, struct sci_port *sci_port)
3038 {
3039 unsigned int regtype;
3040
3041 sci_port->ops = &sci_port_ops;
3042 sci_port->port.ops = &sci_uart_ops;
3043
3044 if (cfg->regtype != SCIx_PROBE_REGTYPE)
3045 return &sci_port_params[cfg->regtype];
3046
3047 switch (cfg->type) {
3048 case PORT_SCI:
3049 regtype = SCIx_SCI_REGTYPE;
3050 break;
3051 case PORT_IRDA:
3052 regtype = SCIx_IRDA_REGTYPE;
3053 break;
3054 case PORT_SCIFA:
3055 regtype = SCIx_SCIFA_REGTYPE;
3056 break;
3057 case PORT_SCIFB:
3058 regtype = SCIx_SCIFB_REGTYPE;
3059 break;
3060 case PORT_SCIF:
3061 /*
3062 * The SH-4 is a bit of a misnomer here, although that's
3063 * where this particular port layout originated. This
3064 * configuration (or some slight variation thereof)
3065 * remains the dominant model for all SCIFs.
3066 */
3067 regtype = SCIx_SH4_SCIF_REGTYPE;
3068 break;
3069 case PORT_HSCIF:
3070 regtype = SCIx_HSCIF_REGTYPE;
3071 break;
3072 default:
3073 pr_err("Can't probe register map for given port\n");
3074 return NULL;
3075 }
3076
3077 return &sci_port_params[regtype];
3078 }
3079
sci_init_single(struct platform_device * dev,struct sci_port * sci_port,unsigned int index,const struct plat_sci_port * p,bool early)3080 static int sci_init_single(struct platform_device *dev,
3081 struct sci_port *sci_port, unsigned int index,
3082 const struct plat_sci_port *p, bool early)
3083 {
3084 struct uart_port *port = &sci_port->port;
3085 const struct resource *res;
3086 unsigned int i;
3087 int ret;
3088
3089 sci_port->cfg = p;
3090
3091 sci_port->type = p->type;
3092 sci_port->regtype = p->regtype;
3093
3094 port->iotype = UPIO_MEM;
3095 port->line = index;
3096 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
3097
3098 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3099 if (res == NULL)
3100 return -ENOMEM;
3101
3102 port->mapbase = res->start;
3103 sci_port->reg_size = resource_size(res);
3104
3105 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
3106 if (i)
3107 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
3108 else
3109 sci_port->irqs[i] = platform_get_irq(dev, i);
3110 }
3111
3112 /*
3113 * The fourth interrupt on SCI and RSCI port is transmit end interrupt, so
3114 * shuffle the interrupts.
3115 */
3116 if (p->type == PORT_SCI || p->type == SCI_PORT_RSCI)
3117 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
3118
3119 /* The SCI generates several interrupts. They can be muxed together or
3120 * connected to different interrupt lines. In the muxed case only one
3121 * interrupt resource is specified as there is only one interrupt ID.
3122 * In the non-muxed case, up to 6 interrupt signals might be generated
3123 * from the SCI, however those signals might have their own individual
3124 * interrupt ID numbers, or muxed together with another interrupt.
3125 */
3126 if (sci_port->irqs[0] < 0)
3127 return -ENXIO;
3128
3129 if (sci_port->irqs[1] < 0)
3130 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
3131 sci_port->irqs[i] = sci_port->irqs[0];
3132
3133 switch (p->type) {
3134 case PORT_SCIFB:
3135 sci_port->rx_trigger = 48;
3136 break;
3137 case PORT_HSCIF:
3138 sci_port->rx_trigger = 64;
3139 break;
3140 case PORT_SCIFA:
3141 sci_port->rx_trigger = 32;
3142 break;
3143 case PORT_SCIF:
3144 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
3145 /* RX triggering not implemented for this IP */
3146 sci_port->rx_trigger = 1;
3147 else
3148 sci_port->rx_trigger = 8;
3149 break;
3150 case SCI_PORT_RSCI:
3151 sci_port->rx_trigger = 15;
3152 break;
3153 default:
3154 sci_port->rx_trigger = 1;
3155 break;
3156 }
3157
3158 sci_port->rx_fifo_timeout = 0;
3159 sci_port->hscif_tot = 0;
3160
3161 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
3162 * match the SoC datasheet, this should be investigated. Let platform
3163 * data override the sampling rate for now.
3164 */
3165 sci_port->sampling_rate_mask = p->sampling_rate
3166 ? SCI_SR(p->sampling_rate)
3167 : sci_port->params->sampling_rate_mask;
3168
3169 if (!early) {
3170 ret = sci_init_clocks(sci_port, &dev->dev);
3171 if (ret < 0)
3172 return ret;
3173 }
3174
3175 port->type = SCI_PUBLIC_PORT_ID(p->type);
3176 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
3177 port->fifosize = sci_port->params->fifosize;
3178
3179 if (p->type == PORT_SCI && !dev->dev.of_node) {
3180 if (sci_port->reg_size >= 0x20)
3181 port->regshift = 2;
3182 else
3183 port->regshift = 1;
3184 }
3185
3186 /*
3187 * The UART port needs an IRQ value, so we peg this to the RX IRQ
3188 * for the multi-IRQ ports, which is where we are primarily
3189 * concerned with the shutdown path synchronization.
3190 *
3191 * For the muxed case there's nothing more to do.
3192 */
3193 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
3194 port->irqflags = 0;
3195
3196 return 0;
3197 }
3198
3199 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
3200 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
serial_console_putchar(struct uart_port * port,unsigned char ch)3201 static void serial_console_putchar(struct uart_port *port, unsigned char ch)
3202 {
3203 to_sci_port(port)->ops->poll_put_char(port, ch);
3204 }
3205
3206 /*
3207 * Print a string to the serial port trying not to disturb
3208 * any possible real use of the port...
3209 */
serial_console_write(struct console * co,const char * s,unsigned count)3210 static void serial_console_write(struct console *co, const char *s,
3211 unsigned count)
3212 {
3213 struct sci_port *sci_port = &sci_ports[co->index];
3214 struct uart_port *port = &sci_port->port;
3215 const struct sci_common_regs *regs = sci_port->params->common_regs;
3216 unsigned int bits;
3217 u32 ctrl;
3218 unsigned long flags;
3219 int locked = 1;
3220
3221 if (port->sysrq)
3222 locked = 0;
3223 else if (oops_in_progress)
3224 locked = uart_port_trylock_irqsave(port, &flags);
3225 else
3226 uart_port_lock_irqsave(port, &flags);
3227
3228 /* first save SCSCR then disable interrupts, keep clock source */
3229
3230 ctrl = sci_port->ops->read_reg(port, regs->control);
3231 sci_port->ops->prepare_console_write(port, ctrl);
3232
3233 uart_console_write(port, s, count, serial_console_putchar);
3234
3235 /* wait until fifo is empty and last bit has been transmitted */
3236
3237 bits = sci_port->params->param_bits->poll_sent_bits;
3238
3239 while ((sci_port->ops->read_reg(port, regs->status) & bits) != bits)
3240 cpu_relax();
3241
3242 /* restore the SCSCR */
3243 sci_port->ops->write_reg(port, regs->control, ctrl);
3244
3245 if (locked)
3246 uart_port_unlock_irqrestore(port, flags);
3247 }
3248
serial_console_setup(struct console * co,char * options)3249 static int serial_console_setup(struct console *co, char *options)
3250 {
3251 struct sci_port *sci_port;
3252 struct uart_port *port;
3253 int baud = 115200;
3254 int bits = 8;
3255 int parity = 'n';
3256 int flow = 'n';
3257 int ret;
3258
3259 /*
3260 * Refuse to handle any bogus ports.
3261 */
3262 if (co->index < 0 || co->index >= SCI_NPORTS)
3263 return -ENODEV;
3264
3265 sci_port = &sci_ports[co->index];
3266 port = &sci_port->port;
3267
3268 /*
3269 * Refuse to handle uninitialized ports.
3270 */
3271 if (!port->ops)
3272 return -ENODEV;
3273
3274 ret = sci_remap_port(port);
3275 if (unlikely(ret != 0))
3276 return ret;
3277
3278 if (options)
3279 uart_parse_options(options, &baud, &parity, &bits, &flow);
3280
3281 return uart_set_options(port, co, baud, parity, bits, flow);
3282 }
3283
3284 static struct console serial_console = {
3285 .name = "ttySC",
3286 .device = uart_console_device,
3287 .write = serial_console_write,
3288 .setup = serial_console_setup,
3289 .flags = CON_PRINTBUFFER,
3290 .index = -1,
3291 .data = &sci_uart_driver,
3292 };
3293
3294 #ifdef CONFIG_SUPERH
3295 static char early_serial_buf[32];
3296
early_serial_console_setup(struct console * co,char * options)3297 static int early_serial_console_setup(struct console *co, char *options)
3298 {
3299 /*
3300 * This early console is always registered using the earlyprintk=
3301 * parameter, which does not call add_preferred_console(). Thus
3302 * @options is always NULL and the options for this early console
3303 * are passed using a custom buffer.
3304 */
3305 WARN_ON(options);
3306
3307 return serial_console_setup(co, early_serial_buf);
3308 }
3309
3310 static struct console early_serial_console = {
3311 .name = "early_ttySC",
3312 .write = serial_console_write,
3313 .setup = early_serial_console_setup,
3314 .flags = CON_PRINTBUFFER,
3315 .index = -1,
3316 };
3317
sci_probe_earlyprintk(struct platform_device * pdev)3318 static int sci_probe_earlyprintk(struct platform_device *pdev)
3319 {
3320 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3321 struct sci_port *sp = &sci_ports[pdev->id];
3322
3323 if (early_serial_console.data)
3324 return -EEXIST;
3325
3326 early_serial_console.index = pdev->id;
3327
3328 sp->params = sci_probe_regmap(cfg, sp);
3329 if (!sp->params)
3330 return -ENODEV;
3331
3332 sci_init_single(pdev, sp, pdev->id, cfg, true);
3333
3334 if (!strstr(early_serial_buf, "keep"))
3335 early_serial_console.flags |= CON_BOOT;
3336
3337 register_console(&early_serial_console);
3338 return 0;
3339 }
3340 #endif
3341
3342 #define SCI_CONSOLE (&serial_console)
3343
3344 #else
sci_probe_earlyprintk(struct platform_device * pdev)3345 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3346 {
3347 return -EINVAL;
3348 }
3349
3350 #define SCI_CONSOLE NULL
3351
3352 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3353
3354 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3355
3356 static DEFINE_MUTEX(sci_uart_registration_lock);
3357 static struct uart_driver sci_uart_driver = {
3358 .owner = THIS_MODULE,
3359 .driver_name = "sci",
3360 .dev_name = "ttySC",
3361 .major = SCI_MAJOR,
3362 .minor = SCI_MINOR_START,
3363 .nr = SCI_NPORTS,
3364 .cons = SCI_CONSOLE,
3365 };
3366
sci_remove(struct platform_device * dev)3367 static void sci_remove(struct platform_device *dev)
3368 {
3369 struct sci_port *s = platform_get_drvdata(dev);
3370 unsigned int type = s->type; /* uart_remove_... clears it */
3371
3372 sci_ports_in_use &= ~BIT(s->port.line);
3373 uart_remove_one_port(&sci_uart_driver, &s->port);
3374
3375 if (s->port.fifosize > 1)
3376 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3377 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF ||
3378 type == SCI_PORT_RSCI)
3379 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3380 }
3381
3382 static const struct sci_of_data of_sci_scif_sh2 = {
3383 .type = PORT_SCIF,
3384 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
3385 .ops = &sci_port_ops,
3386 .uart_ops = &sci_uart_ops,
3387 .params = &sci_port_params[SCIx_SH2_SCIF_FIFODATA_REGTYPE],
3388 };
3389
3390 static const struct sci_of_data of_sci_scif_rz_scifa = {
3391 .type = PORT_SCIF,
3392 .regtype = SCIx_RZ_SCIFA_REGTYPE,
3393 .ops = &sci_port_ops,
3394 .uart_ops = &sci_uart_ops,
3395 .params = &sci_port_params[SCIx_RZ_SCIFA_REGTYPE],
3396 };
3397
3398 static const struct sci_of_data of_sci_scif_rzv2h = {
3399 .type = PORT_SCIF,
3400 .regtype = SCIx_RZV2H_SCIF_REGTYPE,
3401 .ops = &sci_port_ops,
3402 .uart_ops = &sci_uart_ops,
3403 .params = &sci_port_params[SCIx_RZV2H_SCIF_REGTYPE],
3404 };
3405
3406 static const struct sci_of_data of_sci_rcar_scif = {
3407 .type = PORT_SCIF,
3408 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE,
3409 .ops = &sci_port_ops,
3410 .uart_ops = &sci_uart_ops,
3411 .params = &sci_port_params[SCIx_SH4_SCIF_BRG_REGTYPE],
3412 };
3413
3414 static const struct sci_of_data of_sci_scif_sh4 = {
3415 .type = PORT_SCIF,
3416 .regtype = SCIx_SH4_SCIF_REGTYPE,
3417 .ops = &sci_port_ops,
3418 .uart_ops = &sci_uart_ops,
3419 .params = &sci_port_params[SCIx_SH4_SCIF_REGTYPE],
3420 };
3421
3422 static const struct sci_of_data of_sci_scifa = {
3423 .type = PORT_SCIFA,
3424 .regtype = SCIx_SCIFA_REGTYPE,
3425 .ops = &sci_port_ops,
3426 .uart_ops = &sci_uart_ops,
3427 .params = &sci_port_params[SCIx_SCIFA_REGTYPE],
3428 };
3429
3430 static const struct sci_of_data of_sci_scifb = {
3431 .type = PORT_SCIFB,
3432 .regtype = SCIx_SCIFB_REGTYPE,
3433 .ops = &sci_port_ops,
3434 .uart_ops = &sci_uart_ops,
3435 .params = &sci_port_params[SCIx_SCIFB_REGTYPE],
3436 };
3437
3438 static const struct sci_of_data of_sci_hscif = {
3439 .type = PORT_HSCIF,
3440 .regtype = SCIx_HSCIF_REGTYPE,
3441 .ops = &sci_port_ops,
3442 .uart_ops = &sci_uart_ops,
3443 .params = &sci_port_params[SCIx_HSCIF_REGTYPE],
3444 };
3445
3446 static const struct sci_of_data of_sci_sci = {
3447 .type = PORT_SCI,
3448 .regtype = SCIx_SCI_REGTYPE,
3449 .ops = &sci_port_ops,
3450 .uart_ops = &sci_uart_ops,
3451 .params = &sci_port_params[SCIx_SCI_REGTYPE],
3452 };
3453
3454 static const struct of_device_id of_sci_match[] __maybe_unused = {
3455 /* SoC-specific types */
3456 {
3457 .compatible = "renesas,scif-r7s72100",
3458 .data = &of_sci_scif_sh2,
3459 },
3460 {
3461 .compatible = "renesas,scif-r7s9210",
3462 .data = &of_sci_scif_rz_scifa,
3463 },
3464 {
3465 .compatible = "renesas,scif-r9a07g044",
3466 .data = &of_sci_scif_rz_scifa,
3467 },
3468 {
3469 .compatible = "renesas,scif-r9a09g057",
3470 .data = &of_sci_scif_rzv2h,
3471 },
3472 #ifdef CONFIG_SERIAL_RSCI
3473 {
3474 .compatible = "renesas,r9a09g077-rsci",
3475 .data = &of_sci_rsci_data,
3476 },
3477 #endif /* CONFIG_SERIAL_RSCI */
3478 /* Family-specific types */
3479 {
3480 .compatible = "renesas,rcar-gen1-scif",
3481 .data = &of_sci_rcar_scif,
3482 }, {
3483 .compatible = "renesas,rcar-gen2-scif",
3484 .data = &of_sci_rcar_scif,
3485 }, {
3486 .compatible = "renesas,rcar-gen3-scif",
3487 .data = &of_sci_rcar_scif
3488 }, {
3489 .compatible = "renesas,rcar-gen4-scif",
3490 .data = &of_sci_rcar_scif
3491 }, {
3492 .compatible = "renesas,rcar-gen5-scif",
3493 .data = &of_sci_rcar_scif
3494 },
3495 /* Generic types */
3496 {
3497 .compatible = "renesas,scif",
3498 .data = &of_sci_scif_sh4,
3499 }, {
3500 .compatible = "renesas,scifa",
3501 .data = &of_sci_scifa,
3502 }, {
3503 .compatible = "renesas,scifb",
3504 .data = &of_sci_scifb,
3505 }, {
3506 .compatible = "renesas,hscif",
3507 .data = &of_sci_hscif,
3508 }, {
3509 .compatible = "renesas,sci",
3510 .data = &of_sci_sci,
3511 }, {
3512 /* Terminator */
3513 },
3514 };
3515 MODULE_DEVICE_TABLE(of, of_sci_match);
3516
sci_reset_control_assert(void * data)3517 static void sci_reset_control_assert(void *data)
3518 {
3519 reset_control_assert(data);
3520 }
3521
sci_parse_dt(struct platform_device * pdev,unsigned int * dev_id)3522 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3523 unsigned int *dev_id)
3524 {
3525 struct device_node *np = pdev->dev.of_node;
3526 struct reset_control *rstc;
3527 struct plat_sci_port *p;
3528 struct sci_port *sp;
3529 const struct sci_of_data *data;
3530 int id, ret;
3531
3532 if (!IS_ENABLED(CONFIG_OF) || !np)
3533 return ERR_PTR(-EINVAL);
3534
3535 data = of_device_get_match_data(&pdev->dev);
3536
3537 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
3538 if (IS_ERR(rstc))
3539 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc),
3540 "failed to get reset ctrl\n"));
3541
3542 ret = reset_control_deassert(rstc);
3543 if (ret) {
3544 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret);
3545 return ERR_PTR(ret);
3546 }
3547
3548 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc);
3549 if (ret) {
3550 dev_err(&pdev->dev, "failed to register assert devm action, %d\n",
3551 ret);
3552 return ERR_PTR(ret);
3553 }
3554
3555 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3556 if (!p)
3557 return ERR_PTR(-ENOMEM);
3558
3559 /* Get the line number from the aliases node. */
3560 id = of_alias_get_id(np, "serial");
3561 if (id < 0 && ~sci_ports_in_use)
3562 id = ffz(sci_ports_in_use);
3563 if (id < 0) {
3564 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3565 return ERR_PTR(-EINVAL);
3566 }
3567 if (id >= ARRAY_SIZE(sci_ports)) {
3568 dev_err(&pdev->dev, "serial%d out of range\n", id);
3569 return ERR_PTR(-EINVAL);
3570 }
3571
3572 sp = &sci_ports[id];
3573 sp->rstc = rstc;
3574 *dev_id = id;
3575
3576 p->type = data->type;
3577 p->regtype = data->regtype;
3578
3579 sp->ops = data->ops;
3580 sp->port.ops = data->uart_ops;
3581 sp->params = data->params;
3582
3583 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3584
3585 return p;
3586 }
3587
sci_probe_single(struct platform_device * dev,unsigned int index,struct plat_sci_port * p,struct sci_port * sciport,struct resource * sci_res)3588 static int sci_probe_single(struct platform_device *dev,
3589 unsigned int index,
3590 struct plat_sci_port *p,
3591 struct sci_port *sciport,
3592 struct resource *sci_res)
3593 {
3594 int ret;
3595
3596 /* Sanity check */
3597 if (unlikely(index >= SCI_NPORTS)) {
3598 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3599 index+1, SCI_NPORTS);
3600 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3601 return -EINVAL;
3602 }
3603 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3604 if (sci_ports_in_use & BIT(index))
3605 return -EBUSY;
3606
3607 mutex_lock(&sci_uart_registration_lock);
3608 if (!sci_uart_driver.state) {
3609 ret = uart_register_driver(&sci_uart_driver);
3610 if (ret) {
3611 mutex_unlock(&sci_uart_registration_lock);
3612 return ret;
3613 }
3614 }
3615 mutex_unlock(&sci_uart_registration_lock);
3616
3617 ret = sci_init_single(dev, sciport, index, p, false);
3618 if (ret)
3619 return ret;
3620
3621 sciport->port.dev = &dev->dev;
3622 ret = devm_pm_runtime_enable(&dev->dev);
3623 if (ret)
3624 return ret;
3625
3626 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3627 if (IS_ERR(sciport->gpios))
3628 return PTR_ERR(sciport->gpios);
3629
3630 if (sciport->has_rtscts) {
3631 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3632 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3633 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3634 return -EINVAL;
3635 }
3636 sciport->port.flags |= UPF_HARD_FLOW;
3637 }
3638
3639 if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) {
3640 /*
3641 * In case:
3642 * - this is the earlycon port (mapped on index 0 in sci_ports[]) and
3643 * - it now maps to an alias other than zero and
3644 * - the earlycon is still alive (e.g., "earlycon keep_bootcon" is
3645 * available in bootargs)
3646 *
3647 * we need to avoid disabling clocks and PM domains through the runtime
3648 * PM APIs called in __device_attach(). For this, increment the runtime
3649 * PM reference counter (the clocks and PM domains were already enabled
3650 * by the bootloader). Otherwise the earlycon may access the HW when it
3651 * has no clocks enabled leading to failures (infinite loop in
3652 * sci_poll_put_char()).
3653 */
3654 pm_runtime_get_noresume(&dev->dev);
3655
3656 /*
3657 * Skip cleanup the sci_port[0] in early_console_exit(), this
3658 * port is the same as the earlycon one.
3659 */
3660 sci_uart_earlycon_dev_probing = true;
3661 }
3662
3663 return uart_add_one_port(&sci_uart_driver, &sciport->port);
3664 }
3665
sci_probe(struct platform_device * dev)3666 static int sci_probe(struct platform_device *dev)
3667 {
3668 struct plat_sci_port *p;
3669 struct resource *res;
3670 struct sci_port *sp;
3671 unsigned int dev_id;
3672 int ret;
3673
3674 /*
3675 * If we've come here via earlyprintk initialization, head off to
3676 * the special early probe. We don't have sufficient device state
3677 * to make it beyond this yet.
3678 */
3679 #ifdef CONFIG_SUPERH
3680 if (is_sh_early_platform_device(dev))
3681 return sci_probe_earlyprintk(dev);
3682 #endif
3683
3684 if (dev->dev.of_node) {
3685 p = sci_parse_dt(dev, &dev_id);
3686 if (IS_ERR(p))
3687 return PTR_ERR(p);
3688 sp = &sci_ports[dev_id];
3689 } else {
3690 p = dev->dev.platform_data;
3691 if (p == NULL) {
3692 dev_err(&dev->dev, "no platform data supplied\n");
3693 return -EINVAL;
3694 }
3695
3696 dev_id = dev->id;
3697 sp = &sci_ports[dev_id];
3698 sp->params = sci_probe_regmap(p, sp);
3699 if (!sp->params)
3700 return -ENODEV;
3701 }
3702
3703 sp->suspend_regs = devm_kzalloc(&dev->dev,
3704 sp->ops->suspend_regs_size(),
3705 GFP_KERNEL);
3706 if (!sp->suspend_regs)
3707 return -ENOMEM;
3708
3709 /*
3710 * In case:
3711 * - the probed port alias is zero (as the one used by earlycon), and
3712 * - the earlycon is still active (e.g., "earlycon keep_bootcon" in
3713 * bootargs)
3714 *
3715 * defer the probe of this serial. This is a debug scenario and the user
3716 * must be aware of it.
3717 *
3718 * Except when the probed port is the same as the earlycon port.
3719 */
3720
3721 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3722 if (!res)
3723 return -ENODEV;
3724
3725 if (sci_uart_earlycon && sp == &sci_ports[0] && sp->port.mapbase != res->start)
3726 return dev_err_probe(&dev->dev, -EBUSY, "sci_port[0] is used by earlycon!\n");
3727
3728 platform_set_drvdata(dev, sp);
3729
3730 ret = sci_probe_single(dev, dev_id, p, sp, res);
3731 if (ret)
3732 return ret;
3733
3734 if (sp->port.fifosize > 1) {
3735 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3736 if (ret)
3737 return ret;
3738 }
3739 if (sp->type == PORT_SCIFA || sp->type == PORT_SCIFB ||
3740 sp->type == PORT_HSCIF || sp->type == SCI_PORT_RSCI) {
3741 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3742 if (ret) {
3743 if (sp->port.fifosize > 1) {
3744 device_remove_file(&dev->dev,
3745 &dev_attr_rx_fifo_trigger);
3746 }
3747 return ret;
3748 }
3749 }
3750
3751 #ifdef CONFIG_SH_STANDARD_BIOS
3752 sh_bios_gdb_detach();
3753 #endif
3754
3755 sci_ports_in_use |= BIT(dev_id);
3756 return 0;
3757 }
3758
sci_suspend(struct device * dev)3759 static int sci_suspend(struct device *dev)
3760 {
3761 struct sci_port *sport = dev_get_drvdata(dev);
3762
3763 if (sport) {
3764 uart_suspend_port(&sci_uart_driver, &sport->port);
3765
3766 if (!console_suspend_enabled && uart_console(&sport->port)) {
3767 if (sport->ops->console_save)
3768 sport->ops->console_save(&sport->port);
3769 }
3770 else
3771 return reset_control_assert(sport->rstc);
3772 }
3773
3774 return 0;
3775 }
3776
sci_resume(struct device * dev)3777 static int sci_resume(struct device *dev)
3778 {
3779 struct sci_port *sport = dev_get_drvdata(dev);
3780
3781 if (sport) {
3782 if (!console_suspend_enabled && uart_console(&sport->port)) {
3783 if (sport->ops->console_restore)
3784 sport->ops->console_restore(&sport->port);
3785 } else {
3786 int ret = reset_control_deassert(sport->rstc);
3787
3788 if (ret)
3789 return ret;
3790 }
3791
3792 uart_resume_port(&sci_uart_driver, &sport->port);
3793 }
3794
3795 return 0;
3796 }
3797
3798 static DEFINE_SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3799
3800 static struct platform_driver sci_driver = {
3801 .probe = sci_probe,
3802 .remove = sci_remove,
3803 .driver = {
3804 .name = "sh-sci",
3805 .pm = pm_sleep_ptr(&sci_dev_pm_ops),
3806 .of_match_table = of_match_ptr(of_sci_match),
3807 },
3808 };
3809
sci_init(void)3810 static int __init sci_init(void)
3811 {
3812 pr_info("%s\n", banner);
3813
3814 return platform_driver_register(&sci_driver);
3815 }
3816
sci_exit(void)3817 static void __exit sci_exit(void)
3818 {
3819 platform_driver_unregister(&sci_driver);
3820
3821 if (sci_uart_driver.state)
3822 uart_unregister_driver(&sci_uart_driver);
3823 }
3824
3825 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
3826 sh_early_platform_init_buffer("earlyprintk", &sci_driver,
3827 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3828 #endif
3829 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3830 static struct plat_sci_port port_cfg;
3831
early_console_exit(struct console * co)3832 static int early_console_exit(struct console *co)
3833 {
3834 struct sci_port *sci_port = &sci_ports[0];
3835
3836 /*
3837 * Clean the slot used by earlycon. A new SCI device might
3838 * map to this slot.
3839 */
3840 if (!sci_uart_earlycon_dev_probing) {
3841 memset(sci_port, 0, sizeof(*sci_port));
3842 sci_uart_earlycon = false;
3843 }
3844
3845 return 0;
3846 }
3847
scix_early_console_setup(struct earlycon_device * device,const struct sci_of_data * data)3848 int __init scix_early_console_setup(struct earlycon_device *device,
3849 const struct sci_of_data *data)
3850 {
3851 const struct sci_common_regs *regs;
3852
3853 if (!device->port.membase)
3854 return -ENODEV;
3855
3856 device->port.type = SCI_PUBLIC_PORT_ID(data->type);
3857
3858 sci_ports[0].port = device->port;
3859 sci_ports[0].type = data->type;
3860 sci_ports[0].regtype = data->regtype;
3861
3862 port_cfg.type = data->type;
3863 port_cfg.regtype = data->regtype;
3864
3865 sci_ports[0].cfg = &port_cfg;
3866 sci_ports[0].params = data->params;
3867 sci_ports[0].ops = data->ops;
3868 sci_ports[0].port.ops = data->uart_ops;
3869 sci_uart_earlycon = true;
3870 regs = sci_ports[0].params->common_regs;
3871
3872 port_cfg.scscr = sci_ports[0].ops->read_reg(&sci_ports[0].port, regs->control);
3873 sci_ports[0].ops->write_reg(&sci_ports[0].port,
3874 regs->control,
3875 sci_ports[0].params->param_bits->rxtx_enable | port_cfg.scscr);
3876
3877 device->con->write = serial_console_write;
3878 device->con->exit = early_console_exit;
3879
3880 return 0;
3881 }
sci_early_console_setup(struct earlycon_device * device,const char * opt)3882 static int __init sci_early_console_setup(struct earlycon_device *device,
3883 const char *opt)
3884 {
3885 return scix_early_console_setup(device, &of_sci_sci);
3886 }
scif_early_console_setup(struct earlycon_device * device,const char * opt)3887 static int __init scif_early_console_setup(struct earlycon_device *device,
3888 const char *opt)
3889 {
3890 return scix_early_console_setup(device, &of_sci_scif_sh4);
3891 }
rzscifa_early_console_setup(struct earlycon_device * device,const char * opt)3892 static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3893 const char *opt)
3894 {
3895 return scix_early_console_setup(device, &of_sci_scif_rz_scifa);
3896 }
3897
rzv2hscif_early_console_setup(struct earlycon_device * device,const char * opt)3898 static int __init rzv2hscif_early_console_setup(struct earlycon_device *device,
3899 const char *opt)
3900 {
3901 return scix_early_console_setup(device, &of_sci_scif_rzv2h);
3902 }
3903
scifa_early_console_setup(struct earlycon_device * device,const char * opt)3904 static int __init scifa_early_console_setup(struct earlycon_device *device,
3905 const char *opt)
3906 {
3907 return scix_early_console_setup(device, &of_sci_scifa);
3908 }
scifb_early_console_setup(struct earlycon_device * device,const char * opt)3909 static int __init scifb_early_console_setup(struct earlycon_device *device,
3910 const char *opt)
3911 {
3912 return scix_early_console_setup(device, &of_sci_scifb);
3913 }
hscif_early_console_setup(struct earlycon_device * device,const char * opt)3914 static int __init hscif_early_console_setup(struct earlycon_device *device,
3915 const char *opt)
3916 {
3917 return scix_early_console_setup(device, &of_sci_hscif);
3918 }
3919
3920 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3921 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3922 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3923 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
3924 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a09g057", rzv2hscif_early_console_setup);
3925 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3926 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3927 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3928 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3929
3930 module_init(sci_init);
3931 module_exit(sci_exit);
3932
3933 MODULE_LICENSE("GPL");
3934 MODULE_ALIAS("platform:sh-sci");
3935 MODULE_AUTHOR("Paul Mundt");
3936 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
3937