1 /* 2 * serial_tegra.c 3 * 4 * High-speed serial driver for NVIDIA Tegra SoCs 5 * 6 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: Laxman Dewangan <ldewangan@nvidia.com> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms and conditions of the GNU General Public License, 12 * version 2, as published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include <linux/clk.h> 24 #include <linux/debugfs.h> 25 #include <linux/delay.h> 26 #include <linux/dmaengine.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/dmapool.h> 29 #include <linux/err.h> 30 #include <linux/io.h> 31 #include <linux/irq.h> 32 #include <linux/module.h> 33 #include <linux/of.h> 34 #include <linux/of_device.h> 35 #include <linux/pagemap.h> 36 #include <linux/platform_device.h> 37 #include <linux/reset.h> 38 #include <linux/serial.h> 39 #include <linux/serial_8250.h> 40 #include <linux/serial_core.h> 41 #include <linux/serial_reg.h> 42 #include <linux/slab.h> 43 #include <linux/string.h> 44 #include <linux/termios.h> 45 #include <linux/tty.h> 46 #include <linux/tty_flip.h> 47 48 #define TEGRA_UART_TYPE "TEGRA_UART" 49 #define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE) 50 #define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3) 51 52 #define TEGRA_UART_RX_DMA_BUFFER_SIZE 4096 53 #define TEGRA_UART_LSR_TXFIFO_FULL 0x100 54 #define TEGRA_UART_IER_EORD 0x20 55 #define TEGRA_UART_MCR_RTS_EN 0x40 56 #define TEGRA_UART_MCR_CTS_EN 0x20 57 #define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \ 58 UART_LSR_PE | UART_LSR_FE) 59 #define TEGRA_UART_IRDA_CSR 0x08 60 #define TEGRA_UART_SIR_ENABLED 0x80 61 62 #define TEGRA_UART_TX_PIO 1 63 #define TEGRA_UART_TX_DMA 2 64 #define TEGRA_UART_MIN_DMA 16 65 #define TEGRA_UART_FIFO_SIZE 32 66 67 /* 68 * Tx fifo trigger level setting in tegra uart is in 69 * reverse way then conventional uart. 70 */ 71 #define TEGRA_UART_TX_TRIG_16B 0x00 72 #define TEGRA_UART_TX_TRIG_8B 0x10 73 #define TEGRA_UART_TX_TRIG_4B 0x20 74 #define TEGRA_UART_TX_TRIG_1B 0x30 75 76 #define TEGRA_UART_MAXIMUM 5 77 78 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */ 79 #define TEGRA_UART_DEFAULT_BAUD 115200 80 #define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8 81 82 /* Tx transfer mode */ 83 #define TEGRA_TX_PIO 1 84 #define TEGRA_TX_DMA 2 85 86 /** 87 * tegra_uart_chip_data: SOC specific data. 88 * 89 * @tx_fifo_full_status: Status flag available for checking tx fifo full. 90 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not. 91 * Tegra30 does not allow this. 92 * @support_clk_src_div: Clock source support the clock divider. 93 */ 94 struct tegra_uart_chip_data { 95 bool tx_fifo_full_status; 96 bool allow_txfifo_reset_fifo_mode; 97 bool support_clk_src_div; 98 }; 99 100 struct tegra_uart_port { 101 struct uart_port uport; 102 const struct tegra_uart_chip_data *cdata; 103 104 struct clk *uart_clk; 105 struct reset_control *rst; 106 unsigned int current_baud; 107 108 /* Register shadow */ 109 unsigned long fcr_shadow; 110 unsigned long mcr_shadow; 111 unsigned long lcr_shadow; 112 unsigned long ier_shadow; 113 bool rts_active; 114 115 int tx_in_progress; 116 unsigned int tx_bytes; 117 118 bool enable_modem_interrupt; 119 120 bool rx_timeout; 121 int rx_in_progress; 122 int symb_bit; 123 124 struct dma_chan *rx_dma_chan; 125 struct dma_chan *tx_dma_chan; 126 dma_addr_t rx_dma_buf_phys; 127 dma_addr_t tx_dma_buf_phys; 128 unsigned char *rx_dma_buf_virt; 129 unsigned char *tx_dma_buf_virt; 130 struct dma_async_tx_descriptor *tx_dma_desc; 131 struct dma_async_tx_descriptor *rx_dma_desc; 132 dma_cookie_t tx_cookie; 133 dma_cookie_t rx_cookie; 134 unsigned int tx_bytes_requested; 135 unsigned int rx_bytes_requested; 136 }; 137 138 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup); 139 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup); 140 141 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup, 142 unsigned long reg) 143 { 144 return readl(tup->uport.membase + (reg << tup->uport.regshift)); 145 } 146 147 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val, 148 unsigned long reg) 149 { 150 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); 151 } 152 153 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u) 154 { 155 return container_of(u, struct tegra_uart_port, uport); 156 } 157 158 static unsigned int tegra_uart_get_mctrl(struct uart_port *u) 159 { 160 struct tegra_uart_port *tup = to_tegra_uport(u); 161 162 /* 163 * RI - Ring detector is active 164 * CD/DCD/CAR - Carrier detect is always active. For some reason 165 * linux has different names for carrier detect. 166 * DSR - Data Set ready is active as the hardware doesn't support it. 167 * Don't know if the linux support this yet? 168 * CTS - Clear to send. Always set to active, as the hardware handles 169 * CTS automatically. 170 */ 171 if (tup->enable_modem_interrupt) 172 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS; 173 return TIOCM_CTS; 174 } 175 176 static void set_rts(struct tegra_uart_port *tup, bool active) 177 { 178 unsigned long mcr; 179 180 mcr = tup->mcr_shadow; 181 if (active) 182 mcr |= TEGRA_UART_MCR_RTS_EN; 183 else 184 mcr &= ~TEGRA_UART_MCR_RTS_EN; 185 if (mcr != tup->mcr_shadow) { 186 tegra_uart_write(tup, mcr, UART_MCR); 187 tup->mcr_shadow = mcr; 188 } 189 return; 190 } 191 192 static void set_dtr(struct tegra_uart_port *tup, bool active) 193 { 194 unsigned long mcr; 195 196 mcr = tup->mcr_shadow; 197 if (active) 198 mcr |= UART_MCR_DTR; 199 else 200 mcr &= ~UART_MCR_DTR; 201 if (mcr != tup->mcr_shadow) { 202 tegra_uart_write(tup, mcr, UART_MCR); 203 tup->mcr_shadow = mcr; 204 } 205 return; 206 } 207 208 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl) 209 { 210 struct tegra_uart_port *tup = to_tegra_uport(u); 211 unsigned long mcr; 212 int dtr_enable; 213 214 mcr = tup->mcr_shadow; 215 tup->rts_active = !!(mctrl & TIOCM_RTS); 216 set_rts(tup, tup->rts_active); 217 218 dtr_enable = !!(mctrl & TIOCM_DTR); 219 set_dtr(tup, dtr_enable); 220 return; 221 } 222 223 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl) 224 { 225 struct tegra_uart_port *tup = to_tegra_uport(u); 226 unsigned long lcr; 227 228 lcr = tup->lcr_shadow; 229 if (break_ctl) 230 lcr |= UART_LCR_SBC; 231 else 232 lcr &= ~UART_LCR_SBC; 233 tegra_uart_write(tup, lcr, UART_LCR); 234 tup->lcr_shadow = lcr; 235 } 236 237 /** 238 * tegra_uart_wait_cycle_time: Wait for N UART clock periods 239 * 240 * @tup: Tegra serial port data structure. 241 * @cycles: Number of clock periods to wait. 242 * 243 * Tegra UARTs are clocked at 16X the baud/bit rate and hence the UART 244 * clock speed is 16X the current baud rate. 245 */ 246 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup, 247 unsigned int cycles) 248 { 249 if (tup->current_baud) 250 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16)); 251 } 252 253 /* Wait for a symbol-time. */ 254 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup, 255 unsigned int syms) 256 { 257 if (tup->current_baud) 258 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000, 259 tup->current_baud)); 260 } 261 262 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) 263 { 264 unsigned long fcr = tup->fcr_shadow; 265 266 if (tup->cdata->allow_txfifo_reset_fifo_mode) { 267 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 268 tegra_uart_write(tup, fcr, UART_FCR); 269 } else { 270 fcr &= ~UART_FCR_ENABLE_FIFO; 271 tegra_uart_write(tup, fcr, UART_FCR); 272 udelay(60); 273 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 274 tegra_uart_write(tup, fcr, UART_FCR); 275 fcr |= UART_FCR_ENABLE_FIFO; 276 tegra_uart_write(tup, fcr, UART_FCR); 277 } 278 279 /* Dummy read to ensure the write is posted */ 280 tegra_uart_read(tup, UART_SCR); 281 282 /* 283 * For all tegra devices (up to t210), there is a hardware issue that 284 * requires software to wait for 32 UART clock periods for the flush 285 * to propagate, otherwise data could be lost. 286 */ 287 tegra_uart_wait_cycle_time(tup, 32); 288 } 289 290 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud) 291 { 292 unsigned long rate; 293 unsigned int divisor; 294 unsigned long lcr; 295 int ret; 296 297 if (tup->current_baud == baud) 298 return 0; 299 300 if (tup->cdata->support_clk_src_div) { 301 rate = baud * 16; 302 ret = clk_set_rate(tup->uart_clk, rate); 303 if (ret < 0) { 304 dev_err(tup->uport.dev, 305 "clk_set_rate() failed for rate %lu\n", rate); 306 return ret; 307 } 308 divisor = 1; 309 } else { 310 rate = clk_get_rate(tup->uart_clk); 311 divisor = DIV_ROUND_CLOSEST(rate, baud * 16); 312 } 313 314 lcr = tup->lcr_shadow; 315 lcr |= UART_LCR_DLAB; 316 tegra_uart_write(tup, lcr, UART_LCR); 317 318 tegra_uart_write(tup, divisor & 0xFF, UART_TX); 319 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER); 320 321 lcr &= ~UART_LCR_DLAB; 322 tegra_uart_write(tup, lcr, UART_LCR); 323 324 /* Dummy read to ensure the write is posted */ 325 tegra_uart_read(tup, UART_SCR); 326 327 tup->current_baud = baud; 328 329 /* wait two character intervals at new rate */ 330 tegra_uart_wait_sym_time(tup, 2); 331 return 0; 332 } 333 334 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup, 335 unsigned long lsr) 336 { 337 char flag = TTY_NORMAL; 338 339 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) { 340 if (lsr & UART_LSR_OE) { 341 /* Overrrun error */ 342 flag = TTY_OVERRUN; 343 tup->uport.icount.overrun++; 344 dev_err(tup->uport.dev, "Got overrun errors\n"); 345 } else if (lsr & UART_LSR_PE) { 346 /* Parity error */ 347 flag = TTY_PARITY; 348 tup->uport.icount.parity++; 349 dev_err(tup->uport.dev, "Got Parity errors\n"); 350 } else if (lsr & UART_LSR_FE) { 351 flag = TTY_FRAME; 352 tup->uport.icount.frame++; 353 dev_err(tup->uport.dev, "Got frame errors\n"); 354 } else if (lsr & UART_LSR_BI) { 355 dev_err(tup->uport.dev, "Got Break\n"); 356 tup->uport.icount.brk++; 357 /* If FIFO read error without any data, reset Rx FIFO */ 358 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE)) 359 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR); 360 } 361 } 362 return flag; 363 } 364 365 static int tegra_uart_request_port(struct uart_port *u) 366 { 367 return 0; 368 } 369 370 static void tegra_uart_release_port(struct uart_port *u) 371 { 372 /* Nothing to do here */ 373 } 374 375 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes) 376 { 377 struct circ_buf *xmit = &tup->uport.state->xmit; 378 int i; 379 380 for (i = 0; i < max_bytes; i++) { 381 BUG_ON(uart_circ_empty(xmit)); 382 if (tup->cdata->tx_fifo_full_status) { 383 unsigned long lsr = tegra_uart_read(tup, UART_LSR); 384 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL)) 385 break; 386 } 387 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX); 388 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 389 tup->uport.icount.tx++; 390 } 391 } 392 393 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup, 394 unsigned int bytes) 395 { 396 if (bytes > TEGRA_UART_MIN_DMA) 397 bytes = TEGRA_UART_MIN_DMA; 398 399 tup->tx_in_progress = TEGRA_UART_TX_PIO; 400 tup->tx_bytes = bytes; 401 tup->ier_shadow |= UART_IER_THRI; 402 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 403 } 404 405 static void tegra_uart_tx_dma_complete(void *args) 406 { 407 struct tegra_uart_port *tup = args; 408 struct circ_buf *xmit = &tup->uport.state->xmit; 409 struct dma_tx_state state; 410 unsigned long flags; 411 unsigned int count; 412 413 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); 414 count = tup->tx_bytes_requested - state.residue; 415 async_tx_ack(tup->tx_dma_desc); 416 spin_lock_irqsave(&tup->uport.lock, flags); 417 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 418 tup->tx_in_progress = 0; 419 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 420 uart_write_wakeup(&tup->uport); 421 tegra_uart_start_next_tx(tup); 422 spin_unlock_irqrestore(&tup->uport.lock, flags); 423 } 424 425 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup, 426 unsigned long count) 427 { 428 struct circ_buf *xmit = &tup->uport.state->xmit; 429 dma_addr_t tx_phys_addr; 430 431 dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys, 432 UART_XMIT_SIZE, DMA_TO_DEVICE); 433 434 tup->tx_bytes = count & ~(0xF); 435 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail; 436 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan, 437 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV, 438 DMA_PREP_INTERRUPT); 439 if (!tup->tx_dma_desc) { 440 dev_err(tup->uport.dev, "Not able to get desc for Tx\n"); 441 return -EIO; 442 } 443 444 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete; 445 tup->tx_dma_desc->callback_param = tup; 446 tup->tx_in_progress = TEGRA_UART_TX_DMA; 447 tup->tx_bytes_requested = tup->tx_bytes; 448 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc); 449 dma_async_issue_pending(tup->tx_dma_chan); 450 return 0; 451 } 452 453 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup) 454 { 455 unsigned long tail; 456 unsigned long count; 457 struct circ_buf *xmit = &tup->uport.state->xmit; 458 459 tail = (unsigned long)&xmit->buf[xmit->tail]; 460 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 461 if (!count) 462 return; 463 464 if (count < TEGRA_UART_MIN_DMA) 465 tegra_uart_start_pio_tx(tup, count); 466 else if (BYTES_TO_ALIGN(tail) > 0) 467 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail)); 468 else 469 tegra_uart_start_tx_dma(tup, count); 470 } 471 472 /* Called by serial core driver with u->lock taken. */ 473 static void tegra_uart_start_tx(struct uart_port *u) 474 { 475 struct tegra_uart_port *tup = to_tegra_uport(u); 476 struct circ_buf *xmit = &u->state->xmit; 477 478 if (!uart_circ_empty(xmit) && !tup->tx_in_progress) 479 tegra_uart_start_next_tx(tup); 480 } 481 482 static unsigned int tegra_uart_tx_empty(struct uart_port *u) 483 { 484 struct tegra_uart_port *tup = to_tegra_uport(u); 485 unsigned int ret = 0; 486 unsigned long flags; 487 488 spin_lock_irqsave(&u->lock, flags); 489 if (!tup->tx_in_progress) { 490 unsigned long lsr = tegra_uart_read(tup, UART_LSR); 491 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS) 492 ret = TIOCSER_TEMT; 493 } 494 spin_unlock_irqrestore(&u->lock, flags); 495 return ret; 496 } 497 498 static void tegra_uart_stop_tx(struct uart_port *u) 499 { 500 struct tegra_uart_port *tup = to_tegra_uport(u); 501 struct circ_buf *xmit = &tup->uport.state->xmit; 502 struct dma_tx_state state; 503 unsigned int count; 504 505 if (tup->tx_in_progress != TEGRA_UART_TX_DMA) 506 return; 507 508 dmaengine_terminate_all(tup->tx_dma_chan); 509 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); 510 count = tup->tx_bytes_requested - state.residue; 511 async_tx_ack(tup->tx_dma_desc); 512 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 513 tup->tx_in_progress = 0; 514 return; 515 } 516 517 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup) 518 { 519 struct circ_buf *xmit = &tup->uport.state->xmit; 520 521 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes); 522 tup->tx_in_progress = 0; 523 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 524 uart_write_wakeup(&tup->uport); 525 tegra_uart_start_next_tx(tup); 526 return; 527 } 528 529 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup, 530 struct tty_port *tty) 531 { 532 do { 533 char flag = TTY_NORMAL; 534 unsigned long lsr = 0; 535 unsigned char ch; 536 537 lsr = tegra_uart_read(tup, UART_LSR); 538 if (!(lsr & UART_LSR_DR)) 539 break; 540 541 flag = tegra_uart_decode_rx_error(tup, lsr); 542 ch = (unsigned char) tegra_uart_read(tup, UART_RX); 543 tup->uport.icount.rx++; 544 545 if (!uart_handle_sysrq_char(&tup->uport, ch) && tty) 546 tty_insert_flip_char(tty, ch, flag); 547 } while (1); 548 549 return; 550 } 551 552 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup, 553 struct tty_port *tty, 554 unsigned int count) 555 { 556 int copied; 557 558 /* If count is zero, then there is no data to be copied */ 559 if (!count) 560 return; 561 562 tup->uport.icount.rx += count; 563 if (!tty) { 564 dev_err(tup->uport.dev, "No tty port\n"); 565 return; 566 } 567 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys, 568 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE); 569 copied = tty_insert_flip_string(tty, 570 ((unsigned char *)(tup->rx_dma_buf_virt)), count); 571 if (copied != count) { 572 WARN_ON(1); 573 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n"); 574 } 575 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, 576 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE); 577 } 578 579 static void tegra_uart_rx_dma_complete(void *args) 580 { 581 struct tegra_uart_port *tup = args; 582 struct uart_port *u = &tup->uport; 583 unsigned int count = tup->rx_bytes_requested; 584 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); 585 struct tty_port *port = &u->state->port; 586 unsigned long flags; 587 struct dma_tx_state state; 588 enum dma_status status; 589 590 spin_lock_irqsave(&u->lock, flags); 591 592 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); 593 594 if (status == DMA_IN_PROGRESS) { 595 dev_dbg(tup->uport.dev, "RX DMA is in progress\n"); 596 goto done; 597 } 598 599 async_tx_ack(tup->rx_dma_desc); 600 601 /* Deactivate flow control to stop sender */ 602 if (tup->rts_active) 603 set_rts(tup, false); 604 605 /* If we are here, DMA is stopped */ 606 tegra_uart_copy_rx_to_tty(tup, port, count); 607 608 tegra_uart_handle_rx_pio(tup, port); 609 if (tty) { 610 spin_unlock_irqrestore(&u->lock, flags); 611 tty_flip_buffer_push(port); 612 spin_lock_irqsave(&u->lock, flags); 613 tty_kref_put(tty); 614 } 615 tegra_uart_start_rx_dma(tup); 616 617 /* Activate flow control to start transfer */ 618 if (tup->rts_active) 619 set_rts(tup, true); 620 621 done: 622 spin_unlock_irqrestore(&u->lock, flags); 623 } 624 625 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup, 626 unsigned long *flags) 627 { 628 struct dma_tx_state state; 629 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); 630 struct tty_port *port = &tup->uport.state->port; 631 struct uart_port *u = &tup->uport; 632 unsigned int count; 633 634 /* Deactivate flow control to stop sender */ 635 if (tup->rts_active) 636 set_rts(tup, false); 637 638 dmaengine_terminate_all(tup->rx_dma_chan); 639 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); 640 async_tx_ack(tup->rx_dma_desc); 641 count = tup->rx_bytes_requested - state.residue; 642 643 /* If we are here, DMA is stopped */ 644 tegra_uart_copy_rx_to_tty(tup, port, count); 645 646 tegra_uart_handle_rx_pio(tup, port); 647 if (tty) { 648 spin_unlock_irqrestore(&u->lock, *flags); 649 tty_flip_buffer_push(port); 650 spin_lock_irqsave(&u->lock, *flags); 651 tty_kref_put(tty); 652 } 653 tegra_uart_start_rx_dma(tup); 654 655 if (tup->rts_active) 656 set_rts(tup, true); 657 } 658 659 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup) 660 { 661 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE; 662 663 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan, 664 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM, 665 DMA_PREP_INTERRUPT); 666 if (!tup->rx_dma_desc) { 667 dev_err(tup->uport.dev, "Not able to get desc for Rx\n"); 668 return -EIO; 669 } 670 671 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete; 672 tup->rx_dma_desc->callback_param = tup; 673 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, 674 count, DMA_TO_DEVICE); 675 tup->rx_bytes_requested = count; 676 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc); 677 dma_async_issue_pending(tup->rx_dma_chan); 678 return 0; 679 } 680 681 static void tegra_uart_handle_modem_signal_change(struct uart_port *u) 682 { 683 struct tegra_uart_port *tup = to_tegra_uport(u); 684 unsigned long msr; 685 686 msr = tegra_uart_read(tup, UART_MSR); 687 if (!(msr & UART_MSR_ANY_DELTA)) 688 return; 689 690 if (msr & UART_MSR_TERI) 691 tup->uport.icount.rng++; 692 if (msr & UART_MSR_DDSR) 693 tup->uport.icount.dsr++; 694 /* We may only get DDCD when HW init and reset */ 695 if (msr & UART_MSR_DDCD) 696 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD); 697 /* Will start/stop_tx accordingly */ 698 if (msr & UART_MSR_DCTS) 699 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS); 700 return; 701 } 702 703 static irqreturn_t tegra_uart_isr(int irq, void *data) 704 { 705 struct tegra_uart_port *tup = data; 706 struct uart_port *u = &tup->uport; 707 unsigned long iir; 708 unsigned long ier; 709 bool is_rx_int = false; 710 unsigned long flags; 711 712 spin_lock_irqsave(&u->lock, flags); 713 while (1) { 714 iir = tegra_uart_read(tup, UART_IIR); 715 if (iir & UART_IIR_NO_INT) { 716 if (is_rx_int) { 717 tegra_uart_handle_rx_dma(tup, &flags); 718 if (tup->rx_in_progress) { 719 ier = tup->ier_shadow; 720 ier |= (UART_IER_RLSI | UART_IER_RTOIE | 721 TEGRA_UART_IER_EORD); 722 tup->ier_shadow = ier; 723 tegra_uart_write(tup, ier, UART_IER); 724 } 725 } 726 spin_unlock_irqrestore(&u->lock, flags); 727 return IRQ_HANDLED; 728 } 729 730 switch ((iir >> 1) & 0x7) { 731 case 0: /* Modem signal change interrupt */ 732 tegra_uart_handle_modem_signal_change(u); 733 break; 734 735 case 1: /* Transmit interrupt only triggered when using PIO */ 736 tup->ier_shadow &= ~UART_IER_THRI; 737 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 738 tegra_uart_handle_tx_pio(tup); 739 break; 740 741 case 4: /* End of data */ 742 case 6: /* Rx timeout */ 743 case 2: /* Receive */ 744 if (!is_rx_int) { 745 is_rx_int = true; 746 /* Disable Rx interrupts */ 747 ier = tup->ier_shadow; 748 ier |= UART_IER_RDI; 749 tegra_uart_write(tup, ier, UART_IER); 750 ier &= ~(UART_IER_RDI | UART_IER_RLSI | 751 UART_IER_RTOIE | TEGRA_UART_IER_EORD); 752 tup->ier_shadow = ier; 753 tegra_uart_write(tup, ier, UART_IER); 754 } 755 break; 756 757 case 3: /* Receive error */ 758 tegra_uart_decode_rx_error(tup, 759 tegra_uart_read(tup, UART_LSR)); 760 break; 761 762 case 5: /* break nothing to handle */ 763 case 7: /* break nothing to handle */ 764 break; 765 } 766 } 767 } 768 769 static void tegra_uart_stop_rx(struct uart_port *u) 770 { 771 struct tegra_uart_port *tup = to_tegra_uport(u); 772 struct tty_struct *tty; 773 struct tty_port *port = &u->state->port; 774 struct dma_tx_state state; 775 unsigned long ier; 776 int count; 777 778 if (tup->rts_active) 779 set_rts(tup, false); 780 781 if (!tup->rx_in_progress) 782 return; 783 784 tty = tty_port_tty_get(&tup->uport.state->port); 785 786 tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */ 787 788 ier = tup->ier_shadow; 789 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE | 790 TEGRA_UART_IER_EORD); 791 tup->ier_shadow = ier; 792 tegra_uart_write(tup, ier, UART_IER); 793 tup->rx_in_progress = 0; 794 if (tup->rx_dma_chan) { 795 dmaengine_terminate_all(tup->rx_dma_chan); 796 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); 797 async_tx_ack(tup->rx_dma_desc); 798 count = tup->rx_bytes_requested - state.residue; 799 tegra_uart_copy_rx_to_tty(tup, port, count); 800 tegra_uart_handle_rx_pio(tup, port); 801 } else { 802 tegra_uart_handle_rx_pio(tup, port); 803 } 804 if (tty) { 805 tty_flip_buffer_push(port); 806 tty_kref_put(tty); 807 } 808 return; 809 } 810 811 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup) 812 { 813 unsigned long flags; 814 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud); 815 unsigned long fifo_empty_time = tup->uport.fifosize * char_time; 816 unsigned long wait_time; 817 unsigned long lsr; 818 unsigned long msr; 819 unsigned long mcr; 820 821 /* Disable interrupts */ 822 tegra_uart_write(tup, 0, UART_IER); 823 824 lsr = tegra_uart_read(tup, UART_LSR); 825 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) { 826 msr = tegra_uart_read(tup, UART_MSR); 827 mcr = tegra_uart_read(tup, UART_MCR); 828 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS)) 829 dev_err(tup->uport.dev, 830 "Tx Fifo not empty, CTS disabled, waiting\n"); 831 832 /* Wait for Tx fifo to be empty */ 833 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) { 834 wait_time = min(fifo_empty_time, 100lu); 835 udelay(wait_time); 836 fifo_empty_time -= wait_time; 837 if (!fifo_empty_time) { 838 msr = tegra_uart_read(tup, UART_MSR); 839 mcr = tegra_uart_read(tup, UART_MCR); 840 if ((mcr & TEGRA_UART_MCR_CTS_EN) && 841 (msr & UART_MSR_CTS)) 842 dev_err(tup->uport.dev, 843 "Slave not ready\n"); 844 break; 845 } 846 lsr = tegra_uart_read(tup, UART_LSR); 847 } 848 } 849 850 spin_lock_irqsave(&tup->uport.lock, flags); 851 /* Reset the Rx and Tx FIFOs */ 852 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR); 853 tup->current_baud = 0; 854 spin_unlock_irqrestore(&tup->uport.lock, flags); 855 856 clk_disable_unprepare(tup->uart_clk); 857 } 858 859 static int tegra_uart_hw_init(struct tegra_uart_port *tup) 860 { 861 int ret; 862 863 tup->fcr_shadow = 0; 864 tup->mcr_shadow = 0; 865 tup->lcr_shadow = 0; 866 tup->ier_shadow = 0; 867 tup->current_baud = 0; 868 869 clk_prepare_enable(tup->uart_clk); 870 871 /* Reset the UART controller to clear all previous status.*/ 872 reset_control_assert(tup->rst); 873 udelay(10); 874 reset_control_deassert(tup->rst); 875 876 tup->rx_in_progress = 0; 877 tup->tx_in_progress = 0; 878 879 /* 880 * Set the trigger level 881 * 882 * For PIO mode: 883 * 884 * For receive, this will interrupt the CPU after that many number of 885 * bytes are received, for the remaining bytes the receive timeout 886 * interrupt is received. Rx high watermark is set to 4. 887 * 888 * For transmit, if the trasnmit interrupt is enabled, this will 889 * interrupt the CPU when the number of entries in the FIFO reaches the 890 * low watermark. Tx low watermark is set to 16 bytes. 891 * 892 * For DMA mode: 893 * 894 * Set the Tx trigger to 16. This should match the DMA burst size that 895 * programmed in the DMA registers. 896 */ 897 tup->fcr_shadow = UART_FCR_ENABLE_FIFO; 898 tup->fcr_shadow |= UART_FCR_R_TRIG_01; 899 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; 900 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); 901 902 /* Dummy read to ensure the write is posted */ 903 tegra_uart_read(tup, UART_SCR); 904 905 /* 906 * For all tegra devices (up to t210), there is a hardware issue that 907 * requires software to wait for 3 UART clock periods after enabling 908 * the TX fifo, otherwise data could be lost. 909 */ 910 tegra_uart_wait_cycle_time(tup, 3); 911 912 /* 913 * Initialize the UART with default configuration 914 * (115200, N, 8, 1) so that the receive DMA buffer may be 915 * enqueued 916 */ 917 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR; 918 tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD); 919 tup->fcr_shadow |= UART_FCR_DMA_SELECT; 920 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); 921 922 ret = tegra_uart_start_rx_dma(tup); 923 if (ret < 0) { 924 dev_err(tup->uport.dev, "Not able to start Rx DMA\n"); 925 return ret; 926 } 927 tup->rx_in_progress = 1; 928 929 /* 930 * Enable IE_RXS for the receive status interrupts like line errros. 931 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd. 932 * 933 * If using DMA mode, enable EORD instead of receive interrupt which 934 * will interrupt after the UART is done with the receive instead of 935 * the interrupt when the FIFO "threshold" is reached. 936 * 937 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when 938 * the DATA is sitting in the FIFO and couldn't be transferred to the 939 * DMA as the DMA size alignment(4 bytes) is not met. EORD will be 940 * triggered when there is a pause of the incomming data stream for 4 941 * characters long. 942 * 943 * For pauses in the data which is not aligned to 4 bytes, we get 944 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first 945 * then the EORD. 946 */ 947 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD; 948 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 949 return 0; 950 } 951 952 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup, 953 bool dma_to_memory) 954 { 955 if (dma_to_memory) { 956 dmaengine_terminate_all(tup->rx_dma_chan); 957 dma_release_channel(tup->rx_dma_chan); 958 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE, 959 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys); 960 tup->rx_dma_chan = NULL; 961 tup->rx_dma_buf_phys = 0; 962 tup->rx_dma_buf_virt = NULL; 963 } else { 964 dmaengine_terminate_all(tup->tx_dma_chan); 965 dma_release_channel(tup->tx_dma_chan); 966 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys, 967 UART_XMIT_SIZE, DMA_TO_DEVICE); 968 tup->tx_dma_chan = NULL; 969 tup->tx_dma_buf_phys = 0; 970 tup->tx_dma_buf_virt = NULL; 971 } 972 } 973 974 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup, 975 bool dma_to_memory) 976 { 977 struct dma_chan *dma_chan; 978 unsigned char *dma_buf; 979 dma_addr_t dma_phys; 980 int ret; 981 struct dma_slave_config dma_sconfig; 982 983 dma_chan = dma_request_slave_channel_reason(tup->uport.dev, 984 dma_to_memory ? "rx" : "tx"); 985 if (IS_ERR(dma_chan)) { 986 ret = PTR_ERR(dma_chan); 987 dev_err(tup->uport.dev, 988 "DMA channel alloc failed: %d\n", ret); 989 return ret; 990 } 991 992 if (dma_to_memory) { 993 dma_buf = dma_alloc_coherent(tup->uport.dev, 994 TEGRA_UART_RX_DMA_BUFFER_SIZE, 995 &dma_phys, GFP_KERNEL); 996 if (!dma_buf) { 997 dev_err(tup->uport.dev, 998 "Not able to allocate the dma buffer\n"); 999 dma_release_channel(dma_chan); 1000 return -ENOMEM; 1001 } 1002 dma_sconfig.src_addr = tup->uport.mapbase; 1003 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1004 dma_sconfig.src_maxburst = 4; 1005 tup->rx_dma_chan = dma_chan; 1006 tup->rx_dma_buf_virt = dma_buf; 1007 tup->rx_dma_buf_phys = dma_phys; 1008 } else { 1009 dma_phys = dma_map_single(tup->uport.dev, 1010 tup->uport.state->xmit.buf, UART_XMIT_SIZE, 1011 DMA_TO_DEVICE); 1012 if (dma_mapping_error(tup->uport.dev, dma_phys)) { 1013 dev_err(tup->uport.dev, "dma_map_single tx failed\n"); 1014 dma_release_channel(dma_chan); 1015 return -ENOMEM; 1016 } 1017 dma_buf = tup->uport.state->xmit.buf; 1018 dma_sconfig.dst_addr = tup->uport.mapbase; 1019 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1020 dma_sconfig.dst_maxburst = 16; 1021 tup->tx_dma_chan = dma_chan; 1022 tup->tx_dma_buf_virt = dma_buf; 1023 tup->tx_dma_buf_phys = dma_phys; 1024 } 1025 1026 ret = dmaengine_slave_config(dma_chan, &dma_sconfig); 1027 if (ret < 0) { 1028 dev_err(tup->uport.dev, 1029 "Dma slave config failed, err = %d\n", ret); 1030 tegra_uart_dma_channel_free(tup, dma_to_memory); 1031 return ret; 1032 } 1033 1034 return 0; 1035 } 1036 1037 static int tegra_uart_startup(struct uart_port *u) 1038 { 1039 struct tegra_uart_port *tup = to_tegra_uport(u); 1040 int ret; 1041 1042 ret = tegra_uart_dma_channel_allocate(tup, false); 1043 if (ret < 0) { 1044 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", ret); 1045 return ret; 1046 } 1047 1048 ret = tegra_uart_dma_channel_allocate(tup, true); 1049 if (ret < 0) { 1050 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", ret); 1051 goto fail_rx_dma; 1052 } 1053 1054 ret = tegra_uart_hw_init(tup); 1055 if (ret < 0) { 1056 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret); 1057 goto fail_hw_init; 1058 } 1059 1060 ret = request_irq(u->irq, tegra_uart_isr, 0, 1061 dev_name(u->dev), tup); 1062 if (ret < 0) { 1063 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq); 1064 goto fail_hw_init; 1065 } 1066 return 0; 1067 1068 fail_hw_init: 1069 tegra_uart_dma_channel_free(tup, true); 1070 fail_rx_dma: 1071 tegra_uart_dma_channel_free(tup, false); 1072 return ret; 1073 } 1074 1075 /* 1076 * Flush any TX data submitted for DMA and PIO. Called when the 1077 * TX circular buffer is reset. 1078 */ 1079 static void tegra_uart_flush_buffer(struct uart_port *u) 1080 { 1081 struct tegra_uart_port *tup = to_tegra_uport(u); 1082 1083 tup->tx_bytes = 0; 1084 if (tup->tx_dma_chan) 1085 dmaengine_terminate_all(tup->tx_dma_chan); 1086 return; 1087 } 1088 1089 static void tegra_uart_shutdown(struct uart_port *u) 1090 { 1091 struct tegra_uart_port *tup = to_tegra_uport(u); 1092 1093 tegra_uart_hw_deinit(tup); 1094 1095 tup->rx_in_progress = 0; 1096 tup->tx_in_progress = 0; 1097 1098 tegra_uart_dma_channel_free(tup, true); 1099 tegra_uart_dma_channel_free(tup, false); 1100 free_irq(u->irq, tup); 1101 } 1102 1103 static void tegra_uart_enable_ms(struct uart_port *u) 1104 { 1105 struct tegra_uart_port *tup = to_tegra_uport(u); 1106 1107 if (tup->enable_modem_interrupt) { 1108 tup->ier_shadow |= UART_IER_MSI; 1109 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 1110 } 1111 } 1112 1113 static void tegra_uart_set_termios(struct uart_port *u, 1114 struct ktermios *termios, struct ktermios *oldtermios) 1115 { 1116 struct tegra_uart_port *tup = to_tegra_uport(u); 1117 unsigned int baud; 1118 unsigned long flags; 1119 unsigned int lcr; 1120 int symb_bit = 1; 1121 struct clk *parent_clk = clk_get_parent(tup->uart_clk); 1122 unsigned long parent_clk_rate = clk_get_rate(parent_clk); 1123 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF; 1124 1125 max_divider *= 16; 1126 spin_lock_irqsave(&u->lock, flags); 1127 1128 /* Changing configuration, it is safe to stop any rx now */ 1129 if (tup->rts_active) 1130 set_rts(tup, false); 1131 1132 /* Clear all interrupts as configuration is going to be change */ 1133 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER); 1134 tegra_uart_read(tup, UART_IER); 1135 tegra_uart_write(tup, 0, UART_IER); 1136 tegra_uart_read(tup, UART_IER); 1137 1138 /* Parity */ 1139 lcr = tup->lcr_shadow; 1140 lcr &= ~UART_LCR_PARITY; 1141 1142 /* CMSPAR isn't supported by this driver */ 1143 termios->c_cflag &= ~CMSPAR; 1144 1145 if ((termios->c_cflag & PARENB) == PARENB) { 1146 symb_bit++; 1147 if (termios->c_cflag & PARODD) { 1148 lcr |= UART_LCR_PARITY; 1149 lcr &= ~UART_LCR_EPAR; 1150 lcr &= ~UART_LCR_SPAR; 1151 } else { 1152 lcr |= UART_LCR_PARITY; 1153 lcr |= UART_LCR_EPAR; 1154 lcr &= ~UART_LCR_SPAR; 1155 } 1156 } 1157 1158 lcr &= ~UART_LCR_WLEN8; 1159 switch (termios->c_cflag & CSIZE) { 1160 case CS5: 1161 lcr |= UART_LCR_WLEN5; 1162 symb_bit += 5; 1163 break; 1164 case CS6: 1165 lcr |= UART_LCR_WLEN6; 1166 symb_bit += 6; 1167 break; 1168 case CS7: 1169 lcr |= UART_LCR_WLEN7; 1170 symb_bit += 7; 1171 break; 1172 default: 1173 lcr |= UART_LCR_WLEN8; 1174 symb_bit += 8; 1175 break; 1176 } 1177 1178 /* Stop bits */ 1179 if (termios->c_cflag & CSTOPB) { 1180 lcr |= UART_LCR_STOP; 1181 symb_bit += 2; 1182 } else { 1183 lcr &= ~UART_LCR_STOP; 1184 symb_bit++; 1185 } 1186 1187 tegra_uart_write(tup, lcr, UART_LCR); 1188 tup->lcr_shadow = lcr; 1189 tup->symb_bit = symb_bit; 1190 1191 /* Baud rate. */ 1192 baud = uart_get_baud_rate(u, termios, oldtermios, 1193 parent_clk_rate/max_divider, 1194 parent_clk_rate/16); 1195 spin_unlock_irqrestore(&u->lock, flags); 1196 tegra_set_baudrate(tup, baud); 1197 if (tty_termios_baud_rate(termios)) 1198 tty_termios_encode_baud_rate(termios, baud, baud); 1199 spin_lock_irqsave(&u->lock, flags); 1200 1201 /* Flow control */ 1202 if (termios->c_cflag & CRTSCTS) { 1203 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN; 1204 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; 1205 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); 1206 /* if top layer has asked to set rts active then do so here */ 1207 if (tup->rts_active) 1208 set_rts(tup, true); 1209 } else { 1210 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN; 1211 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; 1212 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); 1213 } 1214 1215 /* update the port timeout based on new settings */ 1216 uart_update_timeout(u, termios->c_cflag, baud); 1217 1218 /* Make sure all write has completed */ 1219 tegra_uart_read(tup, UART_IER); 1220 1221 /* Reenable interrupt */ 1222 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 1223 tegra_uart_read(tup, UART_IER); 1224 1225 spin_unlock_irqrestore(&u->lock, flags); 1226 return; 1227 } 1228 1229 static const char *tegra_uart_type(struct uart_port *u) 1230 { 1231 return TEGRA_UART_TYPE; 1232 } 1233 1234 static struct uart_ops tegra_uart_ops = { 1235 .tx_empty = tegra_uart_tx_empty, 1236 .set_mctrl = tegra_uart_set_mctrl, 1237 .get_mctrl = tegra_uart_get_mctrl, 1238 .stop_tx = tegra_uart_stop_tx, 1239 .start_tx = tegra_uart_start_tx, 1240 .stop_rx = tegra_uart_stop_rx, 1241 .flush_buffer = tegra_uart_flush_buffer, 1242 .enable_ms = tegra_uart_enable_ms, 1243 .break_ctl = tegra_uart_break_ctl, 1244 .startup = tegra_uart_startup, 1245 .shutdown = tegra_uart_shutdown, 1246 .set_termios = tegra_uart_set_termios, 1247 .type = tegra_uart_type, 1248 .request_port = tegra_uart_request_port, 1249 .release_port = tegra_uart_release_port, 1250 }; 1251 1252 static struct uart_driver tegra_uart_driver = { 1253 .owner = THIS_MODULE, 1254 .driver_name = "tegra_hsuart", 1255 .dev_name = "ttyTHS", 1256 .cons = NULL, 1257 .nr = TEGRA_UART_MAXIMUM, 1258 }; 1259 1260 static int tegra_uart_parse_dt(struct platform_device *pdev, 1261 struct tegra_uart_port *tup) 1262 { 1263 struct device_node *np = pdev->dev.of_node; 1264 int port; 1265 1266 port = of_alias_get_id(np, "serial"); 1267 if (port < 0) { 1268 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port); 1269 return port; 1270 } 1271 tup->uport.line = port; 1272 1273 tup->enable_modem_interrupt = of_property_read_bool(np, 1274 "nvidia,enable-modem-interrupt"); 1275 return 0; 1276 } 1277 1278 static struct tegra_uart_chip_data tegra20_uart_chip_data = { 1279 .tx_fifo_full_status = false, 1280 .allow_txfifo_reset_fifo_mode = true, 1281 .support_clk_src_div = false, 1282 }; 1283 1284 static struct tegra_uart_chip_data tegra30_uart_chip_data = { 1285 .tx_fifo_full_status = true, 1286 .allow_txfifo_reset_fifo_mode = false, 1287 .support_clk_src_div = true, 1288 }; 1289 1290 static const struct of_device_id tegra_uart_of_match[] = { 1291 { 1292 .compatible = "nvidia,tegra30-hsuart", 1293 .data = &tegra30_uart_chip_data, 1294 }, { 1295 .compatible = "nvidia,tegra20-hsuart", 1296 .data = &tegra20_uart_chip_data, 1297 }, { 1298 }, 1299 }; 1300 MODULE_DEVICE_TABLE(of, tegra_uart_of_match); 1301 1302 static int tegra_uart_probe(struct platform_device *pdev) 1303 { 1304 struct tegra_uart_port *tup; 1305 struct uart_port *u; 1306 struct resource *resource; 1307 int ret; 1308 const struct tegra_uart_chip_data *cdata; 1309 const struct of_device_id *match; 1310 1311 match = of_match_device(tegra_uart_of_match, &pdev->dev); 1312 if (!match) { 1313 dev_err(&pdev->dev, "Error: No device match found\n"); 1314 return -ENODEV; 1315 } 1316 cdata = match->data; 1317 1318 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL); 1319 if (!tup) { 1320 dev_err(&pdev->dev, "Failed to allocate memory for tup\n"); 1321 return -ENOMEM; 1322 } 1323 1324 ret = tegra_uart_parse_dt(pdev, tup); 1325 if (ret < 0) 1326 return ret; 1327 1328 u = &tup->uport; 1329 u->dev = &pdev->dev; 1330 u->ops = &tegra_uart_ops; 1331 u->type = PORT_TEGRA; 1332 u->fifosize = 32; 1333 tup->cdata = cdata; 1334 1335 platform_set_drvdata(pdev, tup); 1336 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1337 if (!resource) { 1338 dev_err(&pdev->dev, "No IO memory resource\n"); 1339 return -ENODEV; 1340 } 1341 1342 u->mapbase = resource->start; 1343 u->membase = devm_ioremap_resource(&pdev->dev, resource); 1344 if (IS_ERR(u->membase)) 1345 return PTR_ERR(u->membase); 1346 1347 tup->uart_clk = devm_clk_get(&pdev->dev, NULL); 1348 if (IS_ERR(tup->uart_clk)) { 1349 dev_err(&pdev->dev, "Couldn't get the clock\n"); 1350 return PTR_ERR(tup->uart_clk); 1351 } 1352 1353 tup->rst = devm_reset_control_get(&pdev->dev, "serial"); 1354 if (IS_ERR(tup->rst)) { 1355 dev_err(&pdev->dev, "Couldn't get the reset\n"); 1356 return PTR_ERR(tup->rst); 1357 } 1358 1359 u->iotype = UPIO_MEM32; 1360 u->irq = platform_get_irq(pdev, 0); 1361 u->regshift = 2; 1362 ret = uart_add_one_port(&tegra_uart_driver, u); 1363 if (ret < 0) { 1364 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret); 1365 return ret; 1366 } 1367 return ret; 1368 } 1369 1370 static int tegra_uart_remove(struct platform_device *pdev) 1371 { 1372 struct tegra_uart_port *tup = platform_get_drvdata(pdev); 1373 struct uart_port *u = &tup->uport; 1374 1375 uart_remove_one_port(&tegra_uart_driver, u); 1376 return 0; 1377 } 1378 1379 #ifdef CONFIG_PM_SLEEP 1380 static int tegra_uart_suspend(struct device *dev) 1381 { 1382 struct tegra_uart_port *tup = dev_get_drvdata(dev); 1383 struct uart_port *u = &tup->uport; 1384 1385 return uart_suspend_port(&tegra_uart_driver, u); 1386 } 1387 1388 static int tegra_uart_resume(struct device *dev) 1389 { 1390 struct tegra_uart_port *tup = dev_get_drvdata(dev); 1391 struct uart_port *u = &tup->uport; 1392 1393 return uart_resume_port(&tegra_uart_driver, u); 1394 } 1395 #endif 1396 1397 static const struct dev_pm_ops tegra_uart_pm_ops = { 1398 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume) 1399 }; 1400 1401 static struct platform_driver tegra_uart_platform_driver = { 1402 .probe = tegra_uart_probe, 1403 .remove = tegra_uart_remove, 1404 .driver = { 1405 .name = "serial-tegra", 1406 .of_match_table = tegra_uart_of_match, 1407 .pm = &tegra_uart_pm_ops, 1408 }, 1409 }; 1410 1411 static int __init tegra_uart_init(void) 1412 { 1413 int ret; 1414 1415 ret = uart_register_driver(&tegra_uart_driver); 1416 if (ret < 0) { 1417 pr_err("Could not register %s driver\n", 1418 tegra_uart_driver.driver_name); 1419 return ret; 1420 } 1421 1422 ret = platform_driver_register(&tegra_uart_platform_driver); 1423 if (ret < 0) { 1424 pr_err("Uart platform driver register failed, e = %d\n", ret); 1425 uart_unregister_driver(&tegra_uart_driver); 1426 return ret; 1427 } 1428 return 0; 1429 } 1430 1431 static void __exit tegra_uart_exit(void) 1432 { 1433 pr_info("Unloading tegra uart driver\n"); 1434 platform_driver_unregister(&tegra_uart_platform_driver); 1435 uart_unregister_driver(&tegra_uart_driver); 1436 } 1437 1438 module_init(tegra_uart_init); 1439 module_exit(tegra_uart_exit); 1440 1441 MODULE_ALIAS("platform:serial-tegra"); 1442 MODULE_DESCRIPTION("High speed UART driver for tegra chipset"); 1443 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); 1444 MODULE_LICENSE("GPL v2"); 1445