1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * serial_tegra.c 4 * 5 * High-speed serial driver for NVIDIA Tegra SoCs 6 * 7 * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved. 8 * 9 * Author: Laxman Dewangan <ldewangan@nvidia.com> 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/debugfs.h> 14 #include <linux/delay.h> 15 #include <linux/dmaengine.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/dmapool.h> 18 #include <linux/err.h> 19 #include <linux/io.h> 20 #include <linux/irq.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/pagemap.h> 24 #include <linux/platform_device.h> 25 #include <linux/reset.h> 26 #include <linux/serial.h> 27 #include <linux/serial_8250.h> 28 #include <linux/serial_core.h> 29 #include <linux/serial_reg.h> 30 #include <linux/slab.h> 31 #include <linux/string.h> 32 #include <linux/termios.h> 33 #include <linux/tty.h> 34 #include <linux/tty_flip.h> 35 36 #define TEGRA_UART_TYPE "TEGRA_UART" 37 #define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE) 38 #define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3) 39 40 #define TEGRA_UART_RX_DMA_BUFFER_SIZE 4096 41 #define TEGRA_UART_LSR_TXFIFO_FULL 0x100 42 #define TEGRA_UART_IER_EORD 0x20 43 #define TEGRA_UART_MCR_RTS_EN 0x40 44 #define TEGRA_UART_MCR_CTS_EN 0x20 45 #define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \ 46 UART_LSR_PE | UART_LSR_FE) 47 #define TEGRA_UART_IRDA_CSR 0x08 48 #define TEGRA_UART_SIR_ENABLED 0x80 49 50 #define TEGRA_UART_TX_PIO 1 51 #define TEGRA_UART_TX_DMA 2 52 #define TEGRA_UART_MIN_DMA 16 53 #define TEGRA_UART_FIFO_SIZE 32 54 55 /* 56 * Tx fifo trigger level setting in tegra uart is in 57 * reverse way then conventional uart. 58 */ 59 #define TEGRA_UART_TX_TRIG_16B 0x00 60 #define TEGRA_UART_TX_TRIG_8B 0x10 61 #define TEGRA_UART_TX_TRIG_4B 0x20 62 #define TEGRA_UART_TX_TRIG_1B 0x30 63 64 #define TEGRA_UART_MAXIMUM 8 65 66 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */ 67 #define TEGRA_UART_DEFAULT_BAUD 115200 68 #define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8 69 70 /* Tx transfer mode */ 71 #define TEGRA_TX_PIO 1 72 #define TEGRA_TX_DMA 2 73 74 #define TEGRA_UART_FCR_IIR_FIFO_EN 0x40 75 76 /** 77 * struct tegra_uart_chip_data: SOC specific data. 78 * 79 * @tx_fifo_full_status: Status flag available for checking tx fifo full. 80 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not. 81 * Tegra30 does not allow this. 82 * @support_clk_src_div: Clock source support the clock divider. 83 * @fifo_mode_enable_status: Is FIFO mode enabled? 84 * @uart_max_port: Maximum number of UART ports 85 * @max_dma_burst_bytes: Maximum size of DMA bursts 86 * @error_tolerance_low_range: Lowest number in the error tolerance range 87 * @error_tolerance_high_range: Highest number in the error tolerance range 88 */ 89 struct tegra_uart_chip_data { 90 bool tx_fifo_full_status; 91 bool allow_txfifo_reset_fifo_mode; 92 bool support_clk_src_div; 93 bool fifo_mode_enable_status; 94 int uart_max_port; 95 int max_dma_burst_bytes; 96 int error_tolerance_low_range; 97 int error_tolerance_high_range; 98 }; 99 100 struct tegra_baud_tolerance { 101 u32 lower_range_baud; 102 u32 upper_range_baud; 103 s32 tolerance; 104 }; 105 106 struct tegra_uart_port { 107 struct uart_port uport; 108 const struct tegra_uart_chip_data *cdata; 109 110 struct clk *uart_clk; 111 struct reset_control *rst; 112 unsigned int current_baud; 113 114 /* Register shadow */ 115 unsigned long fcr_shadow; 116 unsigned long mcr_shadow; 117 unsigned long lcr_shadow; 118 unsigned long ier_shadow; 119 bool rts_active; 120 121 int tx_in_progress; 122 unsigned int tx_bytes; 123 124 bool enable_modem_interrupt; 125 126 bool rx_timeout; 127 int rx_in_progress; 128 int symb_bit; 129 130 struct dma_chan *rx_dma_chan; 131 struct dma_chan *tx_dma_chan; 132 dma_addr_t rx_dma_buf_phys; 133 dma_addr_t tx_dma_buf_phys; 134 unsigned char *rx_dma_buf_virt; 135 unsigned char *tx_dma_buf_virt; 136 struct dma_async_tx_descriptor *tx_dma_desc; 137 struct dma_async_tx_descriptor *rx_dma_desc; 138 dma_cookie_t tx_cookie; 139 dma_cookie_t rx_cookie; 140 unsigned int tx_bytes_requested; 141 unsigned int rx_bytes_requested; 142 struct tegra_baud_tolerance *baud_tolerance; 143 int n_adjustable_baud_rates; 144 int required_rate; 145 int configured_rate; 146 bool use_rx_pio; 147 bool use_tx_pio; 148 bool rx_dma_active; 149 }; 150 151 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup); 152 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup); 153 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup, 154 bool dma_to_memory); 155 156 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup, 157 unsigned long reg) 158 { 159 return readl(tup->uport.membase + (reg << tup->uport.regshift)); 160 } 161 162 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val, 163 unsigned long reg) 164 { 165 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); 166 } 167 168 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u) 169 { 170 return container_of(u, struct tegra_uart_port, uport); 171 } 172 173 static unsigned int tegra_uart_get_mctrl(struct uart_port *u) 174 { 175 struct tegra_uart_port *tup = to_tegra_uport(u); 176 177 /* 178 * RI - Ring detector is active 179 * CD/DCD/CAR - Carrier detect is always active. For some reason 180 * linux has different names for carrier detect. 181 * DSR - Data Set ready is active as the hardware doesn't support it. 182 * Don't know if the linux support this yet? 183 * CTS - Clear to send. Always set to active, as the hardware handles 184 * CTS automatically. 185 */ 186 if (tup->enable_modem_interrupt) 187 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS; 188 return TIOCM_CTS; 189 } 190 191 static void set_rts(struct tegra_uart_port *tup, bool active) 192 { 193 unsigned long mcr; 194 195 mcr = tup->mcr_shadow; 196 if (active) 197 mcr |= TEGRA_UART_MCR_RTS_EN; 198 else 199 mcr &= ~TEGRA_UART_MCR_RTS_EN; 200 if (mcr != tup->mcr_shadow) { 201 tegra_uart_write(tup, mcr, UART_MCR); 202 tup->mcr_shadow = mcr; 203 } 204 } 205 206 static void set_dtr(struct tegra_uart_port *tup, bool active) 207 { 208 unsigned long mcr; 209 210 mcr = tup->mcr_shadow; 211 if (active) 212 mcr |= UART_MCR_DTR; 213 else 214 mcr &= ~UART_MCR_DTR; 215 if (mcr != tup->mcr_shadow) { 216 tegra_uart_write(tup, mcr, UART_MCR); 217 tup->mcr_shadow = mcr; 218 } 219 } 220 221 static void set_loopbk(struct tegra_uart_port *tup, bool active) 222 { 223 unsigned long mcr = tup->mcr_shadow; 224 225 if (active) 226 mcr |= UART_MCR_LOOP; 227 else 228 mcr &= ~UART_MCR_LOOP; 229 230 if (mcr != tup->mcr_shadow) { 231 tegra_uart_write(tup, mcr, UART_MCR); 232 tup->mcr_shadow = mcr; 233 } 234 } 235 236 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl) 237 { 238 struct tegra_uart_port *tup = to_tegra_uport(u); 239 int enable; 240 241 tup->rts_active = !!(mctrl & TIOCM_RTS); 242 set_rts(tup, tup->rts_active); 243 244 enable = !!(mctrl & TIOCM_DTR); 245 set_dtr(tup, enable); 246 247 enable = !!(mctrl & TIOCM_LOOP); 248 set_loopbk(tup, enable); 249 } 250 251 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl) 252 { 253 struct tegra_uart_port *tup = to_tegra_uport(u); 254 unsigned long lcr; 255 256 lcr = tup->lcr_shadow; 257 if (break_ctl) 258 lcr |= UART_LCR_SBC; 259 else 260 lcr &= ~UART_LCR_SBC; 261 tegra_uart_write(tup, lcr, UART_LCR); 262 tup->lcr_shadow = lcr; 263 } 264 265 /** 266 * tegra_uart_wait_cycle_time: Wait for N UART clock periods 267 * 268 * @tup: Tegra serial port data structure. 269 * @cycles: Number of clock periods to wait. 270 * 271 * Tegra UARTs are clocked at 16X the baud/bit rate and hence the UART 272 * clock speed is 16X the current baud rate. 273 */ 274 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup, 275 unsigned int cycles) 276 { 277 if (tup->current_baud) 278 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16)); 279 } 280 281 /* Wait for a symbol-time. */ 282 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup, 283 unsigned int syms) 284 { 285 if (tup->current_baud) 286 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000, 287 tup->current_baud)); 288 } 289 290 static int tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port *tup) 291 { 292 unsigned long iir; 293 unsigned int tmout = 100; 294 295 do { 296 iir = tegra_uart_read(tup, UART_IIR); 297 if (iir & TEGRA_UART_FCR_IIR_FIFO_EN) 298 return 0; 299 udelay(1); 300 } while (--tmout); 301 302 return -ETIMEDOUT; 303 } 304 305 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) 306 { 307 unsigned long fcr = tup->fcr_shadow; 308 unsigned int lsr, tmout = 10000; 309 310 if (tup->rts_active) 311 set_rts(tup, false); 312 313 if (tup->cdata->allow_txfifo_reset_fifo_mode) { 314 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 315 tegra_uart_write(tup, fcr, UART_FCR); 316 } else { 317 fcr &= ~UART_FCR_ENABLE_FIFO; 318 tegra_uart_write(tup, fcr, UART_FCR); 319 udelay(60); 320 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 321 tegra_uart_write(tup, fcr, UART_FCR); 322 fcr |= UART_FCR_ENABLE_FIFO; 323 tegra_uart_write(tup, fcr, UART_FCR); 324 if (tup->cdata->fifo_mode_enable_status) 325 tegra_uart_wait_fifo_mode_enabled(tup); 326 } 327 328 /* Dummy read to ensure the write is posted */ 329 tegra_uart_read(tup, UART_SCR); 330 331 /* 332 * For all tegra devices (up to t210), there is a hardware issue that 333 * requires software to wait for 32 UART clock periods for the flush 334 * to propagate, otherwise data could be lost. 335 */ 336 tegra_uart_wait_cycle_time(tup, 32); 337 338 do { 339 lsr = tegra_uart_read(tup, UART_LSR); 340 if ((lsr & UART_LSR_TEMT) && !(lsr & UART_LSR_DR)) 341 break; 342 udelay(1); 343 } while (--tmout); 344 345 if (tup->rts_active) 346 set_rts(tup, true); 347 } 348 349 static long tegra_get_tolerance_rate(struct tegra_uart_port *tup, 350 unsigned int baud, long rate) 351 { 352 int i; 353 354 for (i = 0; i < tup->n_adjustable_baud_rates; ++i) { 355 if (baud >= tup->baud_tolerance[i].lower_range_baud && 356 baud <= tup->baud_tolerance[i].upper_range_baud) 357 return (rate + (rate * 358 tup->baud_tolerance[i].tolerance) / 10000); 359 } 360 361 return rate; 362 } 363 364 static int tegra_check_rate_in_range(struct tegra_uart_port *tup) 365 { 366 long diff; 367 368 diff = ((long)(tup->configured_rate - tup->required_rate) * 10000) 369 / tup->required_rate; 370 if (diff < (tup->cdata->error_tolerance_low_range * 100) || 371 diff > (tup->cdata->error_tolerance_high_range * 100)) { 372 dev_err(tup->uport.dev, 373 "configured baud rate is out of range by %ld", diff); 374 return -EIO; 375 } 376 377 return 0; 378 } 379 380 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud) 381 { 382 unsigned long rate; 383 unsigned int divisor; 384 unsigned long lcr; 385 unsigned long flags; 386 int ret; 387 388 if (tup->current_baud == baud) 389 return 0; 390 391 if (tup->cdata->support_clk_src_div) { 392 rate = baud * 16; 393 tup->required_rate = rate; 394 395 if (tup->n_adjustable_baud_rates) 396 rate = tegra_get_tolerance_rate(tup, baud, rate); 397 398 ret = clk_set_rate(tup->uart_clk, rate); 399 if (ret < 0) { 400 dev_err(tup->uport.dev, 401 "clk_set_rate() failed for rate %lu\n", rate); 402 return ret; 403 } 404 tup->configured_rate = clk_get_rate(tup->uart_clk); 405 divisor = 1; 406 ret = tegra_check_rate_in_range(tup); 407 if (ret < 0) 408 return ret; 409 } else { 410 rate = clk_get_rate(tup->uart_clk); 411 divisor = DIV_ROUND_CLOSEST(rate, baud * 16); 412 } 413 414 uart_port_lock_irqsave(&tup->uport, &flags); 415 lcr = tup->lcr_shadow; 416 lcr |= UART_LCR_DLAB; 417 tegra_uart_write(tup, lcr, UART_LCR); 418 419 tegra_uart_write(tup, divisor & 0xFF, UART_TX); 420 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER); 421 422 lcr &= ~UART_LCR_DLAB; 423 tegra_uart_write(tup, lcr, UART_LCR); 424 425 /* Dummy read to ensure the write is posted */ 426 tegra_uart_read(tup, UART_SCR); 427 uart_port_unlock_irqrestore(&tup->uport, flags); 428 429 tup->current_baud = baud; 430 431 /* wait two character intervals at new rate */ 432 tegra_uart_wait_sym_time(tup, 2); 433 return 0; 434 } 435 436 static u8 tegra_uart_decode_rx_error(struct tegra_uart_port *tup, 437 unsigned long lsr) 438 { 439 u8 flag = TTY_NORMAL; 440 441 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) { 442 if (lsr & UART_LSR_OE) { 443 /* Overrun error */ 444 flag = TTY_OVERRUN; 445 tup->uport.icount.overrun++; 446 dev_dbg(tup->uport.dev, "Got overrun errors\n"); 447 } else if (lsr & UART_LSR_PE) { 448 /* Parity error */ 449 flag = TTY_PARITY; 450 tup->uport.icount.parity++; 451 dev_dbg(tup->uport.dev, "Got Parity errors\n"); 452 } else if (lsr & UART_LSR_FE) { 453 flag = TTY_FRAME; 454 tup->uport.icount.frame++; 455 dev_dbg(tup->uport.dev, "Got frame errors\n"); 456 } else if (lsr & UART_LSR_BI) { 457 /* 458 * Break error 459 * If FIFO read error without any data, reset Rx FIFO 460 */ 461 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE)) 462 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR); 463 if (tup->uport.ignore_status_mask & UART_LSR_BI) 464 return TTY_BREAK; 465 flag = TTY_BREAK; 466 tup->uport.icount.brk++; 467 dev_dbg(tup->uport.dev, "Got Break\n"); 468 } 469 uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag); 470 } 471 472 return flag; 473 } 474 475 static int tegra_uart_request_port(struct uart_port *u) 476 { 477 return 0; 478 } 479 480 static void tegra_uart_release_port(struct uart_port *u) 481 { 482 /* Nothing to do here */ 483 } 484 485 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes) 486 { 487 struct circ_buf *xmit = &tup->uport.state->xmit; 488 int i; 489 490 for (i = 0; i < max_bytes; i++) { 491 BUG_ON(uart_circ_empty(xmit)); 492 if (tup->cdata->tx_fifo_full_status) { 493 unsigned long lsr = tegra_uart_read(tup, UART_LSR); 494 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL)) 495 break; 496 } 497 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX); 498 uart_xmit_advance(&tup->uport, 1); 499 } 500 } 501 502 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup, 503 unsigned int bytes) 504 { 505 if (bytes > TEGRA_UART_MIN_DMA) 506 bytes = TEGRA_UART_MIN_DMA; 507 508 tup->tx_in_progress = TEGRA_UART_TX_PIO; 509 tup->tx_bytes = bytes; 510 tup->ier_shadow |= UART_IER_THRI; 511 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 512 } 513 514 static void tegra_uart_tx_dma_complete(void *args) 515 { 516 struct tegra_uart_port *tup = args; 517 struct circ_buf *xmit = &tup->uport.state->xmit; 518 struct dma_tx_state state; 519 unsigned long flags; 520 unsigned int count; 521 522 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); 523 count = tup->tx_bytes_requested - state.residue; 524 async_tx_ack(tup->tx_dma_desc); 525 uart_port_lock_irqsave(&tup->uport, &flags); 526 uart_xmit_advance(&tup->uport, count); 527 tup->tx_in_progress = 0; 528 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 529 uart_write_wakeup(&tup->uport); 530 tegra_uart_start_next_tx(tup); 531 uart_port_unlock_irqrestore(&tup->uport, flags); 532 } 533 534 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup, 535 unsigned long count) 536 { 537 struct circ_buf *xmit = &tup->uport.state->xmit; 538 dma_addr_t tx_phys_addr; 539 540 tup->tx_bytes = count & ~(0xF); 541 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail; 542 543 dma_sync_single_for_device(tup->uport.dev, tx_phys_addr, 544 tup->tx_bytes, DMA_TO_DEVICE); 545 546 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan, 547 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV, 548 DMA_PREP_INTERRUPT); 549 if (!tup->tx_dma_desc) { 550 dev_err(tup->uport.dev, "Not able to get desc for Tx\n"); 551 return -EIO; 552 } 553 554 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete; 555 tup->tx_dma_desc->callback_param = tup; 556 tup->tx_in_progress = TEGRA_UART_TX_DMA; 557 tup->tx_bytes_requested = tup->tx_bytes; 558 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc); 559 dma_async_issue_pending(tup->tx_dma_chan); 560 return 0; 561 } 562 563 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup) 564 { 565 unsigned long tail; 566 unsigned long count; 567 struct circ_buf *xmit = &tup->uport.state->xmit; 568 569 if (!tup->current_baud) 570 return; 571 572 tail = (unsigned long)&xmit->buf[xmit->tail]; 573 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 574 if (!count) 575 return; 576 577 if (tup->use_tx_pio || count < TEGRA_UART_MIN_DMA) 578 tegra_uart_start_pio_tx(tup, count); 579 else if (BYTES_TO_ALIGN(tail) > 0) 580 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail)); 581 else 582 tegra_uart_start_tx_dma(tup, count); 583 } 584 585 /* Called by serial core driver with u->lock taken. */ 586 static void tegra_uart_start_tx(struct uart_port *u) 587 { 588 struct tegra_uart_port *tup = to_tegra_uport(u); 589 struct circ_buf *xmit = &u->state->xmit; 590 591 if (!uart_circ_empty(xmit) && !tup->tx_in_progress) 592 tegra_uart_start_next_tx(tup); 593 } 594 595 static unsigned int tegra_uart_tx_empty(struct uart_port *u) 596 { 597 struct tegra_uart_port *tup = to_tegra_uport(u); 598 unsigned int ret = 0; 599 unsigned long flags; 600 601 uart_port_lock_irqsave(u, &flags); 602 if (!tup->tx_in_progress) { 603 unsigned long lsr = tegra_uart_read(tup, UART_LSR); 604 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS) 605 ret = TIOCSER_TEMT; 606 } 607 uart_port_unlock_irqrestore(u, flags); 608 return ret; 609 } 610 611 static void tegra_uart_stop_tx(struct uart_port *u) 612 { 613 struct tegra_uart_port *tup = to_tegra_uport(u); 614 struct dma_tx_state state; 615 unsigned int count; 616 617 if (tup->tx_in_progress != TEGRA_UART_TX_DMA) 618 return; 619 620 dmaengine_pause(tup->tx_dma_chan); 621 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); 622 dmaengine_terminate_all(tup->tx_dma_chan); 623 count = tup->tx_bytes_requested - state.residue; 624 async_tx_ack(tup->tx_dma_desc); 625 uart_xmit_advance(&tup->uport, count); 626 tup->tx_in_progress = 0; 627 } 628 629 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup) 630 { 631 struct circ_buf *xmit = &tup->uport.state->xmit; 632 633 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes); 634 tup->tx_in_progress = 0; 635 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 636 uart_write_wakeup(&tup->uport); 637 tegra_uart_start_next_tx(tup); 638 } 639 640 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup, 641 struct tty_port *port) 642 { 643 do { 644 unsigned long lsr = 0; 645 u8 ch, flag = TTY_NORMAL; 646 647 lsr = tegra_uart_read(tup, UART_LSR); 648 if (!(lsr & UART_LSR_DR)) 649 break; 650 651 flag = tegra_uart_decode_rx_error(tup, lsr); 652 if (flag != TTY_NORMAL) 653 continue; 654 655 ch = (unsigned char) tegra_uart_read(tup, UART_RX); 656 tup->uport.icount.rx++; 657 658 if (uart_handle_sysrq_char(&tup->uport, ch)) 659 continue; 660 661 if (tup->uport.ignore_status_mask & UART_LSR_DR) 662 continue; 663 664 tty_insert_flip_char(port, ch, flag); 665 } while (1); 666 } 667 668 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup, 669 struct tty_port *port, 670 unsigned int count) 671 { 672 int copied; 673 674 /* If count is zero, then there is no data to be copied */ 675 if (!count) 676 return; 677 678 tup->uport.icount.rx += count; 679 680 if (tup->uport.ignore_status_mask & UART_LSR_DR) 681 return; 682 683 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys, 684 count, DMA_FROM_DEVICE); 685 copied = tty_insert_flip_string(port, 686 ((unsigned char *)(tup->rx_dma_buf_virt)), count); 687 if (copied != count) { 688 WARN_ON(1); 689 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n"); 690 } 691 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, 692 count, DMA_TO_DEVICE); 693 } 694 695 static void do_handle_rx_pio(struct tegra_uart_port *tup) 696 { 697 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); 698 struct tty_port *port = &tup->uport.state->port; 699 700 tegra_uart_handle_rx_pio(tup, port); 701 if (tty) { 702 tty_flip_buffer_push(port); 703 tty_kref_put(tty); 704 } 705 } 706 707 static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup, 708 unsigned int residue) 709 { 710 struct tty_port *port = &tup->uport.state->port; 711 unsigned int count; 712 713 async_tx_ack(tup->rx_dma_desc); 714 count = tup->rx_bytes_requested - residue; 715 716 /* If we are here, DMA is stopped */ 717 tegra_uart_copy_rx_to_tty(tup, port, count); 718 719 do_handle_rx_pio(tup); 720 } 721 722 static void tegra_uart_rx_dma_complete(void *args) 723 { 724 struct tegra_uart_port *tup = args; 725 struct uart_port *u = &tup->uport; 726 unsigned long flags; 727 struct dma_tx_state state; 728 enum dma_status status; 729 730 uart_port_lock_irqsave(u, &flags); 731 732 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); 733 734 if (status == DMA_IN_PROGRESS) { 735 dev_dbg(tup->uport.dev, "RX DMA is in progress\n"); 736 goto done; 737 } 738 739 /* Deactivate flow control to stop sender */ 740 if (tup->rts_active) 741 set_rts(tup, false); 742 743 tup->rx_dma_active = false; 744 tegra_uart_rx_buffer_push(tup, 0); 745 tegra_uart_start_rx_dma(tup); 746 747 /* Activate flow control to start transfer */ 748 if (tup->rts_active) 749 set_rts(tup, true); 750 751 done: 752 uart_port_unlock_irqrestore(u, flags); 753 } 754 755 static void tegra_uart_terminate_rx_dma(struct tegra_uart_port *tup) 756 { 757 struct dma_tx_state state; 758 759 if (!tup->rx_dma_active) { 760 do_handle_rx_pio(tup); 761 return; 762 } 763 764 dmaengine_pause(tup->rx_dma_chan); 765 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); 766 dmaengine_terminate_all(tup->rx_dma_chan); 767 768 tegra_uart_rx_buffer_push(tup, state.residue); 769 tup->rx_dma_active = false; 770 } 771 772 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup) 773 { 774 /* Deactivate flow control to stop sender */ 775 if (tup->rts_active) 776 set_rts(tup, false); 777 778 tegra_uart_terminate_rx_dma(tup); 779 780 if (tup->rts_active) 781 set_rts(tup, true); 782 } 783 784 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup) 785 { 786 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE; 787 788 if (tup->rx_dma_active) 789 return 0; 790 791 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan, 792 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM, 793 DMA_PREP_INTERRUPT); 794 if (!tup->rx_dma_desc) { 795 dev_err(tup->uport.dev, "Not able to get desc for Rx\n"); 796 return -EIO; 797 } 798 799 tup->rx_dma_active = true; 800 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete; 801 tup->rx_dma_desc->callback_param = tup; 802 tup->rx_bytes_requested = count; 803 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc); 804 dma_async_issue_pending(tup->rx_dma_chan); 805 return 0; 806 } 807 808 static void tegra_uart_handle_modem_signal_change(struct uart_port *u) 809 { 810 struct tegra_uart_port *tup = to_tegra_uport(u); 811 unsigned long msr; 812 813 msr = tegra_uart_read(tup, UART_MSR); 814 if (!(msr & UART_MSR_ANY_DELTA)) 815 return; 816 817 if (msr & UART_MSR_TERI) 818 tup->uport.icount.rng++; 819 if (msr & UART_MSR_DDSR) 820 tup->uport.icount.dsr++; 821 /* We may only get DDCD when HW init and reset */ 822 if (msr & UART_MSR_DDCD) 823 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD); 824 /* Will start/stop_tx accordingly */ 825 if (msr & UART_MSR_DCTS) 826 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS); 827 } 828 829 static irqreturn_t tegra_uart_isr(int irq, void *data) 830 { 831 struct tegra_uart_port *tup = data; 832 struct uart_port *u = &tup->uport; 833 unsigned long iir; 834 unsigned long ier; 835 bool is_rx_start = false; 836 bool is_rx_int = false; 837 unsigned long flags; 838 839 uart_port_lock_irqsave(u, &flags); 840 while (1) { 841 iir = tegra_uart_read(tup, UART_IIR); 842 if (iir & UART_IIR_NO_INT) { 843 if (!tup->use_rx_pio && is_rx_int) { 844 tegra_uart_handle_rx_dma(tup); 845 if (tup->rx_in_progress) { 846 ier = tup->ier_shadow; 847 ier |= (UART_IER_RLSI | UART_IER_RTOIE | 848 TEGRA_UART_IER_EORD | UART_IER_RDI); 849 tup->ier_shadow = ier; 850 tegra_uart_write(tup, ier, UART_IER); 851 } 852 } else if (is_rx_start) { 853 tegra_uart_start_rx_dma(tup); 854 } 855 uart_port_unlock_irqrestore(u, flags); 856 return IRQ_HANDLED; 857 } 858 859 switch ((iir >> 1) & 0x7) { 860 case 0: /* Modem signal change interrupt */ 861 tegra_uart_handle_modem_signal_change(u); 862 break; 863 864 case 1: /* Transmit interrupt only triggered when using PIO */ 865 tup->ier_shadow &= ~UART_IER_THRI; 866 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 867 tegra_uart_handle_tx_pio(tup); 868 break; 869 870 case 4: /* End of data */ 871 case 6: /* Rx timeout */ 872 if (!tup->use_rx_pio) { 873 is_rx_int = tup->rx_in_progress; 874 /* Disable Rx interrupts */ 875 ier = tup->ier_shadow; 876 ier &= ~(UART_IER_RDI | UART_IER_RLSI | 877 UART_IER_RTOIE | TEGRA_UART_IER_EORD); 878 tup->ier_shadow = ier; 879 tegra_uart_write(tup, ier, UART_IER); 880 break; 881 } 882 fallthrough; 883 case 2: /* Receive */ 884 if (!tup->use_rx_pio) { 885 is_rx_start = tup->rx_in_progress; 886 tup->ier_shadow &= ~UART_IER_RDI; 887 tegra_uart_write(tup, tup->ier_shadow, 888 UART_IER); 889 } else { 890 do_handle_rx_pio(tup); 891 } 892 break; 893 894 case 3: /* Receive error */ 895 tegra_uart_decode_rx_error(tup, 896 tegra_uart_read(tup, UART_LSR)); 897 break; 898 899 case 5: /* break nothing to handle */ 900 case 7: /* break nothing to handle */ 901 break; 902 } 903 } 904 } 905 906 static void tegra_uart_stop_rx(struct uart_port *u) 907 { 908 struct tegra_uart_port *tup = to_tegra_uport(u); 909 struct tty_port *port = &tup->uport.state->port; 910 unsigned long ier; 911 912 if (tup->rts_active) 913 set_rts(tup, false); 914 915 if (!tup->rx_in_progress) 916 return; 917 918 tegra_uart_wait_sym_time(tup, 1); /* wait one character interval */ 919 920 ier = tup->ier_shadow; 921 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE | 922 TEGRA_UART_IER_EORD); 923 tup->ier_shadow = ier; 924 tegra_uart_write(tup, ier, UART_IER); 925 tup->rx_in_progress = 0; 926 927 if (!tup->use_rx_pio) 928 tegra_uart_terminate_rx_dma(tup); 929 else 930 tegra_uart_handle_rx_pio(tup, port); 931 } 932 933 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup) 934 { 935 unsigned long flags; 936 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud); 937 unsigned long fifo_empty_time = tup->uport.fifosize * char_time; 938 unsigned long wait_time; 939 unsigned long lsr; 940 unsigned long msr; 941 unsigned long mcr; 942 943 /* Disable interrupts */ 944 tegra_uart_write(tup, 0, UART_IER); 945 946 lsr = tegra_uart_read(tup, UART_LSR); 947 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) { 948 msr = tegra_uart_read(tup, UART_MSR); 949 mcr = tegra_uart_read(tup, UART_MCR); 950 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS)) 951 dev_err(tup->uport.dev, 952 "Tx Fifo not empty, CTS disabled, waiting\n"); 953 954 /* Wait for Tx fifo to be empty */ 955 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) { 956 wait_time = min(fifo_empty_time, 100lu); 957 udelay(wait_time); 958 fifo_empty_time -= wait_time; 959 if (!fifo_empty_time) { 960 msr = tegra_uart_read(tup, UART_MSR); 961 mcr = tegra_uart_read(tup, UART_MCR); 962 if ((mcr & TEGRA_UART_MCR_CTS_EN) && 963 (msr & UART_MSR_CTS)) 964 dev_err(tup->uport.dev, 965 "Slave not ready\n"); 966 break; 967 } 968 lsr = tegra_uart_read(tup, UART_LSR); 969 } 970 } 971 972 uart_port_lock_irqsave(&tup->uport, &flags); 973 /* Reset the Rx and Tx FIFOs */ 974 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR); 975 tup->current_baud = 0; 976 uart_port_unlock_irqrestore(&tup->uport, flags); 977 978 tup->rx_in_progress = 0; 979 tup->tx_in_progress = 0; 980 981 if (!tup->use_rx_pio) 982 tegra_uart_dma_channel_free(tup, true); 983 if (!tup->use_tx_pio) 984 tegra_uart_dma_channel_free(tup, false); 985 986 clk_disable_unprepare(tup->uart_clk); 987 } 988 989 static int tegra_uart_hw_init(struct tegra_uart_port *tup) 990 { 991 int ret; 992 993 tup->fcr_shadow = 0; 994 tup->mcr_shadow = 0; 995 tup->lcr_shadow = 0; 996 tup->ier_shadow = 0; 997 tup->current_baud = 0; 998 999 ret = clk_prepare_enable(tup->uart_clk); 1000 if (ret) { 1001 dev_err(tup->uport.dev, "could not enable clk\n"); 1002 return ret; 1003 } 1004 1005 /* Reset the UART controller to clear all previous status.*/ 1006 reset_control_assert(tup->rst); 1007 udelay(10); 1008 reset_control_deassert(tup->rst); 1009 1010 tup->rx_in_progress = 0; 1011 tup->tx_in_progress = 0; 1012 1013 /* 1014 * Set the trigger level 1015 * 1016 * For PIO mode: 1017 * 1018 * For receive, this will interrupt the CPU after that many number of 1019 * bytes are received, for the remaining bytes the receive timeout 1020 * interrupt is received. Rx high watermark is set to 4. 1021 * 1022 * For transmit, if the trasnmit interrupt is enabled, this will 1023 * interrupt the CPU when the number of entries in the FIFO reaches the 1024 * low watermark. Tx low watermark is set to 16 bytes. 1025 * 1026 * For DMA mode: 1027 * 1028 * Set the Tx trigger to 16. This should match the DMA burst size that 1029 * programmed in the DMA registers. 1030 */ 1031 tup->fcr_shadow = UART_FCR_ENABLE_FIFO; 1032 1033 if (tup->use_rx_pio) { 1034 tup->fcr_shadow |= UART_FCR_R_TRIG_11; 1035 } else { 1036 if (tup->cdata->max_dma_burst_bytes == 8) 1037 tup->fcr_shadow |= UART_FCR_R_TRIG_10; 1038 else 1039 tup->fcr_shadow |= UART_FCR_R_TRIG_01; 1040 } 1041 1042 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; 1043 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); 1044 1045 /* Dummy read to ensure the write is posted */ 1046 tegra_uart_read(tup, UART_SCR); 1047 1048 if (tup->cdata->fifo_mode_enable_status) { 1049 ret = tegra_uart_wait_fifo_mode_enabled(tup); 1050 if (ret < 0) { 1051 clk_disable_unprepare(tup->uart_clk); 1052 dev_err(tup->uport.dev, 1053 "Failed to enable FIFO mode: %d\n", ret); 1054 return ret; 1055 } 1056 } else { 1057 /* 1058 * For all tegra devices (up to t210), there is a hardware 1059 * issue that requires software to wait for 3 UART clock 1060 * periods after enabling the TX fifo, otherwise data could 1061 * be lost. 1062 */ 1063 tegra_uart_wait_cycle_time(tup, 3); 1064 } 1065 1066 /* 1067 * Initialize the UART with default configuration 1068 * (115200, N, 8, 1) so that the receive DMA buffer may be 1069 * enqueued 1070 */ 1071 ret = tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD); 1072 if (ret < 0) { 1073 clk_disable_unprepare(tup->uart_clk); 1074 dev_err(tup->uport.dev, "Failed to set baud rate\n"); 1075 return ret; 1076 } 1077 if (!tup->use_rx_pio) { 1078 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR; 1079 tup->fcr_shadow |= UART_FCR_DMA_SELECT; 1080 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); 1081 } else { 1082 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); 1083 } 1084 tup->rx_in_progress = 1; 1085 1086 /* 1087 * Enable IE_RXS for the receive status interrupts like line errors. 1088 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd. 1089 * 1090 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when 1091 * the DATA is sitting in the FIFO and couldn't be transferred to the 1092 * DMA as the DMA size alignment (4 bytes) is not met. EORD will be 1093 * triggered when there is a pause of the incomming data stream for 4 1094 * characters long. 1095 * 1096 * For pauses in the data which is not aligned to 4 bytes, we get 1097 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first 1098 * then the EORD. 1099 */ 1100 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | UART_IER_RDI; 1101 1102 /* 1103 * If using DMA mode, enable EORD interrupt to notify about RX 1104 * completion. 1105 */ 1106 if (!tup->use_rx_pio) 1107 tup->ier_shadow |= TEGRA_UART_IER_EORD; 1108 1109 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 1110 return 0; 1111 } 1112 1113 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup, 1114 bool dma_to_memory) 1115 { 1116 if (dma_to_memory) { 1117 dmaengine_terminate_all(tup->rx_dma_chan); 1118 dma_release_channel(tup->rx_dma_chan); 1119 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE, 1120 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys); 1121 tup->rx_dma_chan = NULL; 1122 tup->rx_dma_buf_phys = 0; 1123 tup->rx_dma_buf_virt = NULL; 1124 } else { 1125 dmaengine_terminate_all(tup->tx_dma_chan); 1126 dma_release_channel(tup->tx_dma_chan); 1127 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys, 1128 UART_XMIT_SIZE, DMA_TO_DEVICE); 1129 tup->tx_dma_chan = NULL; 1130 tup->tx_dma_buf_phys = 0; 1131 tup->tx_dma_buf_virt = NULL; 1132 } 1133 } 1134 1135 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup, 1136 bool dma_to_memory) 1137 { 1138 struct dma_chan *dma_chan; 1139 unsigned char *dma_buf; 1140 dma_addr_t dma_phys; 1141 int ret; 1142 struct dma_slave_config dma_sconfig; 1143 1144 dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx"); 1145 if (IS_ERR(dma_chan)) { 1146 ret = PTR_ERR(dma_chan); 1147 dev_err(tup->uport.dev, 1148 "DMA channel alloc failed: %d\n", ret); 1149 return ret; 1150 } 1151 1152 if (dma_to_memory) { 1153 dma_buf = dma_alloc_coherent(tup->uport.dev, 1154 TEGRA_UART_RX_DMA_BUFFER_SIZE, 1155 &dma_phys, GFP_KERNEL); 1156 if (!dma_buf) { 1157 dev_err(tup->uport.dev, 1158 "Not able to allocate the dma buffer\n"); 1159 dma_release_channel(dma_chan); 1160 return -ENOMEM; 1161 } 1162 dma_sync_single_for_device(tup->uport.dev, dma_phys, 1163 TEGRA_UART_RX_DMA_BUFFER_SIZE, 1164 DMA_TO_DEVICE); 1165 dma_sconfig.src_addr = tup->uport.mapbase; 1166 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1167 dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes; 1168 tup->rx_dma_chan = dma_chan; 1169 tup->rx_dma_buf_virt = dma_buf; 1170 tup->rx_dma_buf_phys = dma_phys; 1171 } else { 1172 dma_phys = dma_map_single(tup->uport.dev, 1173 tup->uport.state->xmit.buf, UART_XMIT_SIZE, 1174 DMA_TO_DEVICE); 1175 if (dma_mapping_error(tup->uport.dev, dma_phys)) { 1176 dev_err(tup->uport.dev, "dma_map_single tx failed\n"); 1177 dma_release_channel(dma_chan); 1178 return -ENOMEM; 1179 } 1180 dma_buf = tup->uport.state->xmit.buf; 1181 dma_sconfig.dst_addr = tup->uport.mapbase; 1182 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1183 dma_sconfig.dst_maxburst = 16; 1184 tup->tx_dma_chan = dma_chan; 1185 tup->tx_dma_buf_virt = dma_buf; 1186 tup->tx_dma_buf_phys = dma_phys; 1187 } 1188 1189 ret = dmaengine_slave_config(dma_chan, &dma_sconfig); 1190 if (ret < 0) { 1191 dev_err(tup->uport.dev, 1192 "Dma slave config failed, err = %d\n", ret); 1193 tegra_uart_dma_channel_free(tup, dma_to_memory); 1194 return ret; 1195 } 1196 1197 return 0; 1198 } 1199 1200 static int tegra_uart_startup(struct uart_port *u) 1201 { 1202 struct tegra_uart_port *tup = to_tegra_uport(u); 1203 int ret; 1204 1205 if (!tup->use_tx_pio) { 1206 ret = tegra_uart_dma_channel_allocate(tup, false); 1207 if (ret < 0) { 1208 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", 1209 ret); 1210 return ret; 1211 } 1212 } 1213 1214 if (!tup->use_rx_pio) { 1215 ret = tegra_uart_dma_channel_allocate(tup, true); 1216 if (ret < 0) { 1217 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", 1218 ret); 1219 goto fail_rx_dma; 1220 } 1221 } 1222 1223 ret = tegra_uart_hw_init(tup); 1224 if (ret < 0) { 1225 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret); 1226 goto fail_hw_init; 1227 } 1228 1229 ret = request_irq(u->irq, tegra_uart_isr, 0, 1230 dev_name(u->dev), tup); 1231 if (ret < 0) { 1232 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq); 1233 goto fail_request_irq; 1234 } 1235 return 0; 1236 1237 fail_request_irq: 1238 /* tup->uart_clk is already enabled in tegra_uart_hw_init */ 1239 clk_disable_unprepare(tup->uart_clk); 1240 fail_hw_init: 1241 if (!tup->use_rx_pio) 1242 tegra_uart_dma_channel_free(tup, true); 1243 fail_rx_dma: 1244 if (!tup->use_tx_pio) 1245 tegra_uart_dma_channel_free(tup, false); 1246 return ret; 1247 } 1248 1249 /* 1250 * Flush any TX data submitted for DMA and PIO. Called when the 1251 * TX circular buffer is reset. 1252 */ 1253 static void tegra_uart_flush_buffer(struct uart_port *u) 1254 { 1255 struct tegra_uart_port *tup = to_tegra_uport(u); 1256 1257 tup->tx_bytes = 0; 1258 if (tup->tx_dma_chan) 1259 dmaengine_terminate_all(tup->tx_dma_chan); 1260 } 1261 1262 static void tegra_uart_shutdown(struct uart_port *u) 1263 { 1264 struct tegra_uart_port *tup = to_tegra_uport(u); 1265 1266 tegra_uart_hw_deinit(tup); 1267 free_irq(u->irq, tup); 1268 } 1269 1270 static void tegra_uart_enable_ms(struct uart_port *u) 1271 { 1272 struct tegra_uart_port *tup = to_tegra_uport(u); 1273 1274 if (tup->enable_modem_interrupt) { 1275 tup->ier_shadow |= UART_IER_MSI; 1276 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 1277 } 1278 } 1279 1280 static void tegra_uart_set_termios(struct uart_port *u, 1281 struct ktermios *termios, 1282 const struct ktermios *oldtermios) 1283 { 1284 struct tegra_uart_port *tup = to_tegra_uport(u); 1285 unsigned int baud; 1286 unsigned long flags; 1287 unsigned int lcr; 1288 unsigned char char_bits; 1289 struct clk *parent_clk = clk_get_parent(tup->uart_clk); 1290 unsigned long parent_clk_rate = clk_get_rate(parent_clk); 1291 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF; 1292 int ret; 1293 1294 max_divider *= 16; 1295 uart_port_lock_irqsave(u, &flags); 1296 1297 /* Changing configuration, it is safe to stop any rx now */ 1298 if (tup->rts_active) 1299 set_rts(tup, false); 1300 1301 /* Clear all interrupts as configuration is going to be changed */ 1302 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER); 1303 tegra_uart_read(tup, UART_IER); 1304 tegra_uart_write(tup, 0, UART_IER); 1305 tegra_uart_read(tup, UART_IER); 1306 1307 /* Parity */ 1308 lcr = tup->lcr_shadow; 1309 lcr &= ~UART_LCR_PARITY; 1310 1311 /* CMSPAR isn't supported by this driver */ 1312 termios->c_cflag &= ~CMSPAR; 1313 1314 if ((termios->c_cflag & PARENB) == PARENB) { 1315 if (termios->c_cflag & PARODD) { 1316 lcr |= UART_LCR_PARITY; 1317 lcr &= ~UART_LCR_EPAR; 1318 lcr &= ~UART_LCR_SPAR; 1319 } else { 1320 lcr |= UART_LCR_PARITY; 1321 lcr |= UART_LCR_EPAR; 1322 lcr &= ~UART_LCR_SPAR; 1323 } 1324 } 1325 1326 char_bits = tty_get_char_size(termios->c_cflag); 1327 lcr &= ~UART_LCR_WLEN8; 1328 lcr |= UART_LCR_WLEN(char_bits); 1329 1330 /* Stop bits */ 1331 if (termios->c_cflag & CSTOPB) 1332 lcr |= UART_LCR_STOP; 1333 else 1334 lcr &= ~UART_LCR_STOP; 1335 1336 tegra_uart_write(tup, lcr, UART_LCR); 1337 tup->lcr_shadow = lcr; 1338 tup->symb_bit = tty_get_frame_size(termios->c_cflag); 1339 1340 /* Baud rate. */ 1341 baud = uart_get_baud_rate(u, termios, oldtermios, 1342 parent_clk_rate/max_divider, 1343 parent_clk_rate/16); 1344 uart_port_unlock_irqrestore(u, flags); 1345 ret = tegra_set_baudrate(tup, baud); 1346 if (ret < 0) { 1347 dev_err(tup->uport.dev, "Failed to set baud rate\n"); 1348 return; 1349 } 1350 if (tty_termios_baud_rate(termios)) 1351 tty_termios_encode_baud_rate(termios, baud, baud); 1352 uart_port_lock_irqsave(u, &flags); 1353 1354 /* Flow control */ 1355 if (termios->c_cflag & CRTSCTS) { 1356 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN; 1357 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; 1358 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); 1359 /* if top layer has asked to set rts active then do so here */ 1360 if (tup->rts_active) 1361 set_rts(tup, true); 1362 } else { 1363 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN; 1364 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; 1365 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); 1366 } 1367 1368 /* update the port timeout based on new settings */ 1369 uart_update_timeout(u, termios->c_cflag, baud); 1370 1371 /* Make sure all writes have completed */ 1372 tegra_uart_read(tup, UART_IER); 1373 1374 /* Re-enable interrupt */ 1375 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 1376 tegra_uart_read(tup, UART_IER); 1377 1378 tup->uport.ignore_status_mask = 0; 1379 /* Ignore all characters if CREAD is not set */ 1380 if ((termios->c_cflag & CREAD) == 0) 1381 tup->uport.ignore_status_mask |= UART_LSR_DR; 1382 if (termios->c_iflag & IGNBRK) 1383 tup->uport.ignore_status_mask |= UART_LSR_BI; 1384 1385 uart_port_unlock_irqrestore(u, flags); 1386 } 1387 1388 static const char *tegra_uart_type(struct uart_port *u) 1389 { 1390 return TEGRA_UART_TYPE; 1391 } 1392 1393 static const struct uart_ops tegra_uart_ops = { 1394 .tx_empty = tegra_uart_tx_empty, 1395 .set_mctrl = tegra_uart_set_mctrl, 1396 .get_mctrl = tegra_uart_get_mctrl, 1397 .stop_tx = tegra_uart_stop_tx, 1398 .start_tx = tegra_uart_start_tx, 1399 .stop_rx = tegra_uart_stop_rx, 1400 .flush_buffer = tegra_uart_flush_buffer, 1401 .enable_ms = tegra_uart_enable_ms, 1402 .break_ctl = tegra_uart_break_ctl, 1403 .startup = tegra_uart_startup, 1404 .shutdown = tegra_uart_shutdown, 1405 .set_termios = tegra_uart_set_termios, 1406 .type = tegra_uart_type, 1407 .request_port = tegra_uart_request_port, 1408 .release_port = tegra_uart_release_port, 1409 }; 1410 1411 static struct uart_driver tegra_uart_driver = { 1412 .owner = THIS_MODULE, 1413 .driver_name = "tegra_hsuart", 1414 .dev_name = "ttyTHS", 1415 .cons = NULL, 1416 .nr = TEGRA_UART_MAXIMUM, 1417 }; 1418 1419 static int tegra_uart_parse_dt(struct platform_device *pdev, 1420 struct tegra_uart_port *tup) 1421 { 1422 struct device_node *np = pdev->dev.of_node; 1423 int port; 1424 int ret; 1425 int index; 1426 u32 pval; 1427 int count; 1428 int n_entries; 1429 1430 port = of_alias_get_id(np, "serial"); 1431 if (port < 0) { 1432 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port); 1433 return port; 1434 } 1435 tup->uport.line = port; 1436 1437 tup->enable_modem_interrupt = of_property_read_bool(np, 1438 "nvidia,enable-modem-interrupt"); 1439 1440 index = of_property_match_string(np, "dma-names", "rx"); 1441 if (index < 0) { 1442 tup->use_rx_pio = true; 1443 dev_info(&pdev->dev, "RX in PIO mode\n"); 1444 } 1445 index = of_property_match_string(np, "dma-names", "tx"); 1446 if (index < 0) { 1447 tup->use_tx_pio = true; 1448 dev_info(&pdev->dev, "TX in PIO mode\n"); 1449 } 1450 1451 n_entries = of_property_count_u32_elems(np, "nvidia,adjust-baud-rates"); 1452 if (n_entries > 0) { 1453 tup->n_adjustable_baud_rates = n_entries / 3; 1454 tup->baud_tolerance = 1455 devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) * 1456 sizeof(*tup->baud_tolerance), GFP_KERNEL); 1457 if (!tup->baud_tolerance) 1458 return -ENOMEM; 1459 for (count = 0, index = 0; count < n_entries; count += 3, 1460 index++) { 1461 ret = 1462 of_property_read_u32_index(np, 1463 "nvidia,adjust-baud-rates", 1464 count, &pval); 1465 if (!ret) 1466 tup->baud_tolerance[index].lower_range_baud = 1467 pval; 1468 ret = 1469 of_property_read_u32_index(np, 1470 "nvidia,adjust-baud-rates", 1471 count + 1, &pval); 1472 if (!ret) 1473 tup->baud_tolerance[index].upper_range_baud = 1474 pval; 1475 ret = 1476 of_property_read_u32_index(np, 1477 "nvidia,adjust-baud-rates", 1478 count + 2, &pval); 1479 if (!ret) 1480 tup->baud_tolerance[index].tolerance = 1481 (s32)pval; 1482 } 1483 } else { 1484 tup->n_adjustable_baud_rates = 0; 1485 } 1486 1487 return 0; 1488 } 1489 1490 static struct tegra_uart_chip_data tegra20_uart_chip_data = { 1491 .tx_fifo_full_status = false, 1492 .allow_txfifo_reset_fifo_mode = true, 1493 .support_clk_src_div = false, 1494 .fifo_mode_enable_status = false, 1495 .uart_max_port = 5, 1496 .max_dma_burst_bytes = 4, 1497 .error_tolerance_low_range = -4, 1498 .error_tolerance_high_range = 4, 1499 }; 1500 1501 static struct tegra_uart_chip_data tegra30_uart_chip_data = { 1502 .tx_fifo_full_status = true, 1503 .allow_txfifo_reset_fifo_mode = false, 1504 .support_clk_src_div = true, 1505 .fifo_mode_enable_status = false, 1506 .uart_max_port = 5, 1507 .max_dma_burst_bytes = 4, 1508 .error_tolerance_low_range = -4, 1509 .error_tolerance_high_range = 4, 1510 }; 1511 1512 static struct tegra_uart_chip_data tegra186_uart_chip_data = { 1513 .tx_fifo_full_status = true, 1514 .allow_txfifo_reset_fifo_mode = false, 1515 .support_clk_src_div = true, 1516 .fifo_mode_enable_status = true, 1517 .uart_max_port = 8, 1518 .max_dma_burst_bytes = 8, 1519 .error_tolerance_low_range = 0, 1520 .error_tolerance_high_range = 4, 1521 }; 1522 1523 static struct tegra_uart_chip_data tegra194_uart_chip_data = { 1524 .tx_fifo_full_status = true, 1525 .allow_txfifo_reset_fifo_mode = false, 1526 .support_clk_src_div = true, 1527 .fifo_mode_enable_status = true, 1528 .uart_max_port = 8, 1529 .max_dma_burst_bytes = 8, 1530 .error_tolerance_low_range = -2, 1531 .error_tolerance_high_range = 2, 1532 }; 1533 1534 static const struct of_device_id tegra_uart_of_match[] = { 1535 { 1536 .compatible = "nvidia,tegra30-hsuart", 1537 .data = &tegra30_uart_chip_data, 1538 }, { 1539 .compatible = "nvidia,tegra20-hsuart", 1540 .data = &tegra20_uart_chip_data, 1541 }, { 1542 .compatible = "nvidia,tegra186-hsuart", 1543 .data = &tegra186_uart_chip_data, 1544 }, { 1545 .compatible = "nvidia,tegra194-hsuart", 1546 .data = &tegra194_uart_chip_data, 1547 }, { 1548 }, 1549 }; 1550 MODULE_DEVICE_TABLE(of, tegra_uart_of_match); 1551 1552 static int tegra_uart_probe(struct platform_device *pdev) 1553 { 1554 struct tegra_uart_port *tup; 1555 struct uart_port *u; 1556 struct resource *resource; 1557 int ret; 1558 const struct tegra_uart_chip_data *cdata; 1559 1560 cdata = of_device_get_match_data(&pdev->dev); 1561 if (!cdata) { 1562 dev_err(&pdev->dev, "Error: No device match found\n"); 1563 return -ENODEV; 1564 } 1565 1566 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL); 1567 if (!tup) { 1568 dev_err(&pdev->dev, "Failed to allocate memory for tup\n"); 1569 return -ENOMEM; 1570 } 1571 1572 ret = tegra_uart_parse_dt(pdev, tup); 1573 if (ret < 0) 1574 return ret; 1575 1576 u = &tup->uport; 1577 u->dev = &pdev->dev; 1578 u->ops = &tegra_uart_ops; 1579 u->type = PORT_TEGRA; 1580 u->fifosize = 32; 1581 tup->cdata = cdata; 1582 1583 platform_set_drvdata(pdev, tup); 1584 1585 u->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &resource); 1586 if (IS_ERR(u->membase)) 1587 return PTR_ERR(u->membase); 1588 u->mapbase = resource->start; 1589 1590 tup->uart_clk = devm_clk_get(&pdev->dev, NULL); 1591 if (IS_ERR(tup->uart_clk)) 1592 return dev_err_probe(&pdev->dev, PTR_ERR(tup->uart_clk), "Couldn't get the clock"); 1593 1594 tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial"); 1595 if (IS_ERR(tup->rst)) { 1596 dev_err(&pdev->dev, "Couldn't get the reset\n"); 1597 return PTR_ERR(tup->rst); 1598 } 1599 1600 u->iotype = UPIO_MEM32; 1601 ret = platform_get_irq(pdev, 0); 1602 if (ret < 0) 1603 return ret; 1604 u->irq = ret; 1605 u->regshift = 2; 1606 ret = uart_add_one_port(&tegra_uart_driver, u); 1607 if (ret < 0) { 1608 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret); 1609 return ret; 1610 } 1611 return ret; 1612 } 1613 1614 static int tegra_uart_remove(struct platform_device *pdev) 1615 { 1616 struct tegra_uart_port *tup = platform_get_drvdata(pdev); 1617 struct uart_port *u = &tup->uport; 1618 1619 uart_remove_one_port(&tegra_uart_driver, u); 1620 return 0; 1621 } 1622 1623 #ifdef CONFIG_PM_SLEEP 1624 static int tegra_uart_suspend(struct device *dev) 1625 { 1626 struct tegra_uart_port *tup = dev_get_drvdata(dev); 1627 struct uart_port *u = &tup->uport; 1628 1629 return uart_suspend_port(&tegra_uart_driver, u); 1630 } 1631 1632 static int tegra_uart_resume(struct device *dev) 1633 { 1634 struct tegra_uart_port *tup = dev_get_drvdata(dev); 1635 struct uart_port *u = &tup->uport; 1636 1637 return uart_resume_port(&tegra_uart_driver, u); 1638 } 1639 #endif 1640 1641 static const struct dev_pm_ops tegra_uart_pm_ops = { 1642 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume) 1643 }; 1644 1645 static struct platform_driver tegra_uart_platform_driver = { 1646 .probe = tegra_uart_probe, 1647 .remove = tegra_uart_remove, 1648 .driver = { 1649 .name = "serial-tegra", 1650 .of_match_table = tegra_uart_of_match, 1651 .pm = &tegra_uart_pm_ops, 1652 }, 1653 }; 1654 1655 static int __init tegra_uart_init(void) 1656 { 1657 int ret; 1658 struct device_node *node; 1659 const struct of_device_id *match = NULL; 1660 const struct tegra_uart_chip_data *cdata = NULL; 1661 1662 node = of_find_matching_node(NULL, tegra_uart_of_match); 1663 if (node) 1664 match = of_match_node(tegra_uart_of_match, node); 1665 of_node_put(node); 1666 if (match) 1667 cdata = match->data; 1668 if (cdata) 1669 tegra_uart_driver.nr = cdata->uart_max_port; 1670 1671 ret = uart_register_driver(&tegra_uart_driver); 1672 if (ret < 0) { 1673 pr_err("Could not register %s driver\n", 1674 tegra_uart_driver.driver_name); 1675 return ret; 1676 } 1677 1678 ret = platform_driver_register(&tegra_uart_platform_driver); 1679 if (ret < 0) { 1680 pr_err("Uart platform driver register failed, e = %d\n", ret); 1681 uart_unregister_driver(&tegra_uart_driver); 1682 return ret; 1683 } 1684 return 0; 1685 } 1686 1687 static void __exit tegra_uart_exit(void) 1688 { 1689 pr_info("Unloading tegra uart driver\n"); 1690 platform_driver_unregister(&tegra_uart_platform_driver); 1691 uart_unregister_driver(&tegra_uart_driver); 1692 } 1693 1694 module_init(tegra_uart_init); 1695 module_exit(tegra_uart_exit); 1696 1697 MODULE_ALIAS("platform:serial-tegra"); 1698 MODULE_DESCRIPTION("High speed UART driver for tegra chipset"); 1699 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); 1700 MODULE_LICENSE("GPL v2"); 1701