1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * NXP (Philips) SCC+++(SCN+++) serial driver 4 * 5 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> 6 * 7 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de) 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/module.h> 14 #include <linux/device.h> 15 #include <linux/console.h> 16 #include <linux/serial_core.h> 17 #include <linux/serial.h> 18 #include <linux/io.h> 19 #include <linux/tty.h> 20 #include <linux/tty_flip.h> 21 #include <linux/spinlock.h> 22 #include <linux/platform_device.h> 23 #include <linux/platform_data/serial-sccnxp.h> 24 #include <linux/regulator/consumer.h> 25 26 #define SCCNXP_NAME "uart-sccnxp" 27 #define SCCNXP_MAJOR 204 28 #define SCCNXP_MINOR 205 29 30 #define SCCNXP_MR_REG (0x00) 31 # define MR0_BAUD_NORMAL (0 << 0) 32 # define MR0_BAUD_EXT1 (1 << 0) 33 # define MR0_BAUD_EXT2 (5 << 0) 34 # define MR0_FIFO (1 << 3) 35 # define MR0_TXLVL (1 << 4) 36 # define MR1_BITS_5 (0 << 0) 37 # define MR1_BITS_6 (1 << 0) 38 # define MR1_BITS_7 (2 << 0) 39 # define MR1_BITS_8 (3 << 0) 40 # define MR1_PAR_EVN (0 << 2) 41 # define MR1_PAR_ODD (1 << 2) 42 # define MR1_PAR_NO (4 << 2) 43 # define MR2_STOP1 (7 << 0) 44 # define MR2_STOP2 (0xf << 0) 45 #define SCCNXP_SR_REG (0x01) 46 # define SR_RXRDY (1 << 0) 47 # define SR_FULL (1 << 1) 48 # define SR_TXRDY (1 << 2) 49 # define SR_TXEMT (1 << 3) 50 # define SR_OVR (1 << 4) 51 # define SR_PE (1 << 5) 52 # define SR_FE (1 << 6) 53 # define SR_BRK (1 << 7) 54 #define SCCNXP_CSR_REG (SCCNXP_SR_REG) 55 # define CSR_TIMER_MODE (0x0d) 56 #define SCCNXP_CR_REG (0x02) 57 # define CR_RX_ENABLE (1 << 0) 58 # define CR_RX_DISABLE (1 << 1) 59 # define CR_TX_ENABLE (1 << 2) 60 # define CR_TX_DISABLE (1 << 3) 61 # define CR_CMD_MRPTR1 (0x01 << 4) 62 # define CR_CMD_RX_RESET (0x02 << 4) 63 # define CR_CMD_TX_RESET (0x03 << 4) 64 # define CR_CMD_STATUS_RESET (0x04 << 4) 65 # define CR_CMD_BREAK_RESET (0x05 << 4) 66 # define CR_CMD_START_BREAK (0x06 << 4) 67 # define CR_CMD_STOP_BREAK (0x07 << 4) 68 # define CR_CMD_MRPTR0 (0x0b << 4) 69 #define SCCNXP_RHR_REG (0x03) 70 #define SCCNXP_THR_REG SCCNXP_RHR_REG 71 #define SCCNXP_IPCR_REG (0x04) 72 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 73 # define ACR_BAUD0 (0 << 7) 74 # define ACR_BAUD1 (1 << 7) 75 # define ACR_TIMER_MODE (6 << 4) 76 #define SCCNXP_ISR_REG (0x05) 77 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 78 # define IMR_TXRDY (1 << 0) 79 # define IMR_RXRDY (1 << 1) 80 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 81 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 82 #define SCCNXP_CTPU_REG (0x06) 83 #define SCCNXP_CTPL_REG (0x07) 84 #define SCCNXP_IPR_REG (0x0d) 85 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 86 #define SCCNXP_SOP_REG (0x0e) 87 #define SCCNXP_START_COUNTER_REG SCCNXP_SOP_REG 88 #define SCCNXP_ROP_REG (0x0f) 89 90 /* Route helpers */ 91 #define MCTRL_MASK(sig) (0xf << (sig)) 92 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 93 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 94 95 #define SCCNXP_HAVE_IO 0x00000001 96 #define SCCNXP_HAVE_MR0 0x00000002 97 98 struct sccnxp_chip { 99 const char *name; 100 unsigned int nr; 101 unsigned long freq_min; 102 unsigned long freq_std; 103 unsigned long freq_max; 104 unsigned int flags; 105 unsigned int fifosize; 106 /* Time between read/write cycles */ 107 unsigned int trwd; 108 }; 109 110 struct sccnxp_port { 111 struct uart_driver uart; 112 struct uart_port port[SCCNXP_MAX_UARTS]; 113 bool opened[SCCNXP_MAX_UARTS]; 114 115 int irq; 116 u8 imr; 117 118 struct sccnxp_chip *chip; 119 120 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 121 struct console console; 122 #endif 123 124 spinlock_t lock; 125 126 bool poll; 127 struct timer_list timer; 128 129 struct sccnxp_pdata pdata; 130 131 struct regulator *regulator; 132 }; 133 134 static const struct sccnxp_chip sc2681 = { 135 .name = "SC2681", 136 .nr = 2, 137 .freq_min = 1000000, 138 .freq_std = 3686400, 139 .freq_max = 4000000, 140 .flags = SCCNXP_HAVE_IO, 141 .fifosize = 3, 142 .trwd = 200, 143 }; 144 145 static const struct sccnxp_chip sc2691 = { 146 .name = "SC2691", 147 .nr = 1, 148 .freq_min = 1000000, 149 .freq_std = 3686400, 150 .freq_max = 4000000, 151 .flags = 0, 152 .fifosize = 3, 153 .trwd = 150, 154 }; 155 156 static const struct sccnxp_chip sc2692 = { 157 .name = "SC2692", 158 .nr = 2, 159 .freq_min = 1000000, 160 .freq_std = 3686400, 161 .freq_max = 4000000, 162 .flags = SCCNXP_HAVE_IO, 163 .fifosize = 3, 164 .trwd = 30, 165 }; 166 167 static const struct sccnxp_chip sc2891 = { 168 .name = "SC2891", 169 .nr = 1, 170 .freq_min = 100000, 171 .freq_std = 3686400, 172 .freq_max = 8000000, 173 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0, 174 .fifosize = 16, 175 .trwd = 27, 176 }; 177 178 static const struct sccnxp_chip sc2892 = { 179 .name = "SC2892", 180 .nr = 2, 181 .freq_min = 100000, 182 .freq_std = 3686400, 183 .freq_max = 8000000, 184 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0, 185 .fifosize = 16, 186 .trwd = 17, 187 }; 188 189 static const struct sccnxp_chip sc28202 = { 190 .name = "SC28202", 191 .nr = 2, 192 .freq_min = 1000000, 193 .freq_std = 14745600, 194 .freq_max = 50000000, 195 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0, 196 .fifosize = 256, 197 .trwd = 10, 198 }; 199 200 static const struct sccnxp_chip sc68681 = { 201 .name = "SC68681", 202 .nr = 2, 203 .freq_min = 1000000, 204 .freq_std = 3686400, 205 .freq_max = 4000000, 206 .flags = SCCNXP_HAVE_IO, 207 .fifosize = 3, 208 .trwd = 200, 209 }; 210 211 static const struct sccnxp_chip sc68692 = { 212 .name = "SC68692", 213 .nr = 2, 214 .freq_min = 1000000, 215 .freq_std = 3686400, 216 .freq_max = 4000000, 217 .flags = SCCNXP_HAVE_IO, 218 .fifosize = 3, 219 .trwd = 200, 220 }; 221 222 static u8 sccnxp_read(struct uart_port *port, u8 reg) 223 { 224 struct sccnxp_port *s = dev_get_drvdata(port->dev); 225 u8 ret; 226 227 ret = readb(port->membase + (reg << port->regshift)); 228 229 ndelay(s->chip->trwd); 230 231 return ret; 232 } 233 234 static void sccnxp_write(struct uart_port *port, u8 reg, u8 v) 235 { 236 struct sccnxp_port *s = dev_get_drvdata(port->dev); 237 238 writeb(v, port->membase + (reg << port->regshift)); 239 240 ndelay(s->chip->trwd); 241 } 242 243 static u8 sccnxp_port_read(struct uart_port *port, u8 reg) 244 { 245 return sccnxp_read(port, (port->line << 3) + reg); 246 } 247 248 static void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v) 249 { 250 sccnxp_write(port, (port->line << 3) + reg, v); 251 } 252 253 static int sccnxp_update_best_err(int a, int b, int *besterr) 254 { 255 int err = abs(a - b); 256 257 if (*besterr > err) { 258 *besterr = err; 259 return 0; 260 } 261 262 return 1; 263 } 264 265 static const struct { 266 u8 csr; 267 u8 acr; 268 u8 mr0; 269 int baud; 270 } baud_std[] = { 271 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, }, 272 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, }, 273 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, }, 274 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, }, 275 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, }, 276 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, }, 277 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, }, 278 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, }, 279 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, }, 280 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, }, 281 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, }, 282 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, }, 283 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, }, 284 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, }, 285 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, }, 286 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, }, 287 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, }, 288 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, }, 289 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, }, 290 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, }, 291 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, }, 292 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, }, 293 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, }, 294 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, }, 295 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, }, 296 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, }, 297 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, }, 298 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, }, 299 { 0, 0, 0, 0 } 300 }; 301 302 static int sccnxp_set_baud(struct uart_port *port, int baud) 303 { 304 struct sccnxp_port *s = dev_get_drvdata(port->dev); 305 int div_std, tmp_baud, bestbaud = INT_MAX, besterr = INT_MAX; 306 struct sccnxp_chip *chip = s->chip; 307 u8 i, acr = 0, csr = 0, mr0 = 0; 308 309 /* Find divisor to load to the timer preset registers */ 310 div_std = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * baud); 311 if ((div_std >= 2) && (div_std <= 0xffff)) { 312 bestbaud = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * div_std); 313 sccnxp_update_best_err(baud, bestbaud, &besterr); 314 csr = CSR_TIMER_MODE; 315 sccnxp_port_write(port, SCCNXP_CTPU_REG, div_std >> 8); 316 sccnxp_port_write(port, SCCNXP_CTPL_REG, div_std); 317 /* Issue start timer/counter command */ 318 sccnxp_port_read(port, SCCNXP_START_COUNTER_REG); 319 } 320 321 /* Find best baud from table */ 322 for (i = 0; baud_std[i].baud && besterr; i++) { 323 if (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0)) 324 continue; 325 div_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud); 326 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std); 327 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) { 328 acr = baud_std[i].acr; 329 csr = baud_std[i].csr; 330 mr0 = baud_std[i].mr0; 331 bestbaud = tmp_baud; 332 } 333 } 334 335 if (chip->flags & SCCNXP_HAVE_MR0) { 336 /* Enable FIFO, set half level for TX */ 337 mr0 |= MR0_FIFO | MR0_TXLVL; 338 /* Update MR0 */ 339 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0); 340 sccnxp_port_write(port, SCCNXP_MR_REG, mr0); 341 } 342 343 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE); 344 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr); 345 346 if (baud != bestbaud) 347 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n", 348 baud, bestbaud); 349 350 return bestbaud; 351 } 352 353 static void sccnxp_enable_irq(struct uart_port *port, int mask) 354 { 355 struct sccnxp_port *s = dev_get_drvdata(port->dev); 356 357 s->imr |= mask << (port->line * 4); 358 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 359 } 360 361 static void sccnxp_disable_irq(struct uart_port *port, int mask) 362 { 363 struct sccnxp_port *s = dev_get_drvdata(port->dev); 364 365 s->imr &= ~(mask << (port->line * 4)); 366 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 367 } 368 369 static void sccnxp_set_bit(struct uart_port *port, int sig, int state) 370 { 371 u8 bitmask; 372 struct sccnxp_port *s = dev_get_drvdata(port->dev); 373 374 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) { 375 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig); 376 if (state) 377 sccnxp_write(port, SCCNXP_SOP_REG, bitmask); 378 else 379 sccnxp_write(port, SCCNXP_ROP_REG, bitmask); 380 } 381 } 382 383 static void sccnxp_handle_rx(struct uart_port *port) 384 { 385 u8 sr, ch, flag; 386 387 for (;;) { 388 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 389 if (!(sr & SR_RXRDY)) 390 break; 391 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK; 392 393 ch = sccnxp_port_read(port, SCCNXP_RHR_REG); 394 395 port->icount.rx++; 396 flag = TTY_NORMAL; 397 398 if (unlikely(sr)) { 399 if (sr & SR_BRK) { 400 port->icount.brk++; 401 sccnxp_port_write(port, SCCNXP_CR_REG, 402 CR_CMD_BREAK_RESET); 403 if (uart_handle_break(port)) 404 continue; 405 } else if (sr & SR_PE) 406 port->icount.parity++; 407 else if (sr & SR_FE) 408 port->icount.frame++; 409 else if (sr & SR_OVR) { 410 port->icount.overrun++; 411 sccnxp_port_write(port, SCCNXP_CR_REG, 412 CR_CMD_STATUS_RESET); 413 } 414 415 sr &= port->read_status_mask; 416 if (sr & SR_BRK) 417 flag = TTY_BREAK; 418 else if (sr & SR_PE) 419 flag = TTY_PARITY; 420 else if (sr & SR_FE) 421 flag = TTY_FRAME; 422 else if (sr & SR_OVR) 423 flag = TTY_OVERRUN; 424 } 425 426 if (uart_handle_sysrq_char(port, ch)) 427 continue; 428 429 if (sr & port->ignore_status_mask) 430 continue; 431 432 uart_insert_char(port, sr, SR_OVR, ch, flag); 433 } 434 435 tty_flip_buffer_push(&port->state->port); 436 } 437 438 static void sccnxp_handle_tx(struct uart_port *port) 439 { 440 u8 sr; 441 struct tty_port *tport = &port->state->port; 442 struct sccnxp_port *s = dev_get_drvdata(port->dev); 443 444 if (unlikely(port->x_char)) { 445 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char); 446 port->icount.tx++; 447 port->x_char = 0; 448 return; 449 } 450 451 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) { 452 /* Disable TX if FIFO is empty */ 453 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) { 454 sccnxp_disable_irq(port, IMR_TXRDY); 455 456 /* Set direction to input */ 457 if (s->chip->flags & SCCNXP_HAVE_IO) 458 sccnxp_set_bit(port, DIR_OP, 0); 459 } 460 return; 461 } 462 463 while (1) { 464 unsigned char ch; 465 466 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 467 if (!(sr & SR_TXRDY)) 468 break; 469 470 if (!uart_fifo_get(port, &ch)) 471 break; 472 473 sccnxp_port_write(port, SCCNXP_THR_REG, ch); 474 } 475 476 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 477 uart_write_wakeup(port); 478 } 479 480 static void sccnxp_handle_events(struct sccnxp_port *s) 481 { 482 int i; 483 u8 isr; 484 485 do { 486 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG); 487 isr &= s->imr; 488 if (!isr) 489 break; 490 491 for (i = 0; i < s->uart.nr; i++) { 492 if (s->opened[i] && (isr & ISR_RXRDY(i))) 493 sccnxp_handle_rx(&s->port[i]); 494 if (s->opened[i] && (isr & ISR_TXRDY(i))) 495 sccnxp_handle_tx(&s->port[i]); 496 } 497 } while (1); 498 } 499 500 static void sccnxp_timer(struct timer_list *t) 501 { 502 struct sccnxp_port *s = timer_container_of(s, t, timer); 503 unsigned long flags; 504 505 spin_lock_irqsave(&s->lock, flags); 506 sccnxp_handle_events(s); 507 spin_unlock_irqrestore(&s->lock, flags); 508 509 mod_timer(&s->timer, jiffies + usecs_to_jiffies(s->pdata.poll_time_us)); 510 } 511 512 static irqreturn_t sccnxp_ist(int irq, void *dev_id) 513 { 514 struct sccnxp_port *s = (struct sccnxp_port *)dev_id; 515 unsigned long flags; 516 517 spin_lock_irqsave(&s->lock, flags); 518 sccnxp_handle_events(s); 519 spin_unlock_irqrestore(&s->lock, flags); 520 521 return IRQ_HANDLED; 522 } 523 524 static void sccnxp_start_tx(struct uart_port *port) 525 { 526 struct sccnxp_port *s = dev_get_drvdata(port->dev); 527 unsigned long flags; 528 529 spin_lock_irqsave(&s->lock, flags); 530 531 /* Set direction to output */ 532 if (s->chip->flags & SCCNXP_HAVE_IO) 533 sccnxp_set_bit(port, DIR_OP, 1); 534 535 sccnxp_enable_irq(port, IMR_TXRDY); 536 537 spin_unlock_irqrestore(&s->lock, flags); 538 } 539 540 static void sccnxp_stop_tx(struct uart_port *port) 541 { 542 /* Do nothing */ 543 } 544 545 static void sccnxp_stop_rx(struct uart_port *port) 546 { 547 struct sccnxp_port *s = dev_get_drvdata(port->dev); 548 unsigned long flags; 549 550 spin_lock_irqsave(&s->lock, flags); 551 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE); 552 spin_unlock_irqrestore(&s->lock, flags); 553 } 554 555 static unsigned int sccnxp_tx_empty(struct uart_port *port) 556 { 557 u8 val; 558 unsigned long flags; 559 struct sccnxp_port *s = dev_get_drvdata(port->dev); 560 561 spin_lock_irqsave(&s->lock, flags); 562 val = sccnxp_port_read(port, SCCNXP_SR_REG); 563 spin_unlock_irqrestore(&s->lock, flags); 564 565 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0; 566 } 567 568 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl) 569 { 570 struct sccnxp_port *s = dev_get_drvdata(port->dev); 571 unsigned long flags; 572 573 if (!(s->chip->flags & SCCNXP_HAVE_IO)) 574 return; 575 576 spin_lock_irqsave(&s->lock, flags); 577 578 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR); 579 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS); 580 581 spin_unlock_irqrestore(&s->lock, flags); 582 } 583 584 static unsigned int sccnxp_get_mctrl(struct uart_port *port) 585 { 586 u8 bitmask, ipr; 587 unsigned long flags; 588 struct sccnxp_port *s = dev_get_drvdata(port->dev); 589 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR; 590 591 if (!(s->chip->flags & SCCNXP_HAVE_IO)) 592 return mctrl; 593 594 spin_lock_irqsave(&s->lock, flags); 595 596 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG); 597 598 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) { 599 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 600 DSR_IP); 601 mctrl &= ~TIOCM_DSR; 602 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0; 603 } 604 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) { 605 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 606 CTS_IP); 607 mctrl &= ~TIOCM_CTS; 608 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0; 609 } 610 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) { 611 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 612 DCD_IP); 613 mctrl &= ~TIOCM_CAR; 614 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0; 615 } 616 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) { 617 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 618 RNG_IP); 619 mctrl &= ~TIOCM_RNG; 620 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0; 621 } 622 623 spin_unlock_irqrestore(&s->lock, flags); 624 625 return mctrl; 626 } 627 628 static void sccnxp_break_ctl(struct uart_port *port, int break_state) 629 { 630 struct sccnxp_port *s = dev_get_drvdata(port->dev); 631 unsigned long flags; 632 633 spin_lock_irqsave(&s->lock, flags); 634 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ? 635 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK); 636 spin_unlock_irqrestore(&s->lock, flags); 637 } 638 639 static void sccnxp_set_termios(struct uart_port *port, 640 struct ktermios *termios, 641 const struct ktermios *old) 642 { 643 struct sccnxp_port *s = dev_get_drvdata(port->dev); 644 unsigned long flags; 645 u8 mr1, mr2; 646 int baud; 647 648 spin_lock_irqsave(&s->lock, flags); 649 650 /* Mask termios capabilities we don't support */ 651 termios->c_cflag &= ~CMSPAR; 652 653 /* Disable RX & TX, reset break condition, status and FIFOs */ 654 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET | 655 CR_RX_DISABLE | CR_TX_DISABLE); 656 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 657 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 658 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 659 660 /* Word size */ 661 switch (termios->c_cflag & CSIZE) { 662 case CS5: 663 mr1 = MR1_BITS_5; 664 break; 665 case CS6: 666 mr1 = MR1_BITS_6; 667 break; 668 case CS7: 669 mr1 = MR1_BITS_7; 670 break; 671 case CS8: 672 default: 673 mr1 = MR1_BITS_8; 674 break; 675 } 676 677 /* Parity */ 678 if (termios->c_cflag & PARENB) { 679 if (termios->c_cflag & PARODD) 680 mr1 |= MR1_PAR_ODD; 681 } else 682 mr1 |= MR1_PAR_NO; 683 684 /* Stop bits */ 685 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1; 686 687 /* Update desired format */ 688 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1); 689 sccnxp_port_write(port, SCCNXP_MR_REG, mr1); 690 sccnxp_port_write(port, SCCNXP_MR_REG, mr2); 691 692 /* Set read status mask */ 693 port->read_status_mask = SR_OVR; 694 if (termios->c_iflag & INPCK) 695 port->read_status_mask |= SR_PE | SR_FE; 696 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 697 port->read_status_mask |= SR_BRK; 698 699 /* Set status ignore mask */ 700 port->ignore_status_mask = 0; 701 if (termios->c_iflag & IGNBRK) 702 port->ignore_status_mask |= SR_BRK; 703 if (termios->c_iflag & IGNPAR) 704 port->ignore_status_mask |= SR_PE; 705 if (!(termios->c_cflag & CREAD)) 706 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK; 707 708 /* Setup baudrate */ 709 baud = uart_get_baud_rate(port, termios, old, 50, 710 (s->chip->flags & SCCNXP_HAVE_MR0) ? 711 230400 : 38400); 712 baud = sccnxp_set_baud(port, baud); 713 714 /* Update timeout according to new baud rate */ 715 uart_update_timeout(port, termios->c_cflag, baud); 716 717 /* Report actual baudrate back to core */ 718 if (tty_termios_baud_rate(termios)) 719 tty_termios_encode_baud_rate(termios, baud, baud); 720 721 /* Enable RX & TX */ 722 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 723 724 spin_unlock_irqrestore(&s->lock, flags); 725 } 726 727 static int sccnxp_startup(struct uart_port *port) 728 { 729 struct sccnxp_port *s = dev_get_drvdata(port->dev); 730 unsigned long flags; 731 732 spin_lock_irqsave(&s->lock, flags); 733 734 if (s->chip->flags & SCCNXP_HAVE_IO) { 735 /* Outputs are controlled manually */ 736 sccnxp_write(port, SCCNXP_OPCR_REG, 0); 737 } 738 739 /* Reset break condition, status and FIFOs */ 740 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET); 741 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 742 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 743 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 744 745 /* Enable RX & TX */ 746 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 747 748 /* Enable RX interrupt */ 749 sccnxp_enable_irq(port, IMR_RXRDY); 750 751 s->opened[port->line] = 1; 752 753 spin_unlock_irqrestore(&s->lock, flags); 754 755 return 0; 756 } 757 758 static void sccnxp_shutdown(struct uart_port *port) 759 { 760 struct sccnxp_port *s = dev_get_drvdata(port->dev); 761 unsigned long flags; 762 763 spin_lock_irqsave(&s->lock, flags); 764 765 s->opened[port->line] = 0; 766 767 /* Disable interrupts */ 768 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY); 769 770 /* Disable TX & RX */ 771 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE); 772 773 /* Leave direction to input */ 774 if (s->chip->flags & SCCNXP_HAVE_IO) 775 sccnxp_set_bit(port, DIR_OP, 0); 776 777 spin_unlock_irqrestore(&s->lock, flags); 778 } 779 780 static const char *sccnxp_type(struct uart_port *port) 781 { 782 struct sccnxp_port *s = dev_get_drvdata(port->dev); 783 784 return (port->type == PORT_SC26XX) ? s->chip->name : NULL; 785 } 786 787 static void sccnxp_release_port(struct uart_port *port) 788 { 789 /* Do nothing */ 790 } 791 792 static int sccnxp_request_port(struct uart_port *port) 793 { 794 /* Do nothing */ 795 return 0; 796 } 797 798 static void sccnxp_config_port(struct uart_port *port, int flags) 799 { 800 if (flags & UART_CONFIG_TYPE) 801 port->type = PORT_SC26XX; 802 } 803 804 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s) 805 { 806 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX)) 807 return 0; 808 if (s->irq == port->irq) 809 return 0; 810 811 return -EINVAL; 812 } 813 814 static const struct uart_ops sccnxp_ops = { 815 .tx_empty = sccnxp_tx_empty, 816 .set_mctrl = sccnxp_set_mctrl, 817 .get_mctrl = sccnxp_get_mctrl, 818 .stop_tx = sccnxp_stop_tx, 819 .start_tx = sccnxp_start_tx, 820 .stop_rx = sccnxp_stop_rx, 821 .break_ctl = sccnxp_break_ctl, 822 .startup = sccnxp_startup, 823 .shutdown = sccnxp_shutdown, 824 .set_termios = sccnxp_set_termios, 825 .type = sccnxp_type, 826 .release_port = sccnxp_release_port, 827 .request_port = sccnxp_request_port, 828 .config_port = sccnxp_config_port, 829 .verify_port = sccnxp_verify_port, 830 }; 831 832 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 833 static void sccnxp_console_putchar(struct uart_port *port, unsigned char c) 834 { 835 int tryes = 100000; 836 837 while (tryes--) { 838 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) { 839 sccnxp_port_write(port, SCCNXP_THR_REG, c); 840 break; 841 } 842 barrier(); 843 } 844 } 845 846 static void sccnxp_console_write(struct console *co, const char *c, unsigned n) 847 { 848 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 849 struct uart_port *port = &s->port[co->index]; 850 unsigned long flags; 851 852 spin_lock_irqsave(&s->lock, flags); 853 uart_console_write(port, c, n, sccnxp_console_putchar); 854 spin_unlock_irqrestore(&s->lock, flags); 855 } 856 857 static int sccnxp_console_setup(struct console *co, char *options) 858 { 859 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 860 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0]; 861 int baud = 9600, bits = 8, parity = 'n', flow = 'n'; 862 863 if (options) 864 uart_parse_options(options, &baud, &parity, &bits, &flow); 865 866 return uart_set_options(port, co, baud, parity, bits, flow); 867 } 868 #endif 869 870 static const struct platform_device_id sccnxp_id_table[] = { 871 { .name = "sc2681", .driver_data = (kernel_ulong_t)&sc2681, }, 872 { .name = "sc2691", .driver_data = (kernel_ulong_t)&sc2691, }, 873 { .name = "sc2692", .driver_data = (kernel_ulong_t)&sc2692, }, 874 { .name = "sc2891", .driver_data = (kernel_ulong_t)&sc2891, }, 875 { .name = "sc2892", .driver_data = (kernel_ulong_t)&sc2892, }, 876 { .name = "sc28202", .driver_data = (kernel_ulong_t)&sc28202, }, 877 { .name = "sc68681", .driver_data = (kernel_ulong_t)&sc68681, }, 878 { .name = "sc68692", .driver_data = (kernel_ulong_t)&sc68692, }, 879 { } 880 }; 881 MODULE_DEVICE_TABLE(platform, sccnxp_id_table); 882 883 static int sccnxp_probe(struct platform_device *pdev) 884 { 885 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev); 886 struct resource *res; 887 int i, ret, uartclk; 888 struct sccnxp_port *s; 889 void __iomem *membase; 890 struct clk *clk; 891 892 membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 893 if (IS_ERR(membase)) 894 return PTR_ERR(membase); 895 896 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL); 897 if (!s) { 898 dev_err(&pdev->dev, "Error allocating port structure\n"); 899 return -ENOMEM; 900 } 901 platform_set_drvdata(pdev, s); 902 903 spin_lock_init(&s->lock); 904 905 s->chip = (struct sccnxp_chip *)pdev->id_entry->driver_data; 906 907 s->regulator = devm_regulator_get(&pdev->dev, "vcc"); 908 if (!IS_ERR(s->regulator)) { 909 ret = regulator_enable(s->regulator); 910 if (ret) { 911 dev_err(&pdev->dev, 912 "Failed to enable regulator: %i\n", ret); 913 return ret; 914 } 915 } else if (PTR_ERR(s->regulator) == -EPROBE_DEFER) 916 return -EPROBE_DEFER; 917 918 clk = devm_clk_get_enabled(&pdev->dev, NULL); 919 if (IS_ERR(clk)) { 920 ret = PTR_ERR(clk); 921 if (ret == -EPROBE_DEFER) 922 goto err_out; 923 uartclk = 0; 924 } else { 925 uartclk = clk_get_rate(clk); 926 } 927 928 if (!uartclk) { 929 dev_notice(&pdev->dev, "Using default clock frequency\n"); 930 uartclk = s->chip->freq_std; 931 } 932 933 /* Check input frequency */ 934 if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) { 935 dev_err(&pdev->dev, "Frequency out of bounds\n"); 936 ret = -EINVAL; 937 goto err_out; 938 } 939 940 if (pdata) 941 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata)); 942 943 if (s->pdata.poll_time_us) { 944 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n", 945 s->pdata.poll_time_us); 946 s->poll = 1; 947 } 948 949 if (!s->poll) { 950 s->irq = platform_get_irq(pdev, 0); 951 if (s->irq < 0) { 952 ret = -ENXIO; 953 goto err_out; 954 } 955 } 956 957 s->uart.owner = THIS_MODULE; 958 s->uart.dev_name = "ttySC"; 959 s->uart.major = SCCNXP_MAJOR; 960 s->uart.minor = SCCNXP_MINOR; 961 s->uart.nr = s->chip->nr; 962 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 963 s->uart.cons = &s->console; 964 s->uart.cons->device = uart_console_device; 965 s->uart.cons->write = sccnxp_console_write; 966 s->uart.cons->setup = sccnxp_console_setup; 967 s->uart.cons->flags = CON_PRINTBUFFER; 968 s->uart.cons->index = -1; 969 s->uart.cons->data = s; 970 strcpy(s->uart.cons->name, "ttySC"); 971 #endif 972 ret = uart_register_driver(&s->uart); 973 if (ret) { 974 dev_err(&pdev->dev, "Registering UART driver failed\n"); 975 goto err_out; 976 } 977 978 for (i = 0; i < s->uart.nr; i++) { 979 s->port[i].line = i; 980 s->port[i].dev = &pdev->dev; 981 s->port[i].irq = s->irq; 982 s->port[i].type = PORT_SC26XX; 983 s->port[i].fifosize = s->chip->fifosize; 984 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; 985 s->port[i].iotype = UPIO_MEM; 986 s->port[i].mapbase = res->start; 987 s->port[i].membase = membase; 988 s->port[i].regshift = s->pdata.reg_shift; 989 s->port[i].uartclk = uartclk; 990 s->port[i].ops = &sccnxp_ops; 991 s->port[i].has_sysrq = IS_ENABLED(CONFIG_SERIAL_SCCNXP_CONSOLE); 992 uart_add_one_port(&s->uart, &s->port[i]); 993 /* Set direction to input */ 994 if (s->chip->flags & SCCNXP_HAVE_IO) 995 sccnxp_set_bit(&s->port[i], DIR_OP, 0); 996 } 997 998 /* Disable interrupts */ 999 s->imr = 0; 1000 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0); 1001 1002 if (!s->poll) { 1003 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL, 1004 sccnxp_ist, 1005 IRQF_TRIGGER_FALLING | 1006 IRQF_ONESHOT, 1007 dev_name(&pdev->dev), s); 1008 if (!ret) 1009 return 0; 1010 1011 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq); 1012 } else { 1013 timer_setup(&s->timer, sccnxp_timer, 0); 1014 mod_timer(&s->timer, jiffies + 1015 usecs_to_jiffies(s->pdata.poll_time_us)); 1016 return 0; 1017 } 1018 1019 uart_unregister_driver(&s->uart); 1020 err_out: 1021 if (!IS_ERR(s->regulator)) 1022 regulator_disable(s->regulator); 1023 1024 return ret; 1025 } 1026 1027 static void sccnxp_remove(struct platform_device *pdev) 1028 { 1029 int i; 1030 struct sccnxp_port *s = platform_get_drvdata(pdev); 1031 1032 if (!s->poll) 1033 devm_free_irq(&pdev->dev, s->irq, s); 1034 else 1035 timer_delete_sync(&s->timer); 1036 1037 for (i = 0; i < s->uart.nr; i++) 1038 uart_remove_one_port(&s->uart, &s->port[i]); 1039 1040 uart_unregister_driver(&s->uart); 1041 1042 if (!IS_ERR(s->regulator)) { 1043 int ret = regulator_disable(s->regulator); 1044 if (ret) 1045 dev_err(&pdev->dev, "Failed to disable regulator\n"); 1046 } 1047 } 1048 1049 static struct platform_driver sccnxp_uart_driver = { 1050 .driver = { 1051 .name = SCCNXP_NAME, 1052 }, 1053 .probe = sccnxp_probe, 1054 .remove = sccnxp_remove, 1055 .id_table = sccnxp_id_table, 1056 }; 1057 module_platform_driver(sccnxp_uart_driver); 1058 1059 MODULE_LICENSE("GPL v2"); 1060 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1061 MODULE_DESCRIPTION("SCCNXP serial driver"); 1062