1 /* 2 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint 3 * Author: Jon Ringle <jringle@gridpoint.com> 4 * 5 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 */ 13 14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 15 16 #include <linux/bitops.h> 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/device.h> 20 #include <linux/gpio.h> 21 #include <linux/i2c.h> 22 #include <linux/module.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/regmap.h> 26 #include <linux/serial_core.h> 27 #include <linux/serial.h> 28 #include <linux/tty.h> 29 #include <linux/tty_flip.h> 30 #include <linux/spi/spi.h> 31 #include <linux/uaccess.h> 32 33 #define SC16IS7XX_NAME "sc16is7xx" 34 #define SC16IS7XX_MAX_DEVS 8 35 36 /* SC16IS7XX register definitions */ 37 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */ 38 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */ 39 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */ 40 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */ 41 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */ 42 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */ 43 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */ 44 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */ 45 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */ 46 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */ 47 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */ 48 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */ 49 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction 50 * - only on 75x/76x 51 */ 52 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State 53 * - only on 75x/76x 54 */ 55 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable 56 * - only on 75x/76x 57 */ 58 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control 59 * - only on 75x/76x 60 */ 61 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */ 62 63 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */ 64 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */ 65 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */ 66 67 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */ 68 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */ 69 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */ 70 71 /* Enhanced Register set: Only if (LCR == 0xBF) */ 72 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */ 73 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */ 74 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */ 75 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */ 76 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */ 77 78 /* IER register bits */ 79 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */ 80 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register 81 * interrupt */ 82 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status 83 * interrupt */ 84 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status 85 * interrupt */ 86 87 /* IER register bits - write only if (EFR[4] == 1) */ 88 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */ 89 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */ 90 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */ 91 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */ 92 93 /* FCR register bits */ 94 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */ 95 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */ 96 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */ 97 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */ 98 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */ 99 100 /* FCR register bits - write only if (EFR[4] == 1) */ 101 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */ 102 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */ 103 104 /* IIR register bits */ 105 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */ 106 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */ 107 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */ 108 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */ 109 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */ 110 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */ 111 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt 112 * - only on 75x/76x 113 */ 114 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state 115 * - only on 75x/76x 116 */ 117 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */ 118 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state 119 * from active (LOW) 120 * to inactive (HIGH) 121 */ 122 /* LCR register bits */ 123 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 124 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 125 * 126 * Word length bits table: 127 * 00 -> 5 bit words 128 * 01 -> 6 bit words 129 * 10 -> 7 bit words 130 * 11 -> 8 bit words 131 */ 132 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 133 * 134 * STOP length bit table: 135 * 0 -> 1 stop bit 136 * 1 -> 1-1.5 stop bits if 137 * word length is 5, 138 * 2 stop bits otherwise 139 */ 140 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 141 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 142 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 143 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 144 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */ 145 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00) 146 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01) 147 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02) 148 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03) 149 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special 150 * reg set */ 151 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced 152 * reg set */ 153 154 /* MCR register bits */ 155 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement 156 * - only on 75x/76x 157 */ 158 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */ 159 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */ 160 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */ 161 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any 162 * - write enabled 163 * if (EFR[4] == 1) 164 */ 165 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode 166 * - write enabled 167 * if (EFR[4] == 1) 168 */ 169 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4 170 * - write enabled 171 * if (EFR[4] == 1) 172 */ 173 174 /* LSR register bits */ 175 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */ 176 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */ 177 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */ 178 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */ 179 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */ 180 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */ 181 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */ 182 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */ 183 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */ 184 185 /* MSR register bits */ 186 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */ 187 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready 188 * or (IO4) 189 * - only on 75x/76x 190 */ 191 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator 192 * or (IO7) 193 * - only on 75x/76x 194 */ 195 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect 196 * or (IO6) 197 * - only on 75x/76x 198 */ 199 #define SC16IS7XX_MSR_CTS_BIT (1 << 0) /* CTS */ 200 #define SC16IS7XX_MSR_DSR_BIT (1 << 1) /* DSR (IO4) 201 * - only on 75x/76x 202 */ 203 #define SC16IS7XX_MSR_RI_BIT (1 << 2) /* RI (IO7) 204 * - only on 75x/76x 205 */ 206 #define SC16IS7XX_MSR_CD_BIT (1 << 3) /* CD (IO6) 207 * - only on 75x/76x 208 */ 209 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */ 210 211 /* 212 * TCR register bits 213 * TCR trigger levels are available from 0 to 60 characters with a granularity 214 * of four. 215 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is 216 * no built-in hardware check to make sure this condition is met. Also, the TCR 217 * must be programmed with this condition before auto RTS or software flow 218 * control is enabled to avoid spurious operation of the device. 219 */ 220 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0) 221 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4) 222 223 /* 224 * TLR register bits 225 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the 226 * FIFO Control Register (FCR) are used for the transmit and receive FIFO 227 * trigger levels. Trigger levels from 4 characters to 60 characters are 228 * available with a granularity of four. 229 * 230 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the 231 * trigger level setting defined in FCR. If TLR has non-zero trigger level value 232 * the trigger level defined in FCR is discarded. This applies to both transmit 233 * FIFO and receive FIFO trigger level setting. 234 * 235 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the 236 * default state, that is, '00'. 237 */ 238 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0) 239 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) 240 241 /* IOControl register bits (Only 750/760) */ 242 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ 243 #define SC16IS7XX_IOCONTROL_GPIO_BIT (1 << 1) /* Enable GPIO[7:4] */ 244 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */ 245 246 /* EFCR register bits */ 247 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop 248 * mode (RS485) */ 249 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */ 250 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */ 251 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */ 252 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */ 253 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode 254 * 0 = rate upto 115.2 kbit/s 255 * - Only 750/760 256 * 1 = rate upto 1.152 Mbit/s 257 * - Only 760 258 */ 259 260 /* EFR register bits */ 261 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */ 262 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */ 263 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */ 264 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions 265 * and writing to IER[7:4], 266 * FCR[5:4], MCR[7:5] 267 */ 268 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */ 269 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2 270 * 271 * SWFLOW bits 3 & 2 table: 272 * 00 -> no transmitter flow 273 * control 274 * 01 -> transmitter generates 275 * XON2 and XOFF2 276 * 10 -> transmitter generates 277 * XON1 and XOFF1 278 * 11 -> transmitter generates 279 * XON1, XON2, XOFF1 and 280 * XOFF2 281 */ 282 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */ 283 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3 284 * 285 * SWFLOW bits 3 & 2 table: 286 * 00 -> no received flow 287 * control 288 * 01 -> receiver compares 289 * XON2 and XOFF2 290 * 10 -> receiver compares 291 * XON1 and XOFF1 292 * 11 -> receiver compares 293 * XON1, XON2, XOFF1 and 294 * XOFF2 295 */ 296 297 /* Misc definitions */ 298 #define SC16IS7XX_FIFO_SIZE (64) 299 #define SC16IS7XX_REG_SHIFT 2 300 301 struct sc16is7xx_devtype { 302 char name[10]; 303 int nr_gpio; 304 int nr_uart; 305 }; 306 307 #define SC16IS7XX_RECONF_MD (1 << 0) 308 #define SC16IS7XX_RECONF_IER (1 << 1) 309 #define SC16IS7XX_RECONF_RS485 (1 << 2) 310 311 struct sc16is7xx_one_config { 312 unsigned int flags; 313 u8 ier_clear; 314 }; 315 316 struct sc16is7xx_one { 317 struct uart_port port; 318 u8 line; 319 struct kthread_work tx_work; 320 struct kthread_work reg_work; 321 struct sc16is7xx_one_config config; 322 }; 323 324 struct sc16is7xx_port { 325 const struct sc16is7xx_devtype *devtype; 326 struct regmap *regmap; 327 struct clk *clk; 328 #ifdef CONFIG_GPIOLIB 329 struct gpio_chip gpio; 330 #endif 331 unsigned char buf[SC16IS7XX_FIFO_SIZE]; 332 struct kthread_worker kworker; 333 struct task_struct *kworker_task; 334 struct kthread_work irq_work; 335 struct sc16is7xx_one p[0]; 336 }; 337 338 static unsigned long sc16is7xx_lines; 339 340 static struct uart_driver sc16is7xx_uart = { 341 .owner = THIS_MODULE, 342 .dev_name = "ttySC", 343 .nr = SC16IS7XX_MAX_DEVS, 344 }; 345 346 #define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e))) 347 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e))) 348 349 static int sc16is7xx_line(struct uart_port *port) 350 { 351 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 352 353 return one->line; 354 } 355 356 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg) 357 { 358 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 359 unsigned int val = 0; 360 const u8 line = sc16is7xx_line(port); 361 362 regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val); 363 364 return val; 365 } 366 367 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val) 368 { 369 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 370 const u8 line = sc16is7xx_line(port); 371 372 regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val); 373 } 374 375 static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen) 376 { 377 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 378 const u8 line = sc16is7xx_line(port); 379 u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line; 380 381 regcache_cache_bypass(s->regmap, true); 382 regmap_raw_read(s->regmap, addr, s->buf, rxlen); 383 regcache_cache_bypass(s->regmap, false); 384 } 385 386 static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send) 387 { 388 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 389 const u8 line = sc16is7xx_line(port); 390 u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | line; 391 392 regcache_cache_bypass(s->regmap, true); 393 regmap_raw_write(s->regmap, addr, s->buf, to_send); 394 regcache_cache_bypass(s->regmap, false); 395 } 396 397 static void sc16is7xx_port_update(struct uart_port *port, u8 reg, 398 u8 mask, u8 val) 399 { 400 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 401 const u8 line = sc16is7xx_line(port); 402 403 regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, 404 mask, val); 405 } 406 407 static int sc16is7xx_alloc_line(void) 408 { 409 int i; 410 411 BUILD_BUG_ON(SC16IS7XX_MAX_DEVS > BITS_PER_LONG); 412 413 for (i = 0; i < SC16IS7XX_MAX_DEVS; i++) 414 if (!test_and_set_bit(i, &sc16is7xx_lines)) 415 break; 416 417 return i; 418 } 419 420 static void sc16is7xx_power(struct uart_port *port, int on) 421 { 422 sc16is7xx_port_update(port, SC16IS7XX_IER_REG, 423 SC16IS7XX_IER_SLEEP_BIT, 424 on ? 0 : SC16IS7XX_IER_SLEEP_BIT); 425 } 426 427 static const struct sc16is7xx_devtype sc16is74x_devtype = { 428 .name = "SC16IS74X", 429 .nr_gpio = 0, 430 .nr_uart = 1, 431 }; 432 433 static const struct sc16is7xx_devtype sc16is750_devtype = { 434 .name = "SC16IS750", 435 .nr_gpio = 8, 436 .nr_uart = 1, 437 }; 438 439 static const struct sc16is7xx_devtype sc16is752_devtype = { 440 .name = "SC16IS752", 441 .nr_gpio = 8, 442 .nr_uart = 2, 443 }; 444 445 static const struct sc16is7xx_devtype sc16is760_devtype = { 446 .name = "SC16IS760", 447 .nr_gpio = 8, 448 .nr_uart = 1, 449 }; 450 451 static const struct sc16is7xx_devtype sc16is762_devtype = { 452 .name = "SC16IS762", 453 .nr_gpio = 8, 454 .nr_uart = 2, 455 }; 456 457 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg) 458 { 459 switch (reg >> SC16IS7XX_REG_SHIFT) { 460 case SC16IS7XX_RHR_REG: 461 case SC16IS7XX_IIR_REG: 462 case SC16IS7XX_LSR_REG: 463 case SC16IS7XX_MSR_REG: 464 case SC16IS7XX_TXLVL_REG: 465 case SC16IS7XX_RXLVL_REG: 466 case SC16IS7XX_IOSTATE_REG: 467 return true; 468 default: 469 break; 470 } 471 472 return false; 473 } 474 475 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg) 476 { 477 switch (reg >> SC16IS7XX_REG_SHIFT) { 478 case SC16IS7XX_RHR_REG: 479 return true; 480 default: 481 break; 482 } 483 484 return false; 485 } 486 487 static int sc16is7xx_set_baud(struct uart_port *port, int baud) 488 { 489 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 490 u8 lcr; 491 u8 prescaler = 0; 492 unsigned long clk = port->uartclk, div = clk / 16 / baud; 493 494 if (div > 0xffff) { 495 prescaler = SC16IS7XX_MCR_CLKSEL_BIT; 496 div /= 4; 497 } 498 499 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); 500 501 /* Open the LCR divisors for configuration */ 502 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 503 SC16IS7XX_LCR_CONF_MODE_B); 504 505 /* Enable enhanced features */ 506 regcache_cache_bypass(s->regmap, true); 507 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, 508 SC16IS7XX_EFR_ENABLE_BIT); 509 regcache_cache_bypass(s->regmap, false); 510 511 /* Put LCR back to the normal mode */ 512 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 513 514 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 515 SC16IS7XX_MCR_CLKSEL_BIT, 516 prescaler); 517 518 /* Open the LCR divisors for configuration */ 519 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 520 SC16IS7XX_LCR_CONF_MODE_A); 521 522 /* Write the new divisor */ 523 regcache_cache_bypass(s->regmap, true); 524 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256); 525 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256); 526 regcache_cache_bypass(s->regmap, false); 527 528 /* Put LCR back to the normal mode */ 529 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 530 531 return DIV_ROUND_CLOSEST(clk / 16, div); 532 } 533 534 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen, 535 unsigned int iir) 536 { 537 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 538 unsigned int lsr = 0, ch, flag, bytes_read, i; 539 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false; 540 541 if (unlikely(rxlen >= sizeof(s->buf))) { 542 dev_warn_ratelimited(port->dev, 543 "ttySC%i: Possible RX FIFO overrun: %d\n", 544 port->line, rxlen); 545 port->icount.buf_overrun++; 546 /* Ensure sanity of RX level */ 547 rxlen = sizeof(s->buf); 548 } 549 550 while (rxlen) { 551 /* Only read lsr if there are possible errors in FIFO */ 552 if (read_lsr) { 553 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 554 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT)) 555 read_lsr = false; /* No errors left in FIFO */ 556 } else 557 lsr = 0; 558 559 if (read_lsr) { 560 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG); 561 bytes_read = 1; 562 } else { 563 sc16is7xx_fifo_read(port, rxlen); 564 bytes_read = rxlen; 565 } 566 567 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK; 568 569 port->icount.rx++; 570 flag = TTY_NORMAL; 571 572 if (unlikely(lsr)) { 573 if (lsr & SC16IS7XX_LSR_BI_BIT) { 574 port->icount.brk++; 575 if (uart_handle_break(port)) 576 continue; 577 } else if (lsr & SC16IS7XX_LSR_PE_BIT) 578 port->icount.parity++; 579 else if (lsr & SC16IS7XX_LSR_FE_BIT) 580 port->icount.frame++; 581 else if (lsr & SC16IS7XX_LSR_OE_BIT) 582 port->icount.overrun++; 583 584 lsr &= port->read_status_mask; 585 if (lsr & SC16IS7XX_LSR_BI_BIT) 586 flag = TTY_BREAK; 587 else if (lsr & SC16IS7XX_LSR_PE_BIT) 588 flag = TTY_PARITY; 589 else if (lsr & SC16IS7XX_LSR_FE_BIT) 590 flag = TTY_FRAME; 591 else if (lsr & SC16IS7XX_LSR_OE_BIT) 592 flag = TTY_OVERRUN; 593 } 594 595 for (i = 0; i < bytes_read; ++i) { 596 ch = s->buf[i]; 597 if (uart_handle_sysrq_char(port, ch)) 598 continue; 599 600 if (lsr & port->ignore_status_mask) 601 continue; 602 603 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch, 604 flag); 605 } 606 rxlen -= bytes_read; 607 } 608 609 tty_flip_buffer_push(&port->state->port); 610 } 611 612 static void sc16is7xx_handle_tx(struct uart_port *port) 613 { 614 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 615 struct circ_buf *xmit = &port->state->xmit; 616 unsigned int txlen, to_send, i; 617 618 if (unlikely(port->x_char)) { 619 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char); 620 port->icount.tx++; 621 port->x_char = 0; 622 return; 623 } 624 625 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 626 return; 627 628 /* Get length of data pending in circular buffer */ 629 to_send = uart_circ_chars_pending(xmit); 630 if (likely(to_send)) { 631 /* Limit to size of TX FIFO */ 632 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG); 633 to_send = (to_send > txlen) ? txlen : to_send; 634 635 /* Add data to send */ 636 port->icount.tx += to_send; 637 638 /* Convert to linear buffer */ 639 for (i = 0; i < to_send; ++i) { 640 s->buf[i] = xmit->buf[xmit->tail]; 641 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 642 } 643 644 sc16is7xx_fifo_write(port, to_send); 645 } 646 647 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 648 uart_write_wakeup(port); 649 } 650 651 static void sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno) 652 { 653 struct uart_port *port = &s->p[portno].port; 654 655 do { 656 unsigned int iir, msr, rxlen; 657 658 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG); 659 if (iir & SC16IS7XX_IIR_NO_INT_BIT) 660 break; 661 662 iir &= SC16IS7XX_IIR_ID_MASK; 663 664 switch (iir) { 665 case SC16IS7XX_IIR_RDI_SRC: 666 case SC16IS7XX_IIR_RLSE_SRC: 667 case SC16IS7XX_IIR_RTOI_SRC: 668 case SC16IS7XX_IIR_XOFFI_SRC: 669 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); 670 if (rxlen) 671 sc16is7xx_handle_rx(port, rxlen, iir); 672 break; 673 674 case SC16IS7XX_IIR_CTSRTS_SRC: 675 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG); 676 uart_handle_cts_change(port, 677 !!(msr & SC16IS7XX_MSR_CTS_BIT)); 678 break; 679 case SC16IS7XX_IIR_THRI_SRC: 680 sc16is7xx_handle_tx(port); 681 break; 682 default: 683 dev_err_ratelimited(port->dev, 684 "ttySC%i: Unexpected interrupt: %x", 685 port->line, iir); 686 break; 687 } 688 } while (1); 689 } 690 691 static void sc16is7xx_ist(struct kthread_work *ws) 692 { 693 struct sc16is7xx_port *s = to_sc16is7xx_port(ws, irq_work); 694 int i; 695 696 for (i = 0; i < s->devtype->nr_uart; ++i) 697 sc16is7xx_port_irq(s, i); 698 } 699 700 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id) 701 { 702 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id; 703 704 queue_kthread_work(&s->kworker, &s->irq_work); 705 706 return IRQ_HANDLED; 707 } 708 709 static void sc16is7xx_tx_proc(struct kthread_work *ws) 710 { 711 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port); 712 713 if ((port->rs485.flags & SER_RS485_ENABLED) && 714 (port->rs485.delay_rts_before_send > 0)) 715 msleep(port->rs485.delay_rts_before_send); 716 717 sc16is7xx_handle_tx(port); 718 } 719 720 static void sc16is7xx_reconf_rs485(struct uart_port *port) 721 { 722 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT | 723 SC16IS7XX_EFCR_RTS_INVERT_BIT; 724 u32 efcr = 0; 725 struct serial_rs485 *rs485 = &port->rs485; 726 unsigned long irqflags; 727 728 spin_lock_irqsave(&port->lock, irqflags); 729 if (rs485->flags & SER_RS485_ENABLED) { 730 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT; 731 732 if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 733 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT; 734 } 735 spin_unlock_irqrestore(&port->lock, irqflags); 736 737 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr); 738 } 739 740 static void sc16is7xx_reg_proc(struct kthread_work *ws) 741 { 742 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work); 743 struct sc16is7xx_one_config config; 744 unsigned long irqflags; 745 746 spin_lock_irqsave(&one->port.lock, irqflags); 747 config = one->config; 748 memset(&one->config, 0, sizeof(one->config)); 749 spin_unlock_irqrestore(&one->port.lock, irqflags); 750 751 if (config.flags & SC16IS7XX_RECONF_MD) 752 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, 753 SC16IS7XX_MCR_LOOP_BIT, 754 (one->port.mctrl & TIOCM_LOOP) ? 755 SC16IS7XX_MCR_LOOP_BIT : 0); 756 757 if (config.flags & SC16IS7XX_RECONF_IER) 758 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG, 759 config.ier_clear, 0); 760 761 if (config.flags & SC16IS7XX_RECONF_RS485) 762 sc16is7xx_reconf_rs485(&one->port); 763 } 764 765 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit) 766 { 767 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 768 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 769 770 one->config.flags |= SC16IS7XX_RECONF_IER; 771 one->config.ier_clear |= bit; 772 queue_kthread_work(&s->kworker, &one->reg_work); 773 } 774 775 static void sc16is7xx_stop_tx(struct uart_port *port) 776 { 777 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT); 778 } 779 780 static void sc16is7xx_stop_rx(struct uart_port *port) 781 { 782 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 783 } 784 785 static void sc16is7xx_start_tx(struct uart_port *port) 786 { 787 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 788 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 789 790 queue_kthread_work(&s->kworker, &one->tx_work); 791 } 792 793 static unsigned int sc16is7xx_tx_empty(struct uart_port *port) 794 { 795 unsigned int lsr; 796 797 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 798 799 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0; 800 } 801 802 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port) 803 { 804 /* DCD and DSR are not wired and CTS/RTS is handled automatically 805 * so just indicate DSR and CAR asserted 806 */ 807 return TIOCM_DSR | TIOCM_CAR; 808 } 809 810 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl) 811 { 812 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 813 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 814 815 one->config.flags |= SC16IS7XX_RECONF_MD; 816 queue_kthread_work(&s->kworker, &one->reg_work); 817 } 818 819 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state) 820 { 821 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG, 822 SC16IS7XX_LCR_TXBREAK_BIT, 823 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0); 824 } 825 826 static void sc16is7xx_set_termios(struct uart_port *port, 827 struct ktermios *termios, 828 struct ktermios *old) 829 { 830 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 831 unsigned int lcr, flow = 0; 832 int baud; 833 834 /* Mask termios capabilities we don't support */ 835 termios->c_cflag &= ~CMSPAR; 836 837 /* Word size */ 838 switch (termios->c_cflag & CSIZE) { 839 case CS5: 840 lcr = SC16IS7XX_LCR_WORD_LEN_5; 841 break; 842 case CS6: 843 lcr = SC16IS7XX_LCR_WORD_LEN_6; 844 break; 845 case CS7: 846 lcr = SC16IS7XX_LCR_WORD_LEN_7; 847 break; 848 case CS8: 849 lcr = SC16IS7XX_LCR_WORD_LEN_8; 850 break; 851 default: 852 lcr = SC16IS7XX_LCR_WORD_LEN_8; 853 termios->c_cflag &= ~CSIZE; 854 termios->c_cflag |= CS8; 855 break; 856 } 857 858 /* Parity */ 859 if (termios->c_cflag & PARENB) { 860 lcr |= SC16IS7XX_LCR_PARITY_BIT; 861 if (!(termios->c_cflag & PARODD)) 862 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT; 863 } 864 865 /* Stop bits */ 866 if (termios->c_cflag & CSTOPB) 867 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */ 868 869 /* Set read status mask */ 870 port->read_status_mask = SC16IS7XX_LSR_OE_BIT; 871 if (termios->c_iflag & INPCK) 872 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT | 873 SC16IS7XX_LSR_FE_BIT; 874 if (termios->c_iflag & (BRKINT | PARMRK)) 875 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT; 876 877 /* Set status ignore mask */ 878 port->ignore_status_mask = 0; 879 if (termios->c_iflag & IGNBRK) 880 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT; 881 if (!(termios->c_cflag & CREAD)) 882 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK; 883 884 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 885 SC16IS7XX_LCR_CONF_MODE_B); 886 887 /* Configure flow control */ 888 regcache_cache_bypass(s->regmap, true); 889 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]); 890 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]); 891 if (termios->c_cflag & CRTSCTS) 892 flow |= SC16IS7XX_EFR_AUTOCTS_BIT | 893 SC16IS7XX_EFR_AUTORTS_BIT; 894 if (termios->c_iflag & IXON) 895 flow |= SC16IS7XX_EFR_SWFLOW3_BIT; 896 if (termios->c_iflag & IXOFF) 897 flow |= SC16IS7XX_EFR_SWFLOW1_BIT; 898 899 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow); 900 regcache_cache_bypass(s->regmap, false); 901 902 /* Update LCR register */ 903 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 904 905 /* Get baud rate generator configuration */ 906 baud = uart_get_baud_rate(port, termios, old, 907 port->uartclk / 16 / 4 / 0xffff, 908 port->uartclk / 16); 909 910 /* Setup baudrate generator */ 911 baud = sc16is7xx_set_baud(port, baud); 912 913 /* Update timeout according to new baud rate */ 914 uart_update_timeout(port, termios->c_cflag, baud); 915 } 916 917 static int sc16is7xx_config_rs485(struct uart_port *port, 918 struct serial_rs485 *rs485) 919 { 920 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 921 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 922 923 if (rs485->flags & SER_RS485_ENABLED) { 924 bool rts_during_rx, rts_during_tx; 925 926 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND; 927 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND; 928 929 if (rts_during_rx == rts_during_tx) 930 dev_err(port->dev, 931 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n", 932 rts_during_tx, rts_during_rx); 933 934 /* 935 * RTS signal is handled by HW, it's timing can't be influenced. 936 * However, it's sometimes useful to delay TX even without RTS 937 * control therefore we try to handle .delay_rts_before_send. 938 */ 939 if (rs485->delay_rts_after_send) 940 return -EINVAL; 941 } 942 943 port->rs485 = *rs485; 944 one->config.flags |= SC16IS7XX_RECONF_RS485; 945 queue_kthread_work(&s->kworker, &one->reg_work); 946 947 return 0; 948 } 949 950 static int sc16is7xx_startup(struct uart_port *port) 951 { 952 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 953 unsigned int val; 954 955 sc16is7xx_power(port, 1); 956 957 /* Reset FIFOs*/ 958 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT; 959 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val); 960 udelay(5); 961 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, 962 SC16IS7XX_FCR_FIFO_BIT); 963 964 /* Enable EFR */ 965 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 966 SC16IS7XX_LCR_CONF_MODE_B); 967 968 regcache_cache_bypass(s->regmap, true); 969 970 /* Enable write access to enhanced features and internal clock div */ 971 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, 972 SC16IS7XX_EFR_ENABLE_BIT); 973 974 /* Enable TCR/TLR */ 975 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 976 SC16IS7XX_MCR_TCRTLR_BIT, 977 SC16IS7XX_MCR_TCRTLR_BIT); 978 979 /* Configure flow control levels */ 980 /* Flow control halt level 48, resume level 24 */ 981 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG, 982 SC16IS7XX_TCR_RX_RESUME(24) | 983 SC16IS7XX_TCR_RX_HALT(48)); 984 985 regcache_cache_bypass(s->regmap, false); 986 987 /* Now, initialize the UART */ 988 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8); 989 990 /* Enable the Rx and Tx FIFO */ 991 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 992 SC16IS7XX_EFCR_RXDISABLE_BIT | 993 SC16IS7XX_EFCR_TXDISABLE_BIT, 994 0); 995 996 /* Enable RX, TX, CTS change interrupts */ 997 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT | 998 SC16IS7XX_IER_CTSI_BIT; 999 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); 1000 1001 return 0; 1002 } 1003 1004 static void sc16is7xx_shutdown(struct uart_port *port) 1005 { 1006 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1007 1008 /* Disable all interrupts */ 1009 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0); 1010 /* Disable TX/RX */ 1011 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1012 SC16IS7XX_EFCR_RXDISABLE_BIT | 1013 SC16IS7XX_EFCR_TXDISABLE_BIT, 1014 SC16IS7XX_EFCR_RXDISABLE_BIT | 1015 SC16IS7XX_EFCR_TXDISABLE_BIT); 1016 1017 sc16is7xx_power(port, 0); 1018 1019 flush_kthread_worker(&s->kworker); 1020 } 1021 1022 static const char *sc16is7xx_type(struct uart_port *port) 1023 { 1024 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1025 1026 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL; 1027 } 1028 1029 static int sc16is7xx_request_port(struct uart_port *port) 1030 { 1031 /* Do nothing */ 1032 return 0; 1033 } 1034 1035 static void sc16is7xx_config_port(struct uart_port *port, int flags) 1036 { 1037 if (flags & UART_CONFIG_TYPE) 1038 port->type = PORT_SC16IS7XX; 1039 } 1040 1041 static int sc16is7xx_verify_port(struct uart_port *port, 1042 struct serial_struct *s) 1043 { 1044 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX)) 1045 return -EINVAL; 1046 if (s->irq != port->irq) 1047 return -EINVAL; 1048 1049 return 0; 1050 } 1051 1052 static void sc16is7xx_pm(struct uart_port *port, unsigned int state, 1053 unsigned int oldstate) 1054 { 1055 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0); 1056 } 1057 1058 static void sc16is7xx_null_void(struct uart_port *port) 1059 { 1060 /* Do nothing */ 1061 } 1062 1063 static const struct uart_ops sc16is7xx_ops = { 1064 .tx_empty = sc16is7xx_tx_empty, 1065 .set_mctrl = sc16is7xx_set_mctrl, 1066 .get_mctrl = sc16is7xx_get_mctrl, 1067 .stop_tx = sc16is7xx_stop_tx, 1068 .start_tx = sc16is7xx_start_tx, 1069 .stop_rx = sc16is7xx_stop_rx, 1070 .break_ctl = sc16is7xx_break_ctl, 1071 .startup = sc16is7xx_startup, 1072 .shutdown = sc16is7xx_shutdown, 1073 .set_termios = sc16is7xx_set_termios, 1074 .type = sc16is7xx_type, 1075 .request_port = sc16is7xx_request_port, 1076 .release_port = sc16is7xx_null_void, 1077 .config_port = sc16is7xx_config_port, 1078 .verify_port = sc16is7xx_verify_port, 1079 .pm = sc16is7xx_pm, 1080 }; 1081 1082 #ifdef CONFIG_GPIOLIB 1083 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset) 1084 { 1085 unsigned int val; 1086 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port, 1087 gpio); 1088 struct uart_port *port = &s->p[0].port; 1089 1090 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1091 1092 return !!(val & BIT(offset)); 1093 } 1094 1095 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 1096 { 1097 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port, 1098 gpio); 1099 struct uart_port *port = &s->p[0].port; 1100 1101 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), 1102 val ? BIT(offset) : 0); 1103 } 1104 1105 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip, 1106 unsigned offset) 1107 { 1108 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port, 1109 gpio); 1110 struct uart_port *port = &s->p[0].port; 1111 1112 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0); 1113 1114 return 0; 1115 } 1116 1117 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, 1118 unsigned offset, int val) 1119 { 1120 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port, 1121 gpio); 1122 struct uart_port *port = &s->p[0].port; 1123 1124 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), 1125 val ? BIT(offset) : 0); 1126 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 1127 BIT(offset)); 1128 1129 return 0; 1130 } 1131 #endif 1132 1133 static int sc16is7xx_probe(struct device *dev, 1134 const struct sc16is7xx_devtype *devtype, 1135 struct regmap *regmap, int irq, unsigned long flags) 1136 { 1137 struct sched_param sched_param = { .sched_priority = MAX_RT_PRIO / 2 }; 1138 unsigned long freq, *pfreq = dev_get_platdata(dev); 1139 int i, ret; 1140 struct sc16is7xx_port *s; 1141 1142 if (IS_ERR(regmap)) 1143 return PTR_ERR(regmap); 1144 1145 /* Alloc port structure */ 1146 s = devm_kzalloc(dev, sizeof(*s) + 1147 sizeof(struct sc16is7xx_one) * devtype->nr_uart, 1148 GFP_KERNEL); 1149 if (!s) { 1150 dev_err(dev, "Error allocating port structure\n"); 1151 return -ENOMEM; 1152 } 1153 1154 s->clk = devm_clk_get(dev, NULL); 1155 if (IS_ERR(s->clk)) { 1156 if (pfreq) 1157 freq = *pfreq; 1158 else 1159 return PTR_ERR(s->clk); 1160 } else { 1161 clk_prepare_enable(s->clk); 1162 freq = clk_get_rate(s->clk); 1163 } 1164 1165 s->regmap = regmap; 1166 s->devtype = devtype; 1167 dev_set_drvdata(dev, s); 1168 1169 init_kthread_worker(&s->kworker); 1170 init_kthread_work(&s->irq_work, sc16is7xx_ist); 1171 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker, 1172 "sc16is7xx"); 1173 if (IS_ERR(s->kworker_task)) { 1174 ret = PTR_ERR(s->kworker_task); 1175 goto out_clk; 1176 } 1177 sched_setscheduler(s->kworker_task, SCHED_FIFO, &sched_param); 1178 1179 #ifdef CONFIG_GPIOLIB 1180 if (devtype->nr_gpio) { 1181 /* Setup GPIO cotroller */ 1182 s->gpio.owner = THIS_MODULE; 1183 s->gpio.dev = dev; 1184 s->gpio.label = dev_name(dev); 1185 s->gpio.direction_input = sc16is7xx_gpio_direction_input; 1186 s->gpio.get = sc16is7xx_gpio_get; 1187 s->gpio.direction_output = sc16is7xx_gpio_direction_output; 1188 s->gpio.set = sc16is7xx_gpio_set; 1189 s->gpio.base = -1; 1190 s->gpio.ngpio = devtype->nr_gpio; 1191 s->gpio.can_sleep = 1; 1192 ret = gpiochip_add(&s->gpio); 1193 if (ret) 1194 goto out_thread; 1195 } 1196 #endif 1197 1198 for (i = 0; i < devtype->nr_uart; ++i) { 1199 s->p[i].line = i; 1200 /* Initialize port data */ 1201 s->p[i].port.dev = dev; 1202 s->p[i].port.irq = irq; 1203 s->p[i].port.type = PORT_SC16IS7XX; 1204 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE; 1205 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1206 s->p[i].port.iotype = UPIO_PORT; 1207 s->p[i].port.uartclk = freq; 1208 s->p[i].port.rs485_config = sc16is7xx_config_rs485; 1209 s->p[i].port.ops = &sc16is7xx_ops; 1210 s->p[i].port.line = sc16is7xx_alloc_line(); 1211 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) { 1212 ret = -ENOMEM; 1213 goto out_ports; 1214 } 1215 1216 /* Disable all interrupts */ 1217 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0); 1218 /* Disable TX/RX */ 1219 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG, 1220 SC16IS7XX_EFCR_RXDISABLE_BIT | 1221 SC16IS7XX_EFCR_TXDISABLE_BIT); 1222 /* Initialize kthread work structs */ 1223 init_kthread_work(&s->p[i].tx_work, sc16is7xx_tx_proc); 1224 init_kthread_work(&s->p[i].reg_work, sc16is7xx_reg_proc); 1225 /* Register port */ 1226 uart_add_one_port(&sc16is7xx_uart, &s->p[i].port); 1227 /* Go to suspend mode */ 1228 sc16is7xx_power(&s->p[i].port, 0); 1229 } 1230 1231 /* Setup interrupt */ 1232 ret = devm_request_irq(dev, irq, sc16is7xx_irq, 1233 IRQF_ONESHOT | flags, dev_name(dev), s); 1234 if (!ret) 1235 return 0; 1236 1237 out_ports: 1238 for (i--; i >= 0; i--) { 1239 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1240 clear_bit(s->p[i].port.line, &sc16is7xx_lines); 1241 } 1242 1243 #ifdef CONFIG_GPIOLIB 1244 if (devtype->nr_gpio) 1245 gpiochip_remove(&s->gpio); 1246 1247 out_thread: 1248 #endif 1249 kthread_stop(s->kworker_task); 1250 1251 out_clk: 1252 if (!IS_ERR(s->clk)) 1253 clk_disable_unprepare(s->clk); 1254 1255 return ret; 1256 } 1257 1258 static int sc16is7xx_remove(struct device *dev) 1259 { 1260 struct sc16is7xx_port *s = dev_get_drvdata(dev); 1261 int i; 1262 1263 #ifdef CONFIG_GPIOLIB 1264 if (s->devtype->nr_gpio) 1265 gpiochip_remove(&s->gpio); 1266 #endif 1267 1268 for (i = 0; i < s->devtype->nr_uart; i++) { 1269 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1270 clear_bit(s->p[i].port.line, &sc16is7xx_lines); 1271 sc16is7xx_power(&s->p[i].port, 0); 1272 } 1273 1274 flush_kthread_worker(&s->kworker); 1275 kthread_stop(s->kworker_task); 1276 1277 if (!IS_ERR(s->clk)) 1278 clk_disable_unprepare(s->clk); 1279 1280 return 0; 1281 } 1282 1283 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = { 1284 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, }, 1285 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, }, 1286 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, }, 1287 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, }, 1288 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, }, 1289 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, }, 1290 { } 1291 }; 1292 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids); 1293 1294 static struct regmap_config regcfg = { 1295 .reg_bits = 7, 1296 .pad_bits = 1, 1297 .val_bits = 8, 1298 .cache_type = REGCACHE_RBTREE, 1299 .volatile_reg = sc16is7xx_regmap_volatile, 1300 .precious_reg = sc16is7xx_regmap_precious, 1301 }; 1302 1303 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1304 static int sc16is7xx_spi_probe(struct spi_device *spi) 1305 { 1306 const struct sc16is7xx_devtype *devtype; 1307 unsigned long flags = 0; 1308 struct regmap *regmap; 1309 int ret; 1310 1311 /* Setup SPI bus */ 1312 spi->bits_per_word = 8; 1313 /* only supports mode 0 on SC16IS762 */ 1314 spi->mode = spi->mode ? : SPI_MODE_0; 1315 spi->max_speed_hz = spi->max_speed_hz ? : 15000000; 1316 ret = spi_setup(spi); 1317 if (ret) 1318 return ret; 1319 1320 if (spi->dev.of_node) { 1321 const struct of_device_id *of_id = 1322 of_match_device(sc16is7xx_dt_ids, &spi->dev); 1323 1324 devtype = (struct sc16is7xx_devtype *)of_id->data; 1325 } else { 1326 const struct spi_device_id *id_entry = spi_get_device_id(spi); 1327 1328 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data; 1329 flags = IRQF_TRIGGER_FALLING; 1330 } 1331 1332 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) | 1333 (devtype->nr_uart - 1); 1334 regmap = devm_regmap_init_spi(spi, ®cfg); 1335 1336 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq, flags); 1337 } 1338 1339 static int sc16is7xx_spi_remove(struct spi_device *spi) 1340 { 1341 return sc16is7xx_remove(&spi->dev); 1342 } 1343 1344 static const struct spi_device_id sc16is7xx_spi_id_table[] = { 1345 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1346 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, }, 1347 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, }, 1348 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1349 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1350 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1351 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1352 { } 1353 }; 1354 1355 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table); 1356 1357 static struct spi_driver sc16is7xx_spi_uart_driver = { 1358 .driver = { 1359 .name = SC16IS7XX_NAME, 1360 .owner = THIS_MODULE, 1361 .of_match_table = of_match_ptr(sc16is7xx_dt_ids), 1362 }, 1363 .probe = sc16is7xx_spi_probe, 1364 .remove = sc16is7xx_spi_remove, 1365 .id_table = sc16is7xx_spi_id_table, 1366 }; 1367 1368 MODULE_ALIAS("spi:sc16is7xx"); 1369 #endif 1370 1371 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1372 static int sc16is7xx_i2c_probe(struct i2c_client *i2c, 1373 const struct i2c_device_id *id) 1374 { 1375 const struct sc16is7xx_devtype *devtype; 1376 unsigned long flags = 0; 1377 struct regmap *regmap; 1378 1379 if (i2c->dev.of_node) { 1380 const struct of_device_id *of_id = 1381 of_match_device(sc16is7xx_dt_ids, &i2c->dev); 1382 1383 devtype = (struct sc16is7xx_devtype *)of_id->data; 1384 } else { 1385 devtype = (struct sc16is7xx_devtype *)id->driver_data; 1386 flags = IRQF_TRIGGER_FALLING; 1387 } 1388 1389 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) | 1390 (devtype->nr_uart - 1); 1391 regmap = devm_regmap_init_i2c(i2c, ®cfg); 1392 1393 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq, flags); 1394 } 1395 1396 static int sc16is7xx_i2c_remove(struct i2c_client *client) 1397 { 1398 return sc16is7xx_remove(&client->dev); 1399 } 1400 1401 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = { 1402 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1403 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, }, 1404 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, }, 1405 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1406 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1407 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1408 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1409 { } 1410 }; 1411 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table); 1412 1413 static struct i2c_driver sc16is7xx_i2c_uart_driver = { 1414 .driver = { 1415 .name = SC16IS7XX_NAME, 1416 .of_match_table = of_match_ptr(sc16is7xx_dt_ids), 1417 }, 1418 .probe = sc16is7xx_i2c_probe, 1419 .remove = sc16is7xx_i2c_remove, 1420 .id_table = sc16is7xx_i2c_id_table, 1421 }; 1422 1423 MODULE_ALIAS("i2c:sc16is7xx"); 1424 #endif 1425 1426 static int __init sc16is7xx_init(void) 1427 { 1428 int ret; 1429 1430 ret = uart_register_driver(&sc16is7xx_uart); 1431 if (ret) { 1432 pr_err("Registering UART driver failed\n"); 1433 return ret; 1434 } 1435 1436 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1437 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver); 1438 if (ret < 0) { 1439 pr_err("failed to init sc16is7xx i2c --> %d\n", ret); 1440 return ret; 1441 } 1442 #endif 1443 1444 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1445 ret = spi_register_driver(&sc16is7xx_spi_uart_driver); 1446 if (ret < 0) { 1447 pr_err("failed to init sc16is7xx spi --> %d\n", ret); 1448 return ret; 1449 } 1450 #endif 1451 return ret; 1452 } 1453 module_init(sc16is7xx_init); 1454 1455 static void __exit sc16is7xx_exit(void) 1456 { 1457 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1458 i2c_del_driver(&sc16is7xx_i2c_uart_driver); 1459 #endif 1460 1461 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1462 spi_unregister_driver(&sc16is7xx_spi_uart_driver); 1463 #endif 1464 uart_unregister_driver(&sc16is7xx_uart); 1465 } 1466 module_exit(sc16is7xx_exit); 1467 1468 MODULE_LICENSE("GPL"); 1469 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>"); 1470 MODULE_DESCRIPTION("SC16IS7XX serial driver"); 1471