1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SC16IS7xx tty serial driver - common code 4 * 5 * Copyright (C) 2014 GridPoint 6 * Author: Jon Ringle <jringle@gridpoint.com> 7 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru> 8 */ 9 10 #undef DEFAULT_SYMBOL_NAMESPACE 11 #define DEFAULT_SYMBOL_NAMESPACE SERIAL_NXP_SC16IS7XX 12 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/export.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/idr.h> 19 #include <linux/kthread.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/module.h> 22 #include <linux/property.h> 23 #include <linux/regmap.h> 24 #include <linux/sched.h> 25 #include <linux/serial_core.h> 26 #include <linux/serial.h> 27 #include <linux/string.h> 28 #include <linux/tty.h> 29 #include <linux/tty_flip.h> 30 #include <linux/uaccess.h> 31 #include <linux/units.h> 32 33 #include "sc16is7xx.h" 34 35 #define SC16IS7XX_MAX_DEVS 8 36 37 /* SC16IS7XX register definitions */ 38 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */ 39 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */ 40 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */ 41 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */ 42 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */ 43 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */ 44 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */ 45 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */ 46 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */ 47 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */ 48 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */ 49 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */ 50 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction 51 * - only on 75x/76x 52 */ 53 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State 54 * - only on 75x/76x 55 */ 56 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable 57 * - only on 75x/76x 58 */ 59 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control 60 * - only on 75x/76x 61 */ 62 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */ 63 64 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */ 65 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */ 66 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */ 67 68 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */ 69 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */ 70 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */ 71 72 /* Enhanced Register set: Only if (LCR == 0xBF) */ 73 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */ 74 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */ 75 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */ 76 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */ 77 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */ 78 79 /* IER register bits */ 80 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */ 81 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register 82 * interrupt */ 83 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status 84 * interrupt */ 85 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status 86 * interrupt */ 87 88 /* IER register bits - write only if (EFR[4] == 1) */ 89 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */ 90 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */ 91 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */ 92 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */ 93 94 /* FCR register bits */ 95 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */ 96 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */ 97 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */ 98 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */ 99 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */ 100 101 /* FCR register bits - write only if (EFR[4] == 1) */ 102 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */ 103 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */ 104 105 /* IIR register bits */ 106 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */ 107 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */ 108 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */ 109 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */ 110 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */ 111 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */ 112 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt 113 * - only on 75x/76x 114 */ 115 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state 116 * - only on 75x/76x 117 */ 118 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */ 119 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state 120 * from active (LOW) 121 * to inactive (HIGH) 122 */ 123 /* LCR register bits */ 124 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 125 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 126 * 127 * Word length bits table: 128 * 00 -> 5 bit words 129 * 01 -> 6 bit words 130 * 10 -> 7 bit words 131 * 11 -> 8 bit words 132 */ 133 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 134 * 135 * STOP length bit table: 136 * 0 -> 1 stop bit 137 * 1 -> 1-1.5 stop bits if 138 * word length is 5, 139 * 2 stop bits otherwise 140 */ 141 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 142 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 143 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 144 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 145 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */ 146 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00) 147 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01) 148 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02) 149 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03) 150 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special 151 * reg set */ 152 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced 153 * reg set */ 154 155 /* MCR register bits */ 156 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement 157 * - only on 75x/76x 158 */ 159 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */ 160 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */ 161 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */ 162 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any 163 * - write enabled 164 * if (EFR[4] == 1) 165 */ 166 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode 167 * - write enabled 168 * if (EFR[4] == 1) 169 */ 170 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4 171 * - write enabled 172 * if (EFR[4] == 1) 173 */ 174 175 /* LSR register bits */ 176 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */ 177 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */ 178 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */ 179 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */ 180 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */ 181 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */ 182 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */ 183 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */ 184 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */ 185 186 /* MSR register bits */ 187 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */ 188 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready 189 * or (IO4) 190 * - only on 75x/76x 191 */ 192 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator 193 * or (IO7) 194 * - only on 75x/76x 195 */ 196 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect 197 * or (IO6) 198 * - only on 75x/76x 199 */ 200 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */ 201 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4) 202 * - only on 75x/76x 203 */ 204 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7) 205 * - only on 75x/76x 206 */ 207 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6) 208 * - only on 75x/76x 209 */ 210 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */ 211 212 /* 213 * TCR register bits 214 * TCR trigger levels are available from 0 to 60 characters with a granularity 215 * of four. 216 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is 217 * no built-in hardware check to make sure this condition is met. Also, the TCR 218 * must be programmed with this condition before auto RTS or software flow 219 * control is enabled to avoid spurious operation of the device. 220 */ 221 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0) 222 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4) 223 224 /* 225 * TLR register bits 226 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the 227 * FIFO Control Register (FCR) are used for the transmit and receive FIFO 228 * trigger levels. Trigger levels from 4 characters to 60 characters are 229 * available with a granularity of four. 230 * 231 * When the trigger level setting in TLR is zero, the SC16IS74x/75x/76x uses the 232 * trigger level setting defined in FCR. If TLR has non-zero trigger level value 233 * the trigger level defined in FCR is discarded. This applies to both transmit 234 * FIFO and receive FIFO trigger level setting. 235 * 236 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the 237 * default state, that is, '00'. 238 */ 239 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0) 240 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) 241 242 /* IOControl register bits (Only 75x/76x) */ 243 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ 244 #define SC16IS7XX_IOCONTROL_MODEM_A_BIT (1 << 1) /* Enable GPIO[7:4] as modem A pins */ 245 #define SC16IS7XX_IOCONTROL_MODEM_B_BIT (1 << 2) /* Enable GPIO[3:0] as modem B pins */ 246 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */ 247 248 /* EFCR register bits */ 249 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop 250 * mode (RS485) */ 251 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */ 252 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */ 253 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */ 254 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */ 255 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode 256 * 0 = rate upto 115.2 kbit/s 257 * - Only 75x/76x 258 * 1 = rate upto 1.152 Mbit/s 259 * - Only 76x 260 */ 261 262 /* EFR register bits */ 263 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */ 264 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */ 265 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */ 266 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions 267 * and writing to IER[7:4], 268 * FCR[5:4], MCR[7:5] 269 */ 270 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */ 271 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2 272 * 273 * SWFLOW bits 3 & 2 table: 274 * 00 -> no transmitter flow 275 * control 276 * 01 -> transmitter generates 277 * XON2 and XOFF2 278 * 10 -> transmitter generates 279 * XON1 and XOFF1 280 * 11 -> transmitter generates 281 * XON1, XON2, XOFF1 and 282 * XOFF2 283 */ 284 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */ 285 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3 286 * 287 * SWFLOW bits 3 & 2 table: 288 * 00 -> no received flow 289 * control 290 * 01 -> receiver compares 291 * XON2 and XOFF2 292 * 10 -> receiver compares 293 * XON1 and XOFF1 294 * 11 -> receiver compares 295 * XON1, XON2, XOFF1 and 296 * XOFF2 297 */ 298 #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \ 299 SC16IS7XX_EFR_AUTOCTS_BIT | \ 300 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \ 301 SC16IS7XX_EFR_SWFLOW3_BIT | \ 302 SC16IS7XX_EFR_SWFLOW2_BIT | \ 303 SC16IS7XX_EFR_SWFLOW1_BIT | \ 304 SC16IS7XX_EFR_SWFLOW0_BIT) 305 306 307 /* Misc definitions */ 308 #define SC16IS7XX_FIFO_SIZE (64) 309 #define SC16IS7XX_GPIOS_PER_BANK 4 310 311 #define SC16IS7XX_RECONF_MD (1 << 0) 312 #define SC16IS7XX_RECONF_IER (1 << 1) 313 #define SC16IS7XX_RECONF_RS485 (1 << 2) 314 315 struct sc16is7xx_one_config { 316 unsigned int flags; 317 u8 ier_mask; 318 u8 ier_val; 319 }; 320 321 struct sc16is7xx_one { 322 struct uart_port port; 323 struct regmap *regmap; 324 struct mutex efr_lock; /* EFR registers access */ 325 struct kthread_work tx_work; 326 struct kthread_work reg_work; 327 struct kthread_delayed_work ms_work; 328 struct sc16is7xx_one_config config; 329 unsigned int old_mctrl; 330 u8 old_lcr; /* Value before EFR access. */ 331 bool irda_mode; 332 }; 333 334 struct sc16is7xx_port { 335 const struct sc16is7xx_devtype *devtype; 336 struct clk *clk; 337 #ifdef CONFIG_GPIOLIB 338 struct gpio_chip gpio; 339 unsigned long gpio_valid_mask; 340 #endif 341 u8 mctrl_mask; 342 unsigned char buf[SC16IS7XX_FIFO_SIZE]; 343 struct kthread_worker kworker; 344 struct task_struct *kworker_task; 345 struct sc16is7xx_one p[]; 346 }; 347 348 static DEFINE_IDA(sc16is7xx_lines); 349 350 static struct uart_driver sc16is7xx_uart = { 351 .owner = THIS_MODULE, 352 .driver_name = SC16IS7XX_NAME, 353 .dev_name = "ttySC", 354 .nr = SC16IS7XX_MAX_DEVS, 355 }; 356 357 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e))) 358 359 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg) 360 { 361 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 362 unsigned int val = 0; 363 364 regmap_read(one->regmap, reg, &val); 365 366 return val; 367 } 368 369 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val) 370 { 371 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 372 373 regmap_write(one->regmap, reg, val); 374 } 375 376 static void sc16is7xx_fifo_read(struct uart_port *port, u8 *rxbuf, unsigned int rxlen) 377 { 378 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 379 380 regmap_noinc_read(one->regmap, SC16IS7XX_RHR_REG, rxbuf, rxlen); 381 } 382 383 static void sc16is7xx_fifo_write(struct uart_port *port, u8 *txbuf, u8 to_send) 384 { 385 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 386 387 /* 388 * Don't send zero-length data, at least on SPI it confuses the chip 389 * delivering wrong TXLVL data. 390 */ 391 if (unlikely(!to_send)) 392 return; 393 394 regmap_noinc_write(one->regmap, SC16IS7XX_THR_REG, txbuf, to_send); 395 } 396 397 static void sc16is7xx_port_update(struct uart_port *port, u8 reg, 398 u8 mask, u8 val) 399 { 400 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 401 402 regmap_update_bits(one->regmap, reg, mask, val); 403 } 404 405 static void sc16is7xx_power(struct uart_port *port, int on) 406 { 407 sc16is7xx_port_update(port, SC16IS7XX_IER_REG, 408 SC16IS7XX_IER_SLEEP_BIT, 409 on ? 0 : SC16IS7XX_IER_SLEEP_BIT); 410 } 411 412 /* 413 * In an amazing feat of design, the Enhanced Features Register (EFR) 414 * shares the address of the Interrupt Identification Register (IIR). 415 * Access to EFR is switched on by writing a magic value (0xbf) to the 416 * Line Control Register (LCR). Any interrupt firing during this time will 417 * see the EFR where it expects the IIR to be, leading to 418 * "Unexpected interrupt" messages. 419 * 420 * Prevent this possibility by claiming a mutex while accessing the EFR, 421 * and claiming the same mutex from within the interrupt handler. This is 422 * similar to disabling the interrupt, but that doesn't work because the 423 * bulk of the interrupt processing is run as a workqueue job in thread 424 * context. 425 */ 426 static void sc16is7xx_efr_lock(struct uart_port *port) 427 { 428 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 429 430 mutex_lock(&one->efr_lock); 431 432 /* Backup content of LCR. */ 433 one->old_lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); 434 435 /* Enable access to Enhanced register set */ 436 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_CONF_MODE_B); 437 438 /* Disable cache updates when writing to EFR registers */ 439 regcache_cache_bypass(one->regmap, true); 440 } 441 442 static void sc16is7xx_efr_unlock(struct uart_port *port) 443 { 444 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 445 446 /* Re-enable cache updates when writing to normal registers */ 447 regcache_cache_bypass(one->regmap, false); 448 449 /* Restore original content of LCR */ 450 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, one->old_lcr); 451 452 mutex_unlock(&one->efr_lock); 453 } 454 455 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit) 456 { 457 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 458 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 459 460 lockdep_assert_held_once(&port->lock); 461 462 one->config.flags |= SC16IS7XX_RECONF_IER; 463 one->config.ier_mask |= bit; 464 one->config.ier_val &= ~bit; 465 kthread_queue_work(&s->kworker, &one->reg_work); 466 } 467 468 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit) 469 { 470 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 471 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 472 473 lockdep_assert_held_once(&port->lock); 474 475 one->config.flags |= SC16IS7XX_RECONF_IER; 476 one->config.ier_mask |= bit; 477 one->config.ier_val |= bit; 478 kthread_queue_work(&s->kworker, &one->reg_work); 479 } 480 481 static void sc16is7xx_stop_tx(struct uart_port *port) 482 { 483 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT); 484 } 485 486 static void sc16is7xx_stop_rx(struct uart_port *port) 487 { 488 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 489 } 490 491 const struct sc16is7xx_devtype sc16is74x_devtype = { 492 .name = "SC16IS74X", 493 .nr_gpio = 0, 494 .nr_uart = 1, 495 }; 496 EXPORT_SYMBOL_GPL(sc16is74x_devtype); 497 498 const struct sc16is7xx_devtype sc16is750_devtype = { 499 .name = "SC16IS750", 500 .nr_gpio = 8, 501 .nr_uart = 1, 502 }; 503 EXPORT_SYMBOL_GPL(sc16is750_devtype); 504 505 const struct sc16is7xx_devtype sc16is752_devtype = { 506 .name = "SC16IS752", 507 .nr_gpio = 8, 508 .nr_uart = 2, 509 }; 510 EXPORT_SYMBOL_GPL(sc16is752_devtype); 511 512 const struct sc16is7xx_devtype sc16is760_devtype = { 513 .name = "SC16IS760", 514 .nr_gpio = 8, 515 .nr_uart = 1, 516 }; 517 EXPORT_SYMBOL_GPL(sc16is760_devtype); 518 519 const struct sc16is7xx_devtype sc16is762_devtype = { 520 .name = "SC16IS762", 521 .nr_gpio = 8, 522 .nr_uart = 2, 523 }; 524 EXPORT_SYMBOL_GPL(sc16is762_devtype); 525 526 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg) 527 { 528 switch (reg) { 529 case SC16IS7XX_RHR_REG: 530 case SC16IS7XX_IIR_REG: 531 case SC16IS7XX_LSR_REG: 532 case SC16IS7XX_MSR_REG: 533 case SC16IS7XX_TXLVL_REG: 534 case SC16IS7XX_RXLVL_REG: 535 case SC16IS7XX_IOSTATE_REG: 536 case SC16IS7XX_IOCONTROL_REG: 537 return true; 538 default: 539 return false; 540 } 541 } 542 543 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg) 544 { 545 switch (reg) { 546 case SC16IS7XX_RHR_REG: 547 return true; 548 default: 549 return false; 550 } 551 } 552 553 static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg) 554 { 555 return reg == SC16IS7XX_RHR_REG; 556 } 557 558 static int sc16is7xx_set_baud(struct uart_port *port, int baud) 559 { 560 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 561 u8 lcr; 562 u8 prescaler = 0; 563 unsigned long clk = port->uartclk, div = clk / 16 / baud; 564 565 if (div >= BIT(16)) { 566 prescaler = SC16IS7XX_MCR_CLKSEL_BIT; 567 div /= 4; 568 } 569 570 /* Enable enhanced features */ 571 sc16is7xx_efr_lock(port); 572 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 573 SC16IS7XX_EFR_ENABLE_BIT, 574 SC16IS7XX_EFR_ENABLE_BIT); 575 sc16is7xx_efr_unlock(port); 576 577 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 578 SC16IS7XX_MCR_CLKSEL_BIT, 579 prescaler); 580 581 /* Backup LCR and access special register set (DLL/DLH) */ 582 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); 583 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 584 SC16IS7XX_LCR_CONF_MODE_A); 585 586 /* Write the new divisor */ 587 regcache_cache_bypass(one->regmap, true); 588 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256); 589 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256); 590 regcache_cache_bypass(one->regmap, false); 591 592 /* Restore LCR and access to general register set */ 593 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 594 595 return DIV_ROUND_CLOSEST(clk / 16, div); 596 } 597 598 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen, 599 unsigned int iir) 600 { 601 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 602 unsigned int lsr = 0, bytes_read, i; 603 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false; 604 u8 ch, flag; 605 606 if (unlikely(rxlen >= sizeof(s->buf))) { 607 dev_warn_ratelimited(port->dev, 608 "ttySC%i: Possible RX FIFO overrun: %d\n", 609 port->line, rxlen); 610 port->icount.buf_overrun++; 611 /* Ensure sanity of RX level */ 612 rxlen = sizeof(s->buf); 613 } 614 615 while (rxlen) { 616 /* Only read lsr if there are possible errors in FIFO */ 617 if (read_lsr) { 618 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 619 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT)) 620 read_lsr = false; /* No errors left in FIFO */ 621 } else 622 lsr = 0; 623 624 if (read_lsr) { 625 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG); 626 bytes_read = 1; 627 } else { 628 sc16is7xx_fifo_read(port, s->buf, rxlen); 629 bytes_read = rxlen; 630 } 631 632 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK; 633 634 port->icount.rx++; 635 flag = TTY_NORMAL; 636 637 if (unlikely(lsr)) { 638 if (lsr & SC16IS7XX_LSR_BI_BIT) { 639 port->icount.brk++; 640 if (uart_handle_break(port)) 641 continue; 642 } else if (lsr & SC16IS7XX_LSR_PE_BIT) 643 port->icount.parity++; 644 else if (lsr & SC16IS7XX_LSR_FE_BIT) 645 port->icount.frame++; 646 else if (lsr & SC16IS7XX_LSR_OE_BIT) 647 port->icount.overrun++; 648 649 lsr &= port->read_status_mask; 650 if (lsr & SC16IS7XX_LSR_BI_BIT) 651 flag = TTY_BREAK; 652 else if (lsr & SC16IS7XX_LSR_PE_BIT) 653 flag = TTY_PARITY; 654 else if (lsr & SC16IS7XX_LSR_FE_BIT) 655 flag = TTY_FRAME; 656 else if (lsr & SC16IS7XX_LSR_OE_BIT) 657 flag = TTY_OVERRUN; 658 } 659 660 for (i = 0; i < bytes_read; ++i) { 661 ch = s->buf[i]; 662 if (uart_handle_sysrq_char(port, ch)) 663 continue; 664 665 if (lsr & port->ignore_status_mask) 666 continue; 667 668 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch, 669 flag); 670 } 671 rxlen -= bytes_read; 672 } 673 674 tty_flip_buffer_push(&port->state->port); 675 } 676 677 static void sc16is7xx_handle_tx(struct uart_port *port) 678 { 679 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 680 struct tty_port *tport = &port->state->port; 681 unsigned long flags; 682 unsigned int txlen; 683 684 if (unlikely(port->x_char)) { 685 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char); 686 port->icount.tx++; 687 port->x_char = 0; 688 return; 689 } 690 691 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) { 692 uart_port_lock_irqsave(port, &flags); 693 sc16is7xx_stop_tx(port); 694 uart_port_unlock_irqrestore(port, flags); 695 return; 696 } 697 698 /* Limit to space available in TX FIFO */ 699 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG); 700 if (txlen > SC16IS7XX_FIFO_SIZE) { 701 dev_err_ratelimited(port->dev, 702 "chip reports %d free bytes in TX fifo, but it only has %d", 703 txlen, SC16IS7XX_FIFO_SIZE); 704 txlen = 0; 705 } 706 707 txlen = uart_fifo_out(port, s->buf, txlen); 708 sc16is7xx_fifo_write(port, s->buf, txlen); 709 710 uart_port_lock_irqsave(port, &flags); 711 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 712 uart_write_wakeup(port); 713 714 if (kfifo_is_empty(&tport->xmit_fifo)) 715 sc16is7xx_stop_tx(port); 716 else 717 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT); 718 uart_port_unlock_irqrestore(port, flags); 719 } 720 721 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port) 722 { 723 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG); 724 unsigned int mctrl = 0; 725 726 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0; 727 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0; 728 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0; 729 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0; 730 return mctrl; 731 } 732 733 static void sc16is7xx_update_mlines(struct sc16is7xx_one *one) 734 { 735 struct uart_port *port = &one->port; 736 unsigned long flags; 737 unsigned int status, changed; 738 739 lockdep_assert_held_once(&one->efr_lock); 740 741 status = sc16is7xx_get_hwmctrl(port); 742 changed = status ^ one->old_mctrl; 743 744 if (changed == 0) 745 return; 746 747 one->old_mctrl = status; 748 749 uart_port_lock_irqsave(port, &flags); 750 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG)) 751 port->icount.rng++; 752 if (changed & TIOCM_DSR) 753 port->icount.dsr++; 754 if (changed & TIOCM_CAR) 755 uart_handle_dcd_change(port, status & TIOCM_CAR); 756 if (changed & TIOCM_CTS) 757 uart_handle_cts_change(port, status & TIOCM_CTS); 758 759 wake_up_interruptible(&port->state->port.delta_msr_wait); 760 uart_port_unlock_irqrestore(port, flags); 761 } 762 763 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno) 764 { 765 bool rc = true; 766 unsigned int iir, rxlen; 767 struct uart_port *port = &s->p[portno].port; 768 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 769 770 mutex_lock(&one->efr_lock); 771 772 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG); 773 if (iir & SC16IS7XX_IIR_NO_INT_BIT) { 774 rc = false; 775 goto out_port_irq; 776 } 777 778 iir &= SC16IS7XX_IIR_ID_MASK; 779 780 switch (iir) { 781 case SC16IS7XX_IIR_RDI_SRC: 782 case SC16IS7XX_IIR_RLSE_SRC: 783 case SC16IS7XX_IIR_RTOI_SRC: 784 case SC16IS7XX_IIR_XOFFI_SRC: 785 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); 786 787 /* 788 * There is a silicon bug that makes the chip report a 789 * time-out interrupt but no data in the FIFO. This is 790 * described in errata section 18.1.4. 791 * 792 * When this happens, read one byte from the FIFO to 793 * clear the interrupt. 794 */ 795 if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen) 796 rxlen = 1; 797 798 if (rxlen) 799 sc16is7xx_handle_rx(port, rxlen, iir); 800 break; 801 /* CTSRTS interrupt comes only when CTS goes inactive */ 802 case SC16IS7XX_IIR_CTSRTS_SRC: 803 case SC16IS7XX_IIR_MSI_SRC: 804 sc16is7xx_update_mlines(one); 805 break; 806 case SC16IS7XX_IIR_THRI_SRC: 807 sc16is7xx_handle_tx(port); 808 break; 809 default: 810 dev_err_ratelimited(port->dev, 811 "ttySC%i: Unexpected interrupt: %x", 812 port->line, iir); 813 break; 814 } 815 816 out_port_irq: 817 mutex_unlock(&one->efr_lock); 818 819 return rc; 820 } 821 822 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id) 823 { 824 bool keep_polling; 825 826 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id; 827 828 do { 829 int i; 830 831 keep_polling = false; 832 833 for (i = 0; i < s->devtype->nr_uart; ++i) 834 keep_polling |= sc16is7xx_port_irq(s, i); 835 } while (keep_polling); 836 837 return IRQ_HANDLED; 838 } 839 840 static void sc16is7xx_tx_proc(struct kthread_work *ws) 841 { 842 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port); 843 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 844 845 if ((port->rs485.flags & SER_RS485_ENABLED) && 846 (port->rs485.delay_rts_before_send > 0)) 847 msleep(port->rs485.delay_rts_before_send); 848 849 mutex_lock(&one->efr_lock); 850 sc16is7xx_handle_tx(port); 851 mutex_unlock(&one->efr_lock); 852 } 853 854 static void sc16is7xx_reconf_rs485(struct uart_port *port) 855 { 856 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT | 857 SC16IS7XX_EFCR_RTS_INVERT_BIT; 858 u32 efcr = 0; 859 struct serial_rs485 *rs485 = &port->rs485; 860 unsigned long irqflags; 861 862 uart_port_lock_irqsave(port, &irqflags); 863 if (rs485->flags & SER_RS485_ENABLED) { 864 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT; 865 866 if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 867 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT; 868 } 869 uart_port_unlock_irqrestore(port, irqflags); 870 871 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr); 872 } 873 874 static void sc16is7xx_reg_proc(struct kthread_work *ws) 875 { 876 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work); 877 struct sc16is7xx_one_config config; 878 unsigned long irqflags; 879 880 uart_port_lock_irqsave(&one->port, &irqflags); 881 config = one->config; 882 memset(&one->config, 0, sizeof(one->config)); 883 uart_port_unlock_irqrestore(&one->port, irqflags); 884 885 if (config.flags & SC16IS7XX_RECONF_MD) { 886 u8 mcr = 0; 887 888 /* Device ignores RTS setting when hardware flow is enabled */ 889 if (one->port.mctrl & TIOCM_RTS) 890 mcr |= SC16IS7XX_MCR_RTS_BIT; 891 892 if (one->port.mctrl & TIOCM_DTR) 893 mcr |= SC16IS7XX_MCR_DTR_BIT; 894 895 if (one->port.mctrl & TIOCM_LOOP) 896 mcr |= SC16IS7XX_MCR_LOOP_BIT; 897 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, 898 SC16IS7XX_MCR_RTS_BIT | 899 SC16IS7XX_MCR_DTR_BIT | 900 SC16IS7XX_MCR_LOOP_BIT, 901 mcr); 902 } 903 904 if (config.flags & SC16IS7XX_RECONF_IER) 905 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG, 906 config.ier_mask, config.ier_val); 907 908 if (config.flags & SC16IS7XX_RECONF_RS485) 909 sc16is7xx_reconf_rs485(&one->port); 910 } 911 912 static void sc16is7xx_ms_proc(struct kthread_work *ws) 913 { 914 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work); 915 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev); 916 917 if (one->port.state) { 918 mutex_lock(&one->efr_lock); 919 sc16is7xx_update_mlines(one); 920 mutex_unlock(&one->efr_lock); 921 922 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ); 923 } 924 } 925 926 static void sc16is7xx_enable_ms(struct uart_port *port) 927 { 928 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 929 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 930 931 lockdep_assert_held_once(&port->lock); 932 933 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0); 934 } 935 936 static void sc16is7xx_start_tx(struct uart_port *port) 937 { 938 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 939 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 940 941 kthread_queue_work(&s->kworker, &one->tx_work); 942 } 943 944 static void sc16is7xx_throttle(struct uart_port *port) 945 { 946 unsigned long flags; 947 948 /* 949 * Hardware flow control is enabled and thus the device ignores RTS 950 * value set in MCR register. Stop reading data from RX FIFO so the 951 * AutoRTS feature will de-activate RTS output. 952 */ 953 uart_port_lock_irqsave(port, &flags); 954 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 955 uart_port_unlock_irqrestore(port, flags); 956 } 957 958 static void sc16is7xx_unthrottle(struct uart_port *port) 959 { 960 unsigned long flags; 961 962 uart_port_lock_irqsave(port, &flags); 963 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT); 964 uart_port_unlock_irqrestore(port, flags); 965 } 966 967 static unsigned int sc16is7xx_tx_empty(struct uart_port *port) 968 { 969 unsigned int lsr; 970 971 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 972 973 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0; 974 } 975 976 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port) 977 { 978 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 979 980 /* Called with port lock taken so we can only return cached value */ 981 return one->old_mctrl; 982 } 983 984 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl) 985 { 986 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 987 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 988 989 one->config.flags |= SC16IS7XX_RECONF_MD; 990 kthread_queue_work(&s->kworker, &one->reg_work); 991 } 992 993 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state) 994 { 995 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG, 996 SC16IS7XX_LCR_TXBREAK_BIT, 997 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0); 998 } 999 1000 static void sc16is7xx_set_termios(struct uart_port *port, 1001 struct ktermios *termios, 1002 const struct ktermios *old) 1003 { 1004 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1005 unsigned int lcr, flow = 0; 1006 int baud; 1007 unsigned long flags; 1008 1009 kthread_cancel_delayed_work_sync(&one->ms_work); 1010 1011 /* Mask termios capabilities we don't support */ 1012 termios->c_cflag &= ~CMSPAR; 1013 1014 /* Word size */ 1015 switch (termios->c_cflag & CSIZE) { 1016 case CS5: 1017 lcr = SC16IS7XX_LCR_WORD_LEN_5; 1018 break; 1019 case CS6: 1020 lcr = SC16IS7XX_LCR_WORD_LEN_6; 1021 break; 1022 case CS7: 1023 lcr = SC16IS7XX_LCR_WORD_LEN_7; 1024 break; 1025 case CS8: 1026 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1027 break; 1028 default: 1029 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1030 termios->c_cflag &= ~CSIZE; 1031 termios->c_cflag |= CS8; 1032 break; 1033 } 1034 1035 /* Parity */ 1036 if (termios->c_cflag & PARENB) { 1037 lcr |= SC16IS7XX_LCR_PARITY_BIT; 1038 if (!(termios->c_cflag & PARODD)) 1039 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT; 1040 } 1041 1042 /* Stop bits */ 1043 if (termios->c_cflag & CSTOPB) 1044 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */ 1045 1046 /* Set read status mask */ 1047 port->read_status_mask = SC16IS7XX_LSR_OE_BIT; 1048 if (termios->c_iflag & INPCK) 1049 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT | 1050 SC16IS7XX_LSR_FE_BIT; 1051 if (termios->c_iflag & (BRKINT | PARMRK)) 1052 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT; 1053 1054 /* Set status ignore mask */ 1055 port->ignore_status_mask = 0; 1056 if (termios->c_iflag & IGNBRK) 1057 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT; 1058 if (!(termios->c_cflag & CREAD)) 1059 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK; 1060 1061 /* Configure flow control */ 1062 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1063 if (termios->c_cflag & CRTSCTS) { 1064 flow |= SC16IS7XX_EFR_AUTOCTS_BIT | 1065 SC16IS7XX_EFR_AUTORTS_BIT; 1066 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1067 } 1068 if (termios->c_iflag & IXON) 1069 flow |= SC16IS7XX_EFR_SWFLOW3_BIT; 1070 if (termios->c_iflag & IXOFF) 1071 flow |= SC16IS7XX_EFR_SWFLOW1_BIT; 1072 1073 /* Update LCR register */ 1074 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 1075 1076 /* Update EFR registers */ 1077 sc16is7xx_efr_lock(port); 1078 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]); 1079 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]); 1080 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 1081 SC16IS7XX_EFR_FLOWCTRL_BITS, flow); 1082 sc16is7xx_efr_unlock(port); 1083 1084 /* Get baud rate generator configuration */ 1085 baud = uart_get_baud_rate(port, termios, old, 1086 port->uartclk / 16 / 4 / 0xffff, 1087 port->uartclk / 16); 1088 1089 /* Setup baudrate generator */ 1090 baud = sc16is7xx_set_baud(port, baud); 1091 1092 uart_port_lock_irqsave(port, &flags); 1093 1094 /* Update timeout according to new baud rate */ 1095 uart_update_timeout(port, termios->c_cflag, baud); 1096 1097 if (UART_ENABLE_MS(port, termios->c_cflag)) 1098 sc16is7xx_enable_ms(port); 1099 1100 uart_port_unlock_irqrestore(port, flags); 1101 } 1102 1103 static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios, 1104 struct serial_rs485 *rs485) 1105 { 1106 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1107 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1108 1109 if (rs485->flags & SER_RS485_ENABLED) { 1110 /* 1111 * RTS signal is handled by HW, it's timing can't be influenced. 1112 * However, it's sometimes useful to delay TX even without RTS 1113 * control therefore we try to handle .delay_rts_before_send. 1114 */ 1115 if (rs485->delay_rts_after_send) 1116 return -EINVAL; 1117 } 1118 1119 one->config.flags |= SC16IS7XX_RECONF_RS485; 1120 kthread_queue_work(&s->kworker, &one->reg_work); 1121 1122 return 0; 1123 } 1124 1125 static int sc16is7xx_startup(struct uart_port *port) 1126 { 1127 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1128 unsigned int val; 1129 unsigned long flags; 1130 1131 sc16is7xx_power(port, 1); 1132 1133 /* Reset FIFOs*/ 1134 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT; 1135 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val); 1136 udelay(5); 1137 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, 1138 SC16IS7XX_FCR_FIFO_BIT); 1139 1140 /* Enable EFR */ 1141 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 1142 SC16IS7XX_LCR_CONF_MODE_B); 1143 1144 regcache_cache_bypass(one->regmap, true); 1145 1146 /* Enable write access to enhanced features and internal clock div */ 1147 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 1148 SC16IS7XX_EFR_ENABLE_BIT, 1149 SC16IS7XX_EFR_ENABLE_BIT); 1150 1151 /* Enable TCR/TLR */ 1152 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1153 SC16IS7XX_MCR_TCRTLR_BIT, 1154 SC16IS7XX_MCR_TCRTLR_BIT); 1155 1156 /* Configure flow control levels */ 1157 /* Flow control halt level 48, resume level 24 */ 1158 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG, 1159 SC16IS7XX_TCR_RX_RESUME(24) | 1160 SC16IS7XX_TCR_RX_HALT(48)); 1161 1162 regcache_cache_bypass(one->regmap, false); 1163 1164 /* Now, initialize the UART */ 1165 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8); 1166 1167 /* Enable IrDA mode if requested in DT */ 1168 /* This bit must be written with LCR[7] = 0 */ 1169 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1170 SC16IS7XX_MCR_IRDA_BIT, 1171 one->irda_mode ? 1172 SC16IS7XX_MCR_IRDA_BIT : 0); 1173 1174 /* Enable the Rx and Tx FIFO */ 1175 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1176 SC16IS7XX_EFCR_RXDISABLE_BIT | 1177 SC16IS7XX_EFCR_TXDISABLE_BIT, 1178 0); 1179 1180 /* Enable RX, CTS change and modem lines interrupts */ 1181 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT | 1182 SC16IS7XX_IER_MSI_BIT; 1183 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); 1184 1185 /* Enable modem status polling */ 1186 uart_port_lock_irqsave(port, &flags); 1187 sc16is7xx_enable_ms(port); 1188 uart_port_unlock_irqrestore(port, flags); 1189 1190 return 0; 1191 } 1192 1193 static void sc16is7xx_shutdown(struct uart_port *port) 1194 { 1195 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1196 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1197 1198 kthread_cancel_delayed_work_sync(&one->ms_work); 1199 1200 /* Disable all interrupts */ 1201 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0); 1202 /* Disable TX/RX */ 1203 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1204 SC16IS7XX_EFCR_RXDISABLE_BIT | 1205 SC16IS7XX_EFCR_TXDISABLE_BIT, 1206 SC16IS7XX_EFCR_RXDISABLE_BIT | 1207 SC16IS7XX_EFCR_TXDISABLE_BIT); 1208 1209 sc16is7xx_power(port, 0); 1210 1211 kthread_flush_worker(&s->kworker); 1212 } 1213 1214 static const char *sc16is7xx_type(struct uart_port *port) 1215 { 1216 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1217 1218 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL; 1219 } 1220 1221 static int sc16is7xx_request_port(struct uart_port *port) 1222 { 1223 /* Do nothing */ 1224 return 0; 1225 } 1226 1227 static void sc16is7xx_config_port(struct uart_port *port, int flags) 1228 { 1229 if (flags & UART_CONFIG_TYPE) 1230 port->type = PORT_SC16IS7XX; 1231 } 1232 1233 static int sc16is7xx_verify_port(struct uart_port *port, 1234 struct serial_struct *s) 1235 { 1236 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX)) 1237 return -EINVAL; 1238 if (s->irq != port->irq) 1239 return -EINVAL; 1240 1241 return 0; 1242 } 1243 1244 static void sc16is7xx_pm(struct uart_port *port, unsigned int state, 1245 unsigned int oldstate) 1246 { 1247 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0); 1248 } 1249 1250 static void sc16is7xx_null_void(struct uart_port *port) 1251 { 1252 /* Do nothing */ 1253 } 1254 1255 static const struct uart_ops sc16is7xx_ops = { 1256 .tx_empty = sc16is7xx_tx_empty, 1257 .set_mctrl = sc16is7xx_set_mctrl, 1258 .get_mctrl = sc16is7xx_get_mctrl, 1259 .stop_tx = sc16is7xx_stop_tx, 1260 .start_tx = sc16is7xx_start_tx, 1261 .throttle = sc16is7xx_throttle, 1262 .unthrottle = sc16is7xx_unthrottle, 1263 .stop_rx = sc16is7xx_stop_rx, 1264 .enable_ms = sc16is7xx_enable_ms, 1265 .break_ctl = sc16is7xx_break_ctl, 1266 .startup = sc16is7xx_startup, 1267 .shutdown = sc16is7xx_shutdown, 1268 .set_termios = sc16is7xx_set_termios, 1269 .type = sc16is7xx_type, 1270 .request_port = sc16is7xx_request_port, 1271 .release_port = sc16is7xx_null_void, 1272 .config_port = sc16is7xx_config_port, 1273 .verify_port = sc16is7xx_verify_port, 1274 .pm = sc16is7xx_pm, 1275 }; 1276 1277 #ifdef CONFIG_GPIOLIB 1278 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset) 1279 { 1280 unsigned int val; 1281 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1282 struct uart_port *port = &s->p[0].port; 1283 1284 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1285 1286 return !!(val & BIT(offset)); 1287 } 1288 1289 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 1290 { 1291 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1292 struct uart_port *port = &s->p[0].port; 1293 1294 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), 1295 val ? BIT(offset) : 0); 1296 } 1297 1298 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip, 1299 unsigned offset) 1300 { 1301 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1302 struct uart_port *port = &s->p[0].port; 1303 1304 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0); 1305 1306 return 0; 1307 } 1308 1309 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, 1310 unsigned offset, int val) 1311 { 1312 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1313 struct uart_port *port = &s->p[0].port; 1314 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1315 1316 if (val) 1317 state |= BIT(offset); 1318 else 1319 state &= ~BIT(offset); 1320 1321 /* 1322 * If we write IOSTATE first, and then IODIR, the output value is not 1323 * transferred to the corresponding I/O pin. 1324 * The datasheet states that each register bit will be transferred to 1325 * the corresponding I/O pin programmed as output when writing to 1326 * IOSTATE. Therefore, configure direction first with IODIR, and then 1327 * set value after with IOSTATE. 1328 */ 1329 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 1330 BIT(offset)); 1331 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); 1332 1333 return 0; 1334 } 1335 1336 static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip, 1337 unsigned long *valid_mask, 1338 unsigned int ngpios) 1339 { 1340 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1341 1342 *valid_mask = s->gpio_valid_mask; 1343 1344 return 0; 1345 } 1346 1347 static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s) 1348 { 1349 struct device *dev = s->p[0].port.dev; 1350 1351 if (!s->devtype->nr_gpio) 1352 return 0; 1353 1354 switch (s->mctrl_mask) { 1355 case 0: 1356 s->gpio_valid_mask = GENMASK(7, 0); 1357 break; 1358 case SC16IS7XX_IOCONTROL_MODEM_A_BIT: 1359 s->gpio_valid_mask = GENMASK(3, 0); 1360 break; 1361 case SC16IS7XX_IOCONTROL_MODEM_B_BIT: 1362 s->gpio_valid_mask = GENMASK(7, 4); 1363 break; 1364 default: 1365 break; 1366 } 1367 1368 if (s->gpio_valid_mask == 0) 1369 return 0; 1370 1371 s->gpio.owner = THIS_MODULE; 1372 s->gpio.parent = dev; 1373 s->gpio.label = dev_name(dev); 1374 s->gpio.init_valid_mask = sc16is7xx_gpio_init_valid_mask; 1375 s->gpio.direction_input = sc16is7xx_gpio_direction_input; 1376 s->gpio.get = sc16is7xx_gpio_get; 1377 s->gpio.direction_output = sc16is7xx_gpio_direction_output; 1378 s->gpio.set = sc16is7xx_gpio_set; 1379 s->gpio.base = -1; 1380 s->gpio.ngpio = s->devtype->nr_gpio; 1381 s->gpio.can_sleep = 1; 1382 1383 return gpiochip_add_data(&s->gpio, s); 1384 } 1385 #endif 1386 1387 static void sc16is7xx_setup_irda_ports(struct sc16is7xx_port *s) 1388 { 1389 int i; 1390 int ret; 1391 int count; 1392 u32 irda_port[SC16IS7XX_MAX_PORTS]; 1393 struct device *dev = s->p[0].port.dev; 1394 1395 count = device_property_count_u32(dev, "irda-mode-ports"); 1396 if (count < 0 || count > ARRAY_SIZE(irda_port)) 1397 return; 1398 1399 ret = device_property_read_u32_array(dev, "irda-mode-ports", 1400 irda_port, count); 1401 if (ret) 1402 return; 1403 1404 for (i = 0; i < count; i++) { 1405 if (irda_port[i] < s->devtype->nr_uart) 1406 s->p[irda_port[i]].irda_mode = true; 1407 } 1408 } 1409 1410 /* 1411 * Configure ports designated to operate as modem control lines. 1412 */ 1413 static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s, 1414 struct regmap *regmap) 1415 { 1416 int i; 1417 int ret; 1418 int count; 1419 u32 mctrl_port[SC16IS7XX_MAX_PORTS]; 1420 struct device *dev = s->p[0].port.dev; 1421 1422 count = device_property_count_u32(dev, "nxp,modem-control-line-ports"); 1423 if (count < 0 || count > ARRAY_SIZE(mctrl_port)) 1424 return 0; 1425 1426 ret = device_property_read_u32_array(dev, "nxp,modem-control-line-ports", 1427 mctrl_port, count); 1428 if (ret) 1429 return ret; 1430 1431 s->mctrl_mask = 0; 1432 1433 for (i = 0; i < count; i++) { 1434 /* Use GPIO lines as modem control lines */ 1435 if (mctrl_port[i] == 0) 1436 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT; 1437 else if (mctrl_port[i] == 1) 1438 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT; 1439 } 1440 1441 if (s->mctrl_mask) 1442 regmap_update_bits( 1443 regmap, 1444 SC16IS7XX_IOCONTROL_REG, 1445 SC16IS7XX_IOCONTROL_MODEM_A_BIT | 1446 SC16IS7XX_IOCONTROL_MODEM_B_BIT, s->mctrl_mask); 1447 1448 return 0; 1449 } 1450 1451 static const struct serial_rs485 sc16is7xx_rs485_supported = { 1452 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND, 1453 .delay_rts_before_send = 1, 1454 .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */ 1455 }; 1456 1457 int sc16is7xx_probe(struct device *dev, const struct sc16is7xx_devtype *devtype, 1458 struct regmap *regmaps[], int irq) 1459 { 1460 unsigned long freq = 0, *pfreq = dev_get_platdata(dev); 1461 unsigned int val; 1462 u32 uartclk = 0; 1463 int i, ret; 1464 struct sc16is7xx_port *s; 1465 bool port_registered[SC16IS7XX_MAX_PORTS]; 1466 1467 for (i = 0; i < devtype->nr_uart; i++) 1468 if (IS_ERR(regmaps[i])) 1469 return PTR_ERR(regmaps[i]); 1470 1471 /* 1472 * This device does not have an identification register that would 1473 * tell us if we are really connected to the correct device. 1474 * The best we can do is to check if communication is at all possible. 1475 * 1476 * Note: regmap[0] is used in the probe function to access registers 1477 * common to all channels/ports, as it is guaranteed to be present on 1478 * all variants. 1479 */ 1480 ret = regmap_read(regmaps[0], SC16IS7XX_LSR_REG, &val); 1481 if (ret < 0) 1482 return -EPROBE_DEFER; 1483 1484 /* Alloc port structure */ 1485 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL); 1486 if (!s) { 1487 dev_err(dev, "Error allocating port structure\n"); 1488 return -ENOMEM; 1489 } 1490 1491 /* Always ask for fixed clock rate from a property. */ 1492 device_property_read_u32(dev, "clock-frequency", &uartclk); 1493 1494 s->clk = devm_clk_get_optional(dev, NULL); 1495 if (IS_ERR(s->clk)) 1496 return PTR_ERR(s->clk); 1497 1498 ret = clk_prepare_enable(s->clk); 1499 if (ret) 1500 return ret; 1501 1502 freq = clk_get_rate(s->clk); 1503 if (freq == 0) { 1504 if (uartclk) 1505 freq = uartclk; 1506 if (pfreq) 1507 freq = *pfreq; 1508 if (freq) 1509 dev_dbg(dev, "Clock frequency: %luHz\n", freq); 1510 else 1511 return -EINVAL; 1512 } 1513 1514 s->devtype = devtype; 1515 dev_set_drvdata(dev, s); 1516 1517 kthread_init_worker(&s->kworker); 1518 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker, 1519 "sc16is7xx"); 1520 if (IS_ERR(s->kworker_task)) { 1521 ret = PTR_ERR(s->kworker_task); 1522 goto out_clk; 1523 } 1524 sched_set_fifo(s->kworker_task); 1525 1526 /* reset device, purging any pending irq / data */ 1527 regmap_write(regmaps[0], SC16IS7XX_IOCONTROL_REG, 1528 SC16IS7XX_IOCONTROL_SRESET_BIT); 1529 1530 /* Mark each port line and status as uninitialised. */ 1531 for (i = 0; i < devtype->nr_uart; ++i) { 1532 s->p[i].port.line = SC16IS7XX_MAX_DEVS; 1533 port_registered[i] = false; 1534 } 1535 1536 for (i = 0; i < devtype->nr_uart; ++i) { 1537 ret = ida_alloc_max(&sc16is7xx_lines, 1538 SC16IS7XX_MAX_DEVS - 1, GFP_KERNEL); 1539 if (ret < 0) 1540 goto out_ports; 1541 1542 s->p[i].port.line = ret; 1543 1544 /* Initialize port data */ 1545 s->p[i].port.dev = dev; 1546 s->p[i].port.irq = irq; 1547 s->p[i].port.type = PORT_SC16IS7XX; 1548 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE; 1549 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1550 s->p[i].port.iobase = i; 1551 /* 1552 * Use all ones as membase to make sure uart_configure_port() in 1553 * serial_core.c does not abort for SPI/I2C devices where the 1554 * membase address is not applicable. 1555 */ 1556 s->p[i].port.membase = (void __iomem *)~0; 1557 s->p[i].port.iotype = UPIO_PORT; 1558 s->p[i].port.uartclk = freq; 1559 s->p[i].port.rs485_config = sc16is7xx_config_rs485; 1560 s->p[i].port.rs485_supported = sc16is7xx_rs485_supported; 1561 s->p[i].port.ops = &sc16is7xx_ops; 1562 s->p[i].old_mctrl = 0; 1563 s->p[i].regmap = regmaps[i]; 1564 1565 mutex_init(&s->p[i].efr_lock); 1566 1567 ret = uart_get_rs485_mode(&s->p[i].port); 1568 if (ret) 1569 goto out_ports; 1570 1571 /* Disable all interrupts */ 1572 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0); 1573 /* Disable TX/RX */ 1574 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG, 1575 SC16IS7XX_EFCR_RXDISABLE_BIT | 1576 SC16IS7XX_EFCR_TXDISABLE_BIT); 1577 1578 /* Initialize kthread work structs */ 1579 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc); 1580 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc); 1581 kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc); 1582 1583 /* Register port */ 1584 ret = uart_add_one_port(&sc16is7xx_uart, &s->p[i].port); 1585 if (ret) 1586 goto out_ports; 1587 1588 port_registered[i] = true; 1589 1590 /* Enable EFR */ 1591 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 1592 SC16IS7XX_LCR_CONF_MODE_B); 1593 1594 regcache_cache_bypass(regmaps[i], true); 1595 1596 /* Enable write access to enhanced features */ 1597 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG, 1598 SC16IS7XX_EFR_ENABLE_BIT); 1599 1600 regcache_cache_bypass(regmaps[i], false); 1601 1602 /* Restore access to general registers */ 1603 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00); 1604 1605 /* Go to suspend mode */ 1606 sc16is7xx_power(&s->p[i].port, 0); 1607 } 1608 1609 sc16is7xx_setup_irda_ports(s); 1610 1611 ret = sc16is7xx_setup_mctrl_ports(s, regmaps[0]); 1612 if (ret) 1613 goto out_ports; 1614 1615 #ifdef CONFIG_GPIOLIB 1616 ret = sc16is7xx_setup_gpio_chip(s); 1617 if (ret) 1618 goto out_ports; 1619 #endif 1620 1621 /* 1622 * Setup interrupt. We first try to acquire the IRQ line as level IRQ. 1623 * If that succeeds, we can allow sharing the interrupt as well. 1624 * In case the interrupt controller doesn't support that, we fall 1625 * back to a non-shared falling-edge trigger. 1626 */ 1627 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1628 IRQF_TRIGGER_LOW | IRQF_SHARED | 1629 IRQF_ONESHOT, 1630 dev_name(dev), s); 1631 if (!ret) 1632 return 0; 1633 1634 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1635 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1636 dev_name(dev), s); 1637 if (!ret) 1638 return 0; 1639 1640 #ifdef CONFIG_GPIOLIB 1641 if (s->gpio_valid_mask) 1642 gpiochip_remove(&s->gpio); 1643 #endif 1644 1645 out_ports: 1646 for (i = 0; i < devtype->nr_uart; i++) { 1647 if (s->p[i].port.line < SC16IS7XX_MAX_DEVS) 1648 ida_free(&sc16is7xx_lines, s->p[i].port.line); 1649 if (port_registered[i]) 1650 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1651 } 1652 1653 kthread_stop(s->kworker_task); 1654 1655 out_clk: 1656 clk_disable_unprepare(s->clk); 1657 1658 return ret; 1659 } 1660 EXPORT_SYMBOL_GPL(sc16is7xx_probe); 1661 1662 void sc16is7xx_remove(struct device *dev) 1663 { 1664 struct sc16is7xx_port *s = dev_get_drvdata(dev); 1665 int i; 1666 1667 #ifdef CONFIG_GPIOLIB 1668 if (s->gpio_valid_mask) 1669 gpiochip_remove(&s->gpio); 1670 #endif 1671 1672 for (i = 0; i < s->devtype->nr_uart; i++) { 1673 kthread_cancel_delayed_work_sync(&s->p[i].ms_work); 1674 ida_free(&sc16is7xx_lines, s->p[i].port.line); 1675 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1676 sc16is7xx_power(&s->p[i].port, 0); 1677 } 1678 1679 kthread_flush_worker(&s->kworker); 1680 kthread_stop(s->kworker_task); 1681 1682 clk_disable_unprepare(s->clk); 1683 } 1684 EXPORT_SYMBOL_GPL(sc16is7xx_remove); 1685 1686 const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = { 1687 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, }, 1688 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, }, 1689 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, }, 1690 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, }, 1691 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, }, 1692 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, }, 1693 { } 1694 }; 1695 EXPORT_SYMBOL_GPL(sc16is7xx_dt_ids); 1696 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids); 1697 1698 const struct regmap_config sc16is7xx_regcfg = { 1699 .reg_bits = 5, 1700 .pad_bits = 3, 1701 .val_bits = 8, 1702 .cache_type = REGCACHE_MAPLE, 1703 .volatile_reg = sc16is7xx_regmap_volatile, 1704 .precious_reg = sc16is7xx_regmap_precious, 1705 .writeable_noinc_reg = sc16is7xx_regmap_noinc, 1706 .readable_noinc_reg = sc16is7xx_regmap_noinc, 1707 .max_raw_read = SC16IS7XX_FIFO_SIZE, 1708 .max_raw_write = SC16IS7XX_FIFO_SIZE, 1709 .max_register = SC16IS7XX_EFCR_REG, 1710 }; 1711 EXPORT_SYMBOL_GPL(sc16is7xx_regcfg); 1712 1713 const char *sc16is7xx_regmap_name(u8 port_id) 1714 { 1715 switch (port_id) { 1716 case 0: return "port0"; 1717 case 1: return "port1"; 1718 default: 1719 WARN_ON(true); 1720 return NULL; 1721 } 1722 } 1723 EXPORT_SYMBOL_GPL(sc16is7xx_regmap_name); 1724 1725 unsigned int sc16is7xx_regmap_port_mask(unsigned int port_id) 1726 { 1727 /* CH1,CH0 are at bits 2:1. */ 1728 return port_id << 1; 1729 } 1730 EXPORT_SYMBOL_GPL(sc16is7xx_regmap_port_mask); 1731 1732 static int __init sc16is7xx_init(void) 1733 { 1734 return uart_register_driver(&sc16is7xx_uart); 1735 } 1736 module_init(sc16is7xx_init); 1737 1738 static void __exit sc16is7xx_exit(void) 1739 { 1740 uart_unregister_driver(&sc16is7xx_uart); 1741 } 1742 module_exit(sc16is7xx_exit); 1743 1744 MODULE_LICENSE("GPL"); 1745 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>"); 1746 MODULE_DESCRIPTION("SC16IS7xx tty serial core driver"); 1747