1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SC16IS7xx tty serial driver - common code 4 * 5 * Copyright (C) 2014 GridPoint 6 * Author: Jon Ringle <jringle@gridpoint.com> 7 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru> 8 */ 9 10 #undef DEFAULT_SYMBOL_NAMESPACE 11 #define DEFAULT_SYMBOL_NAMESPACE SERIAL_NXP_SC16IS7XX 12 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/export.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/idr.h> 19 #include <linux/kthread.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/module.h> 22 #include <linux/property.h> 23 #include <linux/regmap.h> 24 #include <linux/sched.h> 25 #include <linux/serial_core.h> 26 #include <linux/serial.h> 27 #include <linux/string.h> 28 #include <linux/tty.h> 29 #include <linux/tty_flip.h> 30 #include <linux/uaccess.h> 31 #include <linux/units.h> 32 33 #include "sc16is7xx.h" 34 35 #define SC16IS7XX_MAX_DEVS 8 36 37 /* SC16IS7XX register definitions */ 38 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */ 39 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */ 40 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */ 41 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */ 42 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */ 43 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */ 44 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */ 45 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */ 46 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */ 47 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */ 48 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */ 49 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */ 50 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction 51 * - only on 75x/76x 52 */ 53 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State 54 * - only on 75x/76x 55 */ 56 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable 57 * - only on 75x/76x 58 */ 59 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control 60 * - only on 75x/76x 61 */ 62 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */ 63 64 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */ 65 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */ 66 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */ 67 68 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */ 69 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */ 70 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */ 71 72 /* Enhanced Register set: Only if (LCR == 0xBF) */ 73 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */ 74 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */ 75 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */ 76 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */ 77 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */ 78 79 /* IER register bits */ 80 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */ 81 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register 82 * interrupt */ 83 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status 84 * interrupt */ 85 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status 86 * interrupt */ 87 88 /* IER register bits - write only if (EFR[4] == 1) */ 89 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */ 90 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */ 91 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */ 92 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */ 93 94 /* FCR register bits */ 95 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */ 96 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */ 97 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */ 98 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */ 99 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */ 100 101 /* FCR register bits - write only if (EFR[4] == 1) */ 102 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */ 103 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */ 104 105 /* IIR register bits */ 106 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */ 107 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */ 108 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */ 109 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */ 110 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */ 111 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */ 112 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt 113 * - only on 75x/76x 114 */ 115 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state 116 * - only on 75x/76x 117 */ 118 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */ 119 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state 120 * from active (LOW) 121 * to inactive (HIGH) 122 */ 123 /* LCR register bits */ 124 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 125 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 126 * 127 * Word length bits table: 128 * 00 -> 5 bit words 129 * 01 -> 6 bit words 130 * 10 -> 7 bit words 131 * 11 -> 8 bit words 132 */ 133 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 134 * 135 * STOP length bit table: 136 * 0 -> 1 stop bit 137 * 1 -> 1-1.5 stop bits if 138 * word length is 5, 139 * 2 stop bits otherwise 140 */ 141 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 142 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 143 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 144 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 145 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */ 146 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00) 147 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01) 148 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02) 149 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03) 150 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special 151 * reg set */ 152 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced 153 * reg set */ 154 155 /* MCR register bits */ 156 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement 157 * - only on 75x/76x 158 */ 159 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */ 160 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */ 161 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */ 162 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any 163 * - write enabled 164 * if (EFR[4] == 1) 165 */ 166 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode 167 * - write enabled 168 * if (EFR[4] == 1) 169 */ 170 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4 171 * - write enabled 172 * if (EFR[4] == 1) 173 */ 174 175 /* LSR register bits */ 176 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */ 177 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */ 178 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */ 179 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */ 180 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */ 181 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */ 182 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */ 183 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */ 184 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */ 185 186 /* MSR register bits */ 187 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */ 188 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready 189 * or (IO4) 190 * - only on 75x/76x 191 */ 192 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator 193 * or (IO7) 194 * - only on 75x/76x 195 */ 196 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect 197 * or (IO6) 198 * - only on 75x/76x 199 */ 200 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */ 201 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4) 202 * - only on 75x/76x 203 */ 204 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7) 205 * - only on 75x/76x 206 */ 207 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6) 208 * - only on 75x/76x 209 */ 210 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */ 211 212 /* 213 * TCR register bits 214 * TCR trigger levels are available from 0 to 60 characters with a granularity 215 * of four. 216 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is 217 * no built-in hardware check to make sure this condition is met. Also, the TCR 218 * must be programmed with this condition before auto RTS or software flow 219 * control is enabled to avoid spurious operation of the device. 220 */ 221 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0) 222 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4) 223 224 /* 225 * TLR register bits 226 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the 227 * FIFO Control Register (FCR) are used for the transmit and receive FIFO 228 * trigger levels. Trigger levels from 4 characters to 60 characters are 229 * available with a granularity of four. 230 * 231 * When the trigger level setting in TLR is zero, the SC16IS74x/75x/76x uses the 232 * trigger level setting defined in FCR. If TLR has non-zero trigger level value 233 * the trigger level defined in FCR is discarded. This applies to both transmit 234 * FIFO and receive FIFO trigger level setting. 235 * 236 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the 237 * default state, that is, '00'. 238 */ 239 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0) 240 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) 241 242 /* IOControl register bits (Only 75x/76x) */ 243 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ 244 #define SC16IS7XX_IOCONTROL_MODEM_A_BIT (1 << 1) /* Enable GPIO[7:4] as modem A pins */ 245 #define SC16IS7XX_IOCONTROL_MODEM_B_BIT (1 << 2) /* Enable GPIO[3:0] as modem B pins */ 246 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */ 247 248 /* EFCR register bits */ 249 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop 250 * mode (RS485) */ 251 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */ 252 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */ 253 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */ 254 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */ 255 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode 256 * 0 = rate upto 115.2 kbit/s 257 * - Only 75x/76x 258 * 1 = rate upto 1.152 Mbit/s 259 * - Only 76x 260 */ 261 262 /* EFR register bits */ 263 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */ 264 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */ 265 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */ 266 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions 267 * and writing to IER[7:4], 268 * FCR[5:4], MCR[7:5] 269 */ 270 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */ 271 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2 272 * 273 * SWFLOW bits 3 & 2 table: 274 * 00 -> no transmitter flow 275 * control 276 * 01 -> transmitter generates 277 * XON2 and XOFF2 278 * 10 -> transmitter generates 279 * XON1 and XOFF1 280 * 11 -> transmitter generates 281 * XON1, XON2, XOFF1 and 282 * XOFF2 283 */ 284 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */ 285 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3 286 * 287 * SWFLOW bits 3 & 2 table: 288 * 00 -> no received flow 289 * control 290 * 01 -> receiver compares 291 * XON2 and XOFF2 292 * 10 -> receiver compares 293 * XON1 and XOFF1 294 * 11 -> receiver compares 295 * XON1, XON2, XOFF1 and 296 * XOFF2 297 */ 298 #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \ 299 SC16IS7XX_EFR_AUTOCTS_BIT | \ 300 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \ 301 SC16IS7XX_EFR_SWFLOW3_BIT | \ 302 SC16IS7XX_EFR_SWFLOW2_BIT | \ 303 SC16IS7XX_EFR_SWFLOW1_BIT | \ 304 SC16IS7XX_EFR_SWFLOW0_BIT) 305 306 307 /* Misc definitions */ 308 #define SC16IS7XX_FIFO_SIZE (64) 309 #define SC16IS7XX_GPIOS_PER_BANK 4 310 311 #define SC16IS7XX_RECONF_MD (1 << 0) 312 #define SC16IS7XX_RECONF_IER (1 << 1) 313 #define SC16IS7XX_RECONF_RS485 (1 << 2) 314 315 struct sc16is7xx_one_config { 316 unsigned int flags; 317 u8 ier_mask; 318 u8 ier_val; 319 }; 320 321 struct sc16is7xx_one { 322 struct uart_port port; 323 struct regmap *regmap; 324 struct mutex efr_lock; /* EFR registers access */ 325 struct kthread_work tx_work; 326 struct kthread_work reg_work; 327 struct kthread_delayed_work ms_work; 328 struct sc16is7xx_one_config config; 329 unsigned int old_mctrl; 330 u8 old_lcr; /* Value before EFR access. */ 331 bool irda_mode; 332 }; 333 334 struct sc16is7xx_port { 335 const struct sc16is7xx_devtype *devtype; 336 struct clk *clk; 337 #ifdef CONFIG_GPIOLIB 338 struct gpio_chip gpio; 339 unsigned long gpio_valid_mask; 340 #endif 341 u8 mctrl_mask; 342 unsigned char buf[SC16IS7XX_FIFO_SIZE]; 343 struct kthread_worker kworker; 344 struct task_struct *kworker_task; 345 struct sc16is7xx_one p[]; 346 }; 347 348 static DEFINE_IDA(sc16is7xx_lines); 349 350 static struct uart_driver sc16is7xx_uart = { 351 .owner = THIS_MODULE, 352 .driver_name = SC16IS7XX_NAME, 353 .dev_name = "ttySC", 354 .nr = SC16IS7XX_MAX_DEVS, 355 }; 356 357 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e))) 358 359 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg) 360 { 361 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 362 unsigned int val = 0; 363 364 regmap_read(one->regmap, reg, &val); 365 366 return val; 367 } 368 369 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val) 370 { 371 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 372 373 regmap_write(one->regmap, reg, val); 374 } 375 376 static void sc16is7xx_fifo_read(struct uart_port *port, u8 *rxbuf, unsigned int rxlen) 377 { 378 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 379 380 regmap_noinc_read(one->regmap, SC16IS7XX_RHR_REG, rxbuf, rxlen); 381 } 382 383 static void sc16is7xx_fifo_write(struct uart_port *port, u8 *txbuf, u8 to_send) 384 { 385 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 386 387 /* 388 * Don't send zero-length data, at least on SPI it confuses the chip 389 * delivering wrong TXLVL data. 390 */ 391 if (unlikely(!to_send)) 392 return; 393 394 regmap_noinc_write(one->regmap, SC16IS7XX_THR_REG, txbuf, to_send); 395 } 396 397 static void sc16is7xx_port_update(struct uart_port *port, u8 reg, 398 u8 mask, u8 val) 399 { 400 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 401 402 regmap_update_bits(one->regmap, reg, mask, val); 403 } 404 405 static void sc16is7xx_power(struct uart_port *port, int on) 406 { 407 sc16is7xx_port_update(port, SC16IS7XX_IER_REG, 408 SC16IS7XX_IER_SLEEP_BIT, 409 on ? 0 : SC16IS7XX_IER_SLEEP_BIT); 410 } 411 412 /* 413 * In an amazing feat of design, the Enhanced Features Register (EFR) 414 * shares the address of the Interrupt Identification Register (IIR). 415 * Access to EFR is switched on by writing a magic value (0xbf) to the 416 * Line Control Register (LCR). Any interrupt firing during this time will 417 * see the EFR where it expects the IIR to be, leading to 418 * "Unexpected interrupt" messages. 419 * 420 * Prevent this possibility by claiming a mutex while accessing the EFR, 421 * and claiming the same mutex from within the interrupt handler. This is 422 * similar to disabling the interrupt, but that doesn't work because the 423 * bulk of the interrupt processing is run as a workqueue job in thread 424 * context. 425 */ 426 static void sc16is7xx_efr_lock(struct uart_port *port) 427 { 428 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 429 430 mutex_lock(&one->efr_lock); 431 432 /* Backup content of LCR. */ 433 one->old_lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); 434 435 /* Enable access to Enhanced register set */ 436 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_CONF_MODE_B); 437 438 /* Disable cache updates when writing to EFR registers */ 439 regcache_cache_bypass(one->regmap, true); 440 } 441 442 static void sc16is7xx_efr_unlock(struct uart_port *port) 443 { 444 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 445 446 /* Re-enable cache updates when writing to normal registers */ 447 regcache_cache_bypass(one->regmap, false); 448 449 /* Restore original content of LCR */ 450 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, one->old_lcr); 451 452 mutex_unlock(&one->efr_lock); 453 } 454 455 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit) 456 { 457 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 458 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 459 460 lockdep_assert_held_once(&port->lock); 461 462 one->config.flags |= SC16IS7XX_RECONF_IER; 463 one->config.ier_mask |= bit; 464 one->config.ier_val &= ~bit; 465 kthread_queue_work(&s->kworker, &one->reg_work); 466 } 467 468 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit) 469 { 470 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 471 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 472 473 lockdep_assert_held_once(&port->lock); 474 475 one->config.flags |= SC16IS7XX_RECONF_IER; 476 one->config.ier_mask |= bit; 477 one->config.ier_val |= bit; 478 kthread_queue_work(&s->kworker, &one->reg_work); 479 } 480 481 static void sc16is7xx_stop_tx(struct uart_port *port) 482 { 483 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT); 484 } 485 486 static void sc16is7xx_stop_rx(struct uart_port *port) 487 { 488 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 489 } 490 491 const struct sc16is7xx_devtype sc16is74x_devtype = { 492 .name = "SC16IS74X", 493 .nr_gpio = 0, 494 .nr_uart = 1, 495 }; 496 EXPORT_SYMBOL_GPL(sc16is74x_devtype); 497 498 const struct sc16is7xx_devtype sc16is750_devtype = { 499 .name = "SC16IS750", 500 .nr_gpio = 8, 501 .nr_uart = 1, 502 }; 503 EXPORT_SYMBOL_GPL(sc16is750_devtype); 504 505 const struct sc16is7xx_devtype sc16is752_devtype = { 506 .name = "SC16IS752", 507 .nr_gpio = 8, 508 .nr_uart = 2, 509 }; 510 EXPORT_SYMBOL_GPL(sc16is752_devtype); 511 512 const struct sc16is7xx_devtype sc16is760_devtype = { 513 .name = "SC16IS760", 514 .nr_gpio = 8, 515 .nr_uart = 1, 516 }; 517 EXPORT_SYMBOL_GPL(sc16is760_devtype); 518 519 const struct sc16is7xx_devtype sc16is762_devtype = { 520 .name = "SC16IS762", 521 .nr_gpio = 8, 522 .nr_uart = 2, 523 }; 524 EXPORT_SYMBOL_GPL(sc16is762_devtype); 525 526 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg) 527 { 528 switch (reg) { 529 case SC16IS7XX_RHR_REG: 530 case SC16IS7XX_IIR_REG: 531 case SC16IS7XX_LSR_REG: 532 case SC16IS7XX_MSR_REG: 533 case SC16IS7XX_TXLVL_REG: 534 case SC16IS7XX_RXLVL_REG: 535 case SC16IS7XX_IOSTATE_REG: 536 case SC16IS7XX_IOCONTROL_REG: 537 return true; 538 default: 539 return false; 540 } 541 } 542 543 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg) 544 { 545 switch (reg) { 546 case SC16IS7XX_RHR_REG: 547 return true; 548 default: 549 return false; 550 } 551 } 552 553 static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg) 554 { 555 return reg == SC16IS7XX_RHR_REG; 556 } 557 558 /* 559 * Configure programmable baud rate generator (divisor) according to the 560 * desired baud rate. 561 * 562 * From the datasheet, the divisor is computed according to: 563 * 564 * XTAL1 input frequency 565 * ----------------------- 566 * prescaler 567 * divisor = --------------------------- 568 * baud-rate x sampling-rate 569 */ 570 static int sc16is7xx_set_baud(struct uart_port *port, int baud) 571 { 572 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 573 u8 lcr; 574 unsigned int prescaler = 1; 575 unsigned long clk = port->uartclk, div = clk / 16 / baud; 576 577 if (div >= BIT(16)) { 578 prescaler = 4; 579 div /= prescaler; 580 } 581 582 /* Enable enhanced features */ 583 sc16is7xx_efr_lock(port); 584 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 585 SC16IS7XX_EFR_ENABLE_BIT, 586 SC16IS7XX_EFR_ENABLE_BIT); 587 sc16is7xx_efr_unlock(port); 588 589 /* If bit MCR_CLKSEL is set, the divide by 4 prescaler is activated. */ 590 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 591 SC16IS7XX_MCR_CLKSEL_BIT, 592 prescaler == 1 ? 0 : SC16IS7XX_MCR_CLKSEL_BIT); 593 594 /* Backup LCR and access special register set (DLL/DLH) */ 595 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); 596 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 597 SC16IS7XX_LCR_CONF_MODE_A); 598 599 /* Write the new divisor */ 600 regcache_cache_bypass(one->regmap, true); 601 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256); 602 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256); 603 regcache_cache_bypass(one->regmap, false); 604 605 /* Restore LCR and access to general register set */ 606 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 607 608 return DIV_ROUND_CLOSEST((clk / prescaler) / 16, div); 609 } 610 611 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen, 612 unsigned int iir) 613 { 614 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 615 unsigned int lsr = 0, bytes_read, i; 616 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false; 617 u8 ch, flag; 618 619 if (unlikely(rxlen >= sizeof(s->buf))) { 620 dev_warn_ratelimited(port->dev, 621 "ttySC%i: Possible RX FIFO overrun: %d\n", 622 port->line, rxlen); 623 port->icount.buf_overrun++; 624 /* Ensure sanity of RX level */ 625 rxlen = sizeof(s->buf); 626 } 627 628 while (rxlen) { 629 /* Only read lsr if there are possible errors in FIFO */ 630 if (read_lsr) { 631 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 632 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT)) 633 read_lsr = false; /* No errors left in FIFO */ 634 } else 635 lsr = 0; 636 637 if (read_lsr) { 638 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG); 639 bytes_read = 1; 640 } else { 641 sc16is7xx_fifo_read(port, s->buf, rxlen); 642 bytes_read = rxlen; 643 } 644 645 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK; 646 647 port->icount.rx++; 648 flag = TTY_NORMAL; 649 650 if (unlikely(lsr)) { 651 if (lsr & SC16IS7XX_LSR_BI_BIT) { 652 port->icount.brk++; 653 if (uart_handle_break(port)) 654 continue; 655 } else if (lsr & SC16IS7XX_LSR_PE_BIT) 656 port->icount.parity++; 657 else if (lsr & SC16IS7XX_LSR_FE_BIT) 658 port->icount.frame++; 659 else if (lsr & SC16IS7XX_LSR_OE_BIT) 660 port->icount.overrun++; 661 662 lsr &= port->read_status_mask; 663 if (lsr & SC16IS7XX_LSR_BI_BIT) 664 flag = TTY_BREAK; 665 else if (lsr & SC16IS7XX_LSR_PE_BIT) 666 flag = TTY_PARITY; 667 else if (lsr & SC16IS7XX_LSR_FE_BIT) 668 flag = TTY_FRAME; 669 else if (lsr & SC16IS7XX_LSR_OE_BIT) 670 flag = TTY_OVERRUN; 671 } 672 673 for (i = 0; i < bytes_read; ++i) { 674 ch = s->buf[i]; 675 if (uart_handle_sysrq_char(port, ch)) 676 continue; 677 678 if (lsr & port->ignore_status_mask) 679 continue; 680 681 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch, 682 flag); 683 } 684 rxlen -= bytes_read; 685 } 686 687 tty_flip_buffer_push(&port->state->port); 688 } 689 690 static void sc16is7xx_handle_tx(struct uart_port *port) 691 { 692 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 693 struct tty_port *tport = &port->state->port; 694 unsigned long flags; 695 unsigned int txlen; 696 697 if (unlikely(port->x_char)) { 698 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char); 699 port->icount.tx++; 700 port->x_char = 0; 701 return; 702 } 703 704 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) { 705 uart_port_lock_irqsave(port, &flags); 706 sc16is7xx_stop_tx(port); 707 uart_port_unlock_irqrestore(port, flags); 708 return; 709 } 710 711 /* Limit to space available in TX FIFO */ 712 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG); 713 if (txlen > SC16IS7XX_FIFO_SIZE) { 714 dev_err_ratelimited(port->dev, 715 "chip reports %d free bytes in TX fifo, but it only has %d", 716 txlen, SC16IS7XX_FIFO_SIZE); 717 txlen = 0; 718 } 719 720 txlen = uart_fifo_out(port, s->buf, txlen); 721 sc16is7xx_fifo_write(port, s->buf, txlen); 722 723 uart_port_lock_irqsave(port, &flags); 724 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 725 uart_write_wakeup(port); 726 727 if (kfifo_is_empty(&tport->xmit_fifo)) 728 sc16is7xx_stop_tx(port); 729 else 730 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT); 731 uart_port_unlock_irqrestore(port, flags); 732 } 733 734 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port) 735 { 736 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG); 737 unsigned int mctrl = 0; 738 739 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0; 740 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0; 741 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0; 742 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0; 743 return mctrl; 744 } 745 746 static void sc16is7xx_update_mlines(struct sc16is7xx_one *one) 747 { 748 struct uart_port *port = &one->port; 749 unsigned long flags; 750 unsigned int status, changed; 751 752 lockdep_assert_held_once(&one->efr_lock); 753 754 status = sc16is7xx_get_hwmctrl(port); 755 changed = status ^ one->old_mctrl; 756 757 if (changed == 0) 758 return; 759 760 one->old_mctrl = status; 761 762 uart_port_lock_irqsave(port, &flags); 763 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG)) 764 port->icount.rng++; 765 if (changed & TIOCM_DSR) 766 port->icount.dsr++; 767 if (changed & TIOCM_CAR) 768 uart_handle_dcd_change(port, status & TIOCM_CAR); 769 if (changed & TIOCM_CTS) 770 uart_handle_cts_change(port, status & TIOCM_CTS); 771 772 wake_up_interruptible(&port->state->port.delta_msr_wait); 773 uart_port_unlock_irqrestore(port, flags); 774 } 775 776 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno) 777 { 778 bool rc = true; 779 unsigned int iir, rxlen; 780 struct uart_port *port = &s->p[portno].port; 781 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 782 783 mutex_lock(&one->efr_lock); 784 785 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG); 786 if (iir & SC16IS7XX_IIR_NO_INT_BIT) { 787 rc = false; 788 goto out_port_irq; 789 } 790 791 iir &= SC16IS7XX_IIR_ID_MASK; 792 793 switch (iir) { 794 case SC16IS7XX_IIR_RDI_SRC: 795 case SC16IS7XX_IIR_RLSE_SRC: 796 case SC16IS7XX_IIR_RTOI_SRC: 797 case SC16IS7XX_IIR_XOFFI_SRC: 798 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); 799 800 /* 801 * There is a silicon bug that makes the chip report a 802 * time-out interrupt but no data in the FIFO. This is 803 * described in errata section 18.1.4. 804 * 805 * When this happens, read one byte from the FIFO to 806 * clear the interrupt. 807 */ 808 if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen) 809 rxlen = 1; 810 811 if (rxlen) 812 sc16is7xx_handle_rx(port, rxlen, iir); 813 break; 814 /* CTSRTS interrupt comes only when CTS goes inactive */ 815 case SC16IS7XX_IIR_CTSRTS_SRC: 816 case SC16IS7XX_IIR_MSI_SRC: 817 sc16is7xx_update_mlines(one); 818 break; 819 case SC16IS7XX_IIR_THRI_SRC: 820 sc16is7xx_handle_tx(port); 821 break; 822 default: 823 dev_err_ratelimited(port->dev, 824 "ttySC%i: Unexpected interrupt: %x", 825 port->line, iir); 826 break; 827 } 828 829 out_port_irq: 830 mutex_unlock(&one->efr_lock); 831 832 return rc; 833 } 834 835 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id) 836 { 837 bool keep_polling; 838 839 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id; 840 841 do { 842 int i; 843 844 keep_polling = false; 845 846 for (i = 0; i < s->devtype->nr_uart; ++i) 847 keep_polling |= sc16is7xx_port_irq(s, i); 848 } while (keep_polling); 849 850 return IRQ_HANDLED; 851 } 852 853 static void sc16is7xx_tx_proc(struct kthread_work *ws) 854 { 855 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port); 856 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 857 858 if ((port->rs485.flags & SER_RS485_ENABLED) && 859 (port->rs485.delay_rts_before_send > 0)) 860 msleep(port->rs485.delay_rts_before_send); 861 862 mutex_lock(&one->efr_lock); 863 sc16is7xx_handle_tx(port); 864 mutex_unlock(&one->efr_lock); 865 } 866 867 static void sc16is7xx_reconf_rs485(struct uart_port *port) 868 { 869 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT | 870 SC16IS7XX_EFCR_RTS_INVERT_BIT; 871 u32 efcr = 0; 872 struct serial_rs485 *rs485 = &port->rs485; 873 unsigned long irqflags; 874 875 uart_port_lock_irqsave(port, &irqflags); 876 if (rs485->flags & SER_RS485_ENABLED) { 877 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT; 878 879 if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 880 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT; 881 } 882 uart_port_unlock_irqrestore(port, irqflags); 883 884 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr); 885 } 886 887 static void sc16is7xx_reg_proc(struct kthread_work *ws) 888 { 889 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work); 890 struct sc16is7xx_one_config config; 891 unsigned long irqflags; 892 893 uart_port_lock_irqsave(&one->port, &irqflags); 894 config = one->config; 895 memset(&one->config, 0, sizeof(one->config)); 896 uart_port_unlock_irqrestore(&one->port, irqflags); 897 898 if (config.flags & SC16IS7XX_RECONF_MD) { 899 u8 mcr = 0; 900 901 /* Device ignores RTS setting when hardware flow is enabled */ 902 if (one->port.mctrl & TIOCM_RTS) 903 mcr |= SC16IS7XX_MCR_RTS_BIT; 904 905 if (one->port.mctrl & TIOCM_DTR) 906 mcr |= SC16IS7XX_MCR_DTR_BIT; 907 908 if (one->port.mctrl & TIOCM_LOOP) 909 mcr |= SC16IS7XX_MCR_LOOP_BIT; 910 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, 911 SC16IS7XX_MCR_RTS_BIT | 912 SC16IS7XX_MCR_DTR_BIT | 913 SC16IS7XX_MCR_LOOP_BIT, 914 mcr); 915 } 916 917 if (config.flags & SC16IS7XX_RECONF_IER) 918 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG, 919 config.ier_mask, config.ier_val); 920 921 if (config.flags & SC16IS7XX_RECONF_RS485) 922 sc16is7xx_reconf_rs485(&one->port); 923 } 924 925 static void sc16is7xx_ms_proc(struct kthread_work *ws) 926 { 927 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work); 928 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev); 929 930 if (one->port.state) { 931 mutex_lock(&one->efr_lock); 932 sc16is7xx_update_mlines(one); 933 mutex_unlock(&one->efr_lock); 934 935 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ); 936 } 937 } 938 939 static void sc16is7xx_enable_ms(struct uart_port *port) 940 { 941 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 942 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 943 944 lockdep_assert_held_once(&port->lock); 945 946 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0); 947 } 948 949 static void sc16is7xx_start_tx(struct uart_port *port) 950 { 951 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 952 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 953 954 kthread_queue_work(&s->kworker, &one->tx_work); 955 } 956 957 static void sc16is7xx_throttle(struct uart_port *port) 958 { 959 unsigned long flags; 960 961 /* 962 * Hardware flow control is enabled and thus the device ignores RTS 963 * value set in MCR register. Stop reading data from RX FIFO so the 964 * AutoRTS feature will de-activate RTS output. 965 */ 966 uart_port_lock_irqsave(port, &flags); 967 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 968 uart_port_unlock_irqrestore(port, flags); 969 } 970 971 static void sc16is7xx_unthrottle(struct uart_port *port) 972 { 973 unsigned long flags; 974 975 uart_port_lock_irqsave(port, &flags); 976 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT); 977 uart_port_unlock_irqrestore(port, flags); 978 } 979 980 static unsigned int sc16is7xx_tx_empty(struct uart_port *port) 981 { 982 unsigned int lsr; 983 984 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 985 986 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0; 987 } 988 989 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port) 990 { 991 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 992 993 /* Called with port lock taken so we can only return cached value */ 994 return one->old_mctrl; 995 } 996 997 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl) 998 { 999 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1000 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1001 1002 one->config.flags |= SC16IS7XX_RECONF_MD; 1003 kthread_queue_work(&s->kworker, &one->reg_work); 1004 } 1005 1006 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state) 1007 { 1008 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG, 1009 SC16IS7XX_LCR_TXBREAK_BIT, 1010 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0); 1011 } 1012 1013 static void sc16is7xx_set_termios(struct uart_port *port, 1014 struct ktermios *termios, 1015 const struct ktermios *old) 1016 { 1017 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1018 unsigned int lcr, flow = 0; 1019 int baud; 1020 unsigned long flags; 1021 1022 kthread_cancel_delayed_work_sync(&one->ms_work); 1023 1024 /* Mask termios capabilities we don't support */ 1025 termios->c_cflag &= ~CMSPAR; 1026 1027 /* Word size */ 1028 switch (termios->c_cflag & CSIZE) { 1029 case CS5: 1030 lcr = SC16IS7XX_LCR_WORD_LEN_5; 1031 break; 1032 case CS6: 1033 lcr = SC16IS7XX_LCR_WORD_LEN_6; 1034 break; 1035 case CS7: 1036 lcr = SC16IS7XX_LCR_WORD_LEN_7; 1037 break; 1038 case CS8: 1039 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1040 break; 1041 default: 1042 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1043 termios->c_cflag &= ~CSIZE; 1044 termios->c_cflag |= CS8; 1045 break; 1046 } 1047 1048 /* Parity */ 1049 if (termios->c_cflag & PARENB) { 1050 lcr |= SC16IS7XX_LCR_PARITY_BIT; 1051 if (!(termios->c_cflag & PARODD)) 1052 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT; 1053 } 1054 1055 /* Stop bits */ 1056 if (termios->c_cflag & CSTOPB) 1057 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */ 1058 1059 /* Set read status mask */ 1060 port->read_status_mask = SC16IS7XX_LSR_OE_BIT; 1061 if (termios->c_iflag & INPCK) 1062 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT | 1063 SC16IS7XX_LSR_FE_BIT; 1064 if (termios->c_iflag & (BRKINT | PARMRK)) 1065 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT; 1066 1067 /* Set status ignore mask */ 1068 port->ignore_status_mask = 0; 1069 if (termios->c_iflag & IGNBRK) 1070 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT; 1071 if (!(termios->c_cflag & CREAD)) 1072 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK; 1073 1074 /* Configure flow control */ 1075 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1076 if (termios->c_cflag & CRTSCTS) { 1077 flow |= SC16IS7XX_EFR_AUTOCTS_BIT | 1078 SC16IS7XX_EFR_AUTORTS_BIT; 1079 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1080 } 1081 if (termios->c_iflag & IXON) 1082 flow |= SC16IS7XX_EFR_SWFLOW3_BIT; 1083 if (termios->c_iflag & IXOFF) 1084 flow |= SC16IS7XX_EFR_SWFLOW1_BIT; 1085 1086 /* Update LCR register */ 1087 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 1088 1089 /* Update EFR registers */ 1090 sc16is7xx_efr_lock(port); 1091 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]); 1092 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]); 1093 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 1094 SC16IS7XX_EFR_FLOWCTRL_BITS, flow); 1095 sc16is7xx_efr_unlock(port); 1096 1097 /* Get baud rate generator configuration */ 1098 baud = uart_get_baud_rate(port, termios, old, 1099 port->uartclk / 16 / 4 / 0xffff, 1100 port->uartclk / 16); 1101 1102 /* Setup baudrate generator */ 1103 baud = sc16is7xx_set_baud(port, baud); 1104 1105 uart_port_lock_irqsave(port, &flags); 1106 1107 /* Update timeout according to new baud rate */ 1108 uart_update_timeout(port, termios->c_cflag, baud); 1109 1110 if (UART_ENABLE_MS(port, termios->c_cflag)) 1111 sc16is7xx_enable_ms(port); 1112 1113 uart_port_unlock_irqrestore(port, flags); 1114 } 1115 1116 static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios, 1117 struct serial_rs485 *rs485) 1118 { 1119 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1120 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1121 1122 if (rs485->flags & SER_RS485_ENABLED) { 1123 /* 1124 * RTS signal is handled by HW, it's timing can't be influenced. 1125 * However, it's sometimes useful to delay TX even without RTS 1126 * control therefore we try to handle .delay_rts_before_send. 1127 */ 1128 if (rs485->delay_rts_after_send) 1129 return -EINVAL; 1130 } 1131 1132 one->config.flags |= SC16IS7XX_RECONF_RS485; 1133 kthread_queue_work(&s->kworker, &one->reg_work); 1134 1135 return 0; 1136 } 1137 1138 static int sc16is7xx_startup(struct uart_port *port) 1139 { 1140 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1141 unsigned int val; 1142 unsigned long flags; 1143 1144 sc16is7xx_power(port, 1); 1145 1146 /* Reset FIFOs*/ 1147 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT; 1148 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val); 1149 udelay(5); 1150 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, 1151 SC16IS7XX_FCR_FIFO_BIT); 1152 1153 /* Enable EFR */ 1154 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 1155 SC16IS7XX_LCR_CONF_MODE_B); 1156 1157 regcache_cache_bypass(one->regmap, true); 1158 1159 /* Enable write access to enhanced features and internal clock div */ 1160 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 1161 SC16IS7XX_EFR_ENABLE_BIT, 1162 SC16IS7XX_EFR_ENABLE_BIT); 1163 1164 /* Enable TCR/TLR */ 1165 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1166 SC16IS7XX_MCR_TCRTLR_BIT, 1167 SC16IS7XX_MCR_TCRTLR_BIT); 1168 1169 /* Configure flow control levels */ 1170 /* Flow control halt level 48, resume level 24 */ 1171 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG, 1172 SC16IS7XX_TCR_RX_RESUME(24) | 1173 SC16IS7XX_TCR_RX_HALT(48)); 1174 1175 regcache_cache_bypass(one->regmap, false); 1176 1177 /* Now, initialize the UART */ 1178 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8); 1179 1180 /* Enable IrDA mode if requested in DT */ 1181 /* This bit must be written with LCR[7] = 0 */ 1182 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1183 SC16IS7XX_MCR_IRDA_BIT, 1184 one->irda_mode ? 1185 SC16IS7XX_MCR_IRDA_BIT : 0); 1186 1187 /* Enable the Rx and Tx FIFO */ 1188 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1189 SC16IS7XX_EFCR_RXDISABLE_BIT | 1190 SC16IS7XX_EFCR_TXDISABLE_BIT, 1191 0); 1192 1193 /* Enable RX, CTS change and modem lines interrupts */ 1194 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT | 1195 SC16IS7XX_IER_MSI_BIT; 1196 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); 1197 1198 /* Enable modem status polling */ 1199 uart_port_lock_irqsave(port, &flags); 1200 sc16is7xx_enable_ms(port); 1201 uart_port_unlock_irqrestore(port, flags); 1202 1203 return 0; 1204 } 1205 1206 static void sc16is7xx_shutdown(struct uart_port *port) 1207 { 1208 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1209 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1210 1211 kthread_cancel_delayed_work_sync(&one->ms_work); 1212 1213 /* Disable all interrupts */ 1214 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0); 1215 /* Disable TX/RX */ 1216 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1217 SC16IS7XX_EFCR_RXDISABLE_BIT | 1218 SC16IS7XX_EFCR_TXDISABLE_BIT, 1219 SC16IS7XX_EFCR_RXDISABLE_BIT | 1220 SC16IS7XX_EFCR_TXDISABLE_BIT); 1221 1222 sc16is7xx_power(port, 0); 1223 1224 kthread_flush_worker(&s->kworker); 1225 } 1226 1227 static const char *sc16is7xx_type(struct uart_port *port) 1228 { 1229 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1230 1231 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL; 1232 } 1233 1234 static int sc16is7xx_request_port(struct uart_port *port) 1235 { 1236 /* Do nothing */ 1237 return 0; 1238 } 1239 1240 static void sc16is7xx_config_port(struct uart_port *port, int flags) 1241 { 1242 if (flags & UART_CONFIG_TYPE) 1243 port->type = PORT_SC16IS7XX; 1244 } 1245 1246 static int sc16is7xx_verify_port(struct uart_port *port, 1247 struct serial_struct *s) 1248 { 1249 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX)) 1250 return -EINVAL; 1251 if (s->irq != port->irq) 1252 return -EINVAL; 1253 1254 return 0; 1255 } 1256 1257 static void sc16is7xx_pm(struct uart_port *port, unsigned int state, 1258 unsigned int oldstate) 1259 { 1260 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0); 1261 } 1262 1263 static void sc16is7xx_null_void(struct uart_port *port) 1264 { 1265 /* Do nothing */ 1266 } 1267 1268 static const struct uart_ops sc16is7xx_ops = { 1269 .tx_empty = sc16is7xx_tx_empty, 1270 .set_mctrl = sc16is7xx_set_mctrl, 1271 .get_mctrl = sc16is7xx_get_mctrl, 1272 .stop_tx = sc16is7xx_stop_tx, 1273 .start_tx = sc16is7xx_start_tx, 1274 .throttle = sc16is7xx_throttle, 1275 .unthrottle = sc16is7xx_unthrottle, 1276 .stop_rx = sc16is7xx_stop_rx, 1277 .enable_ms = sc16is7xx_enable_ms, 1278 .break_ctl = sc16is7xx_break_ctl, 1279 .startup = sc16is7xx_startup, 1280 .shutdown = sc16is7xx_shutdown, 1281 .set_termios = sc16is7xx_set_termios, 1282 .type = sc16is7xx_type, 1283 .request_port = sc16is7xx_request_port, 1284 .release_port = sc16is7xx_null_void, 1285 .config_port = sc16is7xx_config_port, 1286 .verify_port = sc16is7xx_verify_port, 1287 .pm = sc16is7xx_pm, 1288 }; 1289 1290 #ifdef CONFIG_GPIOLIB 1291 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset) 1292 { 1293 unsigned int val; 1294 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1295 struct uart_port *port = &s->p[0].port; 1296 1297 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1298 1299 return !!(val & BIT(offset)); 1300 } 1301 1302 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 1303 { 1304 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1305 struct uart_port *port = &s->p[0].port; 1306 1307 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), 1308 val ? BIT(offset) : 0); 1309 } 1310 1311 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip, 1312 unsigned offset) 1313 { 1314 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1315 struct uart_port *port = &s->p[0].port; 1316 1317 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0); 1318 1319 return 0; 1320 } 1321 1322 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, 1323 unsigned offset, int val) 1324 { 1325 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1326 struct uart_port *port = &s->p[0].port; 1327 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1328 1329 if (val) 1330 state |= BIT(offset); 1331 else 1332 state &= ~BIT(offset); 1333 1334 /* 1335 * If we write IOSTATE first, and then IODIR, the output value is not 1336 * transferred to the corresponding I/O pin. 1337 * The datasheet states that each register bit will be transferred to 1338 * the corresponding I/O pin programmed as output when writing to 1339 * IOSTATE. Therefore, configure direction first with IODIR, and then 1340 * set value after with IOSTATE. 1341 */ 1342 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 1343 BIT(offset)); 1344 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); 1345 1346 return 0; 1347 } 1348 1349 static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip, 1350 unsigned long *valid_mask, 1351 unsigned int ngpios) 1352 { 1353 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1354 1355 *valid_mask = s->gpio_valid_mask; 1356 1357 return 0; 1358 } 1359 1360 static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s) 1361 { 1362 struct device *dev = s->p[0].port.dev; 1363 1364 if (!s->devtype->nr_gpio) 1365 return 0; 1366 1367 switch (s->mctrl_mask) { 1368 case 0: 1369 s->gpio_valid_mask = GENMASK(7, 0); 1370 break; 1371 case SC16IS7XX_IOCONTROL_MODEM_A_BIT: 1372 s->gpio_valid_mask = GENMASK(3, 0); 1373 break; 1374 case SC16IS7XX_IOCONTROL_MODEM_B_BIT: 1375 s->gpio_valid_mask = GENMASK(7, 4); 1376 break; 1377 default: 1378 break; 1379 } 1380 1381 if (s->gpio_valid_mask == 0) 1382 return 0; 1383 1384 s->gpio.owner = THIS_MODULE; 1385 s->gpio.parent = dev; 1386 s->gpio.label = dev_name(dev); 1387 s->gpio.init_valid_mask = sc16is7xx_gpio_init_valid_mask; 1388 s->gpio.direction_input = sc16is7xx_gpio_direction_input; 1389 s->gpio.get = sc16is7xx_gpio_get; 1390 s->gpio.direction_output = sc16is7xx_gpio_direction_output; 1391 s->gpio.set = sc16is7xx_gpio_set; 1392 s->gpio.base = -1; 1393 s->gpio.ngpio = s->devtype->nr_gpio; 1394 s->gpio.can_sleep = 1; 1395 1396 return gpiochip_add_data(&s->gpio, s); 1397 } 1398 #endif 1399 1400 static void sc16is7xx_setup_irda_ports(struct sc16is7xx_port *s) 1401 { 1402 int i; 1403 int ret; 1404 int count; 1405 u32 irda_port[SC16IS7XX_MAX_PORTS]; 1406 struct device *dev = s->p[0].port.dev; 1407 1408 count = device_property_count_u32(dev, "irda-mode-ports"); 1409 if (count < 0 || count > ARRAY_SIZE(irda_port)) 1410 return; 1411 1412 ret = device_property_read_u32_array(dev, "irda-mode-ports", 1413 irda_port, count); 1414 if (ret) 1415 return; 1416 1417 for (i = 0; i < count; i++) { 1418 if (irda_port[i] < s->devtype->nr_uart) 1419 s->p[irda_port[i]].irda_mode = true; 1420 } 1421 } 1422 1423 /* 1424 * Configure ports designated to operate as modem control lines. 1425 */ 1426 static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s, 1427 struct regmap *regmap) 1428 { 1429 int i; 1430 int ret; 1431 int count; 1432 u32 mctrl_port[SC16IS7XX_MAX_PORTS]; 1433 struct device *dev = s->p[0].port.dev; 1434 1435 count = device_property_count_u32(dev, "nxp,modem-control-line-ports"); 1436 if (count < 0 || count > ARRAY_SIZE(mctrl_port)) 1437 return 0; 1438 1439 ret = device_property_read_u32_array(dev, "nxp,modem-control-line-ports", 1440 mctrl_port, count); 1441 if (ret) 1442 return ret; 1443 1444 s->mctrl_mask = 0; 1445 1446 for (i = 0; i < count; i++) { 1447 /* Use GPIO lines as modem control lines */ 1448 if (mctrl_port[i] == 0) 1449 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT; 1450 else if (mctrl_port[i] == 1) 1451 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT; 1452 } 1453 1454 if (s->mctrl_mask) 1455 regmap_update_bits( 1456 regmap, 1457 SC16IS7XX_IOCONTROL_REG, 1458 SC16IS7XX_IOCONTROL_MODEM_A_BIT | 1459 SC16IS7XX_IOCONTROL_MODEM_B_BIT, s->mctrl_mask); 1460 1461 return 0; 1462 } 1463 1464 static const struct serial_rs485 sc16is7xx_rs485_supported = { 1465 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND, 1466 .delay_rts_before_send = 1, 1467 .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */ 1468 }; 1469 1470 int sc16is7xx_probe(struct device *dev, const struct sc16is7xx_devtype *devtype, 1471 struct regmap *regmaps[], int irq) 1472 { 1473 unsigned long freq = 0, *pfreq = dev_get_platdata(dev); 1474 unsigned int val; 1475 u32 uartclk = 0; 1476 int i, ret; 1477 struct sc16is7xx_port *s; 1478 bool port_registered[SC16IS7XX_MAX_PORTS]; 1479 1480 for (i = 0; i < devtype->nr_uart; i++) 1481 if (IS_ERR(regmaps[i])) 1482 return PTR_ERR(regmaps[i]); 1483 1484 /* 1485 * This device does not have an identification register that would 1486 * tell us if we are really connected to the correct device. 1487 * The best we can do is to check if communication is at all possible. 1488 * 1489 * Note: regmap[0] is used in the probe function to access registers 1490 * common to all channels/ports, as it is guaranteed to be present on 1491 * all variants. 1492 */ 1493 ret = regmap_read(regmaps[0], SC16IS7XX_LSR_REG, &val); 1494 if (ret < 0) 1495 return -EPROBE_DEFER; 1496 1497 /* Alloc port structure */ 1498 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL); 1499 if (!s) { 1500 dev_err(dev, "Error allocating port structure\n"); 1501 return -ENOMEM; 1502 } 1503 1504 /* Always ask for fixed clock rate from a property. */ 1505 device_property_read_u32(dev, "clock-frequency", &uartclk); 1506 1507 s->clk = devm_clk_get_optional(dev, NULL); 1508 if (IS_ERR(s->clk)) 1509 return PTR_ERR(s->clk); 1510 1511 ret = clk_prepare_enable(s->clk); 1512 if (ret) 1513 return ret; 1514 1515 freq = clk_get_rate(s->clk); 1516 if (freq == 0) { 1517 if (uartclk) 1518 freq = uartclk; 1519 if (pfreq) 1520 freq = *pfreq; 1521 if (freq) 1522 dev_dbg(dev, "Clock frequency: %luHz\n", freq); 1523 else 1524 return -EINVAL; 1525 } 1526 1527 s->devtype = devtype; 1528 dev_set_drvdata(dev, s); 1529 1530 kthread_init_worker(&s->kworker); 1531 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker, 1532 "sc16is7xx"); 1533 if (IS_ERR(s->kworker_task)) { 1534 ret = PTR_ERR(s->kworker_task); 1535 goto out_clk; 1536 } 1537 sched_set_fifo(s->kworker_task); 1538 1539 /* reset device, purging any pending irq / data */ 1540 regmap_write(regmaps[0], SC16IS7XX_IOCONTROL_REG, 1541 SC16IS7XX_IOCONTROL_SRESET_BIT); 1542 1543 /* Mark each port line and status as uninitialised. */ 1544 for (i = 0; i < devtype->nr_uart; ++i) { 1545 s->p[i].port.line = SC16IS7XX_MAX_DEVS; 1546 port_registered[i] = false; 1547 } 1548 1549 for (i = 0; i < devtype->nr_uart; ++i) { 1550 ret = ida_alloc_max(&sc16is7xx_lines, 1551 SC16IS7XX_MAX_DEVS - 1, GFP_KERNEL); 1552 if (ret < 0) 1553 goto out_ports; 1554 1555 s->p[i].port.line = ret; 1556 1557 /* Initialize port data */ 1558 s->p[i].port.dev = dev; 1559 s->p[i].port.irq = irq; 1560 s->p[i].port.type = PORT_SC16IS7XX; 1561 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE; 1562 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1563 s->p[i].port.iobase = i; 1564 /* 1565 * Use all ones as membase to make sure uart_configure_port() in 1566 * serial_core.c does not abort for SPI/I2C devices where the 1567 * membase address is not applicable. 1568 */ 1569 s->p[i].port.membase = (void __iomem *)~0; 1570 s->p[i].port.iotype = UPIO_PORT; 1571 s->p[i].port.uartclk = freq; 1572 s->p[i].port.rs485_config = sc16is7xx_config_rs485; 1573 s->p[i].port.rs485_supported = sc16is7xx_rs485_supported; 1574 s->p[i].port.ops = &sc16is7xx_ops; 1575 s->p[i].old_mctrl = 0; 1576 s->p[i].regmap = regmaps[i]; 1577 1578 mutex_init(&s->p[i].efr_lock); 1579 1580 ret = uart_get_rs485_mode(&s->p[i].port); 1581 if (ret) 1582 goto out_ports; 1583 1584 /* Disable all interrupts */ 1585 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0); 1586 /* Disable TX/RX */ 1587 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG, 1588 SC16IS7XX_EFCR_RXDISABLE_BIT | 1589 SC16IS7XX_EFCR_TXDISABLE_BIT); 1590 1591 /* Initialize kthread work structs */ 1592 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc); 1593 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc); 1594 kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc); 1595 1596 /* Register port */ 1597 ret = uart_add_one_port(&sc16is7xx_uart, &s->p[i].port); 1598 if (ret) 1599 goto out_ports; 1600 1601 port_registered[i] = true; 1602 1603 /* Enable EFR */ 1604 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 1605 SC16IS7XX_LCR_CONF_MODE_B); 1606 1607 regcache_cache_bypass(regmaps[i], true); 1608 1609 /* Enable write access to enhanced features */ 1610 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG, 1611 SC16IS7XX_EFR_ENABLE_BIT); 1612 1613 regcache_cache_bypass(regmaps[i], false); 1614 1615 /* Restore access to general registers */ 1616 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00); 1617 1618 /* Go to suspend mode */ 1619 sc16is7xx_power(&s->p[i].port, 0); 1620 } 1621 1622 sc16is7xx_setup_irda_ports(s); 1623 1624 ret = sc16is7xx_setup_mctrl_ports(s, regmaps[0]); 1625 if (ret) 1626 goto out_ports; 1627 1628 #ifdef CONFIG_GPIOLIB 1629 ret = sc16is7xx_setup_gpio_chip(s); 1630 if (ret) 1631 goto out_ports; 1632 #endif 1633 1634 /* 1635 * Setup interrupt. We first try to acquire the IRQ line as level IRQ. 1636 * If that succeeds, we can allow sharing the interrupt as well. 1637 * In case the interrupt controller doesn't support that, we fall 1638 * back to a non-shared falling-edge trigger. 1639 */ 1640 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1641 IRQF_TRIGGER_LOW | IRQF_SHARED | 1642 IRQF_ONESHOT, 1643 dev_name(dev), s); 1644 if (!ret) 1645 return 0; 1646 1647 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1648 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1649 dev_name(dev), s); 1650 if (!ret) 1651 return 0; 1652 1653 #ifdef CONFIG_GPIOLIB 1654 if (s->gpio_valid_mask) 1655 gpiochip_remove(&s->gpio); 1656 #endif 1657 1658 out_ports: 1659 for (i = 0; i < devtype->nr_uart; i++) { 1660 if (s->p[i].port.line < SC16IS7XX_MAX_DEVS) 1661 ida_free(&sc16is7xx_lines, s->p[i].port.line); 1662 if (port_registered[i]) 1663 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1664 } 1665 1666 kthread_stop(s->kworker_task); 1667 1668 out_clk: 1669 clk_disable_unprepare(s->clk); 1670 1671 return ret; 1672 } 1673 EXPORT_SYMBOL_GPL(sc16is7xx_probe); 1674 1675 void sc16is7xx_remove(struct device *dev) 1676 { 1677 struct sc16is7xx_port *s = dev_get_drvdata(dev); 1678 int i; 1679 1680 #ifdef CONFIG_GPIOLIB 1681 if (s->gpio_valid_mask) 1682 gpiochip_remove(&s->gpio); 1683 #endif 1684 1685 for (i = 0; i < s->devtype->nr_uart; i++) { 1686 kthread_cancel_delayed_work_sync(&s->p[i].ms_work); 1687 ida_free(&sc16is7xx_lines, s->p[i].port.line); 1688 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1689 sc16is7xx_power(&s->p[i].port, 0); 1690 } 1691 1692 kthread_flush_worker(&s->kworker); 1693 kthread_stop(s->kworker_task); 1694 1695 clk_disable_unprepare(s->clk); 1696 } 1697 EXPORT_SYMBOL_GPL(sc16is7xx_remove); 1698 1699 const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = { 1700 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, }, 1701 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, }, 1702 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, }, 1703 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, }, 1704 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, }, 1705 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, }, 1706 { } 1707 }; 1708 EXPORT_SYMBOL_GPL(sc16is7xx_dt_ids); 1709 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids); 1710 1711 const struct regmap_config sc16is7xx_regcfg = { 1712 .reg_bits = 5, 1713 .pad_bits = 3, 1714 .val_bits = 8, 1715 .cache_type = REGCACHE_MAPLE, 1716 .volatile_reg = sc16is7xx_regmap_volatile, 1717 .precious_reg = sc16is7xx_regmap_precious, 1718 .writeable_noinc_reg = sc16is7xx_regmap_noinc, 1719 .readable_noinc_reg = sc16is7xx_regmap_noinc, 1720 .max_raw_read = SC16IS7XX_FIFO_SIZE, 1721 .max_raw_write = SC16IS7XX_FIFO_SIZE, 1722 .max_register = SC16IS7XX_EFCR_REG, 1723 }; 1724 EXPORT_SYMBOL_GPL(sc16is7xx_regcfg); 1725 1726 const char *sc16is7xx_regmap_name(u8 port_id) 1727 { 1728 switch (port_id) { 1729 case 0: return "port0"; 1730 case 1: return "port1"; 1731 default: 1732 WARN_ON(true); 1733 return NULL; 1734 } 1735 } 1736 EXPORT_SYMBOL_GPL(sc16is7xx_regmap_name); 1737 1738 unsigned int sc16is7xx_regmap_port_mask(unsigned int port_id) 1739 { 1740 /* CH1,CH0 are at bits 2:1. */ 1741 return port_id << 1; 1742 } 1743 EXPORT_SYMBOL_GPL(sc16is7xx_regmap_port_mask); 1744 1745 static int __init sc16is7xx_init(void) 1746 { 1747 return uart_register_driver(&sc16is7xx_uart); 1748 } 1749 module_init(sc16is7xx_init); 1750 1751 static void __exit sc16is7xx_exit(void) 1752 { 1753 uart_unregister_driver(&sc16is7xx_uart); 1754 } 1755 module_exit(sc16is7xx_exit); 1756 1757 MODULE_LICENSE("GPL"); 1758 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>"); 1759 MODULE_DESCRIPTION("SC16IS7xx tty serial core driver"); 1760