1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SC16IS7xx tty serial driver - common code 4 * 5 * Copyright (C) 2014 GridPoint 6 * Author: Jon Ringle <jringle@gridpoint.com> 7 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru> 8 */ 9 10 #undef DEFAULT_SYMBOL_NAMESPACE 11 #define DEFAULT_SYMBOL_NAMESPACE SERIAL_NXP_SC16IS7XX 12 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/export.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/gpio/driver.h> 19 #include <linux/idr.h> 20 #include <linux/kthread.h> 21 #include <linux/mod_devicetable.h> 22 #include <linux/module.h> 23 #include <linux/property.h> 24 #include <linux/regmap.h> 25 #include <linux/sched.h> 26 #include <linux/serial_core.h> 27 #include <linux/serial.h> 28 #include <linux/string.h> 29 #include <linux/tty.h> 30 #include <linux/tty_flip.h> 31 #include <linux/uaccess.h> 32 #include <linux/units.h> 33 34 #include "sc16is7xx.h" 35 36 #define SC16IS7XX_MAX_DEVS 8 37 38 /* SC16IS7XX register definitions */ 39 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */ 40 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */ 41 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */ 42 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */ 43 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */ 44 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */ 45 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */ 46 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */ 47 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */ 48 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */ 49 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */ 50 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */ 51 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction 52 * - only on 75x/76x 53 */ 54 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State 55 * - only on 75x/76x 56 */ 57 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable 58 * - only on 75x/76x 59 */ 60 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control 61 * - only on 75x/76x 62 */ 63 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */ 64 65 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */ 66 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */ 67 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */ 68 69 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */ 70 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */ 71 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */ 72 73 /* Enhanced Register set: Only if (LCR == 0xBF) */ 74 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */ 75 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */ 76 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */ 77 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */ 78 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */ 79 80 /* IER register bits */ 81 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */ 82 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register 83 * interrupt */ 84 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status 85 * interrupt */ 86 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status 87 * interrupt */ 88 89 /* IER register bits - write only if (EFR[4] == 1) */ 90 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */ 91 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */ 92 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */ 93 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */ 94 95 /* FCR register bits */ 96 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */ 97 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */ 98 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */ 99 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */ 100 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */ 101 102 /* FCR register bits - write only if (EFR[4] == 1) */ 103 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */ 104 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */ 105 106 /* IIR register bits */ 107 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */ 108 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */ 109 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */ 110 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */ 111 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */ 112 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */ 113 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt 114 * - only on 75x/76x 115 */ 116 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state 117 * - only on 75x/76x 118 */ 119 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */ 120 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state 121 * from active (LOW) 122 * to inactive (HIGH) 123 */ 124 /* LCR register bits */ 125 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 126 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 127 * 128 * Word length bits table: 129 * 00 -> 5 bit words 130 * 01 -> 6 bit words 131 * 10 -> 7 bit words 132 * 11 -> 8 bit words 133 */ 134 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 135 * 136 * STOP length bit table: 137 * 0 -> 1 stop bit 138 * 1 -> 1-1.5 stop bits if 139 * word length is 5, 140 * 2 stop bits otherwise 141 */ 142 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 143 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 144 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 145 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 146 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */ 147 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00) 148 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01) 149 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02) 150 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03) 151 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special 152 * reg set */ 153 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced 154 * reg set */ 155 156 /* MCR register bits */ 157 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement 158 * - only on 75x/76x 159 */ 160 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */ 161 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */ 162 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */ 163 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any 164 * - write enabled 165 * if (EFR[4] == 1) 166 */ 167 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode 168 * - write enabled 169 * if (EFR[4] == 1) 170 */ 171 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4 172 * - write enabled 173 * if (EFR[4] == 1) 174 */ 175 176 /* LSR register bits */ 177 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */ 178 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */ 179 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */ 180 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */ 181 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */ 182 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */ 183 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */ 184 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */ 185 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */ 186 187 /* MSR register bits */ 188 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */ 189 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready 190 * or (IO4) 191 * - only on 75x/76x 192 */ 193 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator 194 * or (IO7) 195 * - only on 75x/76x 196 */ 197 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect 198 * or (IO6) 199 * - only on 75x/76x 200 */ 201 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */ 202 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4) 203 * - only on 75x/76x 204 */ 205 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7) 206 * - only on 75x/76x 207 */ 208 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6) 209 * - only on 75x/76x 210 */ 211 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */ 212 213 /* 214 * TCR register bits 215 * TCR trigger levels are available from 0 to 60 characters with a granularity 216 * of four. 217 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is 218 * no built-in hardware check to make sure this condition is met. Also, the TCR 219 * must be programmed with this condition before auto RTS or software flow 220 * control is enabled to avoid spurious operation of the device. 221 */ 222 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0) 223 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4) 224 225 /* 226 * TLR register bits 227 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the 228 * FIFO Control Register (FCR) are used for the transmit and receive FIFO 229 * trigger levels. Trigger levels from 4 characters to 60 characters are 230 * available with a granularity of four. 231 * 232 * When the trigger level setting in TLR is zero, the SC16IS74x/75x/76x uses the 233 * trigger level setting defined in FCR. If TLR has non-zero trigger level value 234 * the trigger level defined in FCR is discarded. This applies to both transmit 235 * FIFO and receive FIFO trigger level setting. 236 * 237 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the 238 * default state, that is, '00'. 239 */ 240 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0) 241 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) 242 243 /* IOControl register bits (Only 75x/76x) */ 244 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ 245 #define SC16IS7XX_IOCONTROL_MODEM_A_BIT (1 << 1) /* Enable GPIO[7:4] as modem A pins */ 246 #define SC16IS7XX_IOCONTROL_MODEM_B_BIT (1 << 2) /* Enable GPIO[3:0] as modem B pins */ 247 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */ 248 249 /* EFCR register bits */ 250 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop 251 * mode (RS485) */ 252 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */ 253 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */ 254 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */ 255 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */ 256 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode 257 * 0 = rate upto 115.2 kbit/s 258 * - Only 75x/76x 259 * 1 = rate upto 1.152 Mbit/s 260 * - Only 76x 261 */ 262 263 /* EFR register bits */ 264 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */ 265 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */ 266 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */ 267 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions 268 * and writing to IER[7:4], 269 * FCR[5:4], MCR[7:5] 270 */ 271 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */ 272 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2 273 * 274 * SWFLOW bits 3 & 2 table: 275 * 00 -> no transmitter flow 276 * control 277 * 01 -> transmitter generates 278 * XON2 and XOFF2 279 * 10 -> transmitter generates 280 * XON1 and XOFF1 281 * 11 -> transmitter generates 282 * XON1, XON2, XOFF1 and 283 * XOFF2 284 */ 285 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */ 286 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3 287 * 288 * SWFLOW bits 3 & 2 table: 289 * 00 -> no received flow 290 * control 291 * 01 -> receiver compares 292 * XON2 and XOFF2 293 * 10 -> receiver compares 294 * XON1 and XOFF1 295 * 11 -> receiver compares 296 * XON1, XON2, XOFF1 and 297 * XOFF2 298 */ 299 #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \ 300 SC16IS7XX_EFR_AUTOCTS_BIT | \ 301 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \ 302 SC16IS7XX_EFR_SWFLOW3_BIT | \ 303 SC16IS7XX_EFR_SWFLOW2_BIT | \ 304 SC16IS7XX_EFR_SWFLOW1_BIT | \ 305 SC16IS7XX_EFR_SWFLOW0_BIT) 306 307 308 /* Misc definitions */ 309 #define SC16IS7XX_FIFO_SIZE (64) 310 #define SC16IS7XX_GPIOS_PER_BANK 4 311 312 #define SC16IS7XX_RECONF_MD (1 << 0) 313 #define SC16IS7XX_RECONF_IER (1 << 1) 314 #define SC16IS7XX_RECONF_RS485 (1 << 2) 315 316 struct sc16is7xx_one_config { 317 unsigned int flags; 318 u8 ier_mask; 319 u8 ier_val; 320 }; 321 322 struct sc16is7xx_one { 323 struct uart_port port; 324 struct regmap *regmap; 325 struct mutex efr_lock; /* EFR registers access */ 326 struct kthread_work tx_work; 327 struct kthread_work reg_work; 328 struct kthread_delayed_work ms_work; 329 struct sc16is7xx_one_config config; 330 unsigned char buf[SC16IS7XX_FIFO_SIZE]; /* Rx buffer. */ 331 unsigned int old_mctrl; 332 u8 old_lcr; /* Value before EFR access. */ 333 bool irda_mode; 334 }; 335 336 struct sc16is7xx_port { 337 const struct sc16is7xx_devtype *devtype; 338 struct clk *clk; 339 #ifdef CONFIG_GPIOLIB 340 struct gpio_chip gpio; 341 unsigned long gpio_valid_mask; 342 #endif 343 u8 mctrl_mask; 344 struct kthread_worker kworker; 345 struct task_struct *kworker_task; 346 struct sc16is7xx_one p[]; 347 }; 348 349 static DEFINE_IDA(sc16is7xx_lines); 350 351 static struct uart_driver sc16is7xx_uart = { 352 .owner = THIS_MODULE, 353 .driver_name = SC16IS7XX_NAME, 354 .dev_name = "ttySC", 355 .nr = SC16IS7XX_MAX_DEVS, 356 }; 357 358 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e))) 359 360 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg) 361 { 362 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 363 unsigned int val = 0; 364 365 regmap_read(one->regmap, reg, &val); 366 367 return val; 368 } 369 370 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val) 371 { 372 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 373 374 regmap_write(one->regmap, reg, val); 375 } 376 377 static void sc16is7xx_fifo_read(struct uart_port *port, u8 *rxbuf, unsigned int rxlen) 378 { 379 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 380 381 regmap_noinc_read(one->regmap, SC16IS7XX_RHR_REG, rxbuf, rxlen); 382 } 383 384 static void sc16is7xx_fifo_write(struct uart_port *port, u8 *txbuf, u8 to_send) 385 { 386 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 387 388 /* 389 * Don't send zero-length data, at least on SPI it confuses the chip 390 * delivering wrong TXLVL data. 391 */ 392 if (unlikely(!to_send)) 393 return; 394 395 regmap_noinc_write(one->regmap, SC16IS7XX_THR_REG, txbuf, to_send); 396 } 397 398 static void sc16is7xx_port_update(struct uart_port *port, u8 reg, 399 u8 mask, u8 val) 400 { 401 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 402 403 regmap_update_bits(one->regmap, reg, mask, val); 404 } 405 406 static void sc16is7xx_power(struct uart_port *port, int on) 407 { 408 sc16is7xx_port_update(port, SC16IS7XX_IER_REG, 409 SC16IS7XX_IER_SLEEP_BIT, 410 on ? 0 : SC16IS7XX_IER_SLEEP_BIT); 411 } 412 413 /* 414 * In an amazing feat of design, the Enhanced Features Register (EFR) 415 * shares the address of the Interrupt Identification Register (IIR). 416 * Access to EFR is switched on by writing a magic value (0xbf) to the 417 * Line Control Register (LCR). Any interrupt firing during this time will 418 * see the EFR where it expects the IIR to be, leading to 419 * "Unexpected interrupt" messages. 420 * 421 * Prevent this possibility by claiming a mutex while accessing the EFR, 422 * and claiming the same mutex from within the interrupt handler. This is 423 * similar to disabling the interrupt, but that doesn't work because the 424 * bulk of the interrupt processing is run as a workqueue job in thread 425 * context. 426 */ 427 static void sc16is7xx_efr_lock(struct uart_port *port) 428 { 429 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 430 431 mutex_lock(&one->efr_lock); 432 433 /* Backup content of LCR. */ 434 one->old_lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); 435 436 /* Enable access to Enhanced register set */ 437 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_CONF_MODE_B); 438 439 /* Disable cache updates when writing to EFR registers */ 440 regcache_cache_bypass(one->regmap, true); 441 } 442 443 static void sc16is7xx_efr_unlock(struct uart_port *port) 444 { 445 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 446 447 /* Re-enable cache updates when writing to normal registers */ 448 regcache_cache_bypass(one->regmap, false); 449 450 /* Restore original content of LCR */ 451 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, one->old_lcr); 452 453 mutex_unlock(&one->efr_lock); 454 } 455 456 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit) 457 { 458 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 459 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 460 461 lockdep_assert_held_once(&port->lock); 462 463 one->config.flags |= SC16IS7XX_RECONF_IER; 464 one->config.ier_mask |= bit; 465 one->config.ier_val &= ~bit; 466 kthread_queue_work(&s->kworker, &one->reg_work); 467 } 468 469 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit) 470 { 471 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 472 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 473 474 lockdep_assert_held_once(&port->lock); 475 476 one->config.flags |= SC16IS7XX_RECONF_IER; 477 one->config.ier_mask |= bit; 478 one->config.ier_val |= bit; 479 kthread_queue_work(&s->kworker, &one->reg_work); 480 } 481 482 static void sc16is7xx_stop_tx(struct uart_port *port) 483 { 484 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT); 485 } 486 487 static void sc16is7xx_stop_rx(struct uart_port *port) 488 { 489 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 490 } 491 492 const struct sc16is7xx_devtype sc16is74x_devtype = { 493 .name = "SC16IS74X", 494 .nr_gpio = 0, 495 .nr_uart = 1, 496 }; 497 EXPORT_SYMBOL_GPL(sc16is74x_devtype); 498 499 const struct sc16is7xx_devtype sc16is750_devtype = { 500 .name = "SC16IS750", 501 .nr_gpio = 8, 502 .nr_uart = 1, 503 }; 504 EXPORT_SYMBOL_GPL(sc16is750_devtype); 505 506 const struct sc16is7xx_devtype sc16is752_devtype = { 507 .name = "SC16IS752", 508 .nr_gpio = 8, 509 .nr_uart = 2, 510 }; 511 EXPORT_SYMBOL_GPL(sc16is752_devtype); 512 513 const struct sc16is7xx_devtype sc16is760_devtype = { 514 .name = "SC16IS760", 515 .nr_gpio = 8, 516 .nr_uart = 1, 517 }; 518 EXPORT_SYMBOL_GPL(sc16is760_devtype); 519 520 const struct sc16is7xx_devtype sc16is762_devtype = { 521 .name = "SC16IS762", 522 .nr_gpio = 8, 523 .nr_uart = 2, 524 }; 525 EXPORT_SYMBOL_GPL(sc16is762_devtype); 526 527 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg) 528 { 529 switch (reg) { 530 case SC16IS7XX_RHR_REG: 531 case SC16IS7XX_IIR_REG: 532 case SC16IS7XX_LSR_REG: 533 case SC16IS7XX_MSR_REG: 534 case SC16IS7XX_TXLVL_REG: 535 case SC16IS7XX_RXLVL_REG: 536 case SC16IS7XX_IOSTATE_REG: 537 case SC16IS7XX_IOCONTROL_REG: 538 return true; 539 default: 540 return false; 541 } 542 } 543 544 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg) 545 { 546 switch (reg) { 547 case SC16IS7XX_RHR_REG: 548 return true; 549 default: 550 return false; 551 } 552 } 553 554 static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg) 555 { 556 return reg == SC16IS7XX_RHR_REG; 557 } 558 559 /* 560 * Configure programmable baud rate generator (divisor) according to the 561 * desired baud rate. 562 * 563 * From the datasheet, the divisor is computed according to: 564 * 565 * XTAL1 input frequency 566 * ----------------------- 567 * prescaler 568 * divisor = --------------------------- 569 * baud-rate x sampling-rate 570 */ 571 static int sc16is7xx_set_baud(struct uart_port *port, int baud) 572 { 573 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 574 u8 lcr; 575 unsigned int prescaler = 1; 576 unsigned long clk = port->uartclk, div = clk / 16 / baud; 577 578 if (div >= BIT(16)) { 579 prescaler = 4; 580 div /= prescaler; 581 } 582 583 /* Enable enhanced features */ 584 sc16is7xx_efr_lock(port); 585 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 586 SC16IS7XX_EFR_ENABLE_BIT, 587 SC16IS7XX_EFR_ENABLE_BIT); 588 sc16is7xx_efr_unlock(port); 589 590 /* If bit MCR_CLKSEL is set, the divide by 4 prescaler is activated. */ 591 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 592 SC16IS7XX_MCR_CLKSEL_BIT, 593 prescaler == 1 ? 0 : SC16IS7XX_MCR_CLKSEL_BIT); 594 595 mutex_lock(&one->efr_lock); 596 597 /* Backup LCR and access special register set (DLL/DLH) */ 598 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); 599 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 600 SC16IS7XX_LCR_CONF_MODE_A); 601 602 /* Write the new divisor */ 603 regcache_cache_bypass(one->regmap, true); 604 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256); 605 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256); 606 regcache_cache_bypass(one->regmap, false); 607 608 /* Restore LCR and access to general register set */ 609 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 610 611 mutex_unlock(&one->efr_lock); 612 613 return DIV_ROUND_CLOSEST((clk / prescaler) / 16, div); 614 } 615 616 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen, 617 unsigned int iir) 618 { 619 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 620 unsigned int lsr = 0, bytes_read, i; 621 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false; 622 u8 ch, flag; 623 624 if (unlikely(rxlen >= sizeof(one->buf))) { 625 dev_warn_ratelimited(port->dev, 626 "ttySC%i: Possible RX FIFO overrun: %d\n", 627 port->line, rxlen); 628 port->icount.buf_overrun++; 629 /* Ensure sanity of RX level */ 630 rxlen = sizeof(one->buf); 631 } 632 633 while (rxlen) { 634 /* Only read lsr if there are possible errors in FIFO */ 635 if (read_lsr) { 636 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 637 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT)) 638 read_lsr = false; /* No errors left in FIFO */ 639 } else 640 lsr = 0; 641 642 if (read_lsr) { 643 one->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG); 644 bytes_read = 1; 645 } else { 646 sc16is7xx_fifo_read(port, one->buf, rxlen); 647 bytes_read = rxlen; 648 } 649 650 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK; 651 652 port->icount.rx++; 653 flag = TTY_NORMAL; 654 655 if (unlikely(lsr)) { 656 if (lsr & SC16IS7XX_LSR_BI_BIT) { 657 port->icount.brk++; 658 if (uart_handle_break(port)) 659 continue; 660 } else if (lsr & SC16IS7XX_LSR_PE_BIT) 661 port->icount.parity++; 662 else if (lsr & SC16IS7XX_LSR_FE_BIT) 663 port->icount.frame++; 664 else if (lsr & SC16IS7XX_LSR_OE_BIT) 665 port->icount.overrun++; 666 667 lsr &= port->read_status_mask; 668 if (lsr & SC16IS7XX_LSR_BI_BIT) 669 flag = TTY_BREAK; 670 else if (lsr & SC16IS7XX_LSR_PE_BIT) 671 flag = TTY_PARITY; 672 else if (lsr & SC16IS7XX_LSR_FE_BIT) 673 flag = TTY_FRAME; 674 else if (lsr & SC16IS7XX_LSR_OE_BIT) 675 flag = TTY_OVERRUN; 676 } 677 678 for (i = 0; i < bytes_read; ++i) { 679 ch = one->buf[i]; 680 if (uart_handle_sysrq_char(port, ch)) 681 continue; 682 683 if (lsr & port->ignore_status_mask) 684 continue; 685 686 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch, 687 flag); 688 } 689 rxlen -= bytes_read; 690 } 691 692 tty_flip_buffer_push(&port->state->port); 693 } 694 695 static void sc16is7xx_handle_tx(struct uart_port *port) 696 { 697 struct tty_port *tport = &port->state->port; 698 unsigned long flags; 699 unsigned int txlen; 700 unsigned char *tail; 701 702 if (unlikely(port->x_char)) { 703 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char); 704 port->icount.tx++; 705 port->x_char = 0; 706 return; 707 } 708 709 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) { 710 uart_port_lock_irqsave(port, &flags); 711 sc16is7xx_stop_tx(port); 712 uart_port_unlock_irqrestore(port, flags); 713 return; 714 } 715 716 /* Limit to space available in TX FIFO */ 717 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG); 718 if (txlen > SC16IS7XX_FIFO_SIZE) { 719 dev_err_ratelimited(port->dev, 720 "chip reports %d free bytes in TX fifo, but it only has %d", 721 txlen, SC16IS7XX_FIFO_SIZE); 722 txlen = 0; 723 } 724 725 txlen = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, txlen); 726 sc16is7xx_fifo_write(port, tail, txlen); 727 uart_xmit_advance(port, txlen); 728 729 uart_port_lock_irqsave(port, &flags); 730 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 731 uart_write_wakeup(port); 732 733 if (kfifo_is_empty(&tport->xmit_fifo)) 734 sc16is7xx_stop_tx(port); 735 else 736 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT); 737 uart_port_unlock_irqrestore(port, flags); 738 } 739 740 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port) 741 { 742 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG); 743 unsigned int mctrl = 0; 744 745 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0; 746 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0; 747 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0; 748 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0; 749 return mctrl; 750 } 751 752 static void sc16is7xx_update_mlines(struct sc16is7xx_one *one) 753 { 754 struct uart_port *port = &one->port; 755 unsigned long flags; 756 unsigned int status, changed; 757 758 lockdep_assert_held_once(&one->efr_lock); 759 760 status = sc16is7xx_get_hwmctrl(port); 761 changed = status ^ one->old_mctrl; 762 763 if (changed == 0) 764 return; 765 766 one->old_mctrl = status; 767 768 uart_port_lock_irqsave(port, &flags); 769 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG)) 770 port->icount.rng++; 771 if (changed & TIOCM_DSR) 772 port->icount.dsr++; 773 if (changed & TIOCM_CAR) 774 uart_handle_dcd_change(port, status & TIOCM_CAR); 775 if (changed & TIOCM_CTS) 776 uart_handle_cts_change(port, status & TIOCM_CTS); 777 778 wake_up_interruptible(&port->state->port.delta_msr_wait); 779 uart_port_unlock_irqrestore(port, flags); 780 } 781 782 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno) 783 { 784 bool rc = true; 785 unsigned int iir, rxlen; 786 struct uart_port *port = &s->p[portno].port; 787 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 788 789 mutex_lock(&one->efr_lock); 790 791 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG); 792 if (iir & SC16IS7XX_IIR_NO_INT_BIT) { 793 rc = false; 794 goto out_port_irq; 795 } 796 797 iir &= SC16IS7XX_IIR_ID_MASK; 798 799 switch (iir) { 800 case SC16IS7XX_IIR_RDI_SRC: 801 case SC16IS7XX_IIR_RLSE_SRC: 802 case SC16IS7XX_IIR_RTOI_SRC: 803 case SC16IS7XX_IIR_XOFFI_SRC: 804 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); 805 806 /* 807 * There is a silicon bug that makes the chip report a 808 * time-out interrupt but no data in the FIFO. This is 809 * described in errata section 18.1.4. 810 * 811 * When this happens, read one byte from the FIFO to 812 * clear the interrupt. 813 */ 814 if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen) 815 rxlen = 1; 816 817 if (rxlen) 818 sc16is7xx_handle_rx(port, rxlen, iir); 819 break; 820 /* CTSRTS interrupt comes only when CTS goes inactive */ 821 case SC16IS7XX_IIR_CTSRTS_SRC: 822 case SC16IS7XX_IIR_MSI_SRC: 823 sc16is7xx_update_mlines(one); 824 break; 825 case SC16IS7XX_IIR_THRI_SRC: 826 sc16is7xx_handle_tx(port); 827 break; 828 default: 829 dev_err_ratelimited(port->dev, 830 "ttySC%i: Unexpected interrupt: %x", 831 port->line, iir); 832 break; 833 } 834 835 out_port_irq: 836 mutex_unlock(&one->efr_lock); 837 838 return rc; 839 } 840 841 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id) 842 { 843 bool keep_polling; 844 845 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id; 846 847 do { 848 int i; 849 850 keep_polling = false; 851 852 for (i = 0; i < s->devtype->nr_uart; ++i) 853 keep_polling |= sc16is7xx_port_irq(s, i); 854 } while (keep_polling); 855 856 return IRQ_HANDLED; 857 } 858 859 static void sc16is7xx_tx_proc(struct kthread_work *ws) 860 { 861 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port); 862 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 863 864 if ((port->rs485.flags & SER_RS485_ENABLED) && 865 (port->rs485.delay_rts_before_send > 0)) 866 msleep(port->rs485.delay_rts_before_send); 867 868 mutex_lock(&one->efr_lock); 869 sc16is7xx_handle_tx(port); 870 mutex_unlock(&one->efr_lock); 871 } 872 873 static void sc16is7xx_reconf_rs485(struct uart_port *port) 874 { 875 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT | 876 SC16IS7XX_EFCR_RTS_INVERT_BIT; 877 u32 efcr = 0; 878 struct serial_rs485 *rs485 = &port->rs485; 879 unsigned long irqflags; 880 881 uart_port_lock_irqsave(port, &irqflags); 882 if (rs485->flags & SER_RS485_ENABLED) { 883 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT; 884 885 if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 886 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT; 887 } 888 uart_port_unlock_irqrestore(port, irqflags); 889 890 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr); 891 } 892 893 static void sc16is7xx_reg_proc(struct kthread_work *ws) 894 { 895 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work); 896 struct sc16is7xx_one_config config; 897 unsigned long irqflags; 898 899 uart_port_lock_irqsave(&one->port, &irqflags); 900 config = one->config; 901 memset(&one->config, 0, sizeof(one->config)); 902 uart_port_unlock_irqrestore(&one->port, irqflags); 903 904 if (config.flags & SC16IS7XX_RECONF_MD) { 905 u8 mcr = 0; 906 907 /* Device ignores RTS setting when hardware flow is enabled */ 908 if (one->port.mctrl & TIOCM_RTS) 909 mcr |= SC16IS7XX_MCR_RTS_BIT; 910 911 if (one->port.mctrl & TIOCM_DTR) 912 mcr |= SC16IS7XX_MCR_DTR_BIT; 913 914 if (one->port.mctrl & TIOCM_LOOP) 915 mcr |= SC16IS7XX_MCR_LOOP_BIT; 916 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, 917 SC16IS7XX_MCR_RTS_BIT | 918 SC16IS7XX_MCR_DTR_BIT | 919 SC16IS7XX_MCR_LOOP_BIT, 920 mcr); 921 } 922 923 if (config.flags & SC16IS7XX_RECONF_IER) 924 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG, 925 config.ier_mask, config.ier_val); 926 927 if (config.flags & SC16IS7XX_RECONF_RS485) 928 sc16is7xx_reconf_rs485(&one->port); 929 } 930 931 static void sc16is7xx_ms_proc(struct kthread_work *ws) 932 { 933 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work); 934 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev); 935 936 if (one->port.state) { 937 mutex_lock(&one->efr_lock); 938 sc16is7xx_update_mlines(one); 939 mutex_unlock(&one->efr_lock); 940 941 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ); 942 } 943 } 944 945 static void sc16is7xx_enable_ms(struct uart_port *port) 946 { 947 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 948 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 949 950 lockdep_assert_held_once(&port->lock); 951 952 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0); 953 } 954 955 static void sc16is7xx_start_tx(struct uart_port *port) 956 { 957 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 958 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 959 960 kthread_queue_work(&s->kworker, &one->tx_work); 961 } 962 963 static void sc16is7xx_throttle(struct uart_port *port) 964 { 965 unsigned long flags; 966 967 /* 968 * Hardware flow control is enabled and thus the device ignores RTS 969 * value set in MCR register. Stop reading data from RX FIFO so the 970 * AutoRTS feature will de-activate RTS output. 971 */ 972 uart_port_lock_irqsave(port, &flags); 973 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 974 uart_port_unlock_irqrestore(port, flags); 975 } 976 977 static void sc16is7xx_unthrottle(struct uart_port *port) 978 { 979 unsigned long flags; 980 981 uart_port_lock_irqsave(port, &flags); 982 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT); 983 uart_port_unlock_irqrestore(port, flags); 984 } 985 986 static unsigned int sc16is7xx_tx_empty(struct uart_port *port) 987 { 988 unsigned int lsr; 989 990 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 991 992 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0; 993 } 994 995 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port) 996 { 997 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 998 999 /* Called with port lock taken so we can only return cached value */ 1000 return one->old_mctrl; 1001 } 1002 1003 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl) 1004 { 1005 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1006 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1007 1008 one->config.flags |= SC16IS7XX_RECONF_MD; 1009 kthread_queue_work(&s->kworker, &one->reg_work); 1010 } 1011 1012 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state) 1013 { 1014 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG, 1015 SC16IS7XX_LCR_TXBREAK_BIT, 1016 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0); 1017 } 1018 1019 static void sc16is7xx_set_termios(struct uart_port *port, 1020 struct ktermios *termios, 1021 const struct ktermios *old) 1022 { 1023 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1024 unsigned int lcr, flow = 0; 1025 int baud; 1026 unsigned long flags; 1027 1028 kthread_cancel_delayed_work_sync(&one->ms_work); 1029 1030 /* Mask termios capabilities we don't support */ 1031 termios->c_cflag &= ~CMSPAR; 1032 1033 /* Word size */ 1034 switch (termios->c_cflag & CSIZE) { 1035 case CS5: 1036 lcr = SC16IS7XX_LCR_WORD_LEN_5; 1037 break; 1038 case CS6: 1039 lcr = SC16IS7XX_LCR_WORD_LEN_6; 1040 break; 1041 case CS7: 1042 lcr = SC16IS7XX_LCR_WORD_LEN_7; 1043 break; 1044 case CS8: 1045 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1046 break; 1047 default: 1048 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1049 termios->c_cflag &= ~CSIZE; 1050 termios->c_cflag |= CS8; 1051 break; 1052 } 1053 1054 /* Parity */ 1055 if (termios->c_cflag & PARENB) { 1056 lcr |= SC16IS7XX_LCR_PARITY_BIT; 1057 if (!(termios->c_cflag & PARODD)) 1058 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT; 1059 } 1060 1061 /* Stop bits */ 1062 if (termios->c_cflag & CSTOPB) 1063 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */ 1064 1065 /* Set read status mask */ 1066 port->read_status_mask = SC16IS7XX_LSR_OE_BIT; 1067 if (termios->c_iflag & INPCK) 1068 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT | 1069 SC16IS7XX_LSR_FE_BIT; 1070 if (termios->c_iflag & (BRKINT | PARMRK)) 1071 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT; 1072 1073 /* Set status ignore mask */ 1074 port->ignore_status_mask = 0; 1075 if (termios->c_iflag & IGNBRK) 1076 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT; 1077 if (!(termios->c_cflag & CREAD)) 1078 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK; 1079 1080 /* Configure flow control */ 1081 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1082 if (termios->c_cflag & CRTSCTS) { 1083 flow |= SC16IS7XX_EFR_AUTOCTS_BIT | 1084 SC16IS7XX_EFR_AUTORTS_BIT; 1085 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1086 } 1087 if (termios->c_iflag & IXON) 1088 flow |= SC16IS7XX_EFR_SWFLOW3_BIT; 1089 if (termios->c_iflag & IXOFF) 1090 flow |= SC16IS7XX_EFR_SWFLOW1_BIT; 1091 1092 /* Update LCR register */ 1093 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 1094 1095 /* Update EFR registers */ 1096 sc16is7xx_efr_lock(port); 1097 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]); 1098 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]); 1099 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 1100 SC16IS7XX_EFR_FLOWCTRL_BITS, flow); 1101 sc16is7xx_efr_unlock(port); 1102 1103 /* Get baud rate generator configuration */ 1104 baud = uart_get_baud_rate(port, termios, old, 1105 port->uartclk / 16 / 4 / 0xffff, 1106 port->uartclk / 16); 1107 1108 /* Setup baudrate generator */ 1109 baud = sc16is7xx_set_baud(port, baud); 1110 1111 uart_port_lock_irqsave(port, &flags); 1112 1113 /* Update timeout according to new baud rate */ 1114 uart_update_timeout(port, termios->c_cflag, baud); 1115 1116 if (UART_ENABLE_MS(port, termios->c_cflag)) 1117 sc16is7xx_enable_ms(port); 1118 1119 uart_port_unlock_irqrestore(port, flags); 1120 } 1121 1122 static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios, 1123 struct serial_rs485 *rs485) 1124 { 1125 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1126 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1127 1128 if (rs485->flags & SER_RS485_ENABLED) { 1129 /* 1130 * RTS signal is handled by HW, it's timing can't be influenced. 1131 * However, it's sometimes useful to delay TX even without RTS 1132 * control therefore we try to handle .delay_rts_before_send. 1133 */ 1134 if (rs485->delay_rts_after_send) 1135 return -EINVAL; 1136 } 1137 1138 one->config.flags |= SC16IS7XX_RECONF_RS485; 1139 kthread_queue_work(&s->kworker, &one->reg_work); 1140 1141 return 0; 1142 } 1143 1144 static int sc16is7xx_startup(struct uart_port *port) 1145 { 1146 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1147 unsigned int val; 1148 unsigned long flags; 1149 1150 sc16is7xx_power(port, 1); 1151 1152 /* Reset FIFOs*/ 1153 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT; 1154 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val); 1155 udelay(5); 1156 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, 1157 SC16IS7XX_FCR_FIFO_BIT); 1158 1159 /* Enable EFR */ 1160 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 1161 SC16IS7XX_LCR_CONF_MODE_B); 1162 1163 regcache_cache_bypass(one->regmap, true); 1164 1165 /* Enable write access to enhanced features and internal clock div */ 1166 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 1167 SC16IS7XX_EFR_ENABLE_BIT, 1168 SC16IS7XX_EFR_ENABLE_BIT); 1169 1170 /* Enable TCR/TLR */ 1171 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1172 SC16IS7XX_MCR_TCRTLR_BIT, 1173 SC16IS7XX_MCR_TCRTLR_BIT); 1174 1175 /* Configure flow control levels */ 1176 /* Flow control halt level 48, resume level 24 */ 1177 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG, 1178 SC16IS7XX_TCR_RX_RESUME(24) | 1179 SC16IS7XX_TCR_RX_HALT(48)); 1180 1181 regcache_cache_bypass(one->regmap, false); 1182 1183 /* Now, initialize the UART */ 1184 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8); 1185 1186 /* Enable IrDA mode if requested in DT */ 1187 /* This bit must be written with LCR[7] = 0 */ 1188 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1189 SC16IS7XX_MCR_IRDA_BIT, 1190 one->irda_mode ? 1191 SC16IS7XX_MCR_IRDA_BIT : 0); 1192 1193 /* Enable the Rx and Tx FIFO */ 1194 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1195 SC16IS7XX_EFCR_RXDISABLE_BIT | 1196 SC16IS7XX_EFCR_TXDISABLE_BIT, 1197 0); 1198 1199 /* Enable RX, CTS change and modem lines interrupts */ 1200 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT | 1201 SC16IS7XX_IER_MSI_BIT; 1202 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); 1203 1204 /* Enable modem status polling */ 1205 uart_port_lock_irqsave(port, &flags); 1206 sc16is7xx_enable_ms(port); 1207 uart_port_unlock_irqrestore(port, flags); 1208 1209 return 0; 1210 } 1211 1212 static void sc16is7xx_shutdown(struct uart_port *port) 1213 { 1214 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1215 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1216 1217 kthread_cancel_delayed_work_sync(&one->ms_work); 1218 1219 /* Disable all interrupts */ 1220 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0); 1221 /* Disable TX/RX */ 1222 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1223 SC16IS7XX_EFCR_RXDISABLE_BIT | 1224 SC16IS7XX_EFCR_TXDISABLE_BIT, 1225 SC16IS7XX_EFCR_RXDISABLE_BIT | 1226 SC16IS7XX_EFCR_TXDISABLE_BIT); 1227 1228 sc16is7xx_power(port, 0); 1229 1230 kthread_flush_worker(&s->kworker); 1231 } 1232 1233 static const char *sc16is7xx_type(struct uart_port *port) 1234 { 1235 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1236 1237 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL; 1238 } 1239 1240 static int sc16is7xx_request_port(struct uart_port *port) 1241 { 1242 /* Do nothing */ 1243 return 0; 1244 } 1245 1246 static void sc16is7xx_config_port(struct uart_port *port, int flags) 1247 { 1248 if (flags & UART_CONFIG_TYPE) 1249 port->type = PORT_SC16IS7XX; 1250 } 1251 1252 static int sc16is7xx_verify_port(struct uart_port *port, 1253 struct serial_struct *s) 1254 { 1255 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX)) 1256 return -EINVAL; 1257 if (s->irq != port->irq) 1258 return -EINVAL; 1259 1260 return 0; 1261 } 1262 1263 static void sc16is7xx_pm(struct uart_port *port, unsigned int state, 1264 unsigned int oldstate) 1265 { 1266 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0); 1267 } 1268 1269 static void sc16is7xx_null_void(struct uart_port *port) 1270 { 1271 /* Do nothing */ 1272 } 1273 1274 static const struct uart_ops sc16is7xx_ops = { 1275 .tx_empty = sc16is7xx_tx_empty, 1276 .set_mctrl = sc16is7xx_set_mctrl, 1277 .get_mctrl = sc16is7xx_get_mctrl, 1278 .stop_tx = sc16is7xx_stop_tx, 1279 .start_tx = sc16is7xx_start_tx, 1280 .throttle = sc16is7xx_throttle, 1281 .unthrottle = sc16is7xx_unthrottle, 1282 .stop_rx = sc16is7xx_stop_rx, 1283 .enable_ms = sc16is7xx_enable_ms, 1284 .break_ctl = sc16is7xx_break_ctl, 1285 .startup = sc16is7xx_startup, 1286 .shutdown = sc16is7xx_shutdown, 1287 .set_termios = sc16is7xx_set_termios, 1288 .type = sc16is7xx_type, 1289 .request_port = sc16is7xx_request_port, 1290 .release_port = sc16is7xx_null_void, 1291 .config_port = sc16is7xx_config_port, 1292 .verify_port = sc16is7xx_verify_port, 1293 .pm = sc16is7xx_pm, 1294 }; 1295 1296 #ifdef CONFIG_GPIOLIB 1297 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset) 1298 { 1299 unsigned int val; 1300 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1301 struct uart_port *port = &s->p[0].port; 1302 1303 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1304 1305 return !!(val & BIT(offset)); 1306 } 1307 1308 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 1309 { 1310 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1311 struct uart_port *port = &s->p[0].port; 1312 1313 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), 1314 val ? BIT(offset) : 0); 1315 } 1316 1317 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip, 1318 unsigned offset) 1319 { 1320 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1321 struct uart_port *port = &s->p[0].port; 1322 1323 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0); 1324 1325 return 0; 1326 } 1327 1328 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, 1329 unsigned offset, int val) 1330 { 1331 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1332 struct uart_port *port = &s->p[0].port; 1333 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1334 1335 if (val) 1336 state |= BIT(offset); 1337 else 1338 state &= ~BIT(offset); 1339 1340 /* 1341 * If we write IOSTATE first, and then IODIR, the output value is not 1342 * transferred to the corresponding I/O pin. 1343 * The datasheet states that each register bit will be transferred to 1344 * the corresponding I/O pin programmed as output when writing to 1345 * IOSTATE. Therefore, configure direction first with IODIR, and then 1346 * set value after with IOSTATE. 1347 */ 1348 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 1349 BIT(offset)); 1350 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); 1351 1352 return 0; 1353 } 1354 1355 static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip, 1356 unsigned long *valid_mask, 1357 unsigned int ngpios) 1358 { 1359 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1360 1361 *valid_mask = s->gpio_valid_mask; 1362 1363 return 0; 1364 } 1365 1366 static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s) 1367 { 1368 struct device *dev = s->p[0].port.dev; 1369 1370 if (!s->devtype->nr_gpio) 1371 return 0; 1372 1373 switch (s->mctrl_mask) { 1374 case 0: 1375 s->gpio_valid_mask = GENMASK(7, 0); 1376 break; 1377 case SC16IS7XX_IOCONTROL_MODEM_A_BIT: 1378 s->gpio_valid_mask = GENMASK(3, 0); 1379 break; 1380 case SC16IS7XX_IOCONTROL_MODEM_B_BIT: 1381 s->gpio_valid_mask = GENMASK(7, 4); 1382 break; 1383 default: 1384 break; 1385 } 1386 1387 if (s->gpio_valid_mask == 0) 1388 return 0; 1389 1390 s->gpio.owner = THIS_MODULE; 1391 s->gpio.parent = dev; 1392 s->gpio.label = dev_name(dev); 1393 s->gpio.init_valid_mask = sc16is7xx_gpio_init_valid_mask; 1394 s->gpio.direction_input = sc16is7xx_gpio_direction_input; 1395 s->gpio.get = sc16is7xx_gpio_get; 1396 s->gpio.direction_output = sc16is7xx_gpio_direction_output; 1397 s->gpio.set = sc16is7xx_gpio_set; 1398 s->gpio.base = -1; 1399 s->gpio.ngpio = s->devtype->nr_gpio; 1400 s->gpio.can_sleep = 1; 1401 1402 return gpiochip_add_data(&s->gpio, s); 1403 } 1404 #endif 1405 1406 static void sc16is7xx_setup_irda_ports(struct sc16is7xx_port *s) 1407 { 1408 int i; 1409 int ret; 1410 int count; 1411 u32 irda_port[SC16IS7XX_MAX_PORTS]; 1412 struct device *dev = s->p[0].port.dev; 1413 1414 count = device_property_count_u32(dev, "irda-mode-ports"); 1415 if (count < 0 || count > ARRAY_SIZE(irda_port)) 1416 return; 1417 1418 ret = device_property_read_u32_array(dev, "irda-mode-ports", 1419 irda_port, count); 1420 if (ret) 1421 return; 1422 1423 for (i = 0; i < count; i++) { 1424 if (irda_port[i] < s->devtype->nr_uart) 1425 s->p[irda_port[i]].irda_mode = true; 1426 } 1427 } 1428 1429 /* 1430 * Configure ports designated to operate as modem control lines. 1431 */ 1432 static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s, 1433 struct regmap *regmap) 1434 { 1435 int i; 1436 int ret; 1437 int count; 1438 u32 mctrl_port[SC16IS7XX_MAX_PORTS]; 1439 struct device *dev = s->p[0].port.dev; 1440 1441 count = device_property_count_u32(dev, "nxp,modem-control-line-ports"); 1442 if (count < 0 || count > ARRAY_SIZE(mctrl_port)) 1443 return 0; 1444 1445 ret = device_property_read_u32_array(dev, "nxp,modem-control-line-ports", 1446 mctrl_port, count); 1447 if (ret) 1448 return ret; 1449 1450 s->mctrl_mask = 0; 1451 1452 for (i = 0; i < count; i++) { 1453 /* Use GPIO lines as modem control lines */ 1454 if (mctrl_port[i] == 0) 1455 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT; 1456 else if (mctrl_port[i] == 1) 1457 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT; 1458 } 1459 1460 if (s->mctrl_mask) 1461 regmap_update_bits( 1462 regmap, 1463 SC16IS7XX_IOCONTROL_REG, 1464 SC16IS7XX_IOCONTROL_MODEM_A_BIT | 1465 SC16IS7XX_IOCONTROL_MODEM_B_BIT, s->mctrl_mask); 1466 1467 return 0; 1468 } 1469 1470 static const struct serial_rs485 sc16is7xx_rs485_supported = { 1471 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND, 1472 .delay_rts_before_send = 1, 1473 .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */ 1474 }; 1475 1476 /* Reset device, purging any pending irq / data */ 1477 static int sc16is7xx_reset(struct device *dev, struct regmap *regmap) 1478 { 1479 struct gpio_desc *reset_gpio; 1480 1481 /* Assert reset GPIO if defined and valid. */ 1482 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 1483 if (IS_ERR(reset_gpio)) 1484 return dev_err_probe(dev, PTR_ERR(reset_gpio), "Failed to get reset GPIO\n"); 1485 1486 if (reset_gpio) { 1487 /* The minimum reset pulse width is 3 us. */ 1488 fsleep(5); 1489 gpiod_set_value_cansleep(reset_gpio, 0); /* Deassert GPIO */ 1490 } else { 1491 /* Software reset */ 1492 regmap_write(regmap, SC16IS7XX_IOCONTROL_REG, 1493 SC16IS7XX_IOCONTROL_SRESET_BIT); 1494 } 1495 1496 return 0; 1497 } 1498 1499 int sc16is7xx_probe(struct device *dev, const struct sc16is7xx_devtype *devtype, 1500 struct regmap *regmaps[], int irq) 1501 { 1502 unsigned long freq = 0, *pfreq = dev_get_platdata(dev); 1503 unsigned int val; 1504 u32 uartclk = 0; 1505 int i, ret; 1506 struct sc16is7xx_port *s; 1507 bool port_registered[SC16IS7XX_MAX_PORTS]; 1508 1509 for (i = 0; i < devtype->nr_uart; i++) 1510 if (IS_ERR(regmaps[i])) 1511 return PTR_ERR(regmaps[i]); 1512 1513 /* 1514 * This device does not have an identification register that would 1515 * tell us if we are really connected to the correct device. 1516 * The best we can do is to check if communication is at all possible. 1517 * 1518 * Note: regmap[0] is used in the probe function to access registers 1519 * common to all channels/ports, as it is guaranteed to be present on 1520 * all variants. 1521 */ 1522 ret = regmap_read(regmaps[0], SC16IS7XX_LSR_REG, &val); 1523 if (ret < 0) 1524 return -EPROBE_DEFER; 1525 1526 /* Alloc port structure */ 1527 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL); 1528 if (!s) { 1529 dev_err(dev, "Error allocating port structure\n"); 1530 return -ENOMEM; 1531 } 1532 1533 /* Always ask for fixed clock rate from a property. */ 1534 device_property_read_u32(dev, "clock-frequency", &uartclk); 1535 1536 s->clk = devm_clk_get_optional(dev, NULL); 1537 if (IS_ERR(s->clk)) 1538 return PTR_ERR(s->clk); 1539 1540 ret = clk_prepare_enable(s->clk); 1541 if (ret) 1542 return ret; 1543 1544 freq = clk_get_rate(s->clk); 1545 if (freq == 0) { 1546 if (uartclk) 1547 freq = uartclk; 1548 if (pfreq) 1549 freq = *pfreq; 1550 if (freq) 1551 dev_dbg(dev, "Clock frequency: %luHz\n", freq); 1552 else 1553 return -EINVAL; 1554 } 1555 1556 s->devtype = devtype; 1557 dev_set_drvdata(dev, s); 1558 1559 kthread_init_worker(&s->kworker); 1560 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker, 1561 "sc16is7xx"); 1562 if (IS_ERR(s->kworker_task)) { 1563 ret = PTR_ERR(s->kworker_task); 1564 goto out_clk; 1565 } 1566 sched_set_fifo(s->kworker_task); 1567 1568 ret = sc16is7xx_reset(dev, regmaps[0]); 1569 if (ret) 1570 goto out_kthread; 1571 1572 /* Mark each port line and status as uninitialised. */ 1573 for (i = 0; i < devtype->nr_uart; ++i) { 1574 s->p[i].port.line = SC16IS7XX_MAX_DEVS; 1575 port_registered[i] = false; 1576 } 1577 1578 for (i = 0; i < devtype->nr_uart; ++i) { 1579 ret = ida_alloc_max(&sc16is7xx_lines, 1580 SC16IS7XX_MAX_DEVS - 1, GFP_KERNEL); 1581 if (ret < 0) 1582 goto out_ports; 1583 1584 s->p[i].port.line = ret; 1585 1586 /* Initialize port data */ 1587 s->p[i].port.dev = dev; 1588 s->p[i].port.irq = irq; 1589 s->p[i].port.type = PORT_SC16IS7XX; 1590 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE; 1591 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1592 s->p[i].port.iobase = i; 1593 /* 1594 * Use all ones as membase to make sure uart_configure_port() in 1595 * serial_core.c does not abort for SPI/I2C devices where the 1596 * membase address is not applicable. 1597 */ 1598 s->p[i].port.membase = (void __iomem *)~0; 1599 s->p[i].port.iotype = UPIO_PORT; 1600 s->p[i].port.uartclk = freq; 1601 s->p[i].port.rs485_config = sc16is7xx_config_rs485; 1602 s->p[i].port.rs485_supported = sc16is7xx_rs485_supported; 1603 s->p[i].port.ops = &sc16is7xx_ops; 1604 s->p[i].old_mctrl = 0; 1605 s->p[i].regmap = regmaps[i]; 1606 1607 mutex_init(&s->p[i].efr_lock); 1608 1609 ret = uart_get_rs485_mode(&s->p[i].port); 1610 if (ret) 1611 goto out_ports; 1612 1613 /* Disable all interrupts */ 1614 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0); 1615 /* Disable TX/RX */ 1616 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG, 1617 SC16IS7XX_EFCR_RXDISABLE_BIT | 1618 SC16IS7XX_EFCR_TXDISABLE_BIT); 1619 1620 /* Initialize kthread work structs */ 1621 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc); 1622 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc); 1623 kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc); 1624 1625 /* Register port */ 1626 ret = uart_add_one_port(&sc16is7xx_uart, &s->p[i].port); 1627 if (ret) 1628 goto out_ports; 1629 1630 port_registered[i] = true; 1631 1632 /* Enable EFR */ 1633 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 1634 SC16IS7XX_LCR_CONF_MODE_B); 1635 1636 regcache_cache_bypass(regmaps[i], true); 1637 1638 /* Enable write access to enhanced features */ 1639 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG, 1640 SC16IS7XX_EFR_ENABLE_BIT); 1641 1642 regcache_cache_bypass(regmaps[i], false); 1643 1644 /* Restore access to general registers */ 1645 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00); 1646 1647 /* Go to suspend mode */ 1648 sc16is7xx_power(&s->p[i].port, 0); 1649 } 1650 1651 sc16is7xx_setup_irda_ports(s); 1652 1653 ret = sc16is7xx_setup_mctrl_ports(s, regmaps[0]); 1654 if (ret) 1655 goto out_ports; 1656 1657 #ifdef CONFIG_GPIOLIB 1658 ret = sc16is7xx_setup_gpio_chip(s); 1659 if (ret) 1660 goto out_ports; 1661 #endif 1662 1663 /* 1664 * Setup interrupt. We first try to acquire the IRQ line as level IRQ. 1665 * If that succeeds, we can allow sharing the interrupt as well. 1666 * In case the interrupt controller doesn't support that, we fall 1667 * back to a non-shared falling-edge trigger. 1668 */ 1669 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1670 IRQF_TRIGGER_LOW | IRQF_SHARED | 1671 IRQF_ONESHOT, 1672 dev_name(dev), s); 1673 if (!ret) 1674 return 0; 1675 1676 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1677 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1678 dev_name(dev), s); 1679 if (!ret) 1680 return 0; 1681 1682 #ifdef CONFIG_GPIOLIB 1683 if (s->gpio_valid_mask) 1684 gpiochip_remove(&s->gpio); 1685 #endif 1686 1687 out_ports: 1688 for (i = 0; i < devtype->nr_uart; i++) { 1689 if (s->p[i].port.line < SC16IS7XX_MAX_DEVS) 1690 ida_free(&sc16is7xx_lines, s->p[i].port.line); 1691 if (port_registered[i]) 1692 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1693 } 1694 1695 out_kthread: 1696 kthread_stop(s->kworker_task); 1697 1698 out_clk: 1699 clk_disable_unprepare(s->clk); 1700 1701 return ret; 1702 } 1703 EXPORT_SYMBOL_GPL(sc16is7xx_probe); 1704 1705 void sc16is7xx_remove(struct device *dev) 1706 { 1707 struct sc16is7xx_port *s = dev_get_drvdata(dev); 1708 int i; 1709 1710 #ifdef CONFIG_GPIOLIB 1711 if (s->gpio_valid_mask) 1712 gpiochip_remove(&s->gpio); 1713 #endif 1714 1715 for (i = 0; i < s->devtype->nr_uart; i++) { 1716 kthread_cancel_delayed_work_sync(&s->p[i].ms_work); 1717 ida_free(&sc16is7xx_lines, s->p[i].port.line); 1718 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1719 sc16is7xx_power(&s->p[i].port, 0); 1720 } 1721 1722 kthread_flush_worker(&s->kworker); 1723 kthread_stop(s->kworker_task); 1724 1725 clk_disable_unprepare(s->clk); 1726 } 1727 EXPORT_SYMBOL_GPL(sc16is7xx_remove); 1728 1729 const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = { 1730 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, }, 1731 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, }, 1732 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, }, 1733 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, }, 1734 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, }, 1735 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, }, 1736 { } 1737 }; 1738 EXPORT_SYMBOL_GPL(sc16is7xx_dt_ids); 1739 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids); 1740 1741 const struct regmap_config sc16is7xx_regcfg = { 1742 .reg_bits = 5, 1743 .pad_bits = 3, 1744 .val_bits = 8, 1745 .cache_type = REGCACHE_MAPLE, 1746 .volatile_reg = sc16is7xx_regmap_volatile, 1747 .precious_reg = sc16is7xx_regmap_precious, 1748 .writeable_noinc_reg = sc16is7xx_regmap_noinc, 1749 .readable_noinc_reg = sc16is7xx_regmap_noinc, 1750 .max_raw_read = SC16IS7XX_FIFO_SIZE, 1751 .max_raw_write = SC16IS7XX_FIFO_SIZE, 1752 .max_register = SC16IS7XX_EFCR_REG, 1753 }; 1754 EXPORT_SYMBOL_GPL(sc16is7xx_regcfg); 1755 1756 const char *sc16is7xx_regmap_name(u8 port_id) 1757 { 1758 switch (port_id) { 1759 case 0: return "port0"; 1760 case 1: return "port1"; 1761 default: 1762 WARN_ON(true); 1763 return NULL; 1764 } 1765 } 1766 EXPORT_SYMBOL_GPL(sc16is7xx_regmap_name); 1767 1768 unsigned int sc16is7xx_regmap_port_mask(unsigned int port_id) 1769 { 1770 /* CH1,CH0 are at bits 2:1. */ 1771 return port_id << 1; 1772 } 1773 EXPORT_SYMBOL_GPL(sc16is7xx_regmap_port_mask); 1774 1775 static int __init sc16is7xx_init(void) 1776 { 1777 return uart_register_driver(&sc16is7xx_uart); 1778 } 1779 module_init(sc16is7xx_init); 1780 1781 static void __exit sc16is7xx_exit(void) 1782 { 1783 uart_unregister_driver(&sc16is7xx_uart); 1784 } 1785 module_exit(sc16is7xx_exit); 1786 1787 MODULE_LICENSE("GPL"); 1788 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>"); 1789 MODULE_DESCRIPTION("SC16IS7xx tty serial core driver"); 1790