1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SC16IS7xx tty serial driver - common code 4 * 5 * Copyright (C) 2014 GridPoint 6 * Author: Jon Ringle <jringle@gridpoint.com> 7 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru> 8 */ 9 10 #undef DEFAULT_SYMBOL_NAMESPACE 11 #define DEFAULT_SYMBOL_NAMESPACE SERIAL_NXP_SC16IS7XX 12 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/export.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/gpio/driver.h> 19 #include <linux/idr.h> 20 #include <linux/kthread.h> 21 #include <linux/mod_devicetable.h> 22 #include <linux/module.h> 23 #include <linux/property.h> 24 #include <linux/regmap.h> 25 #include <linux/sched.h> 26 #include <linux/serial_core.h> 27 #include <linux/serial.h> 28 #include <linux/string.h> 29 #include <linux/tty.h> 30 #include <linux/tty_flip.h> 31 #include <linux/uaccess.h> 32 #include <linux/units.h> 33 34 #include "sc16is7xx.h" 35 36 #define SC16IS7XX_MAX_DEVS 8 37 38 /* SC16IS7XX register definitions */ 39 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */ 40 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */ 41 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */ 42 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */ 43 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */ 44 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */ 45 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */ 46 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */ 47 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */ 48 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */ 49 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */ 50 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */ 51 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction 52 * - only on 75x/76x 53 */ 54 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State 55 * - only on 75x/76x 56 */ 57 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable 58 * - only on 75x/76x 59 */ 60 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control 61 * - only on 75x/76x 62 */ 63 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */ 64 65 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */ 66 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */ 67 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */ 68 69 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */ 70 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */ 71 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */ 72 73 /* Enhanced Register set: Only if (LCR == 0xBF) */ 74 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */ 75 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */ 76 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */ 77 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */ 78 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */ 79 80 /* IER register bits */ 81 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */ 82 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register 83 * interrupt */ 84 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status 85 * interrupt */ 86 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status 87 * interrupt */ 88 89 /* IER register bits - write only if (EFR[4] == 1) */ 90 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */ 91 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */ 92 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */ 93 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */ 94 95 /* FCR register bits */ 96 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */ 97 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */ 98 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */ 99 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */ 100 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */ 101 102 /* FCR register bits - write only if (EFR[4] == 1) */ 103 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */ 104 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */ 105 106 /* IIR register bits */ 107 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */ 108 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */ 109 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */ 110 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */ 111 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */ 112 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */ 113 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt 114 * - only on 75x/76x 115 */ 116 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state 117 * - only on 75x/76x 118 */ 119 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */ 120 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state 121 * from active (LOW) 122 * to inactive (HIGH) 123 */ 124 /* LCR register bits */ 125 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 126 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 127 * 128 * Word length bits table: 129 * 00 -> 5 bit words 130 * 01 -> 6 bit words 131 * 10 -> 7 bit words 132 * 11 -> 8 bit words 133 */ 134 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 135 * 136 * STOP length bit table: 137 * 0 -> 1 stop bit 138 * 1 -> 1-1.5 stop bits if 139 * word length is 5, 140 * 2 stop bits otherwise 141 */ 142 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 143 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 144 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 145 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 146 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */ 147 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00) 148 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01) 149 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02) 150 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03) 151 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special 152 * reg set */ 153 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced 154 * reg set */ 155 156 /* MCR register bits */ 157 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement 158 * - only on 75x/76x 159 */ 160 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */ 161 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */ 162 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */ 163 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any 164 * - write enabled 165 * if (EFR[4] == 1) 166 */ 167 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode 168 * - write enabled 169 * if (EFR[4] == 1) 170 */ 171 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4 172 * - write enabled 173 * if (EFR[4] == 1) 174 */ 175 176 /* LSR register bits */ 177 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */ 178 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */ 179 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */ 180 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */ 181 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */ 182 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */ 183 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */ 184 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */ 185 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */ 186 187 /* MSR register bits */ 188 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */ 189 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready 190 * or (IO4) 191 * - only on 75x/76x 192 */ 193 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator 194 * or (IO7) 195 * - only on 75x/76x 196 */ 197 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect 198 * or (IO6) 199 * - only on 75x/76x 200 */ 201 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */ 202 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4) 203 * - only on 75x/76x 204 */ 205 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7) 206 * - only on 75x/76x 207 */ 208 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6) 209 * - only on 75x/76x 210 */ 211 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */ 212 213 /* 214 * TCR register bits 215 * TCR trigger levels are available from 0 to 60 characters with a granularity 216 * of four. 217 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is 218 * no built-in hardware check to make sure this condition is met. Also, the TCR 219 * must be programmed with this condition before auto RTS or software flow 220 * control is enabled to avoid spurious operation of the device. 221 */ 222 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0) 223 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4) 224 225 /* 226 * TLR register bits 227 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the 228 * FIFO Control Register (FCR) are used for the transmit and receive FIFO 229 * trigger levels. Trigger levels from 4 characters to 60 characters are 230 * available with a granularity of four. 231 * 232 * When the trigger level setting in TLR is zero, the SC16IS74x/75x/76x uses the 233 * trigger level setting defined in FCR. If TLR has non-zero trigger level value 234 * the trigger level defined in FCR is discarded. This applies to both transmit 235 * FIFO and receive FIFO trigger level setting. 236 * 237 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the 238 * default state, that is, '00'. 239 */ 240 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0) 241 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) 242 243 /* IOControl register bits (Only 75x/76x) */ 244 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ 245 #define SC16IS7XX_IOCONTROL_MODEM_A_BIT (1 << 1) /* Enable GPIO[7:4] as modem A pins */ 246 #define SC16IS7XX_IOCONTROL_MODEM_B_BIT (1 << 2) /* Enable GPIO[3:0] as modem B pins */ 247 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */ 248 249 /* EFCR register bits */ 250 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop 251 * mode (RS485) */ 252 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */ 253 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */ 254 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */ 255 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */ 256 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode 257 * 0 = rate upto 115.2 kbit/s 258 * - Only 75x/76x 259 * 1 = rate upto 1.152 Mbit/s 260 * - Only 76x 261 */ 262 263 /* EFR register bits */ 264 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */ 265 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */ 266 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */ 267 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions 268 * and writing to IER[7:4], 269 * FCR[5:4], MCR[7:5] 270 */ 271 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */ 272 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2 273 * 274 * SWFLOW bits 3 & 2 table: 275 * 00 -> no transmitter flow 276 * control 277 * 01 -> transmitter generates 278 * XON2 and XOFF2 279 * 10 -> transmitter generates 280 * XON1 and XOFF1 281 * 11 -> transmitter generates 282 * XON1, XON2, XOFF1 and 283 * XOFF2 284 */ 285 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */ 286 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3 287 * 288 * SWFLOW bits 3 & 2 table: 289 * 00 -> no received flow 290 * control 291 * 01 -> receiver compares 292 * XON2 and XOFF2 293 * 10 -> receiver compares 294 * XON1 and XOFF1 295 * 11 -> receiver compares 296 * XON1, XON2, XOFF1 and 297 * XOFF2 298 */ 299 #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \ 300 SC16IS7XX_EFR_AUTOCTS_BIT | \ 301 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \ 302 SC16IS7XX_EFR_SWFLOW3_BIT | \ 303 SC16IS7XX_EFR_SWFLOW2_BIT | \ 304 SC16IS7XX_EFR_SWFLOW1_BIT | \ 305 SC16IS7XX_EFR_SWFLOW0_BIT) 306 307 308 /* Misc definitions */ 309 #define SC16IS7XX_FIFO_SIZE (64) 310 #define SC16IS7XX_GPIOS_PER_BANK 4 311 312 #define SC16IS7XX_RECONF_MD (1 << 0) 313 #define SC16IS7XX_RECONF_IER (1 << 1) 314 #define SC16IS7XX_RECONF_RS485 (1 << 2) 315 316 struct sc16is7xx_one_config { 317 unsigned int flags; 318 u8 ier_mask; 319 u8 ier_val; 320 }; 321 322 struct sc16is7xx_one { 323 struct uart_port port; 324 struct regmap *regmap; 325 struct mutex efr_lock; /* EFR registers access */ 326 struct kthread_work tx_work; 327 struct kthread_work reg_work; 328 struct kthread_delayed_work ms_work; 329 struct sc16is7xx_one_config config; 330 unsigned int old_mctrl; 331 u8 old_lcr; /* Value before EFR access. */ 332 bool irda_mode; 333 }; 334 335 struct sc16is7xx_port { 336 const struct sc16is7xx_devtype *devtype; 337 struct clk *clk; 338 #ifdef CONFIG_GPIOLIB 339 struct gpio_chip gpio; 340 unsigned long gpio_valid_mask; 341 #endif 342 u8 mctrl_mask; 343 unsigned char buf[SC16IS7XX_FIFO_SIZE]; 344 struct kthread_worker kworker; 345 struct task_struct *kworker_task; 346 struct sc16is7xx_one p[]; 347 }; 348 349 static DEFINE_IDA(sc16is7xx_lines); 350 351 static struct uart_driver sc16is7xx_uart = { 352 .owner = THIS_MODULE, 353 .driver_name = SC16IS7XX_NAME, 354 .dev_name = "ttySC", 355 .nr = SC16IS7XX_MAX_DEVS, 356 }; 357 358 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e))) 359 360 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg) 361 { 362 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 363 unsigned int val = 0; 364 365 regmap_read(one->regmap, reg, &val); 366 367 return val; 368 } 369 370 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val) 371 { 372 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 373 374 regmap_write(one->regmap, reg, val); 375 } 376 377 static void sc16is7xx_fifo_read(struct uart_port *port, u8 *rxbuf, unsigned int rxlen) 378 { 379 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 380 381 regmap_noinc_read(one->regmap, SC16IS7XX_RHR_REG, rxbuf, rxlen); 382 } 383 384 static void sc16is7xx_fifo_write(struct uart_port *port, u8 *txbuf, u8 to_send) 385 { 386 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 387 388 /* 389 * Don't send zero-length data, at least on SPI it confuses the chip 390 * delivering wrong TXLVL data. 391 */ 392 if (unlikely(!to_send)) 393 return; 394 395 regmap_noinc_write(one->regmap, SC16IS7XX_THR_REG, txbuf, to_send); 396 } 397 398 static void sc16is7xx_port_update(struct uart_port *port, u8 reg, 399 u8 mask, u8 val) 400 { 401 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 402 403 regmap_update_bits(one->regmap, reg, mask, val); 404 } 405 406 static void sc16is7xx_power(struct uart_port *port, int on) 407 { 408 sc16is7xx_port_update(port, SC16IS7XX_IER_REG, 409 SC16IS7XX_IER_SLEEP_BIT, 410 on ? 0 : SC16IS7XX_IER_SLEEP_BIT); 411 } 412 413 /* 414 * In an amazing feat of design, the Enhanced Features Register (EFR) 415 * shares the address of the Interrupt Identification Register (IIR). 416 * Access to EFR is switched on by writing a magic value (0xbf) to the 417 * Line Control Register (LCR). Any interrupt firing during this time will 418 * see the EFR where it expects the IIR to be, leading to 419 * "Unexpected interrupt" messages. 420 * 421 * Prevent this possibility by claiming a mutex while accessing the EFR, 422 * and claiming the same mutex from within the interrupt handler. This is 423 * similar to disabling the interrupt, but that doesn't work because the 424 * bulk of the interrupt processing is run as a workqueue job in thread 425 * context. 426 */ 427 static void sc16is7xx_efr_lock(struct uart_port *port) 428 { 429 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 430 431 mutex_lock(&one->efr_lock); 432 433 /* Backup content of LCR. */ 434 one->old_lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); 435 436 /* Enable access to Enhanced register set */ 437 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_CONF_MODE_B); 438 439 /* Disable cache updates when writing to EFR registers */ 440 regcache_cache_bypass(one->regmap, true); 441 } 442 443 static void sc16is7xx_efr_unlock(struct uart_port *port) 444 { 445 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 446 447 /* Re-enable cache updates when writing to normal registers */ 448 regcache_cache_bypass(one->regmap, false); 449 450 /* Restore original content of LCR */ 451 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, one->old_lcr); 452 453 mutex_unlock(&one->efr_lock); 454 } 455 456 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit) 457 { 458 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 459 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 460 461 lockdep_assert_held_once(&port->lock); 462 463 one->config.flags |= SC16IS7XX_RECONF_IER; 464 one->config.ier_mask |= bit; 465 one->config.ier_val &= ~bit; 466 kthread_queue_work(&s->kworker, &one->reg_work); 467 } 468 469 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit) 470 { 471 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 472 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 473 474 lockdep_assert_held_once(&port->lock); 475 476 one->config.flags |= SC16IS7XX_RECONF_IER; 477 one->config.ier_mask |= bit; 478 one->config.ier_val |= bit; 479 kthread_queue_work(&s->kworker, &one->reg_work); 480 } 481 482 static void sc16is7xx_stop_tx(struct uart_port *port) 483 { 484 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT); 485 } 486 487 static void sc16is7xx_stop_rx(struct uart_port *port) 488 { 489 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 490 } 491 492 const struct sc16is7xx_devtype sc16is74x_devtype = { 493 .name = "SC16IS74X", 494 .nr_gpio = 0, 495 .nr_uart = 1, 496 }; 497 EXPORT_SYMBOL_GPL(sc16is74x_devtype); 498 499 const struct sc16is7xx_devtype sc16is750_devtype = { 500 .name = "SC16IS750", 501 .nr_gpio = 8, 502 .nr_uart = 1, 503 }; 504 EXPORT_SYMBOL_GPL(sc16is750_devtype); 505 506 const struct sc16is7xx_devtype sc16is752_devtype = { 507 .name = "SC16IS752", 508 .nr_gpio = 8, 509 .nr_uart = 2, 510 }; 511 EXPORT_SYMBOL_GPL(sc16is752_devtype); 512 513 const struct sc16is7xx_devtype sc16is760_devtype = { 514 .name = "SC16IS760", 515 .nr_gpio = 8, 516 .nr_uart = 1, 517 }; 518 EXPORT_SYMBOL_GPL(sc16is760_devtype); 519 520 const struct sc16is7xx_devtype sc16is762_devtype = { 521 .name = "SC16IS762", 522 .nr_gpio = 8, 523 .nr_uart = 2, 524 }; 525 EXPORT_SYMBOL_GPL(sc16is762_devtype); 526 527 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg) 528 { 529 switch (reg) { 530 case SC16IS7XX_RHR_REG: 531 case SC16IS7XX_IIR_REG: 532 case SC16IS7XX_LSR_REG: 533 case SC16IS7XX_MSR_REG: 534 case SC16IS7XX_TXLVL_REG: 535 case SC16IS7XX_RXLVL_REG: 536 case SC16IS7XX_IOSTATE_REG: 537 case SC16IS7XX_IOCONTROL_REG: 538 return true; 539 default: 540 return false; 541 } 542 } 543 544 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg) 545 { 546 switch (reg) { 547 case SC16IS7XX_RHR_REG: 548 return true; 549 default: 550 return false; 551 } 552 } 553 554 static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg) 555 { 556 return reg == SC16IS7XX_RHR_REG; 557 } 558 559 /* 560 * Configure programmable baud rate generator (divisor) according to the 561 * desired baud rate. 562 * 563 * From the datasheet, the divisor is computed according to: 564 * 565 * XTAL1 input frequency 566 * ----------------------- 567 * prescaler 568 * divisor = --------------------------- 569 * baud-rate x sampling-rate 570 */ 571 static int sc16is7xx_set_baud(struct uart_port *port, int baud) 572 { 573 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 574 u8 lcr; 575 unsigned int prescaler = 1; 576 unsigned long clk = port->uartclk, div = clk / 16 / baud; 577 578 if (div >= BIT(16)) { 579 prescaler = 4; 580 div /= prescaler; 581 } 582 583 /* Enable enhanced features */ 584 sc16is7xx_efr_lock(port); 585 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 586 SC16IS7XX_EFR_ENABLE_BIT, 587 SC16IS7XX_EFR_ENABLE_BIT); 588 sc16is7xx_efr_unlock(port); 589 590 /* If bit MCR_CLKSEL is set, the divide by 4 prescaler is activated. */ 591 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 592 SC16IS7XX_MCR_CLKSEL_BIT, 593 prescaler == 1 ? 0 : SC16IS7XX_MCR_CLKSEL_BIT); 594 595 /* Backup LCR and access special register set (DLL/DLH) */ 596 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); 597 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 598 SC16IS7XX_LCR_CONF_MODE_A); 599 600 /* Write the new divisor */ 601 regcache_cache_bypass(one->regmap, true); 602 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256); 603 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256); 604 regcache_cache_bypass(one->regmap, false); 605 606 /* Restore LCR and access to general register set */ 607 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 608 609 return DIV_ROUND_CLOSEST((clk / prescaler) / 16, div); 610 } 611 612 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen, 613 unsigned int iir) 614 { 615 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 616 unsigned int lsr = 0, bytes_read, i; 617 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false; 618 u8 ch, flag; 619 620 if (unlikely(rxlen >= sizeof(s->buf))) { 621 dev_warn_ratelimited(port->dev, 622 "ttySC%i: Possible RX FIFO overrun: %d\n", 623 port->line, rxlen); 624 port->icount.buf_overrun++; 625 /* Ensure sanity of RX level */ 626 rxlen = sizeof(s->buf); 627 } 628 629 while (rxlen) { 630 /* Only read lsr if there are possible errors in FIFO */ 631 if (read_lsr) { 632 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 633 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT)) 634 read_lsr = false; /* No errors left in FIFO */ 635 } else 636 lsr = 0; 637 638 if (read_lsr) { 639 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG); 640 bytes_read = 1; 641 } else { 642 sc16is7xx_fifo_read(port, s->buf, rxlen); 643 bytes_read = rxlen; 644 } 645 646 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK; 647 648 port->icount.rx++; 649 flag = TTY_NORMAL; 650 651 if (unlikely(lsr)) { 652 if (lsr & SC16IS7XX_LSR_BI_BIT) { 653 port->icount.brk++; 654 if (uart_handle_break(port)) 655 continue; 656 } else if (lsr & SC16IS7XX_LSR_PE_BIT) 657 port->icount.parity++; 658 else if (lsr & SC16IS7XX_LSR_FE_BIT) 659 port->icount.frame++; 660 else if (lsr & SC16IS7XX_LSR_OE_BIT) 661 port->icount.overrun++; 662 663 lsr &= port->read_status_mask; 664 if (lsr & SC16IS7XX_LSR_BI_BIT) 665 flag = TTY_BREAK; 666 else if (lsr & SC16IS7XX_LSR_PE_BIT) 667 flag = TTY_PARITY; 668 else if (lsr & SC16IS7XX_LSR_FE_BIT) 669 flag = TTY_FRAME; 670 else if (lsr & SC16IS7XX_LSR_OE_BIT) 671 flag = TTY_OVERRUN; 672 } 673 674 for (i = 0; i < bytes_read; ++i) { 675 ch = s->buf[i]; 676 if (uart_handle_sysrq_char(port, ch)) 677 continue; 678 679 if (lsr & port->ignore_status_mask) 680 continue; 681 682 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch, 683 flag); 684 } 685 rxlen -= bytes_read; 686 } 687 688 tty_flip_buffer_push(&port->state->port); 689 } 690 691 static void sc16is7xx_handle_tx(struct uart_port *port) 692 { 693 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 694 struct tty_port *tport = &port->state->port; 695 unsigned long flags; 696 unsigned int txlen; 697 698 if (unlikely(port->x_char)) { 699 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char); 700 port->icount.tx++; 701 port->x_char = 0; 702 return; 703 } 704 705 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) { 706 uart_port_lock_irqsave(port, &flags); 707 sc16is7xx_stop_tx(port); 708 uart_port_unlock_irqrestore(port, flags); 709 return; 710 } 711 712 /* Limit to space available in TX FIFO */ 713 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG); 714 if (txlen > SC16IS7XX_FIFO_SIZE) { 715 dev_err_ratelimited(port->dev, 716 "chip reports %d free bytes in TX fifo, but it only has %d", 717 txlen, SC16IS7XX_FIFO_SIZE); 718 txlen = 0; 719 } 720 721 txlen = uart_fifo_out(port, s->buf, txlen); 722 sc16is7xx_fifo_write(port, s->buf, txlen); 723 724 uart_port_lock_irqsave(port, &flags); 725 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 726 uart_write_wakeup(port); 727 728 if (kfifo_is_empty(&tport->xmit_fifo)) 729 sc16is7xx_stop_tx(port); 730 else 731 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT); 732 uart_port_unlock_irqrestore(port, flags); 733 } 734 735 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port) 736 { 737 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG); 738 unsigned int mctrl = 0; 739 740 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0; 741 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0; 742 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0; 743 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0; 744 return mctrl; 745 } 746 747 static void sc16is7xx_update_mlines(struct sc16is7xx_one *one) 748 { 749 struct uart_port *port = &one->port; 750 unsigned long flags; 751 unsigned int status, changed; 752 753 lockdep_assert_held_once(&one->efr_lock); 754 755 status = sc16is7xx_get_hwmctrl(port); 756 changed = status ^ one->old_mctrl; 757 758 if (changed == 0) 759 return; 760 761 one->old_mctrl = status; 762 763 uart_port_lock_irqsave(port, &flags); 764 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG)) 765 port->icount.rng++; 766 if (changed & TIOCM_DSR) 767 port->icount.dsr++; 768 if (changed & TIOCM_CAR) 769 uart_handle_dcd_change(port, status & TIOCM_CAR); 770 if (changed & TIOCM_CTS) 771 uart_handle_cts_change(port, status & TIOCM_CTS); 772 773 wake_up_interruptible(&port->state->port.delta_msr_wait); 774 uart_port_unlock_irqrestore(port, flags); 775 } 776 777 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno) 778 { 779 bool rc = true; 780 unsigned int iir, rxlen; 781 struct uart_port *port = &s->p[portno].port; 782 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 783 784 mutex_lock(&one->efr_lock); 785 786 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG); 787 if (iir & SC16IS7XX_IIR_NO_INT_BIT) { 788 rc = false; 789 goto out_port_irq; 790 } 791 792 iir &= SC16IS7XX_IIR_ID_MASK; 793 794 switch (iir) { 795 case SC16IS7XX_IIR_RDI_SRC: 796 case SC16IS7XX_IIR_RLSE_SRC: 797 case SC16IS7XX_IIR_RTOI_SRC: 798 case SC16IS7XX_IIR_XOFFI_SRC: 799 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); 800 801 /* 802 * There is a silicon bug that makes the chip report a 803 * time-out interrupt but no data in the FIFO. This is 804 * described in errata section 18.1.4. 805 * 806 * When this happens, read one byte from the FIFO to 807 * clear the interrupt. 808 */ 809 if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen) 810 rxlen = 1; 811 812 if (rxlen) 813 sc16is7xx_handle_rx(port, rxlen, iir); 814 break; 815 /* CTSRTS interrupt comes only when CTS goes inactive */ 816 case SC16IS7XX_IIR_CTSRTS_SRC: 817 case SC16IS7XX_IIR_MSI_SRC: 818 sc16is7xx_update_mlines(one); 819 break; 820 case SC16IS7XX_IIR_THRI_SRC: 821 sc16is7xx_handle_tx(port); 822 break; 823 default: 824 dev_err_ratelimited(port->dev, 825 "ttySC%i: Unexpected interrupt: %x", 826 port->line, iir); 827 break; 828 } 829 830 out_port_irq: 831 mutex_unlock(&one->efr_lock); 832 833 return rc; 834 } 835 836 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id) 837 { 838 bool keep_polling; 839 840 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id; 841 842 do { 843 int i; 844 845 keep_polling = false; 846 847 for (i = 0; i < s->devtype->nr_uart; ++i) 848 keep_polling |= sc16is7xx_port_irq(s, i); 849 } while (keep_polling); 850 851 return IRQ_HANDLED; 852 } 853 854 static void sc16is7xx_tx_proc(struct kthread_work *ws) 855 { 856 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port); 857 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 858 859 if ((port->rs485.flags & SER_RS485_ENABLED) && 860 (port->rs485.delay_rts_before_send > 0)) 861 msleep(port->rs485.delay_rts_before_send); 862 863 mutex_lock(&one->efr_lock); 864 sc16is7xx_handle_tx(port); 865 mutex_unlock(&one->efr_lock); 866 } 867 868 static void sc16is7xx_reconf_rs485(struct uart_port *port) 869 { 870 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT | 871 SC16IS7XX_EFCR_RTS_INVERT_BIT; 872 u32 efcr = 0; 873 struct serial_rs485 *rs485 = &port->rs485; 874 unsigned long irqflags; 875 876 uart_port_lock_irqsave(port, &irqflags); 877 if (rs485->flags & SER_RS485_ENABLED) { 878 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT; 879 880 if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 881 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT; 882 } 883 uart_port_unlock_irqrestore(port, irqflags); 884 885 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr); 886 } 887 888 static void sc16is7xx_reg_proc(struct kthread_work *ws) 889 { 890 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work); 891 struct sc16is7xx_one_config config; 892 unsigned long irqflags; 893 894 uart_port_lock_irqsave(&one->port, &irqflags); 895 config = one->config; 896 memset(&one->config, 0, sizeof(one->config)); 897 uart_port_unlock_irqrestore(&one->port, irqflags); 898 899 if (config.flags & SC16IS7XX_RECONF_MD) { 900 u8 mcr = 0; 901 902 /* Device ignores RTS setting when hardware flow is enabled */ 903 if (one->port.mctrl & TIOCM_RTS) 904 mcr |= SC16IS7XX_MCR_RTS_BIT; 905 906 if (one->port.mctrl & TIOCM_DTR) 907 mcr |= SC16IS7XX_MCR_DTR_BIT; 908 909 if (one->port.mctrl & TIOCM_LOOP) 910 mcr |= SC16IS7XX_MCR_LOOP_BIT; 911 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, 912 SC16IS7XX_MCR_RTS_BIT | 913 SC16IS7XX_MCR_DTR_BIT | 914 SC16IS7XX_MCR_LOOP_BIT, 915 mcr); 916 } 917 918 if (config.flags & SC16IS7XX_RECONF_IER) 919 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG, 920 config.ier_mask, config.ier_val); 921 922 if (config.flags & SC16IS7XX_RECONF_RS485) 923 sc16is7xx_reconf_rs485(&one->port); 924 } 925 926 static void sc16is7xx_ms_proc(struct kthread_work *ws) 927 { 928 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work); 929 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev); 930 931 if (one->port.state) { 932 mutex_lock(&one->efr_lock); 933 sc16is7xx_update_mlines(one); 934 mutex_unlock(&one->efr_lock); 935 936 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ); 937 } 938 } 939 940 static void sc16is7xx_enable_ms(struct uart_port *port) 941 { 942 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 943 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 944 945 lockdep_assert_held_once(&port->lock); 946 947 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0); 948 } 949 950 static void sc16is7xx_start_tx(struct uart_port *port) 951 { 952 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 953 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 954 955 kthread_queue_work(&s->kworker, &one->tx_work); 956 } 957 958 static void sc16is7xx_throttle(struct uart_port *port) 959 { 960 unsigned long flags; 961 962 /* 963 * Hardware flow control is enabled and thus the device ignores RTS 964 * value set in MCR register. Stop reading data from RX FIFO so the 965 * AutoRTS feature will de-activate RTS output. 966 */ 967 uart_port_lock_irqsave(port, &flags); 968 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 969 uart_port_unlock_irqrestore(port, flags); 970 } 971 972 static void sc16is7xx_unthrottle(struct uart_port *port) 973 { 974 unsigned long flags; 975 976 uart_port_lock_irqsave(port, &flags); 977 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT); 978 uart_port_unlock_irqrestore(port, flags); 979 } 980 981 static unsigned int sc16is7xx_tx_empty(struct uart_port *port) 982 { 983 unsigned int lsr; 984 985 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 986 987 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0; 988 } 989 990 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port) 991 { 992 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 993 994 /* Called with port lock taken so we can only return cached value */ 995 return one->old_mctrl; 996 } 997 998 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl) 999 { 1000 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1001 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1002 1003 one->config.flags |= SC16IS7XX_RECONF_MD; 1004 kthread_queue_work(&s->kworker, &one->reg_work); 1005 } 1006 1007 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state) 1008 { 1009 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG, 1010 SC16IS7XX_LCR_TXBREAK_BIT, 1011 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0); 1012 } 1013 1014 static void sc16is7xx_set_termios(struct uart_port *port, 1015 struct ktermios *termios, 1016 const struct ktermios *old) 1017 { 1018 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1019 unsigned int lcr, flow = 0; 1020 int baud; 1021 unsigned long flags; 1022 1023 kthread_cancel_delayed_work_sync(&one->ms_work); 1024 1025 /* Mask termios capabilities we don't support */ 1026 termios->c_cflag &= ~CMSPAR; 1027 1028 /* Word size */ 1029 switch (termios->c_cflag & CSIZE) { 1030 case CS5: 1031 lcr = SC16IS7XX_LCR_WORD_LEN_5; 1032 break; 1033 case CS6: 1034 lcr = SC16IS7XX_LCR_WORD_LEN_6; 1035 break; 1036 case CS7: 1037 lcr = SC16IS7XX_LCR_WORD_LEN_7; 1038 break; 1039 case CS8: 1040 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1041 break; 1042 default: 1043 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1044 termios->c_cflag &= ~CSIZE; 1045 termios->c_cflag |= CS8; 1046 break; 1047 } 1048 1049 /* Parity */ 1050 if (termios->c_cflag & PARENB) { 1051 lcr |= SC16IS7XX_LCR_PARITY_BIT; 1052 if (!(termios->c_cflag & PARODD)) 1053 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT; 1054 } 1055 1056 /* Stop bits */ 1057 if (termios->c_cflag & CSTOPB) 1058 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */ 1059 1060 /* Set read status mask */ 1061 port->read_status_mask = SC16IS7XX_LSR_OE_BIT; 1062 if (termios->c_iflag & INPCK) 1063 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT | 1064 SC16IS7XX_LSR_FE_BIT; 1065 if (termios->c_iflag & (BRKINT | PARMRK)) 1066 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT; 1067 1068 /* Set status ignore mask */ 1069 port->ignore_status_mask = 0; 1070 if (termios->c_iflag & IGNBRK) 1071 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT; 1072 if (!(termios->c_cflag & CREAD)) 1073 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK; 1074 1075 /* Configure flow control */ 1076 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1077 if (termios->c_cflag & CRTSCTS) { 1078 flow |= SC16IS7XX_EFR_AUTOCTS_BIT | 1079 SC16IS7XX_EFR_AUTORTS_BIT; 1080 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1081 } 1082 if (termios->c_iflag & IXON) 1083 flow |= SC16IS7XX_EFR_SWFLOW3_BIT; 1084 if (termios->c_iflag & IXOFF) 1085 flow |= SC16IS7XX_EFR_SWFLOW1_BIT; 1086 1087 /* Update LCR register */ 1088 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 1089 1090 /* Update EFR registers */ 1091 sc16is7xx_efr_lock(port); 1092 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]); 1093 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]); 1094 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 1095 SC16IS7XX_EFR_FLOWCTRL_BITS, flow); 1096 sc16is7xx_efr_unlock(port); 1097 1098 /* Get baud rate generator configuration */ 1099 baud = uart_get_baud_rate(port, termios, old, 1100 port->uartclk / 16 / 4 / 0xffff, 1101 port->uartclk / 16); 1102 1103 /* Setup baudrate generator */ 1104 baud = sc16is7xx_set_baud(port, baud); 1105 1106 uart_port_lock_irqsave(port, &flags); 1107 1108 /* Update timeout according to new baud rate */ 1109 uart_update_timeout(port, termios->c_cflag, baud); 1110 1111 if (UART_ENABLE_MS(port, termios->c_cflag)) 1112 sc16is7xx_enable_ms(port); 1113 1114 uart_port_unlock_irqrestore(port, flags); 1115 } 1116 1117 static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios, 1118 struct serial_rs485 *rs485) 1119 { 1120 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1121 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1122 1123 if (rs485->flags & SER_RS485_ENABLED) { 1124 /* 1125 * RTS signal is handled by HW, it's timing can't be influenced. 1126 * However, it's sometimes useful to delay TX even without RTS 1127 * control therefore we try to handle .delay_rts_before_send. 1128 */ 1129 if (rs485->delay_rts_after_send) 1130 return -EINVAL; 1131 } 1132 1133 one->config.flags |= SC16IS7XX_RECONF_RS485; 1134 kthread_queue_work(&s->kworker, &one->reg_work); 1135 1136 return 0; 1137 } 1138 1139 static int sc16is7xx_startup(struct uart_port *port) 1140 { 1141 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1142 unsigned int val; 1143 unsigned long flags; 1144 1145 sc16is7xx_power(port, 1); 1146 1147 /* Reset FIFOs*/ 1148 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT; 1149 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val); 1150 udelay(5); 1151 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, 1152 SC16IS7XX_FCR_FIFO_BIT); 1153 1154 /* Enable EFR */ 1155 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 1156 SC16IS7XX_LCR_CONF_MODE_B); 1157 1158 regcache_cache_bypass(one->regmap, true); 1159 1160 /* Enable write access to enhanced features and internal clock div */ 1161 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 1162 SC16IS7XX_EFR_ENABLE_BIT, 1163 SC16IS7XX_EFR_ENABLE_BIT); 1164 1165 /* Enable TCR/TLR */ 1166 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1167 SC16IS7XX_MCR_TCRTLR_BIT, 1168 SC16IS7XX_MCR_TCRTLR_BIT); 1169 1170 /* Configure flow control levels */ 1171 /* Flow control halt level 48, resume level 24 */ 1172 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG, 1173 SC16IS7XX_TCR_RX_RESUME(24) | 1174 SC16IS7XX_TCR_RX_HALT(48)); 1175 1176 regcache_cache_bypass(one->regmap, false); 1177 1178 /* Now, initialize the UART */ 1179 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8); 1180 1181 /* Enable IrDA mode if requested in DT */ 1182 /* This bit must be written with LCR[7] = 0 */ 1183 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1184 SC16IS7XX_MCR_IRDA_BIT, 1185 one->irda_mode ? 1186 SC16IS7XX_MCR_IRDA_BIT : 0); 1187 1188 /* Enable the Rx and Tx FIFO */ 1189 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1190 SC16IS7XX_EFCR_RXDISABLE_BIT | 1191 SC16IS7XX_EFCR_TXDISABLE_BIT, 1192 0); 1193 1194 /* Enable RX, CTS change and modem lines interrupts */ 1195 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT | 1196 SC16IS7XX_IER_MSI_BIT; 1197 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); 1198 1199 /* Enable modem status polling */ 1200 uart_port_lock_irqsave(port, &flags); 1201 sc16is7xx_enable_ms(port); 1202 uart_port_unlock_irqrestore(port, flags); 1203 1204 return 0; 1205 } 1206 1207 static void sc16is7xx_shutdown(struct uart_port *port) 1208 { 1209 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1210 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1211 1212 kthread_cancel_delayed_work_sync(&one->ms_work); 1213 1214 /* Disable all interrupts */ 1215 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0); 1216 /* Disable TX/RX */ 1217 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1218 SC16IS7XX_EFCR_RXDISABLE_BIT | 1219 SC16IS7XX_EFCR_TXDISABLE_BIT, 1220 SC16IS7XX_EFCR_RXDISABLE_BIT | 1221 SC16IS7XX_EFCR_TXDISABLE_BIT); 1222 1223 sc16is7xx_power(port, 0); 1224 1225 kthread_flush_worker(&s->kworker); 1226 } 1227 1228 static const char *sc16is7xx_type(struct uart_port *port) 1229 { 1230 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1231 1232 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL; 1233 } 1234 1235 static int sc16is7xx_request_port(struct uart_port *port) 1236 { 1237 /* Do nothing */ 1238 return 0; 1239 } 1240 1241 static void sc16is7xx_config_port(struct uart_port *port, int flags) 1242 { 1243 if (flags & UART_CONFIG_TYPE) 1244 port->type = PORT_SC16IS7XX; 1245 } 1246 1247 static int sc16is7xx_verify_port(struct uart_port *port, 1248 struct serial_struct *s) 1249 { 1250 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX)) 1251 return -EINVAL; 1252 if (s->irq != port->irq) 1253 return -EINVAL; 1254 1255 return 0; 1256 } 1257 1258 static void sc16is7xx_pm(struct uart_port *port, unsigned int state, 1259 unsigned int oldstate) 1260 { 1261 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0); 1262 } 1263 1264 static void sc16is7xx_null_void(struct uart_port *port) 1265 { 1266 /* Do nothing */ 1267 } 1268 1269 static const struct uart_ops sc16is7xx_ops = { 1270 .tx_empty = sc16is7xx_tx_empty, 1271 .set_mctrl = sc16is7xx_set_mctrl, 1272 .get_mctrl = sc16is7xx_get_mctrl, 1273 .stop_tx = sc16is7xx_stop_tx, 1274 .start_tx = sc16is7xx_start_tx, 1275 .throttle = sc16is7xx_throttle, 1276 .unthrottle = sc16is7xx_unthrottle, 1277 .stop_rx = sc16is7xx_stop_rx, 1278 .enable_ms = sc16is7xx_enable_ms, 1279 .break_ctl = sc16is7xx_break_ctl, 1280 .startup = sc16is7xx_startup, 1281 .shutdown = sc16is7xx_shutdown, 1282 .set_termios = sc16is7xx_set_termios, 1283 .type = sc16is7xx_type, 1284 .request_port = sc16is7xx_request_port, 1285 .release_port = sc16is7xx_null_void, 1286 .config_port = sc16is7xx_config_port, 1287 .verify_port = sc16is7xx_verify_port, 1288 .pm = sc16is7xx_pm, 1289 }; 1290 1291 #ifdef CONFIG_GPIOLIB 1292 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset) 1293 { 1294 unsigned int val; 1295 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1296 struct uart_port *port = &s->p[0].port; 1297 1298 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1299 1300 return !!(val & BIT(offset)); 1301 } 1302 1303 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 1304 { 1305 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1306 struct uart_port *port = &s->p[0].port; 1307 1308 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), 1309 val ? BIT(offset) : 0); 1310 } 1311 1312 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip, 1313 unsigned offset) 1314 { 1315 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1316 struct uart_port *port = &s->p[0].port; 1317 1318 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0); 1319 1320 return 0; 1321 } 1322 1323 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, 1324 unsigned offset, int val) 1325 { 1326 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1327 struct uart_port *port = &s->p[0].port; 1328 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1329 1330 if (val) 1331 state |= BIT(offset); 1332 else 1333 state &= ~BIT(offset); 1334 1335 /* 1336 * If we write IOSTATE first, and then IODIR, the output value is not 1337 * transferred to the corresponding I/O pin. 1338 * The datasheet states that each register bit will be transferred to 1339 * the corresponding I/O pin programmed as output when writing to 1340 * IOSTATE. Therefore, configure direction first with IODIR, and then 1341 * set value after with IOSTATE. 1342 */ 1343 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 1344 BIT(offset)); 1345 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); 1346 1347 return 0; 1348 } 1349 1350 static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip, 1351 unsigned long *valid_mask, 1352 unsigned int ngpios) 1353 { 1354 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1355 1356 *valid_mask = s->gpio_valid_mask; 1357 1358 return 0; 1359 } 1360 1361 static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s) 1362 { 1363 struct device *dev = s->p[0].port.dev; 1364 1365 if (!s->devtype->nr_gpio) 1366 return 0; 1367 1368 switch (s->mctrl_mask) { 1369 case 0: 1370 s->gpio_valid_mask = GENMASK(7, 0); 1371 break; 1372 case SC16IS7XX_IOCONTROL_MODEM_A_BIT: 1373 s->gpio_valid_mask = GENMASK(3, 0); 1374 break; 1375 case SC16IS7XX_IOCONTROL_MODEM_B_BIT: 1376 s->gpio_valid_mask = GENMASK(7, 4); 1377 break; 1378 default: 1379 break; 1380 } 1381 1382 if (s->gpio_valid_mask == 0) 1383 return 0; 1384 1385 s->gpio.owner = THIS_MODULE; 1386 s->gpio.parent = dev; 1387 s->gpio.label = dev_name(dev); 1388 s->gpio.init_valid_mask = sc16is7xx_gpio_init_valid_mask; 1389 s->gpio.direction_input = sc16is7xx_gpio_direction_input; 1390 s->gpio.get = sc16is7xx_gpio_get; 1391 s->gpio.direction_output = sc16is7xx_gpio_direction_output; 1392 s->gpio.set = sc16is7xx_gpio_set; 1393 s->gpio.base = -1; 1394 s->gpio.ngpio = s->devtype->nr_gpio; 1395 s->gpio.can_sleep = 1; 1396 1397 return gpiochip_add_data(&s->gpio, s); 1398 } 1399 #endif 1400 1401 static void sc16is7xx_setup_irda_ports(struct sc16is7xx_port *s) 1402 { 1403 int i; 1404 int ret; 1405 int count; 1406 u32 irda_port[SC16IS7XX_MAX_PORTS]; 1407 struct device *dev = s->p[0].port.dev; 1408 1409 count = device_property_count_u32(dev, "irda-mode-ports"); 1410 if (count < 0 || count > ARRAY_SIZE(irda_port)) 1411 return; 1412 1413 ret = device_property_read_u32_array(dev, "irda-mode-ports", 1414 irda_port, count); 1415 if (ret) 1416 return; 1417 1418 for (i = 0; i < count; i++) { 1419 if (irda_port[i] < s->devtype->nr_uart) 1420 s->p[irda_port[i]].irda_mode = true; 1421 } 1422 } 1423 1424 /* 1425 * Configure ports designated to operate as modem control lines. 1426 */ 1427 static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s, 1428 struct regmap *regmap) 1429 { 1430 int i; 1431 int ret; 1432 int count; 1433 u32 mctrl_port[SC16IS7XX_MAX_PORTS]; 1434 struct device *dev = s->p[0].port.dev; 1435 1436 count = device_property_count_u32(dev, "nxp,modem-control-line-ports"); 1437 if (count < 0 || count > ARRAY_SIZE(mctrl_port)) 1438 return 0; 1439 1440 ret = device_property_read_u32_array(dev, "nxp,modem-control-line-ports", 1441 mctrl_port, count); 1442 if (ret) 1443 return ret; 1444 1445 s->mctrl_mask = 0; 1446 1447 for (i = 0; i < count; i++) { 1448 /* Use GPIO lines as modem control lines */ 1449 if (mctrl_port[i] == 0) 1450 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT; 1451 else if (mctrl_port[i] == 1) 1452 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT; 1453 } 1454 1455 if (s->mctrl_mask) 1456 regmap_update_bits( 1457 regmap, 1458 SC16IS7XX_IOCONTROL_REG, 1459 SC16IS7XX_IOCONTROL_MODEM_A_BIT | 1460 SC16IS7XX_IOCONTROL_MODEM_B_BIT, s->mctrl_mask); 1461 1462 return 0; 1463 } 1464 1465 static const struct serial_rs485 sc16is7xx_rs485_supported = { 1466 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND, 1467 .delay_rts_before_send = 1, 1468 .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */ 1469 }; 1470 1471 /* Reset device, purging any pending irq / data */ 1472 static int sc16is7xx_reset(struct device *dev, struct regmap *regmap) 1473 { 1474 struct gpio_desc *reset_gpio; 1475 1476 /* Assert reset GPIO if defined and valid. */ 1477 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 1478 if (IS_ERR(reset_gpio)) 1479 return dev_err_probe(dev, PTR_ERR(reset_gpio), "Failed to get reset GPIO\n"); 1480 1481 if (reset_gpio) { 1482 /* The minimum reset pulse width is 3 us. */ 1483 fsleep(5); 1484 gpiod_set_value_cansleep(reset_gpio, 0); /* Deassert GPIO */ 1485 } else { 1486 /* Software reset */ 1487 regmap_write(regmap, SC16IS7XX_IOCONTROL_REG, 1488 SC16IS7XX_IOCONTROL_SRESET_BIT); 1489 } 1490 1491 return 0; 1492 } 1493 1494 int sc16is7xx_probe(struct device *dev, const struct sc16is7xx_devtype *devtype, 1495 struct regmap *regmaps[], int irq) 1496 { 1497 unsigned long freq = 0, *pfreq = dev_get_platdata(dev); 1498 unsigned int val; 1499 u32 uartclk = 0; 1500 int i, ret; 1501 struct sc16is7xx_port *s; 1502 bool port_registered[SC16IS7XX_MAX_PORTS]; 1503 1504 for (i = 0; i < devtype->nr_uart; i++) 1505 if (IS_ERR(regmaps[i])) 1506 return PTR_ERR(regmaps[i]); 1507 1508 /* 1509 * This device does not have an identification register that would 1510 * tell us if we are really connected to the correct device. 1511 * The best we can do is to check if communication is at all possible. 1512 * 1513 * Note: regmap[0] is used in the probe function to access registers 1514 * common to all channels/ports, as it is guaranteed to be present on 1515 * all variants. 1516 */ 1517 ret = regmap_read(regmaps[0], SC16IS7XX_LSR_REG, &val); 1518 if (ret < 0) 1519 return -EPROBE_DEFER; 1520 1521 /* Alloc port structure */ 1522 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL); 1523 if (!s) { 1524 dev_err(dev, "Error allocating port structure\n"); 1525 return -ENOMEM; 1526 } 1527 1528 /* Always ask for fixed clock rate from a property. */ 1529 device_property_read_u32(dev, "clock-frequency", &uartclk); 1530 1531 s->clk = devm_clk_get_optional(dev, NULL); 1532 if (IS_ERR(s->clk)) 1533 return PTR_ERR(s->clk); 1534 1535 ret = clk_prepare_enable(s->clk); 1536 if (ret) 1537 return ret; 1538 1539 freq = clk_get_rate(s->clk); 1540 if (freq == 0) { 1541 if (uartclk) 1542 freq = uartclk; 1543 if (pfreq) 1544 freq = *pfreq; 1545 if (freq) 1546 dev_dbg(dev, "Clock frequency: %luHz\n", freq); 1547 else 1548 return -EINVAL; 1549 } 1550 1551 s->devtype = devtype; 1552 dev_set_drvdata(dev, s); 1553 1554 kthread_init_worker(&s->kworker); 1555 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker, 1556 "sc16is7xx"); 1557 if (IS_ERR(s->kworker_task)) { 1558 ret = PTR_ERR(s->kworker_task); 1559 goto out_clk; 1560 } 1561 sched_set_fifo(s->kworker_task); 1562 1563 ret = sc16is7xx_reset(dev, regmaps[0]); 1564 if (ret) 1565 goto out_kthread; 1566 1567 /* Mark each port line and status as uninitialised. */ 1568 for (i = 0; i < devtype->nr_uart; ++i) { 1569 s->p[i].port.line = SC16IS7XX_MAX_DEVS; 1570 port_registered[i] = false; 1571 } 1572 1573 for (i = 0; i < devtype->nr_uart; ++i) { 1574 ret = ida_alloc_max(&sc16is7xx_lines, 1575 SC16IS7XX_MAX_DEVS - 1, GFP_KERNEL); 1576 if (ret < 0) 1577 goto out_ports; 1578 1579 s->p[i].port.line = ret; 1580 1581 /* Initialize port data */ 1582 s->p[i].port.dev = dev; 1583 s->p[i].port.irq = irq; 1584 s->p[i].port.type = PORT_SC16IS7XX; 1585 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE; 1586 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1587 s->p[i].port.iobase = i; 1588 /* 1589 * Use all ones as membase to make sure uart_configure_port() in 1590 * serial_core.c does not abort for SPI/I2C devices where the 1591 * membase address is not applicable. 1592 */ 1593 s->p[i].port.membase = (void __iomem *)~0; 1594 s->p[i].port.iotype = UPIO_PORT; 1595 s->p[i].port.uartclk = freq; 1596 s->p[i].port.rs485_config = sc16is7xx_config_rs485; 1597 s->p[i].port.rs485_supported = sc16is7xx_rs485_supported; 1598 s->p[i].port.ops = &sc16is7xx_ops; 1599 s->p[i].old_mctrl = 0; 1600 s->p[i].regmap = regmaps[i]; 1601 1602 mutex_init(&s->p[i].efr_lock); 1603 1604 ret = uart_get_rs485_mode(&s->p[i].port); 1605 if (ret) 1606 goto out_ports; 1607 1608 /* Disable all interrupts */ 1609 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0); 1610 /* Disable TX/RX */ 1611 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG, 1612 SC16IS7XX_EFCR_RXDISABLE_BIT | 1613 SC16IS7XX_EFCR_TXDISABLE_BIT); 1614 1615 /* Initialize kthread work structs */ 1616 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc); 1617 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc); 1618 kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc); 1619 1620 /* Register port */ 1621 ret = uart_add_one_port(&sc16is7xx_uart, &s->p[i].port); 1622 if (ret) 1623 goto out_ports; 1624 1625 port_registered[i] = true; 1626 1627 /* Enable EFR */ 1628 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 1629 SC16IS7XX_LCR_CONF_MODE_B); 1630 1631 regcache_cache_bypass(regmaps[i], true); 1632 1633 /* Enable write access to enhanced features */ 1634 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG, 1635 SC16IS7XX_EFR_ENABLE_BIT); 1636 1637 regcache_cache_bypass(regmaps[i], false); 1638 1639 /* Restore access to general registers */ 1640 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00); 1641 1642 /* Go to suspend mode */ 1643 sc16is7xx_power(&s->p[i].port, 0); 1644 } 1645 1646 sc16is7xx_setup_irda_ports(s); 1647 1648 ret = sc16is7xx_setup_mctrl_ports(s, regmaps[0]); 1649 if (ret) 1650 goto out_ports; 1651 1652 #ifdef CONFIG_GPIOLIB 1653 ret = sc16is7xx_setup_gpio_chip(s); 1654 if (ret) 1655 goto out_ports; 1656 #endif 1657 1658 /* 1659 * Setup interrupt. We first try to acquire the IRQ line as level IRQ. 1660 * If that succeeds, we can allow sharing the interrupt as well. 1661 * In case the interrupt controller doesn't support that, we fall 1662 * back to a non-shared falling-edge trigger. 1663 */ 1664 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1665 IRQF_TRIGGER_LOW | IRQF_SHARED | 1666 IRQF_ONESHOT, 1667 dev_name(dev), s); 1668 if (!ret) 1669 return 0; 1670 1671 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1672 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1673 dev_name(dev), s); 1674 if (!ret) 1675 return 0; 1676 1677 #ifdef CONFIG_GPIOLIB 1678 if (s->gpio_valid_mask) 1679 gpiochip_remove(&s->gpio); 1680 #endif 1681 1682 out_ports: 1683 for (i = 0; i < devtype->nr_uart; i++) { 1684 if (s->p[i].port.line < SC16IS7XX_MAX_DEVS) 1685 ida_free(&sc16is7xx_lines, s->p[i].port.line); 1686 if (port_registered[i]) 1687 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1688 } 1689 1690 out_kthread: 1691 kthread_stop(s->kworker_task); 1692 1693 out_clk: 1694 clk_disable_unprepare(s->clk); 1695 1696 return ret; 1697 } 1698 EXPORT_SYMBOL_GPL(sc16is7xx_probe); 1699 1700 void sc16is7xx_remove(struct device *dev) 1701 { 1702 struct sc16is7xx_port *s = dev_get_drvdata(dev); 1703 int i; 1704 1705 #ifdef CONFIG_GPIOLIB 1706 if (s->gpio_valid_mask) 1707 gpiochip_remove(&s->gpio); 1708 #endif 1709 1710 for (i = 0; i < s->devtype->nr_uart; i++) { 1711 kthread_cancel_delayed_work_sync(&s->p[i].ms_work); 1712 ida_free(&sc16is7xx_lines, s->p[i].port.line); 1713 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1714 sc16is7xx_power(&s->p[i].port, 0); 1715 } 1716 1717 kthread_flush_worker(&s->kworker); 1718 kthread_stop(s->kworker_task); 1719 1720 clk_disable_unprepare(s->clk); 1721 } 1722 EXPORT_SYMBOL_GPL(sc16is7xx_remove); 1723 1724 const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = { 1725 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, }, 1726 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, }, 1727 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, }, 1728 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, }, 1729 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, }, 1730 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, }, 1731 { } 1732 }; 1733 EXPORT_SYMBOL_GPL(sc16is7xx_dt_ids); 1734 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids); 1735 1736 const struct regmap_config sc16is7xx_regcfg = { 1737 .reg_bits = 5, 1738 .pad_bits = 3, 1739 .val_bits = 8, 1740 .cache_type = REGCACHE_MAPLE, 1741 .volatile_reg = sc16is7xx_regmap_volatile, 1742 .precious_reg = sc16is7xx_regmap_precious, 1743 .writeable_noinc_reg = sc16is7xx_regmap_noinc, 1744 .readable_noinc_reg = sc16is7xx_regmap_noinc, 1745 .max_raw_read = SC16IS7XX_FIFO_SIZE, 1746 .max_raw_write = SC16IS7XX_FIFO_SIZE, 1747 .max_register = SC16IS7XX_EFCR_REG, 1748 }; 1749 EXPORT_SYMBOL_GPL(sc16is7xx_regcfg); 1750 1751 const char *sc16is7xx_regmap_name(u8 port_id) 1752 { 1753 switch (port_id) { 1754 case 0: return "port0"; 1755 case 1: return "port1"; 1756 default: 1757 WARN_ON(true); 1758 return NULL; 1759 } 1760 } 1761 EXPORT_SYMBOL_GPL(sc16is7xx_regmap_name); 1762 1763 unsigned int sc16is7xx_regmap_port_mask(unsigned int port_id) 1764 { 1765 /* CH1,CH0 are at bits 2:1. */ 1766 return port_id << 1; 1767 } 1768 EXPORT_SYMBOL_GPL(sc16is7xx_regmap_port_mask); 1769 1770 static int __init sc16is7xx_init(void) 1771 { 1772 return uart_register_driver(&sc16is7xx_uart); 1773 } 1774 module_init(sc16is7xx_init); 1775 1776 static void __exit sc16is7xx_exit(void) 1777 { 1778 uart_unregister_driver(&sc16is7xx_uart); 1779 } 1780 module_exit(sc16is7xx_exit); 1781 1782 MODULE_LICENSE("GPL"); 1783 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>"); 1784 MODULE_DESCRIPTION("SC16IS7xx tty serial core driver"); 1785