1 /* 2 * Support for the asynchronous serial interface (DUART) included 3 * in the BCM1250 and derived System-On-a-Chip (SOC) devices. 4 * 5 * Copyright (c) 2007 Maciej W. Rozycki 6 * 7 * Derived from drivers/char/sb1250_duart.c for which the following 8 * copyright applies: 9 * 10 * Copyright (c) 2000, 2001, 2002, 2003, 2004 Broadcom Corporation 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License 14 * as published by the Free Software Foundation; either version 15 * 2 of the License, or (at your option) any later version. 16 * 17 * References: 18 * 19 * "BCM1250/BCM1125/BCM1125H User Manual", Broadcom Corporation 20 */ 21 22 #if defined(CONFIG_SERIAL_SB1250_DUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 23 #define SUPPORT_SYSRQ 24 #endif 25 26 #include <linux/compiler.h> 27 #include <linux/console.h> 28 #include <linux/delay.h> 29 #include <linux/errno.h> 30 #include <linux/init.h> 31 #include <linux/interrupt.h> 32 #include <linux/ioport.h> 33 #include <linux/kernel.h> 34 #include <linux/major.h> 35 #include <linux/serial.h> 36 #include <linux/serial_core.h> 37 #include <linux/spinlock.h> 38 #include <linux/sysrq.h> 39 #include <linux/tty.h> 40 #include <linux/tty_flip.h> 41 #include <linux/types.h> 42 43 #include <linux/atomic.h> 44 #include <asm/io.h> 45 #include <asm/war.h> 46 47 #include <asm/sibyte/sb1250.h> 48 #include <asm/sibyte/sb1250_uart.h> 49 #include <asm/sibyte/swarm.h> 50 51 52 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 53 #include <asm/sibyte/bcm1480_regs.h> 54 #include <asm/sibyte/bcm1480_int.h> 55 56 #define SBD_CHANREGS(line) A_BCM1480_DUART_CHANREG((line), 0) 57 #define SBD_CTRLREGS(line) A_BCM1480_DUART_CTRLREG((line), 0) 58 #define SBD_INT(line) (K_BCM1480_INT_UART_0 + (line)) 59 60 #define DUART_CHANREG_SPACING BCM1480_DUART_CHANREG_SPACING 61 62 #define R_DUART_IMRREG(line) R_BCM1480_DUART_IMRREG(line) 63 #define R_DUART_INCHREG(line) R_BCM1480_DUART_INCHREG(line) 64 #define R_DUART_ISRREG(line) R_BCM1480_DUART_ISRREG(line) 65 66 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) 67 #include <asm/sibyte/sb1250_regs.h> 68 #include <asm/sibyte/sb1250_int.h> 69 70 #define SBD_CHANREGS(line) A_DUART_CHANREG((line), 0) 71 #define SBD_CTRLREGS(line) A_DUART_CTRLREG(0) 72 #define SBD_INT(line) (K_INT_UART_0 + (line)) 73 74 #else 75 #error invalid SB1250 UART configuration 76 77 #endif 78 79 80 MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>"); 81 MODULE_DESCRIPTION("BCM1xxx on-chip DUART serial driver"); 82 MODULE_LICENSE("GPL"); 83 84 85 #define DUART_MAX_CHIP 2 86 #define DUART_MAX_SIDE 2 87 88 /* 89 * Per-port state. 90 */ 91 struct sbd_port { 92 struct sbd_duart *duart; 93 struct uart_port port; 94 unsigned char __iomem *memctrl; 95 int tx_stopped; 96 int initialised; 97 }; 98 99 /* 100 * Per-DUART state for the shared register space. 101 */ 102 struct sbd_duart { 103 struct sbd_port sport[2]; 104 unsigned long mapctrl; 105 atomic_t map_guard; 106 }; 107 108 #define to_sport(uport) container_of(uport, struct sbd_port, port) 109 110 static struct sbd_duart sbd_duarts[DUART_MAX_CHIP]; 111 112 113 /* 114 * Reading and writing SB1250 DUART registers. 115 * 116 * There are three register spaces: two per-channel ones and 117 * a shared one. We have to define accessors appropriately. 118 * All registers are 64-bit and all but the Baud Rate Clock 119 * registers only define 8 least significant bits. There is 120 * also a workaround to take into account. Raw accessors use 121 * the full register width, but cooked ones truncate it 122 * intentionally so that the rest of the driver does not care. 123 */ 124 static u64 __read_sbdchn(struct sbd_port *sport, int reg) 125 { 126 void __iomem *csr = sport->port.membase + reg; 127 128 return __raw_readq(csr); 129 } 130 131 static u64 __read_sbdshr(struct sbd_port *sport, int reg) 132 { 133 void __iomem *csr = sport->memctrl + reg; 134 135 return __raw_readq(csr); 136 } 137 138 static void __write_sbdchn(struct sbd_port *sport, int reg, u64 value) 139 { 140 void __iomem *csr = sport->port.membase + reg; 141 142 __raw_writeq(value, csr); 143 } 144 145 static void __write_sbdshr(struct sbd_port *sport, int reg, u64 value) 146 { 147 void __iomem *csr = sport->memctrl + reg; 148 149 __raw_writeq(value, csr); 150 } 151 152 /* 153 * In bug 1956, we get glitches that can mess up uart registers. This 154 * "read-mode-reg after any register access" is an accepted workaround. 155 */ 156 static void __war_sbd1956(struct sbd_port *sport) 157 { 158 __read_sbdchn(sport, R_DUART_MODE_REG_1); 159 __read_sbdchn(sport, R_DUART_MODE_REG_2); 160 } 161 162 static unsigned char read_sbdchn(struct sbd_port *sport, int reg) 163 { 164 unsigned char retval; 165 166 retval = __read_sbdchn(sport, reg); 167 if (SIBYTE_1956_WAR) 168 __war_sbd1956(sport); 169 return retval; 170 } 171 172 static unsigned char read_sbdshr(struct sbd_port *sport, int reg) 173 { 174 unsigned char retval; 175 176 retval = __read_sbdshr(sport, reg); 177 if (SIBYTE_1956_WAR) 178 __war_sbd1956(sport); 179 return retval; 180 } 181 182 static void write_sbdchn(struct sbd_port *sport, int reg, unsigned int value) 183 { 184 __write_sbdchn(sport, reg, value); 185 if (SIBYTE_1956_WAR) 186 __war_sbd1956(sport); 187 } 188 189 static void write_sbdshr(struct sbd_port *sport, int reg, unsigned int value) 190 { 191 __write_sbdshr(sport, reg, value); 192 if (SIBYTE_1956_WAR) 193 __war_sbd1956(sport); 194 } 195 196 197 static int sbd_receive_ready(struct sbd_port *sport) 198 { 199 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_RX_RDY; 200 } 201 202 static int sbd_receive_drain(struct sbd_port *sport) 203 { 204 int loops = 10000; 205 206 while (sbd_receive_ready(sport) && --loops) 207 read_sbdchn(sport, R_DUART_RX_HOLD); 208 return loops; 209 } 210 211 static int __maybe_unused sbd_transmit_ready(struct sbd_port *sport) 212 { 213 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_RDY; 214 } 215 216 static int __maybe_unused sbd_transmit_drain(struct sbd_port *sport) 217 { 218 int loops = 10000; 219 220 while (!sbd_transmit_ready(sport) && --loops) 221 udelay(2); 222 return loops; 223 } 224 225 static int sbd_transmit_empty(struct sbd_port *sport) 226 { 227 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_EMT; 228 } 229 230 static int sbd_line_drain(struct sbd_port *sport) 231 { 232 int loops = 10000; 233 234 while (!sbd_transmit_empty(sport) && --loops) 235 udelay(2); 236 return loops; 237 } 238 239 240 static unsigned int sbd_tx_empty(struct uart_port *uport) 241 { 242 struct sbd_port *sport = to_sport(uport); 243 244 return sbd_transmit_empty(sport) ? TIOCSER_TEMT : 0; 245 } 246 247 static unsigned int sbd_get_mctrl(struct uart_port *uport) 248 { 249 struct sbd_port *sport = to_sport(uport); 250 unsigned int mctrl, status; 251 252 status = read_sbdshr(sport, R_DUART_IN_PORT); 253 status >>= (uport->line) % 2; 254 mctrl = (!(status & M_DUART_IN_PIN0_VAL) ? TIOCM_CTS : 0) | 255 (!(status & M_DUART_IN_PIN4_VAL) ? TIOCM_CAR : 0) | 256 (!(status & M_DUART_RIN0_PIN) ? TIOCM_RNG : 0) | 257 (!(status & M_DUART_IN_PIN2_VAL) ? TIOCM_DSR : 0); 258 return mctrl; 259 } 260 261 static void sbd_set_mctrl(struct uart_port *uport, unsigned int mctrl) 262 { 263 struct sbd_port *sport = to_sport(uport); 264 unsigned int clr = 0, set = 0, mode2; 265 266 if (mctrl & TIOCM_DTR) 267 set |= M_DUART_SET_OPR2; 268 else 269 clr |= M_DUART_CLR_OPR2; 270 if (mctrl & TIOCM_RTS) 271 set |= M_DUART_SET_OPR0; 272 else 273 clr |= M_DUART_CLR_OPR0; 274 clr <<= (uport->line) % 2; 275 set <<= (uport->line) % 2; 276 277 mode2 = read_sbdchn(sport, R_DUART_MODE_REG_2); 278 mode2 &= ~M_DUART_CHAN_MODE; 279 if (mctrl & TIOCM_LOOP) 280 mode2 |= V_DUART_CHAN_MODE_LCL_LOOP; 281 else 282 mode2 |= V_DUART_CHAN_MODE_NORMAL; 283 284 write_sbdshr(sport, R_DUART_CLEAR_OPR, clr); 285 write_sbdshr(sport, R_DUART_SET_OPR, set); 286 write_sbdchn(sport, R_DUART_MODE_REG_2, mode2); 287 } 288 289 static void sbd_stop_tx(struct uart_port *uport) 290 { 291 struct sbd_port *sport = to_sport(uport); 292 293 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS); 294 sport->tx_stopped = 1; 295 }; 296 297 static void sbd_start_tx(struct uart_port *uport) 298 { 299 struct sbd_port *sport = to_sport(uport); 300 unsigned int mask; 301 302 /* Enable tx interrupts. */ 303 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2)); 304 mask |= M_DUART_IMR_TX; 305 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask); 306 307 /* Go!, go!, go!... */ 308 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN); 309 sport->tx_stopped = 0; 310 }; 311 312 static void sbd_stop_rx(struct uart_port *uport) 313 { 314 struct sbd_port *sport = to_sport(uport); 315 316 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0); 317 }; 318 319 static void sbd_enable_ms(struct uart_port *uport) 320 { 321 struct sbd_port *sport = to_sport(uport); 322 323 write_sbdchn(sport, R_DUART_AUXCTL_X, 324 M_DUART_CIN_CHNG_ENA | M_DUART_CTS_CHNG_ENA); 325 } 326 327 static void sbd_break_ctl(struct uart_port *uport, int break_state) 328 { 329 struct sbd_port *sport = to_sport(uport); 330 331 if (break_state == -1) 332 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_START_BREAK); 333 else 334 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_STOP_BREAK); 335 } 336 337 338 static void sbd_receive_chars(struct sbd_port *sport) 339 { 340 struct uart_port *uport = &sport->port; 341 struct uart_icount *icount; 342 unsigned int status, ch, flag; 343 int count; 344 345 for (count = 16; count; count--) { 346 status = read_sbdchn(sport, R_DUART_STATUS); 347 if (!(status & M_DUART_RX_RDY)) 348 break; 349 350 ch = read_sbdchn(sport, R_DUART_RX_HOLD); 351 352 flag = TTY_NORMAL; 353 354 icount = &uport->icount; 355 icount->rx++; 356 357 if (unlikely(status & 358 (M_DUART_RCVD_BRK | M_DUART_FRM_ERR | 359 M_DUART_PARITY_ERR | M_DUART_OVRUN_ERR))) { 360 if (status & M_DUART_RCVD_BRK) { 361 icount->brk++; 362 if (uart_handle_break(uport)) 363 continue; 364 } else if (status & M_DUART_FRM_ERR) 365 icount->frame++; 366 else if (status & M_DUART_PARITY_ERR) 367 icount->parity++; 368 if (status & M_DUART_OVRUN_ERR) 369 icount->overrun++; 370 371 status &= uport->read_status_mask; 372 if (status & M_DUART_RCVD_BRK) 373 flag = TTY_BREAK; 374 else if (status & M_DUART_FRM_ERR) 375 flag = TTY_FRAME; 376 else if (status & M_DUART_PARITY_ERR) 377 flag = TTY_PARITY; 378 } 379 380 if (uart_handle_sysrq_char(uport, ch)) 381 continue; 382 383 uart_insert_char(uport, status, M_DUART_OVRUN_ERR, ch, flag); 384 } 385 386 tty_flip_buffer_push(uport->state->port.tty); 387 } 388 389 static void sbd_transmit_chars(struct sbd_port *sport) 390 { 391 struct uart_port *uport = &sport->port; 392 struct circ_buf *xmit = &sport->port.state->xmit; 393 unsigned int mask; 394 int stop_tx; 395 396 /* XON/XOFF chars. */ 397 if (sport->port.x_char) { 398 write_sbdchn(sport, R_DUART_TX_HOLD, sport->port.x_char); 399 sport->port.icount.tx++; 400 sport->port.x_char = 0; 401 return; 402 } 403 404 /* If nothing to do or stopped or hardware stopped. */ 405 stop_tx = (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)); 406 407 /* Send char. */ 408 if (!stop_tx) { 409 write_sbdchn(sport, R_DUART_TX_HOLD, xmit->buf[xmit->tail]); 410 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 411 sport->port.icount.tx++; 412 413 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 414 uart_write_wakeup(&sport->port); 415 } 416 417 /* Are we are done? */ 418 if (stop_tx || uart_circ_empty(xmit)) { 419 /* Disable tx interrupts. */ 420 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2)); 421 mask &= ~M_DUART_IMR_TX; 422 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask); 423 } 424 } 425 426 static void sbd_status_handle(struct sbd_port *sport) 427 { 428 struct uart_port *uport = &sport->port; 429 unsigned int delta; 430 431 delta = read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2)); 432 delta >>= (uport->line) % 2; 433 434 if (delta & (M_DUART_IN_PIN0_VAL << S_DUART_IN_PIN_CHNG)) 435 uart_handle_cts_change(uport, !(delta & M_DUART_IN_PIN0_VAL)); 436 437 if (delta & (M_DUART_IN_PIN2_VAL << S_DUART_IN_PIN_CHNG)) 438 uport->icount.dsr++; 439 440 if (delta & ((M_DUART_IN_PIN2_VAL | M_DUART_IN_PIN0_VAL) << 441 S_DUART_IN_PIN_CHNG)) 442 wake_up_interruptible(&uport->state->port.delta_msr_wait); 443 } 444 445 static irqreturn_t sbd_interrupt(int irq, void *dev_id) 446 { 447 struct sbd_port *sport = dev_id; 448 struct uart_port *uport = &sport->port; 449 irqreturn_t status = IRQ_NONE; 450 unsigned int intstat; 451 int count; 452 453 for (count = 16; count; count--) { 454 intstat = read_sbdshr(sport, 455 R_DUART_ISRREG((uport->line) % 2)); 456 intstat &= read_sbdshr(sport, 457 R_DUART_IMRREG((uport->line) % 2)); 458 intstat &= M_DUART_ISR_ALL; 459 if (!intstat) 460 break; 461 462 if (intstat & M_DUART_ISR_RX) 463 sbd_receive_chars(sport); 464 if (intstat & M_DUART_ISR_IN) 465 sbd_status_handle(sport); 466 if (intstat & M_DUART_ISR_TX) 467 sbd_transmit_chars(sport); 468 469 status = IRQ_HANDLED; 470 } 471 472 return status; 473 } 474 475 476 static int sbd_startup(struct uart_port *uport) 477 { 478 struct sbd_port *sport = to_sport(uport); 479 unsigned int mode1; 480 int ret; 481 482 ret = request_irq(sport->port.irq, sbd_interrupt, 483 IRQF_SHARED, "sb1250-duart", sport); 484 if (ret) 485 return ret; 486 487 /* Clear the receive FIFO. */ 488 sbd_receive_drain(sport); 489 490 /* Clear the interrupt registers. */ 491 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT); 492 read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2)); 493 494 /* Set rx/tx interrupt to FIFO available. */ 495 mode1 = read_sbdchn(sport, R_DUART_MODE_REG_1); 496 mode1 &= ~(M_DUART_RX_IRQ_SEL_RXFULL | M_DUART_TX_IRQ_SEL_TXEMPT); 497 write_sbdchn(sport, R_DUART_MODE_REG_1, mode1); 498 499 /* Disable tx, enable rx. */ 500 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_EN); 501 sport->tx_stopped = 1; 502 503 /* Enable interrupts. */ 504 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 505 M_DUART_IMR_IN | M_DUART_IMR_RX); 506 507 return 0; 508 } 509 510 static void sbd_shutdown(struct uart_port *uport) 511 { 512 struct sbd_port *sport = to_sport(uport); 513 514 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS); 515 sport->tx_stopped = 1; 516 free_irq(sport->port.irq, sport); 517 } 518 519 520 static void sbd_init_port(struct sbd_port *sport) 521 { 522 struct uart_port *uport = &sport->port; 523 524 if (sport->initialised) 525 return; 526 527 /* There is no DUART reset feature, so just set some sane defaults. */ 528 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_TX); 529 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_RX); 530 write_sbdchn(sport, R_DUART_MODE_REG_1, V_DUART_BITS_PER_CHAR_8); 531 write_sbdchn(sport, R_DUART_MODE_REG_2, 0); 532 write_sbdchn(sport, R_DUART_FULL_CTL, 533 V_DUART_INT_TIME(0) | V_DUART_SIG_FULL(15)); 534 write_sbdchn(sport, R_DUART_OPCR_X, 0); 535 write_sbdchn(sport, R_DUART_AUXCTL_X, 0); 536 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0); 537 538 sport->initialised = 1; 539 } 540 541 static void sbd_set_termios(struct uart_port *uport, struct ktermios *termios, 542 struct ktermios *old_termios) 543 { 544 struct sbd_port *sport = to_sport(uport); 545 unsigned int mode1 = 0, mode2 = 0, aux = 0; 546 unsigned int mode1mask = 0, mode2mask = 0, auxmask = 0; 547 unsigned int oldmode1, oldmode2, oldaux; 548 unsigned int baud, brg; 549 unsigned int command; 550 551 mode1mask |= ~(M_DUART_PARITY_MODE | M_DUART_PARITY_TYPE_ODD | 552 M_DUART_BITS_PER_CHAR); 553 mode2mask |= ~M_DUART_STOP_BIT_LEN_2; 554 auxmask |= ~M_DUART_CTS_CHNG_ENA; 555 556 /* Byte size. */ 557 switch (termios->c_cflag & CSIZE) { 558 case CS5: 559 case CS6: 560 /* Unsupported, leave unchanged. */ 561 mode1mask |= M_DUART_PARITY_MODE; 562 break; 563 case CS7: 564 mode1 |= V_DUART_BITS_PER_CHAR_7; 565 break; 566 case CS8: 567 default: 568 mode1 |= V_DUART_BITS_PER_CHAR_8; 569 break; 570 } 571 572 /* Parity and stop bits. */ 573 if (termios->c_cflag & CSTOPB) 574 mode2 |= M_DUART_STOP_BIT_LEN_2; 575 else 576 mode2 |= M_DUART_STOP_BIT_LEN_1; 577 if (termios->c_cflag & PARENB) 578 mode1 |= V_DUART_PARITY_MODE_ADD; 579 else 580 mode1 |= V_DUART_PARITY_MODE_NONE; 581 if (termios->c_cflag & PARODD) 582 mode1 |= M_DUART_PARITY_TYPE_ODD; 583 else 584 mode1 |= M_DUART_PARITY_TYPE_EVEN; 585 586 baud = uart_get_baud_rate(uport, termios, old_termios, 1200, 5000000); 587 brg = V_DUART_BAUD_RATE(baud); 588 /* The actual lower bound is 1221bps, so compensate. */ 589 if (brg > M_DUART_CLK_COUNTER) 590 brg = M_DUART_CLK_COUNTER; 591 592 uart_update_timeout(uport, termios->c_cflag, baud); 593 594 uport->read_status_mask = M_DUART_OVRUN_ERR; 595 if (termios->c_iflag & INPCK) 596 uport->read_status_mask |= M_DUART_FRM_ERR | 597 M_DUART_PARITY_ERR; 598 if (termios->c_iflag & (BRKINT | PARMRK)) 599 uport->read_status_mask |= M_DUART_RCVD_BRK; 600 601 uport->ignore_status_mask = 0; 602 if (termios->c_iflag & IGNPAR) 603 uport->ignore_status_mask |= M_DUART_FRM_ERR | 604 M_DUART_PARITY_ERR; 605 if (termios->c_iflag & IGNBRK) { 606 uport->ignore_status_mask |= M_DUART_RCVD_BRK; 607 if (termios->c_iflag & IGNPAR) 608 uport->ignore_status_mask |= M_DUART_OVRUN_ERR; 609 } 610 611 if (termios->c_cflag & CREAD) 612 command = M_DUART_RX_EN; 613 else 614 command = M_DUART_RX_DIS; 615 616 if (termios->c_cflag & CRTSCTS) 617 aux |= M_DUART_CTS_CHNG_ENA; 618 else 619 aux &= ~M_DUART_CTS_CHNG_ENA; 620 621 spin_lock(&uport->lock); 622 623 if (sport->tx_stopped) 624 command |= M_DUART_TX_DIS; 625 else 626 command |= M_DUART_TX_EN; 627 628 oldmode1 = read_sbdchn(sport, R_DUART_MODE_REG_1) & mode1mask; 629 oldmode2 = read_sbdchn(sport, R_DUART_MODE_REG_2) & mode2mask; 630 oldaux = read_sbdchn(sport, R_DUART_AUXCTL_X) & auxmask; 631 632 if (!sport->tx_stopped) 633 sbd_line_drain(sport); 634 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS); 635 636 write_sbdchn(sport, R_DUART_MODE_REG_1, mode1 | oldmode1); 637 write_sbdchn(sport, R_DUART_MODE_REG_2, mode2 | oldmode2); 638 write_sbdchn(sport, R_DUART_CLK_SEL, brg); 639 write_sbdchn(sport, R_DUART_AUXCTL_X, aux | oldaux); 640 641 write_sbdchn(sport, R_DUART_CMD, command); 642 643 spin_unlock(&uport->lock); 644 } 645 646 647 static const char *sbd_type(struct uart_port *uport) 648 { 649 return "SB1250 DUART"; 650 } 651 652 static void sbd_release_port(struct uart_port *uport) 653 { 654 struct sbd_port *sport = to_sport(uport); 655 struct sbd_duart *duart = sport->duart; 656 int map_guard; 657 658 iounmap(sport->memctrl); 659 sport->memctrl = NULL; 660 iounmap(uport->membase); 661 uport->membase = NULL; 662 663 map_guard = atomic_add_return(-1, &duart->map_guard); 664 if (!map_guard) 665 release_mem_region(duart->mapctrl, DUART_CHANREG_SPACING); 666 release_mem_region(uport->mapbase, DUART_CHANREG_SPACING); 667 } 668 669 static int sbd_map_port(struct uart_port *uport) 670 { 671 const char *err = KERN_ERR "sbd: Cannot map MMIO\n"; 672 struct sbd_port *sport = to_sport(uport); 673 struct sbd_duart *duart = sport->duart; 674 675 if (!uport->membase) 676 uport->membase = ioremap_nocache(uport->mapbase, 677 DUART_CHANREG_SPACING); 678 if (!uport->membase) { 679 printk(err); 680 return -ENOMEM; 681 } 682 683 if (!sport->memctrl) 684 sport->memctrl = ioremap_nocache(duart->mapctrl, 685 DUART_CHANREG_SPACING); 686 if (!sport->memctrl) { 687 printk(err); 688 iounmap(uport->membase); 689 uport->membase = NULL; 690 return -ENOMEM; 691 } 692 693 return 0; 694 } 695 696 static int sbd_request_port(struct uart_port *uport) 697 { 698 const char *err = KERN_ERR "sbd: Unable to reserve MMIO resource\n"; 699 struct sbd_duart *duart = to_sport(uport)->duart; 700 int map_guard; 701 int ret = 0; 702 703 if (!request_mem_region(uport->mapbase, DUART_CHANREG_SPACING, 704 "sb1250-duart")) { 705 printk(err); 706 return -EBUSY; 707 } 708 map_guard = atomic_add_return(1, &duart->map_guard); 709 if (map_guard == 1) { 710 if (!request_mem_region(duart->mapctrl, DUART_CHANREG_SPACING, 711 "sb1250-duart")) { 712 atomic_add(-1, &duart->map_guard); 713 printk(err); 714 ret = -EBUSY; 715 } 716 } 717 if (!ret) { 718 ret = sbd_map_port(uport); 719 if (ret) { 720 map_guard = atomic_add_return(-1, &duart->map_guard); 721 if (!map_guard) 722 release_mem_region(duart->mapctrl, 723 DUART_CHANREG_SPACING); 724 } 725 } 726 if (ret) { 727 release_mem_region(uport->mapbase, DUART_CHANREG_SPACING); 728 return ret; 729 } 730 return 0; 731 } 732 733 static void sbd_config_port(struct uart_port *uport, int flags) 734 { 735 struct sbd_port *sport = to_sport(uport); 736 737 if (flags & UART_CONFIG_TYPE) { 738 if (sbd_request_port(uport)) 739 return; 740 741 uport->type = PORT_SB1250_DUART; 742 743 sbd_init_port(sport); 744 } 745 } 746 747 static int sbd_verify_port(struct uart_port *uport, struct serial_struct *ser) 748 { 749 int ret = 0; 750 751 if (ser->type != PORT_UNKNOWN && ser->type != PORT_SB1250_DUART) 752 ret = -EINVAL; 753 if (ser->irq != uport->irq) 754 ret = -EINVAL; 755 if (ser->baud_base != uport->uartclk / 16) 756 ret = -EINVAL; 757 return ret; 758 } 759 760 761 static const struct uart_ops sbd_ops = { 762 .tx_empty = sbd_tx_empty, 763 .set_mctrl = sbd_set_mctrl, 764 .get_mctrl = sbd_get_mctrl, 765 .stop_tx = sbd_stop_tx, 766 .start_tx = sbd_start_tx, 767 .stop_rx = sbd_stop_rx, 768 .enable_ms = sbd_enable_ms, 769 .break_ctl = sbd_break_ctl, 770 .startup = sbd_startup, 771 .shutdown = sbd_shutdown, 772 .set_termios = sbd_set_termios, 773 .type = sbd_type, 774 .release_port = sbd_release_port, 775 .request_port = sbd_request_port, 776 .config_port = sbd_config_port, 777 .verify_port = sbd_verify_port, 778 }; 779 780 /* Initialize SB1250 DUART port structures. */ 781 static void __init sbd_probe_duarts(void) 782 { 783 static int probed; 784 int chip, side; 785 int max_lines, line; 786 787 if (probed) 788 return; 789 790 /* Set the number of available units based on the SOC type. */ 791 switch (soc_type) { 792 case K_SYS_SOC_TYPE_BCM1x55: 793 case K_SYS_SOC_TYPE_BCM1x80: 794 max_lines = 4; 795 break; 796 default: 797 /* Assume at least two serial ports at the normal address. */ 798 max_lines = 2; 799 break; 800 } 801 802 probed = 1; 803 804 for (chip = 0, line = 0; chip < DUART_MAX_CHIP && line < max_lines; 805 chip++) { 806 sbd_duarts[chip].mapctrl = SBD_CTRLREGS(line); 807 808 for (side = 0; side < DUART_MAX_SIDE && line < max_lines; 809 side++, line++) { 810 struct sbd_port *sport = &sbd_duarts[chip].sport[side]; 811 struct uart_port *uport = &sport->port; 812 813 sport->duart = &sbd_duarts[chip]; 814 815 uport->irq = SBD_INT(line); 816 uport->uartclk = 100000000 / 20 * 16; 817 uport->fifosize = 16; 818 uport->iotype = UPIO_MEM; 819 uport->flags = UPF_BOOT_AUTOCONF; 820 uport->ops = &sbd_ops; 821 uport->line = line; 822 uport->mapbase = SBD_CHANREGS(line); 823 } 824 } 825 } 826 827 828 #ifdef CONFIG_SERIAL_SB1250_DUART_CONSOLE 829 /* 830 * Serial console stuff. Very basic, polling driver for doing serial 831 * console output. The console_lock is held by the caller, so we 832 * shouldn't be interrupted for more console activity. 833 */ 834 static void sbd_console_putchar(struct uart_port *uport, int ch) 835 { 836 struct sbd_port *sport = to_sport(uport); 837 838 sbd_transmit_drain(sport); 839 write_sbdchn(sport, R_DUART_TX_HOLD, ch); 840 } 841 842 static void sbd_console_write(struct console *co, const char *s, 843 unsigned int count) 844 { 845 int chip = co->index / DUART_MAX_SIDE; 846 int side = co->index % DUART_MAX_SIDE; 847 struct sbd_port *sport = &sbd_duarts[chip].sport[side]; 848 struct uart_port *uport = &sport->port; 849 unsigned long flags; 850 unsigned int mask; 851 852 /* Disable transmit interrupts and enable the transmitter. */ 853 spin_lock_irqsave(&uport->lock, flags); 854 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2)); 855 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 856 mask & ~M_DUART_IMR_TX); 857 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN); 858 spin_unlock_irqrestore(&uport->lock, flags); 859 860 uart_console_write(&sport->port, s, count, sbd_console_putchar); 861 862 /* Restore transmit interrupts and the transmitter enable. */ 863 spin_lock_irqsave(&uport->lock, flags); 864 sbd_line_drain(sport); 865 if (sport->tx_stopped) 866 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS); 867 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask); 868 spin_unlock_irqrestore(&uport->lock, flags); 869 } 870 871 static int __init sbd_console_setup(struct console *co, char *options) 872 { 873 int chip = co->index / DUART_MAX_SIDE; 874 int side = co->index % DUART_MAX_SIDE; 875 struct sbd_port *sport = &sbd_duarts[chip].sport[side]; 876 struct uart_port *uport = &sport->port; 877 int baud = 115200; 878 int bits = 8; 879 int parity = 'n'; 880 int flow = 'n'; 881 int ret; 882 883 if (!sport->duart) 884 return -ENXIO; 885 886 ret = sbd_map_port(uport); 887 if (ret) 888 return ret; 889 890 sbd_init_port(sport); 891 892 if (options) 893 uart_parse_options(options, &baud, &parity, &bits, &flow); 894 return uart_set_options(uport, co, baud, parity, bits, flow); 895 } 896 897 static struct uart_driver sbd_reg; 898 static struct console sbd_console = { 899 .name = "duart", 900 .write = sbd_console_write, 901 .device = uart_console_device, 902 .setup = sbd_console_setup, 903 .flags = CON_PRINTBUFFER, 904 .index = -1, 905 .data = &sbd_reg 906 }; 907 908 static int __init sbd_serial_console_init(void) 909 { 910 sbd_probe_duarts(); 911 register_console(&sbd_console); 912 913 return 0; 914 } 915 916 console_initcall(sbd_serial_console_init); 917 918 #define SERIAL_SB1250_DUART_CONSOLE &sbd_console 919 #else 920 #define SERIAL_SB1250_DUART_CONSOLE NULL 921 #endif /* CONFIG_SERIAL_SB1250_DUART_CONSOLE */ 922 923 924 static struct uart_driver sbd_reg = { 925 .owner = THIS_MODULE, 926 .driver_name = "sb1250_duart", 927 .dev_name = "duart", 928 .major = TTY_MAJOR, 929 .minor = SB1250_DUART_MINOR_BASE, 930 .nr = DUART_MAX_CHIP * DUART_MAX_SIDE, 931 .cons = SERIAL_SB1250_DUART_CONSOLE, 932 }; 933 934 /* Set up the driver and register it. */ 935 static int __init sbd_init(void) 936 { 937 int i, ret; 938 939 sbd_probe_duarts(); 940 941 ret = uart_register_driver(&sbd_reg); 942 if (ret) 943 return ret; 944 945 for (i = 0; i < DUART_MAX_CHIP * DUART_MAX_SIDE; i++) { 946 struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE]; 947 struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE]; 948 struct uart_port *uport = &sport->port; 949 950 if (sport->duart) 951 uart_add_one_port(&sbd_reg, uport); 952 } 953 954 return 0; 955 } 956 957 /* Unload the driver. Unregister stuff, get ready to go away. */ 958 static void __exit sbd_exit(void) 959 { 960 int i; 961 962 for (i = DUART_MAX_CHIP * DUART_MAX_SIDE - 1; i >= 0; i--) { 963 struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE]; 964 struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE]; 965 struct uart_port *uport = &sport->port; 966 967 if (sport->duart) 968 uart_remove_one_port(&sbd_reg, uport); 969 } 970 971 uart_unregister_driver(&sbd_reg); 972 } 973 974 module_init(sbd_init); 975 module_exit(sbd_exit); 976