1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver core for Samsung SoC onboard UARTs. 4 * 5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics 6 * http://armlinux.simtec.co.uk/ 7 */ 8 9 /* Note on 2410 error handling 10 * 11 * The s3c2410 manual has a love/hate affair with the contents of the 12 * UERSTAT register in the UART blocks, and keeps marking some of the 13 * error bits as reserved. Having checked with the s3c2410x01, 14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED 15 * feature from the latter versions of the manual. 16 * 17 * If it becomes aparrent that latter versions of the 2410 remove these 18 * bits, then action will have to be taken to differentiate the versions 19 * and change the policy on BREAK 20 * 21 * BJD, 04-Nov-2004 22 */ 23 24 #include <linux/console.h> 25 #include <linux/clk.h> 26 #include <linux/cpufreq.h> 27 #include <linux/delay.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/dmaengine.h> 30 #include <linux/init.h> 31 #include <linux/io.h> 32 #include <linux/ioport.h> 33 #include <linux/math.h> 34 #include <linux/module.h> 35 #include <linux/of.h> 36 #include <linux/platform_device.h> 37 #include <linux/serial.h> 38 #include <linux/serial_core.h> 39 #include <linux/serial_s3c.h> 40 #include <linux/slab.h> 41 #include <linux/sysrq.h> 42 #include <linux/tty.h> 43 #include <linux/tty_flip.h> 44 #include <linux/types.h> 45 46 #include <asm/irq.h> 47 48 /* UART name and device definitions */ 49 50 #define S3C24XX_SERIAL_NAME "ttySAC" 51 #define S3C24XX_SERIAL_MAJOR 204 52 #define S3C24XX_SERIAL_MINOR 64 53 54 #ifdef CONFIG_ARM64 55 #define UART_NR 12 56 #else 57 #define UART_NR CONFIG_SERIAL_SAMSUNG_UARTS 58 #endif 59 60 #define S3C24XX_TX_PIO 1 61 #define S3C24XX_TX_DMA 2 62 #define S3C24XX_RX_PIO 1 63 #define S3C24XX_RX_DMA 2 64 65 /* flag to ignore all characters coming in */ 66 #define RXSTAT_DUMMY_READ (0x10000000) 67 68 enum s3c24xx_port_type { 69 TYPE_S3C6400, 70 TYPE_APPLE_S5L, 71 }; 72 73 struct s3c24xx_uart_info { 74 const char *name; 75 enum s3c24xx_port_type type; 76 unsigned int port_type; 77 unsigned int fifosize; 78 u32 rx_fifomask; 79 u32 rx_fifoshift; 80 u32 rx_fifofull; 81 u32 tx_fifomask; 82 u32 tx_fifoshift; 83 u32 tx_fifofull; 84 u32 clksel_mask; 85 u32 clksel_shift; 86 u32 ucon_mask; 87 u8 def_clk_sel; 88 u8 num_clks; 89 u8 iotype; 90 91 /* uart port features */ 92 bool has_divslot; 93 }; 94 95 struct s3c24xx_serial_drv_data { 96 const struct s3c24xx_uart_info info; 97 const struct s3c2410_uartcfg def_cfg; 98 const unsigned int fifosize[UART_NR]; 99 }; 100 101 struct s3c24xx_uart_dma { 102 unsigned int rx_chan_id; 103 unsigned int tx_chan_id; 104 105 struct dma_slave_config rx_conf; 106 struct dma_slave_config tx_conf; 107 108 struct dma_chan *rx_chan; 109 struct dma_chan *tx_chan; 110 111 dma_addr_t rx_addr; 112 dma_addr_t tx_addr; 113 114 dma_cookie_t rx_cookie; 115 dma_cookie_t tx_cookie; 116 117 char *rx_buf; 118 119 dma_addr_t tx_transfer_addr; 120 121 size_t rx_size; 122 size_t tx_size; 123 124 struct dma_async_tx_descriptor *tx_desc; 125 struct dma_async_tx_descriptor *rx_desc; 126 127 int tx_bytes_requested; 128 int rx_bytes_requested; 129 }; 130 131 struct s3c24xx_uart_port { 132 unsigned char rx_enabled; 133 unsigned char tx_enabled; 134 unsigned int pm_level; 135 unsigned long baudclk_rate; 136 unsigned int min_dma_size; 137 138 unsigned int rx_irq; 139 unsigned int tx_irq; 140 141 unsigned int tx_in_progress; 142 unsigned int tx_mode; 143 unsigned int rx_mode; 144 145 const struct s3c24xx_uart_info *info; 146 struct clk *clk; 147 struct clk *baudclk; 148 struct uart_port port; 149 const struct s3c24xx_serial_drv_data *drv_data; 150 151 /* reference to platform data */ 152 const struct s3c2410_uartcfg *cfg; 153 154 struct s3c24xx_uart_dma *dma; 155 }; 156 157 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport); 158 159 /* conversion functions */ 160 161 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev) 162 163 /* register access controls */ 164 165 #define portaddr(port, reg) ((port)->membase + (reg)) 166 #define portaddrl(port, reg) \ 167 ((unsigned long *)(unsigned long)((port)->membase + (reg))) 168 169 static u32 rd_reg(const struct uart_port *port, u32 reg) 170 { 171 switch (port->iotype) { 172 case UPIO_MEM: 173 return readb_relaxed(portaddr(port, reg)); 174 case UPIO_MEM32: 175 return readl_relaxed(portaddr(port, reg)); 176 default: 177 return 0; 178 } 179 return 0; 180 } 181 182 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg))) 183 184 static void wr_reg(const struct uart_port *port, u32 reg, u32 val) 185 { 186 switch (port->iotype) { 187 case UPIO_MEM: 188 writeb_relaxed(val, portaddr(port, reg)); 189 break; 190 case UPIO_MEM32: 191 writel_relaxed(val, portaddr(port, reg)); 192 break; 193 } 194 } 195 196 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg)) 197 198 /* Byte-order aware bit setting/clearing functions. */ 199 200 static inline void s3c24xx_set_bit(const struct uart_port *port, int idx, 201 u32 reg) 202 { 203 unsigned long flags; 204 u32 val; 205 206 local_irq_save(flags); 207 val = rd_regl(port, reg); 208 val |= (1 << idx); 209 wr_regl(port, reg, val); 210 local_irq_restore(flags); 211 } 212 213 static inline void s3c24xx_clear_bit(const struct uart_port *port, int idx, 214 u32 reg) 215 { 216 unsigned long flags; 217 u32 val; 218 219 local_irq_save(flags); 220 val = rd_regl(port, reg); 221 val &= ~(1 << idx); 222 wr_regl(port, reg, val); 223 local_irq_restore(flags); 224 } 225 226 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port) 227 { 228 return container_of(port, struct s3c24xx_uart_port, port); 229 } 230 231 /* translate a port to the device name */ 232 233 static inline const char *s3c24xx_serial_portname(const struct uart_port *port) 234 { 235 return to_platform_device(port->dev)->name; 236 } 237 238 static bool s3c24xx_serial_txempty_nofifo(const struct uart_port *port) 239 { 240 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE; 241 } 242 243 static void s3c24xx_serial_rx_enable(struct uart_port *port) 244 { 245 struct s3c24xx_uart_port *ourport = to_ourport(port); 246 unsigned long flags; 247 int count = 10000; 248 u32 ucon, ufcon; 249 250 uart_port_lock_irqsave(port, &flags); 251 252 while (--count && !s3c24xx_serial_txempty_nofifo(port)) 253 udelay(100); 254 255 ufcon = rd_regl(port, S3C2410_UFCON); 256 ufcon |= S3C2410_UFCON_RESETRX; 257 wr_regl(port, S3C2410_UFCON, ufcon); 258 259 ucon = rd_regl(port, S3C2410_UCON); 260 ucon |= S3C2410_UCON_RXIRQMODE; 261 wr_regl(port, S3C2410_UCON, ucon); 262 263 ourport->rx_enabled = 1; 264 uart_port_unlock_irqrestore(port, flags); 265 } 266 267 static void s3c24xx_serial_rx_disable(struct uart_port *port) 268 { 269 struct s3c24xx_uart_port *ourport = to_ourport(port); 270 unsigned long flags; 271 u32 ucon; 272 273 uart_port_lock_irqsave(port, &flags); 274 275 ucon = rd_regl(port, S3C2410_UCON); 276 ucon &= ~S3C2410_UCON_RXIRQMODE; 277 wr_regl(port, S3C2410_UCON, ucon); 278 279 ourport->rx_enabled = 0; 280 uart_port_unlock_irqrestore(port, flags); 281 } 282 283 static void s3c24xx_serial_stop_tx(struct uart_port *port) 284 { 285 struct s3c24xx_uart_port *ourport = to_ourport(port); 286 struct s3c24xx_uart_dma *dma = ourport->dma; 287 struct dma_tx_state state; 288 int count; 289 290 if (!ourport->tx_enabled) 291 return; 292 293 switch (ourport->info->type) { 294 case TYPE_S3C6400: 295 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM); 296 break; 297 case TYPE_APPLE_S5L: 298 s3c24xx_clear_bit(port, APPLE_S5L_UCON_TXTHRESH_ENA, S3C2410_UCON); 299 break; 300 default: 301 disable_irq_nosync(ourport->tx_irq); 302 break; 303 } 304 305 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) { 306 dmaengine_pause(dma->tx_chan); 307 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state); 308 dmaengine_terminate_all(dma->tx_chan); 309 dma_sync_single_for_cpu(dma->tx_chan->device->dev, 310 dma->tx_transfer_addr, dma->tx_size, 311 DMA_TO_DEVICE); 312 async_tx_ack(dma->tx_desc); 313 count = dma->tx_bytes_requested - state.residue; 314 uart_xmit_advance(port, count); 315 } 316 317 ourport->tx_enabled = 0; 318 ourport->tx_in_progress = 0; 319 320 if (port->flags & UPF_CONS_FLOW) 321 s3c24xx_serial_rx_enable(port); 322 323 ourport->tx_mode = 0; 324 } 325 326 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport); 327 328 static void s3c24xx_serial_tx_dma_complete(void *args) 329 { 330 struct s3c24xx_uart_port *ourport = args; 331 struct uart_port *port = &ourport->port; 332 struct tty_port *tport = &port->state->port; 333 struct s3c24xx_uart_dma *dma = ourport->dma; 334 struct dma_tx_state state; 335 unsigned long flags; 336 int count; 337 338 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state); 339 count = dma->tx_bytes_requested - state.residue; 340 async_tx_ack(dma->tx_desc); 341 342 dma_sync_single_for_cpu(dma->tx_chan->device->dev, 343 dma->tx_transfer_addr, dma->tx_size, 344 DMA_TO_DEVICE); 345 346 uart_port_lock_irqsave(port, &flags); 347 348 uart_xmit_advance(port, count); 349 ourport->tx_in_progress = 0; 350 351 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 352 uart_write_wakeup(port); 353 354 s3c24xx_serial_start_next_tx(ourport); 355 uart_port_unlock_irqrestore(port, flags); 356 } 357 358 static void enable_tx_dma(struct s3c24xx_uart_port *ourport) 359 { 360 const struct uart_port *port = &ourport->port; 361 u32 ucon; 362 363 /* Mask Tx interrupt */ 364 switch (ourport->info->type) { 365 case TYPE_S3C6400: 366 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM); 367 break; 368 case TYPE_APPLE_S5L: 369 WARN_ON(1); // No DMA 370 break; 371 default: 372 disable_irq_nosync(ourport->tx_irq); 373 break; 374 } 375 376 /* Enable tx dma mode */ 377 ucon = rd_regl(port, S3C2410_UCON); 378 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK); 379 ucon |= S3C64XX_UCON_TXBURST_1; 380 ucon |= S3C64XX_UCON_TXMODE_DMA; 381 wr_regl(port, S3C2410_UCON, ucon); 382 383 ourport->tx_mode = S3C24XX_TX_DMA; 384 } 385 386 static void enable_tx_pio(struct s3c24xx_uart_port *ourport) 387 { 388 const struct uart_port *port = &ourport->port; 389 u32 ucon, ufcon; 390 391 /* Set ufcon txtrig */ 392 ourport->tx_in_progress = S3C24XX_TX_PIO; 393 ufcon = rd_regl(port, S3C2410_UFCON); 394 wr_regl(port, S3C2410_UFCON, ufcon); 395 396 /* Enable tx pio mode */ 397 ucon = rd_regl(port, S3C2410_UCON); 398 ucon &= ~(S3C64XX_UCON_TXMODE_MASK); 399 ucon |= S3C64XX_UCON_TXMODE_CPU; 400 wr_regl(port, S3C2410_UCON, ucon); 401 402 /* Unmask Tx interrupt */ 403 switch (ourport->info->type) { 404 case TYPE_S3C6400: 405 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD, 406 S3C64XX_UINTM); 407 break; 408 case TYPE_APPLE_S5L: 409 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK; 410 wr_regl(port, S3C2410_UCON, ucon); 411 break; 412 default: 413 enable_irq(ourport->tx_irq); 414 break; 415 } 416 417 ourport->tx_mode = S3C24XX_TX_PIO; 418 419 /* 420 * The Apple version only has edge triggered TX IRQs, so we need 421 * to kick off the process by sending some characters here. 422 */ 423 if (ourport->info->type == TYPE_APPLE_S5L) 424 s3c24xx_serial_tx_chars(ourport); 425 } 426 427 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport) 428 { 429 if (ourport->tx_mode != S3C24XX_TX_PIO) 430 enable_tx_pio(ourport); 431 } 432 433 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport, 434 unsigned int count, unsigned int tail) 435 { 436 struct s3c24xx_uart_dma *dma = ourport->dma; 437 438 if (ourport->tx_mode != S3C24XX_TX_DMA) 439 enable_tx_dma(ourport); 440 441 dma->tx_size = count & ~(dma_get_cache_alignment() - 1); 442 dma->tx_transfer_addr = dma->tx_addr + tail; 443 444 dma_sync_single_for_device(dma->tx_chan->device->dev, 445 dma->tx_transfer_addr, dma->tx_size, 446 DMA_TO_DEVICE); 447 448 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan, 449 dma->tx_transfer_addr, dma->tx_size, 450 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 451 if (!dma->tx_desc) { 452 dev_err(ourport->port.dev, "Unable to get desc for Tx\n"); 453 return -EIO; 454 } 455 456 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete; 457 dma->tx_desc->callback_param = ourport; 458 dma->tx_bytes_requested = dma->tx_size; 459 460 ourport->tx_in_progress = S3C24XX_TX_DMA; 461 dma->tx_cookie = dmaengine_submit(dma->tx_desc); 462 dma_async_issue_pending(dma->tx_chan); 463 return 0; 464 } 465 466 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport) 467 { 468 struct uart_port *port = &ourport->port; 469 struct tty_port *tport = &port->state->port; 470 unsigned int count, tail; 471 472 /* Get data size up to the end of buffer */ 473 count = kfifo_out_linear(&tport->xmit_fifo, &tail, UART_XMIT_SIZE); 474 475 if (!count) { 476 s3c24xx_serial_stop_tx(port); 477 return; 478 } 479 480 if (!ourport->dma || !ourport->dma->tx_chan || 481 count < ourport->min_dma_size || 482 tail & (dma_get_cache_alignment() - 1)) 483 s3c24xx_serial_start_tx_pio(ourport); 484 else 485 s3c24xx_serial_start_tx_dma(ourport, count, tail); 486 } 487 488 static void s3c24xx_serial_start_tx(struct uart_port *port) 489 { 490 struct s3c24xx_uart_port *ourport = to_ourport(port); 491 struct tty_port *tport = &port->state->port; 492 493 if (!ourport->tx_enabled) { 494 if (port->flags & UPF_CONS_FLOW) 495 s3c24xx_serial_rx_disable(port); 496 497 ourport->tx_enabled = 1; 498 if (!ourport->dma || !ourport->dma->tx_chan) 499 s3c24xx_serial_start_tx_pio(ourport); 500 } 501 502 if (ourport->dma && ourport->dma->tx_chan) { 503 if (!kfifo_is_empty(&tport->xmit_fifo) && 504 !ourport->tx_in_progress) 505 s3c24xx_serial_start_next_tx(ourport); 506 } 507 } 508 509 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport, 510 struct tty_port *tty, int count) 511 { 512 struct s3c24xx_uart_dma *dma = ourport->dma; 513 int copied; 514 515 if (!count) 516 return; 517 518 dma_sync_single_for_cpu(dma->rx_chan->device->dev, dma->rx_addr, 519 dma->rx_size, DMA_FROM_DEVICE); 520 521 ourport->port.icount.rx += count; 522 if (!tty) { 523 dev_err(ourport->port.dev, "No tty port\n"); 524 return; 525 } 526 copied = tty_insert_flip_string(tty, 527 ((unsigned char *)(ourport->dma->rx_buf)), count); 528 if (copied != count) { 529 WARN_ON(1); 530 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n"); 531 } 532 } 533 534 static void s3c24xx_serial_stop_rx(struct uart_port *port) 535 { 536 struct s3c24xx_uart_port *ourport = to_ourport(port); 537 struct s3c24xx_uart_dma *dma = ourport->dma; 538 struct tty_port *t = &port->state->port; 539 struct dma_tx_state state; 540 enum dma_status dma_status; 541 unsigned int received; 542 543 if (ourport->rx_enabled) { 544 dev_dbg(port->dev, "stopping rx\n"); 545 switch (ourport->info->type) { 546 case TYPE_S3C6400: 547 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD, 548 S3C64XX_UINTM); 549 break; 550 case TYPE_APPLE_S5L: 551 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON); 552 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON); 553 break; 554 default: 555 disable_irq_nosync(ourport->rx_irq); 556 break; 557 } 558 ourport->rx_enabled = 0; 559 } 560 if (dma && dma->rx_chan) { 561 dmaengine_pause(dma->tx_chan); 562 dma_status = dmaengine_tx_status(dma->rx_chan, 563 dma->rx_cookie, &state); 564 if (dma_status == DMA_IN_PROGRESS || 565 dma_status == DMA_PAUSED) { 566 received = dma->rx_bytes_requested - state.residue; 567 dmaengine_terminate_all(dma->rx_chan); 568 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 569 } 570 } 571 } 572 573 static inline const struct s3c24xx_uart_info 574 *s3c24xx_port_to_info(struct uart_port *port) 575 { 576 return to_ourport(port)->info; 577 } 578 579 static inline const struct s3c2410_uartcfg 580 *s3c24xx_port_to_cfg(const struct uart_port *port) 581 { 582 const struct s3c24xx_uart_port *ourport; 583 584 if (port->dev == NULL) 585 return NULL; 586 587 ourport = container_of(port, struct s3c24xx_uart_port, port); 588 return ourport->cfg; 589 } 590 591 static unsigned int 592 s3c24xx_serial_rx_fifocnt(const struct s3c24xx_uart_port *ourport, u32 ufstat) 593 { 594 const struct s3c24xx_uart_info *info = ourport->info; 595 596 if (ufstat & info->rx_fifofull) 597 return ourport->port.fifosize; 598 599 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift; 600 } 601 602 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport); 603 static void s3c24xx_serial_rx_dma_complete(void *args) 604 { 605 struct s3c24xx_uart_port *ourport = args; 606 struct uart_port *port = &ourport->port; 607 608 struct s3c24xx_uart_dma *dma = ourport->dma; 609 struct tty_port *t = &port->state->port; 610 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port); 611 612 struct dma_tx_state state; 613 unsigned long flags; 614 int received; 615 616 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state); 617 received = dma->rx_bytes_requested - state.residue; 618 async_tx_ack(dma->rx_desc); 619 620 uart_port_lock_irqsave(port, &flags); 621 622 if (received) 623 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 624 625 if (tty) { 626 tty_flip_buffer_push(t); 627 tty_kref_put(tty); 628 } 629 630 s3c64xx_start_rx_dma(ourport); 631 632 uart_port_unlock_irqrestore(port, flags); 633 } 634 635 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport) 636 { 637 struct s3c24xx_uart_dma *dma = ourport->dma; 638 639 dma_sync_single_for_device(dma->rx_chan->device->dev, dma->rx_addr, 640 dma->rx_size, DMA_FROM_DEVICE); 641 642 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan, 643 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM, 644 DMA_PREP_INTERRUPT); 645 if (!dma->rx_desc) { 646 dev_err(ourport->port.dev, "Unable to get desc for Rx\n"); 647 return; 648 } 649 650 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete; 651 dma->rx_desc->callback_param = ourport; 652 dma->rx_bytes_requested = dma->rx_size; 653 654 dma->rx_cookie = dmaengine_submit(dma->rx_desc); 655 dma_async_issue_pending(dma->rx_chan); 656 } 657 658 /* ? - where has parity gone?? */ 659 #define S3C2410_UERSTAT_PARITY (0x1000) 660 661 static void enable_rx_dma(struct s3c24xx_uart_port *ourport) 662 { 663 struct uart_port *port = &ourport->port; 664 u32 ucon; 665 666 /* set Rx mode to DMA mode */ 667 ucon = rd_regl(port, S3C2410_UCON); 668 ucon &= ~(S3C64XX_UCON_RXBURST_MASK | 669 S3C64XX_UCON_TIMEOUT_MASK | 670 S3C64XX_UCON_EMPTYINT_EN | 671 S3C64XX_UCON_DMASUS_EN | 672 S3C64XX_UCON_TIMEOUT_EN | 673 S3C64XX_UCON_RXMODE_MASK); 674 ucon |= S3C64XX_UCON_RXBURST_1 | 675 0xf << S3C64XX_UCON_TIMEOUT_SHIFT | 676 S3C64XX_UCON_EMPTYINT_EN | 677 S3C64XX_UCON_TIMEOUT_EN | 678 S3C64XX_UCON_RXMODE_DMA; 679 wr_regl(port, S3C2410_UCON, ucon); 680 681 ourport->rx_mode = S3C24XX_RX_DMA; 682 } 683 684 static void enable_rx_pio(struct s3c24xx_uart_port *ourport) 685 { 686 struct uart_port *port = &ourport->port; 687 u32 ucon; 688 689 /* set Rx mode to DMA mode */ 690 ucon = rd_regl(port, S3C2410_UCON); 691 ucon &= ~S3C64XX_UCON_RXMODE_MASK; 692 ucon |= S3C64XX_UCON_RXMODE_CPU; 693 694 /* Apple types use these bits for IRQ masks */ 695 if (ourport->info->type != TYPE_APPLE_S5L) { 696 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK | 697 S3C64XX_UCON_EMPTYINT_EN | 698 S3C64XX_UCON_DMASUS_EN | 699 S3C64XX_UCON_TIMEOUT_EN); 700 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT | 701 S3C64XX_UCON_TIMEOUT_EN; 702 } 703 wr_regl(port, S3C2410_UCON, ucon); 704 705 ourport->rx_mode = S3C24XX_RX_PIO; 706 } 707 708 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport); 709 710 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id) 711 { 712 struct s3c24xx_uart_port *ourport = dev_id; 713 struct uart_port *port = &ourport->port; 714 struct s3c24xx_uart_dma *dma = ourport->dma; 715 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port); 716 struct tty_port *t = &port->state->port; 717 struct dma_tx_state state; 718 unsigned int received; 719 u32 utrstat; 720 721 utrstat = rd_regl(port, S3C2410_UTRSTAT); 722 rd_regl(port, S3C2410_UFSTAT); 723 724 uart_port_lock(port); 725 726 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) { 727 s3c64xx_start_rx_dma(ourport); 728 if (ourport->rx_mode == S3C24XX_RX_PIO) 729 enable_rx_dma(ourport); 730 goto finish; 731 } 732 733 if (ourport->rx_mode == S3C24XX_RX_DMA) { 734 dmaengine_pause(dma->rx_chan); 735 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state); 736 dmaengine_terminate_all(dma->rx_chan); 737 received = dma->rx_bytes_requested - state.residue; 738 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 739 740 enable_rx_pio(ourport); 741 } 742 743 s3c24xx_serial_rx_drain_fifo(ourport); 744 745 if (tty) { 746 tty_flip_buffer_push(t); 747 tty_kref_put(tty); 748 } 749 750 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT); 751 752 finish: 753 uart_port_unlock(port); 754 755 return IRQ_HANDLED; 756 } 757 758 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport) 759 { 760 struct uart_port *port = &ourport->port; 761 unsigned int max_count = port->fifosize; 762 unsigned int fifocnt = 0; 763 u32 ufcon, ufstat, uerstat; 764 u8 ch, flag; 765 766 while (max_count-- > 0) { 767 /* 768 * Receive all characters known to be in FIFO 769 * before reading FIFO level again 770 */ 771 if (fifocnt == 0) { 772 ufstat = rd_regl(port, S3C2410_UFSTAT); 773 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat); 774 if (fifocnt == 0) 775 break; 776 } 777 fifocnt--; 778 779 uerstat = rd_regl(port, S3C2410_UERSTAT); 780 ch = rd_reg(port, S3C2410_URXH); 781 782 if (port->flags & UPF_CONS_FLOW) { 783 bool txe = s3c24xx_serial_txempty_nofifo(port); 784 785 if (ourport->rx_enabled) { 786 if (!txe) { 787 ourport->rx_enabled = 0; 788 continue; 789 } 790 } else { 791 if (txe) { 792 ufcon = rd_regl(port, S3C2410_UFCON); 793 ufcon |= S3C2410_UFCON_RESETRX; 794 wr_regl(port, S3C2410_UFCON, ufcon); 795 ourport->rx_enabled = 1; 796 return; 797 } 798 continue; 799 } 800 } 801 802 /* insert the character into the buffer */ 803 804 flag = TTY_NORMAL; 805 port->icount.rx++; 806 807 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) { 808 dev_dbg(port->dev, 809 "rxerr: port ch=0x%02x, rxs=0x%08x\n", 810 ch, uerstat); 811 812 /* check for break */ 813 if (uerstat & S3C2410_UERSTAT_BREAK) { 814 dev_dbg(port->dev, "break!\n"); 815 port->icount.brk++; 816 if (uart_handle_break(port)) 817 continue; /* Ignore character */ 818 } 819 820 if (uerstat & S3C2410_UERSTAT_FRAME) 821 port->icount.frame++; 822 if (uerstat & S3C2410_UERSTAT_OVERRUN) 823 port->icount.overrun++; 824 825 uerstat &= port->read_status_mask; 826 827 if (uerstat & S3C2410_UERSTAT_BREAK) 828 flag = TTY_BREAK; 829 else if (uerstat & S3C2410_UERSTAT_PARITY) 830 flag = TTY_PARITY; 831 else if (uerstat & (S3C2410_UERSTAT_FRAME | 832 S3C2410_UERSTAT_OVERRUN)) 833 flag = TTY_FRAME; 834 } 835 836 if (uart_handle_sysrq_char(port, ch)) 837 continue; /* Ignore character */ 838 839 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, 840 ch, flag); 841 } 842 843 tty_flip_buffer_push(&port->state->port); 844 } 845 846 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id) 847 { 848 struct s3c24xx_uart_port *ourport = dev_id; 849 struct uart_port *port = &ourport->port; 850 851 uart_port_lock(port); 852 s3c24xx_serial_rx_drain_fifo(ourport); 853 uart_port_unlock(port); 854 855 return IRQ_HANDLED; 856 } 857 858 static irqreturn_t s3c24xx_serial_rx_irq(int irq, void *dev_id) 859 { 860 struct s3c24xx_uart_port *ourport = dev_id; 861 862 if (ourport->dma && ourport->dma->rx_chan) 863 return s3c24xx_serial_rx_chars_dma(dev_id); 864 return s3c24xx_serial_rx_chars_pio(dev_id); 865 } 866 867 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport) 868 { 869 struct uart_port *port = &ourport->port; 870 struct tty_port *tport = &port->state->port; 871 unsigned int count, dma_count = 0, tail; 872 873 count = kfifo_out_linear(&tport->xmit_fifo, &tail, UART_XMIT_SIZE); 874 875 if (ourport->dma && ourport->dma->tx_chan && 876 count >= ourport->min_dma_size) { 877 int align = dma_get_cache_alignment() - 878 (tail & (dma_get_cache_alignment() - 1)); 879 if (count - align >= ourport->min_dma_size) { 880 dma_count = count - align; 881 count = align; 882 tail += align; 883 } 884 } 885 886 if (port->x_char) { 887 wr_reg(port, S3C2410_UTXH, port->x_char); 888 port->icount.tx++; 889 port->x_char = 0; 890 return; 891 } 892 893 /* if there isn't anything more to transmit, or the uart is now 894 * stopped, disable the uart and exit 895 */ 896 897 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) { 898 s3c24xx_serial_stop_tx(port); 899 return; 900 } 901 902 /* try and drain the buffer... */ 903 904 if (count > port->fifosize) { 905 count = port->fifosize; 906 dma_count = 0; 907 } 908 909 while (!(rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)) { 910 unsigned char ch; 911 912 if (!uart_fifo_get(port, &ch)) 913 break; 914 915 wr_reg(port, S3C2410_UTXH, ch); 916 count--; 917 } 918 919 if (!count && dma_count) { 920 s3c24xx_serial_start_tx_dma(ourport, dma_count, tail); 921 return; 922 } 923 924 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 925 uart_write_wakeup(port); 926 927 if (kfifo_is_empty(&tport->xmit_fifo)) 928 s3c24xx_serial_stop_tx(port); 929 } 930 931 static irqreturn_t s3c24xx_serial_tx_irq(int irq, void *id) 932 { 933 struct s3c24xx_uart_port *ourport = id; 934 struct uart_port *port = &ourport->port; 935 936 uart_port_lock(port); 937 938 s3c24xx_serial_tx_chars(ourport); 939 940 uart_port_unlock(port); 941 return IRQ_HANDLED; 942 } 943 944 /* interrupt handler for s3c64xx and later SoC's.*/ 945 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id) 946 { 947 const struct s3c24xx_uart_port *ourport = id; 948 const struct uart_port *port = &ourport->port; 949 u32 pend = rd_regl(port, S3C64XX_UINTP); 950 irqreturn_t ret = IRQ_HANDLED; 951 952 if (pend & S3C64XX_UINTM_RXD_MSK) { 953 ret = s3c24xx_serial_rx_irq(irq, id); 954 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK); 955 } 956 if (pend & S3C64XX_UINTM_TXD_MSK) { 957 ret = s3c24xx_serial_tx_irq(irq, id); 958 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK); 959 } 960 return ret; 961 } 962 963 /* interrupt handler for Apple SoC's.*/ 964 static irqreturn_t apple_serial_handle_irq(int irq, void *id) 965 { 966 const struct s3c24xx_uart_port *ourport = id; 967 const struct uart_port *port = &ourport->port; 968 u32 pend = rd_regl(port, S3C2410_UTRSTAT); 969 irqreturn_t ret = IRQ_NONE; 970 971 if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) { 972 wr_regl(port, S3C2410_UTRSTAT, 973 APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO); 974 ret = s3c24xx_serial_rx_irq(irq, id); 975 } 976 if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) { 977 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH); 978 ret = s3c24xx_serial_tx_irq(irq, id); 979 } 980 981 return ret; 982 } 983 984 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) 985 { 986 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 987 u32 ufstat = rd_regl(port, S3C2410_UFSTAT); 988 u32 ufcon = rd_regl(port, S3C2410_UFCON); 989 990 if (ufcon & S3C2410_UFCON_FIFOMODE) { 991 if ((ufstat & info->tx_fifomask) || 992 (ufstat & info->tx_fifofull)) 993 return 0; 994 return TIOCSER_TEMT; 995 } 996 997 return s3c24xx_serial_txempty_nofifo(port) ? TIOCSER_TEMT : 0; 998 } 999 1000 /* no modem control lines */ 1001 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) 1002 { 1003 u32 umstat = rd_reg(port, S3C2410_UMSTAT); 1004 1005 if (umstat & S3C2410_UMSTAT_CTS) 1006 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 1007 else 1008 return TIOCM_CAR | TIOCM_DSR; 1009 } 1010 1011 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) 1012 { 1013 u32 umcon = rd_regl(port, S3C2410_UMCON); 1014 u32 ucon = rd_regl(port, S3C2410_UCON); 1015 1016 if (mctrl & TIOCM_RTS) 1017 umcon |= S3C2410_UMCOM_RTS_LOW; 1018 else 1019 umcon &= ~S3C2410_UMCOM_RTS_LOW; 1020 1021 wr_regl(port, S3C2410_UMCON, umcon); 1022 1023 if (mctrl & TIOCM_LOOP) 1024 ucon |= S3C2410_UCON_LOOPBACK; 1025 else 1026 ucon &= ~S3C2410_UCON_LOOPBACK; 1027 1028 wr_regl(port, S3C2410_UCON, ucon); 1029 } 1030 1031 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state) 1032 { 1033 unsigned long flags; 1034 u32 ucon; 1035 1036 uart_port_lock_irqsave(port, &flags); 1037 1038 ucon = rd_regl(port, S3C2410_UCON); 1039 1040 if (break_state) 1041 ucon |= S3C2410_UCON_SBREAK; 1042 else 1043 ucon &= ~S3C2410_UCON_SBREAK; 1044 1045 wr_regl(port, S3C2410_UCON, ucon); 1046 1047 uart_port_unlock_irqrestore(port, flags); 1048 } 1049 1050 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p) 1051 { 1052 struct s3c24xx_uart_dma *dma = p->dma; 1053 struct dma_slave_caps dma_caps; 1054 const char *reason = NULL; 1055 int ret; 1056 1057 /* Default slave configuration parameters */ 1058 dma->rx_conf.direction = DMA_DEV_TO_MEM; 1059 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1060 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH; 1061 dma->rx_conf.src_maxburst = 1; 1062 1063 dma->tx_conf.direction = DMA_MEM_TO_DEV; 1064 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1065 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH; 1066 dma->tx_conf.dst_maxburst = 1; 1067 1068 dma->rx_chan = dma_request_chan(p->port.dev, "rx"); 1069 1070 if (IS_ERR(dma->rx_chan)) { 1071 reason = "DMA RX channel request failed"; 1072 ret = PTR_ERR(dma->rx_chan); 1073 goto err_warn; 1074 } 1075 1076 ret = dma_get_slave_caps(dma->rx_chan, &dma_caps); 1077 if (ret < 0 || 1078 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) { 1079 reason = "insufficient DMA RX engine capabilities"; 1080 ret = -EOPNOTSUPP; 1081 goto err_release_rx; 1082 } 1083 1084 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf); 1085 1086 dma->tx_chan = dma_request_chan(p->port.dev, "tx"); 1087 if (IS_ERR(dma->tx_chan)) { 1088 reason = "DMA TX channel request failed"; 1089 ret = PTR_ERR(dma->tx_chan); 1090 goto err_release_rx; 1091 } 1092 1093 ret = dma_get_slave_caps(dma->tx_chan, &dma_caps); 1094 if (ret < 0 || 1095 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) { 1096 reason = "insufficient DMA TX engine capabilities"; 1097 ret = -EOPNOTSUPP; 1098 goto err_release_tx; 1099 } 1100 1101 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf); 1102 1103 /* RX buffer */ 1104 dma->rx_size = PAGE_SIZE; 1105 1106 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL); 1107 if (!dma->rx_buf) { 1108 ret = -ENOMEM; 1109 goto err_release_tx; 1110 } 1111 1112 dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf, 1113 dma->rx_size, DMA_FROM_DEVICE); 1114 if (dma_mapping_error(dma->rx_chan->device->dev, dma->rx_addr)) { 1115 reason = "DMA mapping error for RX buffer"; 1116 ret = -EIO; 1117 goto err_free_rx; 1118 } 1119 1120 /* TX buffer */ 1121 dma->tx_addr = dma_map_single(dma->tx_chan->device->dev, 1122 p->port.state->port.xmit_buf, 1123 UART_XMIT_SIZE, 1124 DMA_TO_DEVICE); 1125 if (dma_mapping_error(dma->tx_chan->device->dev, dma->tx_addr)) { 1126 reason = "DMA mapping error for TX buffer"; 1127 ret = -EIO; 1128 goto err_unmap_rx; 1129 } 1130 1131 return 0; 1132 1133 err_unmap_rx: 1134 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr, 1135 dma->rx_size, DMA_FROM_DEVICE); 1136 err_free_rx: 1137 kfree(dma->rx_buf); 1138 err_release_tx: 1139 dma_release_channel(dma->tx_chan); 1140 err_release_rx: 1141 dma_release_channel(dma->rx_chan); 1142 err_warn: 1143 if (reason) 1144 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason); 1145 return ret; 1146 } 1147 1148 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p) 1149 { 1150 struct s3c24xx_uart_dma *dma = p->dma; 1151 1152 if (dma->rx_chan) { 1153 dmaengine_terminate_all(dma->rx_chan); 1154 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr, 1155 dma->rx_size, DMA_FROM_DEVICE); 1156 kfree(dma->rx_buf); 1157 dma_release_channel(dma->rx_chan); 1158 dma->rx_chan = NULL; 1159 } 1160 1161 if (dma->tx_chan) { 1162 dmaengine_terminate_all(dma->tx_chan); 1163 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr, 1164 UART_XMIT_SIZE, DMA_TO_DEVICE); 1165 dma_release_channel(dma->tx_chan); 1166 dma->tx_chan = NULL; 1167 } 1168 } 1169 1170 static void s3c64xx_serial_shutdown(struct uart_port *port) 1171 { 1172 struct s3c24xx_uart_port *ourport = to_ourport(port); 1173 1174 ourport->tx_enabled = 0; 1175 ourport->tx_mode = 0; 1176 ourport->rx_enabled = 0; 1177 1178 free_irq(port->irq, ourport); 1179 1180 wr_regl(port, S3C64XX_UINTP, 0xf); 1181 wr_regl(port, S3C64XX_UINTM, 0xf); 1182 1183 if (ourport->dma) 1184 s3c24xx_serial_release_dma(ourport); 1185 1186 ourport->tx_in_progress = 0; 1187 } 1188 1189 static void apple_s5l_serial_shutdown(struct uart_port *port) 1190 { 1191 struct s3c24xx_uart_port *ourport = to_ourport(port); 1192 1193 u32 ucon; 1194 1195 ucon = rd_regl(port, S3C2410_UCON); 1196 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | 1197 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 1198 APPLE_S5L_UCON_RXTO_ENA_MSK); 1199 wr_regl(port, S3C2410_UCON, ucon); 1200 1201 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS); 1202 1203 free_irq(port->irq, ourport); 1204 1205 ourport->tx_enabled = 0; 1206 ourport->tx_mode = 0; 1207 ourport->rx_enabled = 0; 1208 1209 if (ourport->dma) 1210 s3c24xx_serial_release_dma(ourport); 1211 1212 ourport->tx_in_progress = 0; 1213 } 1214 1215 static int s3c64xx_serial_startup(struct uart_port *port) 1216 { 1217 struct s3c24xx_uart_port *ourport = to_ourport(port); 1218 unsigned long flags; 1219 u32 ufcon; 1220 int ret; 1221 1222 wr_regl(port, S3C64XX_UINTM, 0xf); 1223 if (ourport->dma) { 1224 ret = s3c24xx_serial_request_dma(ourport); 1225 if (ret < 0) { 1226 devm_kfree(port->dev, ourport->dma); 1227 ourport->dma = NULL; 1228 } 1229 } 1230 1231 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED, 1232 s3c24xx_serial_portname(port), ourport); 1233 if (ret) { 1234 dev_err(port->dev, "cannot get irq %d\n", port->irq); 1235 return ret; 1236 } 1237 1238 /* For compatibility with s3c24xx Soc's */ 1239 ourport->rx_enabled = 1; 1240 ourport->tx_enabled = 0; 1241 1242 uart_port_lock_irqsave(port, &flags); 1243 1244 ufcon = rd_regl(port, S3C2410_UFCON); 1245 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8; 1246 if (!uart_console(port)) 1247 ufcon |= S3C2410_UFCON_RESETTX; 1248 wr_regl(port, S3C2410_UFCON, ufcon); 1249 1250 enable_rx_pio(ourport); 1251 1252 uart_port_unlock_irqrestore(port, flags); 1253 1254 /* Enable Rx Interrupt */ 1255 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM); 1256 1257 return ret; 1258 } 1259 1260 static int apple_s5l_serial_startup(struct uart_port *port) 1261 { 1262 struct s3c24xx_uart_port *ourport = to_ourport(port); 1263 unsigned long flags; 1264 u32 ufcon; 1265 int ret; 1266 1267 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS); 1268 1269 ret = request_irq(port->irq, apple_serial_handle_irq, 0, 1270 s3c24xx_serial_portname(port), ourport); 1271 if (ret) { 1272 dev_err(port->dev, "cannot get irq %d\n", port->irq); 1273 return ret; 1274 } 1275 1276 /* For compatibility with s3c24xx Soc's */ 1277 ourport->rx_enabled = 1; 1278 ourport->tx_enabled = 0; 1279 1280 uart_port_lock_irqsave(port, &flags); 1281 1282 ufcon = rd_regl(port, S3C2410_UFCON); 1283 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8; 1284 if (!uart_console(port)) 1285 ufcon |= S3C2410_UFCON_RESETTX; 1286 wr_regl(port, S3C2410_UFCON, ufcon); 1287 1288 enable_rx_pio(ourport); 1289 1290 uart_port_unlock_irqrestore(port, flags); 1291 1292 /* Enable Rx Interrupt */ 1293 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON); 1294 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON); 1295 1296 return ret; 1297 } 1298 1299 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, 1300 unsigned int old) 1301 { 1302 struct s3c24xx_uart_port *ourport = to_ourport(port); 1303 int timeout = 10000; 1304 1305 ourport->pm_level = level; 1306 1307 switch (level) { 1308 case 3: 1309 while (--timeout && !s3c24xx_serial_txempty_nofifo(port)) 1310 udelay(100); 1311 1312 if (!IS_ERR(ourport->baudclk)) 1313 clk_disable_unprepare(ourport->baudclk); 1314 1315 clk_disable_unprepare(ourport->clk); 1316 break; 1317 1318 case 0: 1319 clk_prepare_enable(ourport->clk); 1320 1321 if (!IS_ERR(ourport->baudclk)) 1322 clk_prepare_enable(ourport->baudclk); 1323 break; 1324 default: 1325 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level); 1326 } 1327 } 1328 1329 /* baud rate calculation 1330 * 1331 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number 1332 * of different sources, including the peripheral clock ("pclk") and an 1333 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk") 1334 * with a programmable extra divisor. 1335 * 1336 * The following code goes through the clock sources, and calculates the 1337 * baud clocks (and the resultant actual baud rates) and then tries to 1338 * pick the closest one and select that. 1339 * 1340 */ 1341 1342 #define MAX_CLK_NAME_LENGTH 15 1343 1344 static inline u8 s3c24xx_serial_getsource(struct uart_port *port) 1345 { 1346 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1347 u32 ucon; 1348 1349 if (info->num_clks == 1) 1350 return 0; 1351 1352 ucon = rd_regl(port, S3C2410_UCON); 1353 ucon &= info->clksel_mask; 1354 return ucon >> info->clksel_shift; 1355 } 1356 1357 static void s3c24xx_serial_setsource(struct uart_port *port, u8 clk_sel) 1358 { 1359 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1360 u32 ucon; 1361 1362 if (info->num_clks == 1) 1363 return; 1364 1365 ucon = rd_regl(port, S3C2410_UCON); 1366 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel) 1367 return; 1368 1369 ucon &= ~info->clksel_mask; 1370 ucon |= clk_sel << info->clksel_shift; 1371 wr_regl(port, S3C2410_UCON, ucon); 1372 } 1373 1374 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport, 1375 unsigned int req_baud, struct clk **best_clk, 1376 u8 *clk_num) 1377 { 1378 const struct s3c24xx_uart_info *info = ourport->info; 1379 struct clk *clk; 1380 unsigned long rate; 1381 unsigned int baud, quot, best_quot = 0; 1382 char clkname[MAX_CLK_NAME_LENGTH]; 1383 int calc_deviation, deviation = (1 << 30) - 1; 1384 u8 cnt; 1385 1386 for (cnt = 0; cnt < info->num_clks; cnt++) { 1387 /* Keep selected clock if provided */ 1388 if (ourport->cfg->clk_sel && 1389 !(ourport->cfg->clk_sel & (1 << cnt))) 1390 continue; 1391 1392 sprintf(clkname, "clk_uart_baud%d", cnt); 1393 clk = clk_get(ourport->port.dev, clkname); 1394 if (IS_ERR(clk)) 1395 continue; 1396 1397 rate = clk_get_rate(clk); 1398 if (!rate) { 1399 dev_err(ourport->port.dev, 1400 "Failed to get clock rate for %s.\n", clkname); 1401 clk_put(clk); 1402 continue; 1403 } 1404 1405 if (ourport->info->has_divslot) { 1406 unsigned long div = rate / req_baud; 1407 1408 /* The UDIVSLOT register on the newer UARTs allows us to 1409 * get a divisor adjustment of 1/16th on the baud clock. 1410 * 1411 * We don't keep the UDIVSLOT value (the 16ths we 1412 * calculated by not multiplying the baud by 16) as it 1413 * is easy enough to recalculate. 1414 */ 1415 1416 quot = div / 16; 1417 baud = rate / div; 1418 } else { 1419 quot = (rate + (8 * req_baud)) / (16 * req_baud); 1420 baud = rate / (quot * 16); 1421 } 1422 quot--; 1423 1424 calc_deviation = abs(req_baud - baud); 1425 1426 if (calc_deviation < deviation) { 1427 /* 1428 * If we find a better clk, release the previous one, if 1429 * any. 1430 */ 1431 if (!IS_ERR(*best_clk)) 1432 clk_put(*best_clk); 1433 *best_clk = clk; 1434 best_quot = quot; 1435 *clk_num = cnt; 1436 deviation = calc_deviation; 1437 } else { 1438 clk_put(clk); 1439 } 1440 } 1441 1442 return best_quot; 1443 } 1444 1445 /* udivslot_table[] 1446 * 1447 * This table takes the fractional value of the baud divisor and gives 1448 * the recommended setting for the UDIVSLOT register. 1449 */ 1450 static const u16 udivslot_table[16] = { 1451 [0] = 0x0000, 1452 [1] = 0x0080, 1453 [2] = 0x0808, 1454 [3] = 0x0888, 1455 [4] = 0x2222, 1456 [5] = 0x4924, 1457 [6] = 0x4A52, 1458 [7] = 0x54AA, 1459 [8] = 0x5555, 1460 [9] = 0xD555, 1461 [10] = 0xD5D5, 1462 [11] = 0xDDD5, 1463 [12] = 0xDDDD, 1464 [13] = 0xDFDD, 1465 [14] = 0xDFDF, 1466 [15] = 0xFFDF, 1467 }; 1468 1469 static void s3c24xx_serial_set_termios(struct uart_port *port, 1470 struct ktermios *termios, 1471 const struct ktermios *old) 1472 { 1473 const struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port); 1474 struct s3c24xx_uart_port *ourport = to_ourport(port); 1475 struct clk *clk = ERR_PTR(-EINVAL); 1476 unsigned long flags; 1477 unsigned int baud, quot; 1478 unsigned int udivslot = 0; 1479 u32 ulcon, umcon; 1480 u8 clk_sel = 0; 1481 1482 /* 1483 * We don't support modem control lines. 1484 */ 1485 termios->c_cflag &= ~(HUPCL | CMSPAR); 1486 termios->c_cflag |= CLOCAL; 1487 1488 /* 1489 * Ask the core to calculate the divisor for us. 1490 */ 1491 1492 baud = uart_get_baud_rate(port, termios, old, 0, 3000000); 1493 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel); 1494 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) 1495 quot = port->custom_divisor; 1496 if (IS_ERR(clk)) 1497 return; 1498 1499 /* check to see if we need to change clock source */ 1500 1501 if (ourport->baudclk != clk) { 1502 clk_prepare_enable(clk); 1503 1504 s3c24xx_serial_setsource(port, clk_sel); 1505 1506 if (!IS_ERR(ourport->baudclk)) { 1507 clk_disable_unprepare(ourport->baudclk); 1508 ourport->baudclk = ERR_PTR(-EINVAL); 1509 } 1510 1511 ourport->baudclk = clk; 1512 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0; 1513 } 1514 1515 if (ourport->info->has_divslot) { 1516 unsigned int div = ourport->baudclk_rate / baud; 1517 1518 if (cfg->has_fracval) { 1519 udivslot = (div & 15); 1520 dev_dbg(port->dev, "fracval = %04x\n", udivslot); 1521 } else { 1522 udivslot = udivslot_table[div & 15]; 1523 dev_dbg(port->dev, "udivslot = %04x (div %d)\n", 1524 udivslot, div & 15); 1525 } 1526 } 1527 1528 switch (termios->c_cflag & CSIZE) { 1529 case CS5: 1530 dev_dbg(port->dev, "config: 5bits/char\n"); 1531 ulcon = S3C2410_LCON_CS5; 1532 break; 1533 case CS6: 1534 dev_dbg(port->dev, "config: 6bits/char\n"); 1535 ulcon = S3C2410_LCON_CS6; 1536 break; 1537 case CS7: 1538 dev_dbg(port->dev, "config: 7bits/char\n"); 1539 ulcon = S3C2410_LCON_CS7; 1540 break; 1541 case CS8: 1542 default: 1543 dev_dbg(port->dev, "config: 8bits/char\n"); 1544 ulcon = S3C2410_LCON_CS8; 1545 break; 1546 } 1547 1548 /* preserve original lcon IR settings */ 1549 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM); 1550 1551 if (termios->c_cflag & CSTOPB) 1552 ulcon |= S3C2410_LCON_STOPB; 1553 1554 if (termios->c_cflag & PARENB) { 1555 if (termios->c_cflag & PARODD) 1556 ulcon |= S3C2410_LCON_PODD; 1557 else 1558 ulcon |= S3C2410_LCON_PEVEN; 1559 } else { 1560 ulcon |= S3C2410_LCON_PNONE; 1561 } 1562 1563 uart_port_lock_irqsave(port, &flags); 1564 1565 dev_dbg(port->dev, 1566 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n", 1567 ulcon, quot, udivslot); 1568 1569 wr_regl(port, S3C2410_ULCON, ulcon); 1570 wr_regl(port, S3C2410_UBRDIV, quot); 1571 1572 port->status &= ~UPSTAT_AUTOCTS; 1573 1574 umcon = rd_regl(port, S3C2410_UMCON); 1575 if (termios->c_cflag & CRTSCTS) { 1576 umcon |= S3C2410_UMCOM_AFC; 1577 /* Disable RTS when RX FIFO contains 63 bytes */ 1578 umcon &= ~S3C2412_UMCON_AFC_8; 1579 port->status = UPSTAT_AUTOCTS; 1580 } else { 1581 umcon &= ~S3C2410_UMCOM_AFC; 1582 } 1583 wr_regl(port, S3C2410_UMCON, umcon); 1584 1585 if (ourport->info->has_divslot) 1586 wr_regl(port, S3C2443_DIVSLOT, udivslot); 1587 1588 dev_dbg(port->dev, 1589 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n", 1590 rd_regl(port, S3C2410_ULCON), 1591 rd_regl(port, S3C2410_UCON), 1592 rd_regl(port, S3C2410_UFCON)); 1593 1594 /* 1595 * Update the per-port timeout. 1596 */ 1597 uart_update_timeout(port, termios->c_cflag, baud); 1598 1599 /* 1600 * Which character status flags are we interested in? 1601 */ 1602 port->read_status_mask = S3C2410_UERSTAT_OVERRUN; 1603 if (termios->c_iflag & INPCK) 1604 port->read_status_mask |= S3C2410_UERSTAT_FRAME | 1605 S3C2410_UERSTAT_PARITY; 1606 /* 1607 * Which character status flags should we ignore? 1608 */ 1609 port->ignore_status_mask = 0; 1610 if (termios->c_iflag & IGNPAR) 1611 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN; 1612 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR) 1613 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME; 1614 1615 /* 1616 * Ignore all characters if CREAD is not set. 1617 */ 1618 if ((termios->c_cflag & CREAD) == 0) 1619 port->ignore_status_mask |= RXSTAT_DUMMY_READ; 1620 1621 uart_port_unlock_irqrestore(port, flags); 1622 } 1623 1624 static const char *s3c24xx_serial_type(struct uart_port *port) 1625 { 1626 const struct s3c24xx_uart_port *ourport = to_ourport(port); 1627 1628 switch (ourport->info->type) { 1629 case TYPE_S3C6400: 1630 return "S3C6400/10"; 1631 case TYPE_APPLE_S5L: 1632 return "APPLE S5L"; 1633 default: 1634 return NULL; 1635 } 1636 } 1637 1638 static void s3c24xx_serial_config_port(struct uart_port *port, int flags) 1639 { 1640 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1641 1642 if (flags & UART_CONFIG_TYPE) 1643 port->type = info->port_type; 1644 } 1645 1646 /* 1647 * verify the new serial_struct (for TIOCSSERIAL). 1648 */ 1649 static int 1650 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser) 1651 { 1652 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1653 1654 if (ser->type != PORT_UNKNOWN && ser->type != info->port_type) 1655 return -EINVAL; 1656 1657 return 0; 1658 } 1659 1660 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 1661 1662 static struct console s3c24xx_serial_console; 1663 1664 static void __init s3c24xx_serial_register_console(void) 1665 { 1666 register_console(&s3c24xx_serial_console); 1667 } 1668 1669 static void s3c24xx_serial_unregister_console(void) 1670 { 1671 if (console_is_registered(&s3c24xx_serial_console)) 1672 unregister_console(&s3c24xx_serial_console); 1673 } 1674 1675 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console 1676 #else 1677 static inline void s3c24xx_serial_register_console(void) { } 1678 static inline void s3c24xx_serial_unregister_console(void) { } 1679 #define S3C24XX_SERIAL_CONSOLE NULL 1680 #endif 1681 1682 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1683 static int s3c24xx_serial_get_poll_char(struct uart_port *port); 1684 static void s3c24xx_serial_put_poll_char(struct uart_port *port, 1685 unsigned char c); 1686 #endif 1687 1688 static const struct uart_ops s3c64xx_serial_ops = { 1689 .pm = s3c24xx_serial_pm, 1690 .tx_empty = s3c24xx_serial_tx_empty, 1691 .get_mctrl = s3c24xx_serial_get_mctrl, 1692 .set_mctrl = s3c24xx_serial_set_mctrl, 1693 .stop_tx = s3c24xx_serial_stop_tx, 1694 .start_tx = s3c24xx_serial_start_tx, 1695 .stop_rx = s3c24xx_serial_stop_rx, 1696 .break_ctl = s3c24xx_serial_break_ctl, 1697 .startup = s3c64xx_serial_startup, 1698 .shutdown = s3c64xx_serial_shutdown, 1699 .set_termios = s3c24xx_serial_set_termios, 1700 .type = s3c24xx_serial_type, 1701 .config_port = s3c24xx_serial_config_port, 1702 .verify_port = s3c24xx_serial_verify_port, 1703 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1704 .poll_get_char = s3c24xx_serial_get_poll_char, 1705 .poll_put_char = s3c24xx_serial_put_poll_char, 1706 #endif 1707 }; 1708 1709 static const struct uart_ops apple_s5l_serial_ops = { 1710 .pm = s3c24xx_serial_pm, 1711 .tx_empty = s3c24xx_serial_tx_empty, 1712 .get_mctrl = s3c24xx_serial_get_mctrl, 1713 .set_mctrl = s3c24xx_serial_set_mctrl, 1714 .stop_tx = s3c24xx_serial_stop_tx, 1715 .start_tx = s3c24xx_serial_start_tx, 1716 .stop_rx = s3c24xx_serial_stop_rx, 1717 .break_ctl = s3c24xx_serial_break_ctl, 1718 .startup = apple_s5l_serial_startup, 1719 .shutdown = apple_s5l_serial_shutdown, 1720 .set_termios = s3c24xx_serial_set_termios, 1721 .type = s3c24xx_serial_type, 1722 .config_port = s3c24xx_serial_config_port, 1723 .verify_port = s3c24xx_serial_verify_port, 1724 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1725 .poll_get_char = s3c24xx_serial_get_poll_char, 1726 .poll_put_char = s3c24xx_serial_put_poll_char, 1727 #endif 1728 }; 1729 1730 static struct uart_driver s3c24xx_uart_drv = { 1731 .owner = THIS_MODULE, 1732 .driver_name = "s3c2410_serial", 1733 .nr = UART_NR, 1734 .cons = S3C24XX_SERIAL_CONSOLE, 1735 .dev_name = S3C24XX_SERIAL_NAME, 1736 .major = S3C24XX_SERIAL_MAJOR, 1737 .minor = S3C24XX_SERIAL_MINOR, 1738 }; 1739 1740 static struct s3c24xx_uart_port s3c24xx_serial_ports[UART_NR]; 1741 1742 static void s3c24xx_serial_init_port_default(int index) 1743 { 1744 struct uart_port *port = &s3c24xx_serial_ports[index].port; 1745 1746 spin_lock_init(&port->lock); 1747 1748 port->uartclk = 0; 1749 port->fifosize = 16; 1750 port->flags = UPF_BOOT_AUTOCONF; 1751 port->line = index; 1752 } 1753 1754 /* s3c24xx_serial_resetport 1755 * 1756 * reset the fifos and other the settings. 1757 */ 1758 1759 static void s3c24xx_serial_resetport(struct uart_port *port, 1760 const struct s3c2410_uartcfg *cfg) 1761 { 1762 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1763 u32 ucon = rd_regl(port, S3C2410_UCON); 1764 1765 ucon &= (info->clksel_mask | info->ucon_mask); 1766 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); 1767 1768 /* reset both fifos */ 1769 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); 1770 wr_regl(port, S3C2410_UFCON, cfg->ufcon); 1771 1772 /* some delay is required after fifo reset */ 1773 udelay(1); 1774 } 1775 1776 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport) 1777 { 1778 struct device *dev = ourport->port.dev; 1779 const struct s3c24xx_uart_info *info = ourport->info; 1780 char clk_name[MAX_CLK_NAME_LENGTH]; 1781 struct clk *clk; 1782 int ret; 1783 u8 clk_sel, clk_num; 1784 1785 clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel; 1786 for (clk_num = 0; clk_num < info->num_clks; clk_num++) { 1787 if (!(clk_sel & (1 << clk_num))) 1788 continue; 1789 1790 sprintf(clk_name, "clk_uart_baud%d", clk_num); 1791 clk = clk_get(dev, clk_name); 1792 if (IS_ERR(clk)) 1793 continue; 1794 1795 ret = clk_prepare_enable(clk); 1796 if (ret) { 1797 clk_put(clk); 1798 continue; 1799 } 1800 1801 ourport->baudclk = clk; 1802 ourport->baudclk_rate = clk_get_rate(clk); 1803 s3c24xx_serial_setsource(&ourport->port, clk_num); 1804 1805 return 0; 1806 } 1807 1808 return -EINVAL; 1809 } 1810 1811 /* s3c24xx_serial_init_port 1812 * 1813 * initialise a single serial port from the platform device given 1814 */ 1815 1816 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, 1817 struct platform_device *platdev) 1818 { 1819 struct uart_port *port = &ourport->port; 1820 const struct s3c2410_uartcfg *cfg = ourport->cfg; 1821 struct resource *res; 1822 int ret; 1823 1824 if (platdev == NULL) 1825 return -ENODEV; 1826 1827 if (port->mapbase != 0) 1828 return -EINVAL; 1829 1830 /* setup info for port */ 1831 port->dev = &platdev->dev; 1832 1833 port->uartclk = 1; 1834 1835 if (cfg->uart_flags & UPF_CONS_FLOW) { 1836 dev_dbg(port->dev, "enabling flow control\n"); 1837 port->flags |= UPF_CONS_FLOW; 1838 } 1839 1840 /* sort our the physical and virtual addresses for each UART */ 1841 1842 res = platform_get_resource(platdev, IORESOURCE_MEM, 0); 1843 if (res == NULL) { 1844 dev_err(port->dev, "failed to find memory resource for uart\n"); 1845 return -EINVAL; 1846 } 1847 1848 dev_dbg(port->dev, "resource %pR)\n", res); 1849 1850 port->membase = devm_ioremap_resource(port->dev, res); 1851 if (IS_ERR(port->membase)) { 1852 dev_err(port->dev, "failed to remap controller address\n"); 1853 return -EBUSY; 1854 } 1855 1856 port->mapbase = res->start; 1857 ret = platform_get_irq(platdev, 0); 1858 if (ret < 0) { 1859 port->irq = 0; 1860 } else { 1861 port->irq = ret; 1862 ourport->rx_irq = ret; 1863 ourport->tx_irq = ret + 1; 1864 } 1865 1866 /* 1867 * DMA is currently supported only on DT platforms, if DMA properties 1868 * are specified. 1869 */ 1870 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node, 1871 "dmas", NULL)) { 1872 ourport->dma = devm_kzalloc(port->dev, 1873 sizeof(*ourport->dma), 1874 GFP_KERNEL); 1875 if (!ourport->dma) { 1876 ret = -ENOMEM; 1877 goto err; 1878 } 1879 } 1880 1881 ourport->clk = clk_get(&platdev->dev, "uart"); 1882 if (IS_ERR(ourport->clk)) { 1883 pr_err("%s: Controller clock not found\n", 1884 dev_name(&platdev->dev)); 1885 ret = PTR_ERR(ourport->clk); 1886 goto err; 1887 } 1888 1889 ret = clk_prepare_enable(ourport->clk); 1890 if (ret) { 1891 pr_err("uart: clock failed to prepare+enable: %d\n", ret); 1892 clk_put(ourport->clk); 1893 goto err; 1894 } 1895 1896 ret = s3c24xx_serial_enable_baudclk(ourport); 1897 if (ret) 1898 pr_warn("uart: failed to enable baudclk\n"); 1899 1900 /* Keep all interrupts masked and cleared */ 1901 switch (ourport->info->type) { 1902 case TYPE_S3C6400: 1903 wr_regl(port, S3C64XX_UINTM, 0xf); 1904 wr_regl(port, S3C64XX_UINTP, 0xf); 1905 wr_regl(port, S3C64XX_UINTSP, 0xf); 1906 break; 1907 case TYPE_APPLE_S5L: { 1908 u32 ucon; 1909 1910 ucon = rd_regl(port, S3C2410_UCON); 1911 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | 1912 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 1913 APPLE_S5L_UCON_RXTO_ENA_MSK); 1914 wr_regl(port, S3C2410_UCON, ucon); 1915 1916 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS); 1917 break; 1918 } 1919 default: 1920 break; 1921 } 1922 1923 dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n", 1924 &port->mapbase, port->membase, port->irq, 1925 ourport->rx_irq, ourport->tx_irq, port->uartclk); 1926 1927 /* reset the fifos (and setup the uart) */ 1928 s3c24xx_serial_resetport(port, cfg); 1929 1930 return 0; 1931 1932 err: 1933 port->mapbase = 0; 1934 return ret; 1935 } 1936 1937 /* Device driver serial port probe */ 1938 1939 static int probe_index; 1940 1941 static inline const struct s3c24xx_serial_drv_data * 1942 s3c24xx_get_driver_data(struct platform_device *pdev) 1943 { 1944 if (dev_of_node(&pdev->dev)) 1945 return of_device_get_match_data(&pdev->dev); 1946 1947 return (struct s3c24xx_serial_drv_data *) 1948 platform_get_device_id(pdev)->driver_data; 1949 } 1950 1951 static int s3c24xx_serial_probe(struct platform_device *pdev) 1952 { 1953 struct device_node *np = pdev->dev.of_node; 1954 struct s3c24xx_uart_port *ourport; 1955 int index = probe_index; 1956 int ret, prop = 0, fifosize_prop = 1; 1957 1958 if (np) { 1959 ret = of_alias_get_id(np, "serial"); 1960 if (ret >= 0) 1961 index = ret; 1962 } 1963 1964 if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) { 1965 dev_err(&pdev->dev, "serial%d out of range\n", index); 1966 return -EINVAL; 1967 } 1968 ourport = &s3c24xx_serial_ports[index]; 1969 1970 s3c24xx_serial_init_port_default(index); 1971 1972 ourport->drv_data = s3c24xx_get_driver_data(pdev); 1973 if (!ourport->drv_data) { 1974 dev_err(&pdev->dev, "could not find driver data\n"); 1975 return -ENODEV; 1976 } 1977 1978 ourport->baudclk = ERR_PTR(-EINVAL); 1979 ourport->info = &ourport->drv_data->info; 1980 ourport->cfg = (dev_get_platdata(&pdev->dev)) ? 1981 dev_get_platdata(&pdev->dev) : 1982 &ourport->drv_data->def_cfg; 1983 1984 switch (ourport->info->type) { 1985 case TYPE_S3C6400: 1986 ourport->port.ops = &s3c64xx_serial_ops; 1987 break; 1988 case TYPE_APPLE_S5L: 1989 ourport->port.ops = &apple_s5l_serial_ops; 1990 break; 1991 } 1992 1993 ourport->port.iotype = ourport->info->iotype; 1994 1995 if (np) { 1996 fifosize_prop = of_property_read_u32(np, "samsung,uart-fifosize", 1997 &ourport->port.fifosize); 1998 1999 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) { 2000 switch (prop) { 2001 case 1: 2002 ourport->port.iotype = UPIO_MEM; 2003 break; 2004 case 4: 2005 ourport->port.iotype = UPIO_MEM32; 2006 break; 2007 default: 2008 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n", 2009 prop); 2010 return -EINVAL; 2011 } 2012 } 2013 } 2014 2015 if (fifosize_prop) { 2016 if (ourport->drv_data->fifosize[index]) 2017 ourport->port.fifosize = ourport->drv_data->fifosize[index]; 2018 else if (ourport->info->fifosize) 2019 ourport->port.fifosize = ourport->info->fifosize; 2020 } 2021 2022 ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE); 2023 2024 /* 2025 * DMA transfers must be aligned at least to cache line size, 2026 * so find minimal transfer size suitable for DMA mode 2027 */ 2028 ourport->min_dma_size = max_t(int, ourport->port.fifosize, 2029 dma_get_cache_alignment()); 2030 2031 dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport); 2032 2033 ret = s3c24xx_serial_init_port(ourport, pdev); 2034 if (ret < 0) 2035 return ret; 2036 2037 if (!s3c24xx_uart_drv.state) { 2038 ret = uart_register_driver(&s3c24xx_uart_drv); 2039 if (ret < 0) { 2040 pr_err("Failed to register Samsung UART driver\n"); 2041 return ret; 2042 } 2043 } 2044 2045 dev_dbg(&pdev->dev, "%s: adding port\n", __func__); 2046 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port); 2047 platform_set_drvdata(pdev, &ourport->port); 2048 2049 /* 2050 * Deactivate the clock enabled in s3c24xx_serial_init_port here, 2051 * so that a potential re-enablement through the pm-callback overlaps 2052 * and keeps the clock enabled in this case. 2053 */ 2054 clk_disable_unprepare(ourport->clk); 2055 if (!IS_ERR(ourport->baudclk)) 2056 clk_disable_unprepare(ourport->baudclk); 2057 2058 probe_index++; 2059 2060 return 0; 2061 } 2062 2063 static void s3c24xx_serial_remove(struct platform_device *dev) 2064 { 2065 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); 2066 2067 if (port) 2068 uart_remove_one_port(&s3c24xx_uart_drv, port); 2069 2070 uart_unregister_driver(&s3c24xx_uart_drv); 2071 } 2072 2073 /* UART power management code */ 2074 #ifdef CONFIG_PM_SLEEP 2075 static int s3c24xx_serial_suspend(struct device *dev) 2076 { 2077 struct uart_port *port = s3c24xx_dev_to_port(dev); 2078 2079 if (port) 2080 uart_suspend_port(&s3c24xx_uart_drv, port); 2081 2082 return 0; 2083 } 2084 2085 static int s3c24xx_serial_resume(struct device *dev) 2086 { 2087 struct uart_port *port = s3c24xx_dev_to_port(dev); 2088 struct s3c24xx_uart_port *ourport = to_ourport(port); 2089 2090 if (port) { 2091 clk_prepare_enable(ourport->clk); 2092 if (!IS_ERR(ourport->baudclk)) 2093 clk_prepare_enable(ourport->baudclk); 2094 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port)); 2095 if (!IS_ERR(ourport->baudclk)) 2096 clk_disable_unprepare(ourport->baudclk); 2097 clk_disable_unprepare(ourport->clk); 2098 2099 uart_resume_port(&s3c24xx_uart_drv, port); 2100 } 2101 2102 return 0; 2103 } 2104 2105 static int s3c24xx_serial_resume_noirq(struct device *dev) 2106 { 2107 struct uart_port *port = s3c24xx_dev_to_port(dev); 2108 struct s3c24xx_uart_port *ourport = to_ourport(port); 2109 2110 if (port) { 2111 /* restore IRQ mask */ 2112 switch (ourport->info->type) { 2113 case TYPE_S3C6400: { 2114 u32 uintm = 0xf; 2115 2116 if (ourport->tx_enabled) 2117 uintm &= ~S3C64XX_UINTM_TXD_MSK; 2118 if (ourport->rx_enabled) 2119 uintm &= ~S3C64XX_UINTM_RXD_MSK; 2120 clk_prepare_enable(ourport->clk); 2121 if (!IS_ERR(ourport->baudclk)) 2122 clk_prepare_enable(ourport->baudclk); 2123 wr_regl(port, S3C64XX_UINTM, uintm); 2124 if (!IS_ERR(ourport->baudclk)) 2125 clk_disable_unprepare(ourport->baudclk); 2126 clk_disable_unprepare(ourport->clk); 2127 break; 2128 } 2129 case TYPE_APPLE_S5L: { 2130 u32 ucon; 2131 int ret; 2132 2133 ret = clk_prepare_enable(ourport->clk); 2134 if (ret) { 2135 dev_err(dev, "clk_enable clk failed: %d\n", ret); 2136 return ret; 2137 } 2138 if (!IS_ERR(ourport->baudclk)) { 2139 ret = clk_prepare_enable(ourport->baudclk); 2140 if (ret) { 2141 dev_err(dev, "clk_enable baudclk failed: %d\n", ret); 2142 clk_disable_unprepare(ourport->clk); 2143 return ret; 2144 } 2145 } 2146 2147 ucon = rd_regl(port, S3C2410_UCON); 2148 2149 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | 2150 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 2151 APPLE_S5L_UCON_RXTO_ENA_MSK); 2152 2153 if (ourport->tx_enabled) 2154 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK; 2155 if (ourport->rx_enabled) 2156 ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 2157 APPLE_S5L_UCON_RXTO_ENA_MSK; 2158 2159 wr_regl(port, S3C2410_UCON, ucon); 2160 2161 if (!IS_ERR(ourport->baudclk)) 2162 clk_disable_unprepare(ourport->baudclk); 2163 clk_disable_unprepare(ourport->clk); 2164 break; 2165 } 2166 default: 2167 break; 2168 } 2169 } 2170 2171 return 0; 2172 } 2173 2174 static const struct dev_pm_ops s3c24xx_serial_pm_ops = { 2175 SET_SYSTEM_SLEEP_PM_OPS(s3c24xx_serial_suspend, s3c24xx_serial_resume) 2176 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, s3c24xx_serial_resume_noirq) 2177 }; 2178 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops) 2179 2180 #else /* !CONFIG_PM_SLEEP */ 2181 2182 #define SERIAL_SAMSUNG_PM_OPS NULL 2183 #endif /* CONFIG_PM_SLEEP */ 2184 2185 /* Console code */ 2186 2187 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 2188 2189 static struct uart_port *cons_uart; 2190 2191 static bool 2192 s3c24xx_serial_console_txrdy(struct uart_port *port, u32 ufcon) 2193 { 2194 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 2195 u32 ufstat, utrstat; 2196 2197 if (ufcon & S3C2410_UFCON_FIFOMODE) { 2198 /* fifo mode - check amount of data in fifo registers... */ 2199 2200 ufstat = rd_regl(port, S3C2410_UFSTAT); 2201 return !(ufstat & info->tx_fifofull); 2202 } 2203 2204 /* in non-fifo mode, we go and use the tx buffer empty */ 2205 2206 utrstat = rd_regl(port, S3C2410_UTRSTAT); 2207 return utrstat & S3C2410_UTRSTAT_TXE; 2208 } 2209 2210 static bool 2211 s3c24xx_port_configured(u32 ucon) 2212 { 2213 /* consider the serial port configured if the tx/rx mode set */ 2214 return (ucon & 0xf) != 0; 2215 } 2216 2217 #ifdef CONFIG_CONSOLE_POLL 2218 /* 2219 * Console polling routines for writing and reading from the uart while 2220 * in an interrupt or debug context. 2221 */ 2222 2223 static int s3c24xx_serial_get_poll_char(struct uart_port *port) 2224 { 2225 const struct s3c24xx_uart_port *ourport = to_ourport(port); 2226 u32 ufstat; 2227 2228 ufstat = rd_regl(port, S3C2410_UFSTAT); 2229 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0) 2230 return NO_POLL_CHAR; 2231 2232 return rd_reg(port, S3C2410_URXH); 2233 } 2234 2235 static void s3c24xx_serial_put_poll_char(struct uart_port *port, 2236 unsigned char c) 2237 { 2238 u32 ufcon = rd_regl(port, S3C2410_UFCON); 2239 u32 ucon = rd_regl(port, S3C2410_UCON); 2240 2241 /* not possible to xmit on unconfigured port */ 2242 if (!s3c24xx_port_configured(ucon)) 2243 return; 2244 2245 while (!s3c24xx_serial_console_txrdy(port, ufcon)) 2246 cpu_relax(); 2247 wr_reg(port, S3C2410_UTXH, c); 2248 } 2249 2250 #endif /* CONFIG_CONSOLE_POLL */ 2251 2252 static void 2253 s3c24xx_serial_console_putchar(struct uart_port *port, unsigned char ch) 2254 { 2255 u32 ufcon = rd_regl(port, S3C2410_UFCON); 2256 2257 while (!s3c24xx_serial_console_txrdy(port, ufcon)) 2258 cpu_relax(); 2259 wr_reg(port, S3C2410_UTXH, ch); 2260 } 2261 2262 static void 2263 s3c24xx_serial_console_write(struct console *co, const char *s, 2264 unsigned int count) 2265 { 2266 u32 ucon = rd_regl(cons_uart, S3C2410_UCON); 2267 unsigned long flags; 2268 bool locked = true; 2269 2270 /* not possible to xmit on unconfigured port */ 2271 if (!s3c24xx_port_configured(ucon)) 2272 return; 2273 2274 if (cons_uart->sysrq) 2275 locked = false; 2276 else if (oops_in_progress) 2277 locked = uart_port_trylock_irqsave(cons_uart, &flags); 2278 else 2279 uart_port_lock_irqsave(cons_uart, &flags); 2280 2281 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar); 2282 2283 if (locked) 2284 uart_port_unlock_irqrestore(cons_uart, flags); 2285 } 2286 2287 /* Shouldn't be __init, as it can be instantiated from other module */ 2288 static void 2289 s3c24xx_serial_get_options(struct uart_port *port, int *baud, 2290 int *parity, int *bits) 2291 { 2292 struct clk *clk; 2293 unsigned long rate; 2294 u32 ulcon, ucon, ubrdiv; 2295 char clk_name[MAX_CLK_NAME_LENGTH]; 2296 u8 clk_sel; 2297 2298 ulcon = rd_regl(port, S3C2410_ULCON); 2299 ucon = rd_regl(port, S3C2410_UCON); 2300 ubrdiv = rd_regl(port, S3C2410_UBRDIV); 2301 2302 if (s3c24xx_port_configured(ucon)) { 2303 switch (ulcon & S3C2410_LCON_CSMASK) { 2304 case S3C2410_LCON_CS5: 2305 *bits = 5; 2306 break; 2307 case S3C2410_LCON_CS6: 2308 *bits = 6; 2309 break; 2310 case S3C2410_LCON_CS7: 2311 *bits = 7; 2312 break; 2313 case S3C2410_LCON_CS8: 2314 default: 2315 *bits = 8; 2316 break; 2317 } 2318 2319 switch (ulcon & S3C2410_LCON_PMASK) { 2320 case S3C2410_LCON_PEVEN: 2321 *parity = 'e'; 2322 break; 2323 2324 case S3C2410_LCON_PODD: 2325 *parity = 'o'; 2326 break; 2327 2328 case S3C2410_LCON_PNONE: 2329 default: 2330 *parity = 'n'; 2331 } 2332 2333 /* now calculate the baud rate */ 2334 2335 clk_sel = s3c24xx_serial_getsource(port); 2336 sprintf(clk_name, "clk_uart_baud%d", clk_sel); 2337 2338 clk = clk_get(port->dev, clk_name); 2339 if (!IS_ERR(clk)) 2340 rate = clk_get_rate(clk); 2341 else 2342 rate = 1; 2343 2344 *baud = rate / (16 * (ubrdiv + 1)); 2345 dev_dbg(port->dev, "calculated baud %d\n", *baud); 2346 } 2347 } 2348 2349 /* Shouldn't be __init, as it can be instantiated from other module */ 2350 static int 2351 s3c24xx_serial_console_setup(struct console *co, char *options) 2352 { 2353 struct uart_port *port; 2354 int baud = 9600; 2355 int bits = 8; 2356 int parity = 'n'; 2357 int flow = 'n'; 2358 2359 /* is this a valid port */ 2360 2361 if (co->index == -1 || co->index >= UART_NR) 2362 co->index = 0; 2363 2364 port = &s3c24xx_serial_ports[co->index].port; 2365 2366 /* is the port configured? */ 2367 2368 if (port->mapbase == 0x0) 2369 return -ENODEV; 2370 2371 cons_uart = port; 2372 2373 /* 2374 * Check whether an invalid uart number has been specified, and 2375 * if so, search for the first available port that does have 2376 * console support. 2377 */ 2378 if (options) 2379 uart_parse_options(options, &baud, &parity, &bits, &flow); 2380 else 2381 s3c24xx_serial_get_options(port, &baud, &parity, &bits); 2382 2383 dev_dbg(port->dev, "baud %d\n", baud); 2384 2385 return uart_set_options(port, co, baud, parity, bits, flow); 2386 } 2387 2388 static struct console s3c24xx_serial_console = { 2389 .name = S3C24XX_SERIAL_NAME, 2390 .device = uart_console_device, 2391 .flags = CON_PRINTBUFFER, 2392 .index = -1, 2393 .write = s3c24xx_serial_console_write, 2394 .setup = s3c24xx_serial_console_setup, 2395 .data = &s3c24xx_uart_drv, 2396 }; 2397 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */ 2398 2399 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) 2400 static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = { 2401 .info = { 2402 .name = "Samsung S3C6400 UART", 2403 .type = TYPE_S3C6400, 2404 .port_type = PORT_S3C6400, 2405 .iotype = UPIO_MEM, 2406 .fifosize = 64, 2407 .has_divslot = true, 2408 .rx_fifomask = S3C2440_UFSTAT_RXMASK, 2409 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, 2410 .rx_fifofull = S3C2440_UFSTAT_RXFULL, 2411 .tx_fifofull = S3C2440_UFSTAT_TXFULL, 2412 .tx_fifomask = S3C2440_UFSTAT_TXMASK, 2413 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, 2414 .def_clk_sel = S3C2410_UCON_CLKSEL2, 2415 .num_clks = 4, 2416 .clksel_mask = S3C6400_UCON_CLKMASK, 2417 .clksel_shift = S3C6400_UCON_CLKSHIFT, 2418 }, 2419 .def_cfg = { 2420 .ucon = S3C2410_UCON_DEFAULT, 2421 .ufcon = S3C2410_UFCON_DEFAULT, 2422 }, 2423 }; 2424 #define S3C6400_SERIAL_DRV_DATA (&s3c6400_serial_drv_data) 2425 #else 2426 #define S3C6400_SERIAL_DRV_DATA NULL 2427 #endif 2428 2429 #ifdef CONFIG_CPU_S5PV210 2430 static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { 2431 .info = { 2432 .name = "Samsung S5PV210 UART", 2433 .type = TYPE_S3C6400, 2434 .port_type = PORT_S3C6400, 2435 .iotype = UPIO_MEM, 2436 .has_divslot = true, 2437 .rx_fifomask = S5PV210_UFSTAT_RXMASK, 2438 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, 2439 .rx_fifofull = S5PV210_UFSTAT_RXFULL, 2440 .tx_fifofull = S5PV210_UFSTAT_TXFULL, 2441 .tx_fifomask = S5PV210_UFSTAT_TXMASK, 2442 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, 2443 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2444 .num_clks = 2, 2445 .clksel_mask = S5PV210_UCON_CLKMASK, 2446 .clksel_shift = S5PV210_UCON_CLKSHIFT, 2447 }, 2448 .def_cfg = { 2449 .ucon = S5PV210_UCON_DEFAULT, 2450 .ufcon = S5PV210_UFCON_DEFAULT, 2451 }, 2452 .fifosize = { 256, 64, 16, 16 }, 2453 }; 2454 #define S5PV210_SERIAL_DRV_DATA (&s5pv210_serial_drv_data) 2455 #else 2456 #define S5PV210_SERIAL_DRV_DATA NULL 2457 #endif 2458 2459 #if defined(CONFIG_ARCH_EXYNOS) 2460 #define EXYNOS_COMMON_SERIAL_DRV_DATA \ 2461 .info = { \ 2462 .name = "Samsung Exynos UART", \ 2463 .type = TYPE_S3C6400, \ 2464 .port_type = PORT_S3C6400, \ 2465 .iotype = UPIO_MEM, \ 2466 .has_divslot = true, \ 2467 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ 2468 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \ 2469 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \ 2470 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \ 2471 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \ 2472 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \ 2473 .def_clk_sel = S3C2410_UCON_CLKSEL0, \ 2474 .num_clks = 1, \ 2475 .clksel_mask = 0, \ 2476 .clksel_shift = 0, \ 2477 }, \ 2478 .def_cfg = { \ 2479 .ucon = S5PV210_UCON_DEFAULT, \ 2480 .ufcon = S5PV210_UFCON_DEFAULT, \ 2481 .has_fracval = 1, \ 2482 } \ 2483 2484 static const struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = { 2485 EXYNOS_COMMON_SERIAL_DRV_DATA, 2486 .fifosize = { 256, 64, 16, 16 }, 2487 }; 2488 2489 static const struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = { 2490 EXYNOS_COMMON_SERIAL_DRV_DATA, 2491 .fifosize = { 64, 256, 16, 256 }, 2492 }; 2493 2494 static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = { 2495 EXYNOS_COMMON_SERIAL_DRV_DATA, 2496 .fifosize = { 256, 64, 64, 64 }, 2497 }; 2498 2499 static const struct s3c24xx_serial_drv_data gs101_serial_drv_data = { 2500 .info = { 2501 .name = "Google GS101 UART", 2502 .type = TYPE_S3C6400, 2503 .port_type = PORT_S3C6400, 2504 .iotype = UPIO_MEM32, 2505 .has_divslot = true, 2506 .rx_fifomask = S5PV210_UFSTAT_RXMASK, 2507 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, 2508 .rx_fifofull = S5PV210_UFSTAT_RXFULL, 2509 .tx_fifofull = S5PV210_UFSTAT_TXFULL, 2510 .tx_fifomask = S5PV210_UFSTAT_TXMASK, 2511 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, 2512 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2513 .num_clks = 1, 2514 .clksel_mask = 0, 2515 .clksel_shift = 0, 2516 }, 2517 .def_cfg = { 2518 .ucon = S5PV210_UCON_DEFAULT, 2519 .ufcon = S5PV210_UFCON_DEFAULT, 2520 .has_fracval = 1, 2521 }, 2522 /* samsung,uart-fifosize must be specified in the device tree. */ 2523 .fifosize = { 0 }, 2524 }; 2525 2526 #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data) 2527 #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data) 2528 #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data) 2529 #define GS101_SERIAL_DRV_DATA (&gs101_serial_drv_data) 2530 2531 #else 2532 #define EXYNOS4210_SERIAL_DRV_DATA NULL 2533 #define EXYNOS5433_SERIAL_DRV_DATA NULL 2534 #define EXYNOS850_SERIAL_DRV_DATA NULL 2535 #define GS101_SERIAL_DRV_DATA NULL 2536 #endif 2537 2538 #ifdef CONFIG_ARCH_APPLE 2539 static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = { 2540 .info = { 2541 .name = "Apple S5L UART", 2542 .type = TYPE_APPLE_S5L, 2543 .port_type = PORT_8250, 2544 .iotype = UPIO_MEM, 2545 .fifosize = 16, 2546 .rx_fifomask = S3C2410_UFSTAT_RXMASK, 2547 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT, 2548 .rx_fifofull = S3C2410_UFSTAT_RXFULL, 2549 .tx_fifofull = S3C2410_UFSTAT_TXFULL, 2550 .tx_fifomask = S3C2410_UFSTAT_TXMASK, 2551 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT, 2552 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2553 .num_clks = 1, 2554 .clksel_mask = 0, 2555 .clksel_shift = 0, 2556 .ucon_mask = APPLE_S5L_UCON_MASK, 2557 }, 2558 .def_cfg = { 2559 .ucon = APPLE_S5L_UCON_DEFAULT, 2560 .ufcon = S3C2410_UFCON_DEFAULT, 2561 }, 2562 }; 2563 #define S5L_SERIAL_DRV_DATA (&s5l_serial_drv_data) 2564 #else 2565 #define S5L_SERIAL_DRV_DATA NULL 2566 #endif 2567 2568 #if defined(CONFIG_ARCH_ARTPEC) 2569 static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = { 2570 .info = { 2571 .name = "Axis ARTPEC-8 UART", 2572 .type = TYPE_S3C6400, 2573 .port_type = PORT_S3C6400, 2574 .iotype = UPIO_MEM, 2575 .fifosize = 64, 2576 .has_divslot = true, 2577 .rx_fifomask = S5PV210_UFSTAT_RXMASK, 2578 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, 2579 .rx_fifofull = S5PV210_UFSTAT_RXFULL, 2580 .tx_fifofull = S5PV210_UFSTAT_TXFULL, 2581 .tx_fifomask = S5PV210_UFSTAT_TXMASK, 2582 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, 2583 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2584 .num_clks = 1, 2585 .clksel_mask = 0, 2586 .clksel_shift = 0, 2587 }, 2588 .def_cfg = { 2589 .ucon = S5PV210_UCON_DEFAULT, 2590 .ufcon = S5PV210_UFCON_DEFAULT, 2591 .has_fracval = 1, 2592 } 2593 }; 2594 #define ARTPEC8_SERIAL_DRV_DATA (&artpec8_serial_drv_data) 2595 #else 2596 #define ARTPEC8_SERIAL_DRV_DATA (NULL) 2597 #endif 2598 2599 static const struct platform_device_id s3c24xx_serial_driver_ids[] = { 2600 { 2601 .name = "s3c6400-uart", 2602 .driver_data = (kernel_ulong_t)S3C6400_SERIAL_DRV_DATA, 2603 }, { 2604 .name = "s5pv210-uart", 2605 .driver_data = (kernel_ulong_t)S5PV210_SERIAL_DRV_DATA, 2606 }, { 2607 .name = "exynos4210-uart", 2608 .driver_data = (kernel_ulong_t)EXYNOS4210_SERIAL_DRV_DATA, 2609 }, { 2610 .name = "exynos5433-uart", 2611 .driver_data = (kernel_ulong_t)EXYNOS5433_SERIAL_DRV_DATA, 2612 }, { 2613 .name = "s5l-uart", 2614 .driver_data = (kernel_ulong_t)S5L_SERIAL_DRV_DATA, 2615 }, { 2616 .name = "exynos850-uart", 2617 .driver_data = (kernel_ulong_t)EXYNOS850_SERIAL_DRV_DATA, 2618 }, { 2619 .name = "artpec8-uart", 2620 .driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA, 2621 }, { 2622 .name = "gs101-uart", 2623 .driver_data = (kernel_ulong_t)GS101_SERIAL_DRV_DATA, 2624 }, 2625 { }, 2626 }; 2627 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids); 2628 2629 #ifdef CONFIG_OF 2630 static const struct of_device_id s3c24xx_uart_dt_match[] = { 2631 { .compatible = "samsung,s3c6400-uart", 2632 .data = S3C6400_SERIAL_DRV_DATA }, 2633 { .compatible = "samsung,s5pv210-uart", 2634 .data = S5PV210_SERIAL_DRV_DATA }, 2635 { .compatible = "samsung,exynos4210-uart", 2636 .data = EXYNOS4210_SERIAL_DRV_DATA }, 2637 { .compatible = "samsung,exynos5433-uart", 2638 .data = EXYNOS5433_SERIAL_DRV_DATA }, 2639 { .compatible = "apple,s5l-uart", 2640 .data = S5L_SERIAL_DRV_DATA }, 2641 { .compatible = "samsung,exynos850-uart", 2642 .data = EXYNOS850_SERIAL_DRV_DATA }, 2643 { .compatible = "axis,artpec8-uart", 2644 .data = ARTPEC8_SERIAL_DRV_DATA }, 2645 { .compatible = "google,gs101-uart", 2646 .data = GS101_SERIAL_DRV_DATA }, 2647 {}, 2648 }; 2649 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); 2650 #endif 2651 2652 static struct platform_driver samsung_serial_driver = { 2653 .probe = s3c24xx_serial_probe, 2654 .remove_new = s3c24xx_serial_remove, 2655 .id_table = s3c24xx_serial_driver_ids, 2656 .driver = { 2657 .name = "samsung-uart", 2658 .pm = SERIAL_SAMSUNG_PM_OPS, 2659 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match), 2660 }, 2661 }; 2662 2663 static int __init samsung_serial_init(void) 2664 { 2665 int ret; 2666 2667 s3c24xx_serial_register_console(); 2668 2669 ret = platform_driver_register(&samsung_serial_driver); 2670 if (ret) { 2671 s3c24xx_serial_unregister_console(); 2672 return ret; 2673 } 2674 2675 return 0; 2676 } 2677 2678 static void __exit samsung_serial_exit(void) 2679 { 2680 platform_driver_unregister(&samsung_serial_driver); 2681 s3c24xx_serial_unregister_console(); 2682 } 2683 2684 module_init(samsung_serial_init); 2685 module_exit(samsung_serial_exit); 2686 2687 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 2688 /* 2689 * Early console. 2690 */ 2691 2692 static void wr_reg_barrier(const struct uart_port *port, u32 reg, u32 val) 2693 { 2694 switch (port->iotype) { 2695 case UPIO_MEM: 2696 writeb(val, portaddr(port, reg)); 2697 break; 2698 case UPIO_MEM32: 2699 writel(val, portaddr(port, reg)); 2700 break; 2701 } 2702 } 2703 2704 struct samsung_early_console_data { 2705 u32 txfull_mask; 2706 u32 rxfifo_mask; 2707 }; 2708 2709 static void samsung_early_busyuart(const struct uart_port *port) 2710 { 2711 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE)) 2712 ; 2713 } 2714 2715 static void samsung_early_busyuart_fifo(const struct uart_port *port) 2716 { 2717 const struct samsung_early_console_data *data = port->private_data; 2718 2719 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask) 2720 ; 2721 } 2722 2723 static void samsung_early_putc(struct uart_port *port, unsigned char c) 2724 { 2725 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) 2726 samsung_early_busyuart_fifo(port); 2727 else 2728 samsung_early_busyuart(port); 2729 2730 wr_reg_barrier(port, S3C2410_UTXH, c); 2731 } 2732 2733 static void samsung_early_write(struct console *con, const char *s, 2734 unsigned int n) 2735 { 2736 struct earlycon_device *dev = con->data; 2737 2738 uart_console_write(&dev->port, s, n, samsung_early_putc); 2739 } 2740 2741 static int samsung_early_read(struct console *con, char *s, unsigned int n) 2742 { 2743 struct earlycon_device *dev = con->data; 2744 const struct samsung_early_console_data *data = dev->port.private_data; 2745 int num_read = 0; 2746 u32 ch, ufstat; 2747 2748 while (num_read < n) { 2749 ufstat = rd_regl(&dev->port, S3C2410_UFSTAT); 2750 if (!(ufstat & data->rxfifo_mask)) 2751 break; 2752 ch = rd_reg(&dev->port, S3C2410_URXH); 2753 if (ch == NO_POLL_CHAR) 2754 break; 2755 2756 s[num_read++] = ch; 2757 } 2758 2759 return num_read; 2760 } 2761 2762 static int __init samsung_early_console_setup(struct earlycon_device *device, 2763 const char *opt) 2764 { 2765 if (!device->port.membase) 2766 return -ENODEV; 2767 2768 device->con->write = samsung_early_write; 2769 device->con->read = samsung_early_read; 2770 return 0; 2771 } 2772 2773 /* S3C2410 */ 2774 static struct samsung_early_console_data s3c2410_early_console_data = { 2775 .txfull_mask = S3C2410_UFSTAT_TXFULL, 2776 .rxfifo_mask = S3C2410_UFSTAT_RXFULL | S3C2410_UFSTAT_RXMASK, 2777 }; 2778 2779 /* S3C64xx */ 2780 static struct samsung_early_console_data s3c2440_early_console_data = { 2781 .txfull_mask = S3C2440_UFSTAT_TXFULL, 2782 .rxfifo_mask = S3C2440_UFSTAT_RXFULL | S3C2440_UFSTAT_RXMASK, 2783 }; 2784 2785 static int __init s3c2440_early_console_setup(struct earlycon_device *device, 2786 const char *opt) 2787 { 2788 device->port.private_data = &s3c2440_early_console_data; 2789 return samsung_early_console_setup(device, opt); 2790 } 2791 2792 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart", 2793 s3c2440_early_console_setup); 2794 2795 /* S5PV210, Exynos */ 2796 static struct samsung_early_console_data s5pv210_early_console_data = { 2797 .txfull_mask = S5PV210_UFSTAT_TXFULL, 2798 .rxfifo_mask = S5PV210_UFSTAT_RXFULL | S5PV210_UFSTAT_RXMASK, 2799 }; 2800 2801 static int __init s5pv210_early_console_setup(struct earlycon_device *device, 2802 const char *opt) 2803 { 2804 device->port.private_data = &s5pv210_early_console_data; 2805 return samsung_early_console_setup(device, opt); 2806 } 2807 2808 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart", 2809 s5pv210_early_console_setup); 2810 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart", 2811 s5pv210_early_console_setup); 2812 OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart", 2813 s5pv210_early_console_setup); 2814 2815 static int __init gs101_early_console_setup(struct earlycon_device *device, 2816 const char *opt) 2817 { 2818 /* gs101 always expects MMIO32 register accesses. */ 2819 device->port.iotype = UPIO_MEM32; 2820 2821 return s5pv210_early_console_setup(device, opt); 2822 } 2823 2824 OF_EARLYCON_DECLARE(gs101, "google,gs101-uart", gs101_early_console_setup); 2825 2826 /* Apple S5L */ 2827 static int __init apple_s5l_early_console_setup(struct earlycon_device *device, 2828 const char *opt) 2829 { 2830 /* Close enough to S3C2410 for earlycon... */ 2831 device->port.private_data = &s3c2410_early_console_data; 2832 2833 #ifdef CONFIG_ARM64 2834 /* ... but we need to override the existing fixmap entry as nGnRnE */ 2835 __set_fixmap(FIX_EARLYCON_MEM_BASE, device->port.mapbase, 2836 __pgprot(PROT_DEVICE_nGnRnE)); 2837 #endif 2838 return samsung_early_console_setup(device, opt); 2839 } 2840 2841 OF_EARLYCON_DECLARE(s5l, "apple,s5l-uart", apple_s5l_early_console_setup); 2842 #endif 2843 2844 MODULE_ALIAS("platform:samsung-uart"); 2845 MODULE_DESCRIPTION("Samsung SoC Serial port driver"); 2846 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); 2847 MODULE_LICENSE("GPL v2"); 2848