1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver core for Samsung SoC onboard UARTs. 4 * 5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics 6 * http://armlinux.simtec.co.uk/ 7 */ 8 9 /* Note on 2410 error handling 10 * 11 * The s3c2410 manual has a love/hate affair with the contents of the 12 * UERSTAT register in the UART blocks, and keeps marking some of the 13 * error bits as reserved. Having checked with the s3c2410x01, 14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED 15 * feature from the latter versions of the manual. 16 * 17 * If it becomes aparrent that latter versions of the 2410 remove these 18 * bits, then action will have to be taken to differentiate the versions 19 * and change the policy on BREAK 20 * 21 * BJD, 04-Nov-2004 22 */ 23 24 #include <linux/dmaengine.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/slab.h> 27 #include <linux/module.h> 28 #include <linux/ioport.h> 29 #include <linux/io.h> 30 #include <linux/platform_device.h> 31 #include <linux/init.h> 32 #include <linux/sysrq.h> 33 #include <linux/console.h> 34 #include <linux/tty.h> 35 #include <linux/tty_flip.h> 36 #include <linux/serial_core.h> 37 #include <linux/serial.h> 38 #include <linux/serial_s3c.h> 39 #include <linux/delay.h> 40 #include <linux/clk.h> 41 #include <linux/cpufreq.h> 42 #include <linux/of.h> 43 #include <asm/irq.h> 44 45 /* UART name and device definitions */ 46 47 #define S3C24XX_SERIAL_NAME "ttySAC" 48 #define S3C24XX_SERIAL_MAJOR 204 49 #define S3C24XX_SERIAL_MINOR 64 50 51 #define S3C24XX_TX_PIO 1 52 #define S3C24XX_TX_DMA 2 53 #define S3C24XX_RX_PIO 1 54 #define S3C24XX_RX_DMA 2 55 56 /* flag to ignore all characters coming in */ 57 #define RXSTAT_DUMMY_READ (0x10000000) 58 59 enum s3c24xx_port_type { 60 TYPE_S3C24XX, 61 TYPE_S3C6400, 62 TYPE_APPLE_S5L, 63 }; 64 65 struct s3c24xx_uart_info { 66 char *name; 67 enum s3c24xx_port_type type; 68 unsigned int port_type; 69 unsigned int fifosize; 70 unsigned long rx_fifomask; 71 unsigned long rx_fifoshift; 72 unsigned long rx_fifofull; 73 unsigned long tx_fifomask; 74 unsigned long tx_fifoshift; 75 unsigned long tx_fifofull; 76 unsigned int def_clk_sel; 77 unsigned long num_clks; 78 unsigned long clksel_mask; 79 unsigned long clksel_shift; 80 unsigned long ucon_mask; 81 82 /* uart port features */ 83 84 unsigned int has_divslot:1; 85 }; 86 87 struct s3c24xx_serial_drv_data { 88 struct s3c24xx_uart_info *info; 89 struct s3c2410_uartcfg *def_cfg; 90 unsigned int fifosize[CONFIG_SERIAL_SAMSUNG_UARTS]; 91 }; 92 93 struct s3c24xx_uart_dma { 94 unsigned int rx_chan_id; 95 unsigned int tx_chan_id; 96 97 struct dma_slave_config rx_conf; 98 struct dma_slave_config tx_conf; 99 100 struct dma_chan *rx_chan; 101 struct dma_chan *tx_chan; 102 103 dma_addr_t rx_addr; 104 dma_addr_t tx_addr; 105 106 dma_cookie_t rx_cookie; 107 dma_cookie_t tx_cookie; 108 109 char *rx_buf; 110 111 dma_addr_t tx_transfer_addr; 112 113 size_t rx_size; 114 size_t tx_size; 115 116 struct dma_async_tx_descriptor *tx_desc; 117 struct dma_async_tx_descriptor *rx_desc; 118 119 int tx_bytes_requested; 120 int rx_bytes_requested; 121 }; 122 123 struct s3c24xx_uart_port { 124 unsigned char rx_claimed; 125 unsigned char tx_claimed; 126 unsigned char rx_enabled; 127 unsigned char tx_enabled; 128 unsigned int pm_level; 129 unsigned long baudclk_rate; 130 unsigned int min_dma_size; 131 132 unsigned int rx_irq; 133 unsigned int tx_irq; 134 135 unsigned int tx_in_progress; 136 unsigned int tx_mode; 137 unsigned int rx_mode; 138 139 struct s3c24xx_uart_info *info; 140 struct clk *clk; 141 struct clk *baudclk; 142 struct uart_port port; 143 struct s3c24xx_serial_drv_data *drv_data; 144 145 /* reference to platform data */ 146 struct s3c2410_uartcfg *cfg; 147 148 struct s3c24xx_uart_dma *dma; 149 150 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ 151 struct notifier_block freq_transition; 152 #endif 153 }; 154 155 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport); 156 157 /* conversion functions */ 158 159 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev) 160 161 /* register access controls */ 162 163 #define portaddr(port, reg) ((port)->membase + (reg)) 164 #define portaddrl(port, reg) \ 165 ((unsigned long *)(unsigned long)((port)->membase + (reg))) 166 167 static u32 rd_reg(struct uart_port *port, u32 reg) 168 { 169 switch (port->iotype) { 170 case UPIO_MEM: 171 return readb_relaxed(portaddr(port, reg)); 172 case UPIO_MEM32: 173 return readl_relaxed(portaddr(port, reg)); 174 default: 175 return 0; 176 } 177 return 0; 178 } 179 180 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg))) 181 182 static void wr_reg(struct uart_port *port, u32 reg, u32 val) 183 { 184 switch (port->iotype) { 185 case UPIO_MEM: 186 writeb_relaxed(val, portaddr(port, reg)); 187 break; 188 case UPIO_MEM32: 189 writel_relaxed(val, portaddr(port, reg)); 190 break; 191 } 192 } 193 194 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg)) 195 196 /* Byte-order aware bit setting/clearing functions. */ 197 198 static inline void s3c24xx_set_bit(struct uart_port *port, int idx, 199 unsigned int reg) 200 { 201 unsigned long flags; 202 u32 val; 203 204 local_irq_save(flags); 205 val = rd_regl(port, reg); 206 val |= (1 << idx); 207 wr_regl(port, reg, val); 208 local_irq_restore(flags); 209 } 210 211 static inline void s3c24xx_clear_bit(struct uart_port *port, int idx, 212 unsigned int reg) 213 { 214 unsigned long flags; 215 u32 val; 216 217 local_irq_save(flags); 218 val = rd_regl(port, reg); 219 val &= ~(1 << idx); 220 wr_regl(port, reg, val); 221 local_irq_restore(flags); 222 } 223 224 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port) 225 { 226 return container_of(port, struct s3c24xx_uart_port, port); 227 } 228 229 /* translate a port to the device name */ 230 231 static inline const char *s3c24xx_serial_portname(struct uart_port *port) 232 { 233 return to_platform_device(port->dev)->name; 234 } 235 236 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port) 237 { 238 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE; 239 } 240 241 static void s3c24xx_serial_rx_enable(struct uart_port *port) 242 { 243 struct s3c24xx_uart_port *ourport = to_ourport(port); 244 unsigned long flags; 245 unsigned int ucon, ufcon; 246 int count = 10000; 247 248 spin_lock_irqsave(&port->lock, flags); 249 250 while (--count && !s3c24xx_serial_txempty_nofifo(port)) 251 udelay(100); 252 253 ufcon = rd_regl(port, S3C2410_UFCON); 254 ufcon |= S3C2410_UFCON_RESETRX; 255 wr_regl(port, S3C2410_UFCON, ufcon); 256 257 ucon = rd_regl(port, S3C2410_UCON); 258 ucon |= S3C2410_UCON_RXIRQMODE; 259 wr_regl(port, S3C2410_UCON, ucon); 260 261 ourport->rx_enabled = 1; 262 spin_unlock_irqrestore(&port->lock, flags); 263 } 264 265 static void s3c24xx_serial_rx_disable(struct uart_port *port) 266 { 267 struct s3c24xx_uart_port *ourport = to_ourport(port); 268 unsigned long flags; 269 unsigned int ucon; 270 271 spin_lock_irqsave(&port->lock, flags); 272 273 ucon = rd_regl(port, S3C2410_UCON); 274 ucon &= ~S3C2410_UCON_RXIRQMODE; 275 wr_regl(port, S3C2410_UCON, ucon); 276 277 ourport->rx_enabled = 0; 278 spin_unlock_irqrestore(&port->lock, flags); 279 } 280 281 static void s3c24xx_serial_stop_tx(struct uart_port *port) 282 { 283 struct s3c24xx_uart_port *ourport = to_ourport(port); 284 struct s3c24xx_uart_dma *dma = ourport->dma; 285 struct circ_buf *xmit = &port->state->xmit; 286 struct dma_tx_state state; 287 int count; 288 289 if (!ourport->tx_enabled) 290 return; 291 292 switch (ourport->info->type) { 293 case TYPE_S3C6400: 294 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM); 295 break; 296 case TYPE_APPLE_S5L: 297 s3c24xx_clear_bit(port, APPLE_S5L_UCON_TXTHRESH_ENA, S3C2410_UCON); 298 break; 299 default: 300 disable_irq_nosync(ourport->tx_irq); 301 break; 302 } 303 304 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) { 305 dmaengine_pause(dma->tx_chan); 306 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state); 307 dmaengine_terminate_all(dma->tx_chan); 308 dma_sync_single_for_cpu(ourport->port.dev, 309 dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE); 310 async_tx_ack(dma->tx_desc); 311 count = dma->tx_bytes_requested - state.residue; 312 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 313 port->icount.tx += count; 314 } 315 316 ourport->tx_enabled = 0; 317 ourport->tx_in_progress = 0; 318 319 if (port->flags & UPF_CONS_FLOW) 320 s3c24xx_serial_rx_enable(port); 321 322 ourport->tx_mode = 0; 323 } 324 325 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport); 326 327 static void s3c24xx_serial_tx_dma_complete(void *args) 328 { 329 struct s3c24xx_uart_port *ourport = args; 330 struct uart_port *port = &ourport->port; 331 struct circ_buf *xmit = &port->state->xmit; 332 struct s3c24xx_uart_dma *dma = ourport->dma; 333 struct dma_tx_state state; 334 unsigned long flags; 335 int count; 336 337 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state); 338 count = dma->tx_bytes_requested - state.residue; 339 async_tx_ack(dma->tx_desc); 340 341 dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr, 342 dma->tx_size, DMA_TO_DEVICE); 343 344 spin_lock_irqsave(&port->lock, flags); 345 346 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 347 port->icount.tx += count; 348 ourport->tx_in_progress = 0; 349 350 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 351 uart_write_wakeup(port); 352 353 s3c24xx_serial_start_next_tx(ourport); 354 spin_unlock_irqrestore(&port->lock, flags); 355 } 356 357 static void enable_tx_dma(struct s3c24xx_uart_port *ourport) 358 { 359 struct uart_port *port = &ourport->port; 360 u32 ucon; 361 362 /* Mask Tx interrupt */ 363 switch (ourport->info->type) { 364 case TYPE_S3C6400: 365 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM); 366 break; 367 case TYPE_APPLE_S5L: 368 WARN_ON(1); // No DMA 369 break; 370 default: 371 disable_irq_nosync(ourport->tx_irq); 372 break; 373 } 374 375 /* Enable tx dma mode */ 376 ucon = rd_regl(port, S3C2410_UCON); 377 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK); 378 ucon |= (dma_get_cache_alignment() >= 16) ? 379 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1; 380 ucon |= S3C64XX_UCON_TXMODE_DMA; 381 wr_regl(port, S3C2410_UCON, ucon); 382 383 ourport->tx_mode = S3C24XX_TX_DMA; 384 } 385 386 static void enable_tx_pio(struct s3c24xx_uart_port *ourport) 387 { 388 struct uart_port *port = &ourport->port; 389 u32 ucon, ufcon; 390 391 /* Set ufcon txtrig */ 392 ourport->tx_in_progress = S3C24XX_TX_PIO; 393 ufcon = rd_regl(port, S3C2410_UFCON); 394 wr_regl(port, S3C2410_UFCON, ufcon); 395 396 /* Enable tx pio mode */ 397 ucon = rd_regl(port, S3C2410_UCON); 398 ucon &= ~(S3C64XX_UCON_TXMODE_MASK); 399 ucon |= S3C64XX_UCON_TXMODE_CPU; 400 wr_regl(port, S3C2410_UCON, ucon); 401 402 /* Unmask Tx interrupt */ 403 switch (ourport->info->type) { 404 case TYPE_S3C6400: 405 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD, 406 S3C64XX_UINTM); 407 break; 408 case TYPE_APPLE_S5L: 409 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK; 410 wr_regl(port, S3C2410_UCON, ucon); 411 break; 412 default: 413 enable_irq(ourport->tx_irq); 414 break; 415 } 416 417 ourport->tx_mode = S3C24XX_TX_PIO; 418 419 /* 420 * The Apple version only has edge triggered TX IRQs, so we need 421 * to kick off the process by sending some characters here. 422 */ 423 if (ourport->info->type == TYPE_APPLE_S5L) 424 s3c24xx_serial_tx_chars(ourport); 425 } 426 427 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport) 428 { 429 if (ourport->tx_mode != S3C24XX_TX_PIO) 430 enable_tx_pio(ourport); 431 } 432 433 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport, 434 unsigned int count) 435 { 436 struct uart_port *port = &ourport->port; 437 struct circ_buf *xmit = &port->state->xmit; 438 struct s3c24xx_uart_dma *dma = ourport->dma; 439 440 if (ourport->tx_mode != S3C24XX_TX_DMA) 441 enable_tx_dma(ourport); 442 443 dma->tx_size = count & ~(dma_get_cache_alignment() - 1); 444 dma->tx_transfer_addr = dma->tx_addr + xmit->tail; 445 446 dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr, 447 dma->tx_size, DMA_TO_DEVICE); 448 449 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan, 450 dma->tx_transfer_addr, dma->tx_size, 451 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 452 if (!dma->tx_desc) { 453 dev_err(ourport->port.dev, "Unable to get desc for Tx\n"); 454 return -EIO; 455 } 456 457 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete; 458 dma->tx_desc->callback_param = ourport; 459 dma->tx_bytes_requested = dma->tx_size; 460 461 ourport->tx_in_progress = S3C24XX_TX_DMA; 462 dma->tx_cookie = dmaengine_submit(dma->tx_desc); 463 dma_async_issue_pending(dma->tx_chan); 464 return 0; 465 } 466 467 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport) 468 { 469 struct uart_port *port = &ourport->port; 470 struct circ_buf *xmit = &port->state->xmit; 471 unsigned long count; 472 473 /* Get data size up to the end of buffer */ 474 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 475 476 if (!count) { 477 s3c24xx_serial_stop_tx(port); 478 return; 479 } 480 481 if (!ourport->dma || !ourport->dma->tx_chan || 482 count < ourport->min_dma_size || 483 xmit->tail & (dma_get_cache_alignment() - 1)) 484 s3c24xx_serial_start_tx_pio(ourport); 485 else 486 s3c24xx_serial_start_tx_dma(ourport, count); 487 } 488 489 static void s3c24xx_serial_start_tx(struct uart_port *port) 490 { 491 struct s3c24xx_uart_port *ourport = to_ourport(port); 492 struct circ_buf *xmit = &port->state->xmit; 493 494 if (!ourport->tx_enabled) { 495 if (port->flags & UPF_CONS_FLOW) 496 s3c24xx_serial_rx_disable(port); 497 498 ourport->tx_enabled = 1; 499 if (!ourport->dma || !ourport->dma->tx_chan) 500 s3c24xx_serial_start_tx_pio(ourport); 501 } 502 503 if (ourport->dma && ourport->dma->tx_chan) { 504 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress) 505 s3c24xx_serial_start_next_tx(ourport); 506 } 507 } 508 509 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport, 510 struct tty_port *tty, int count) 511 { 512 struct s3c24xx_uart_dma *dma = ourport->dma; 513 int copied; 514 515 if (!count) 516 return; 517 518 dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr, 519 dma->rx_size, DMA_FROM_DEVICE); 520 521 ourport->port.icount.rx += count; 522 if (!tty) { 523 dev_err(ourport->port.dev, "No tty port\n"); 524 return; 525 } 526 copied = tty_insert_flip_string(tty, 527 ((unsigned char *)(ourport->dma->rx_buf)), count); 528 if (copied != count) { 529 WARN_ON(1); 530 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n"); 531 } 532 } 533 534 static void s3c24xx_serial_stop_rx(struct uart_port *port) 535 { 536 struct s3c24xx_uart_port *ourport = to_ourport(port); 537 struct s3c24xx_uart_dma *dma = ourport->dma; 538 struct tty_port *t = &port->state->port; 539 struct dma_tx_state state; 540 enum dma_status dma_status; 541 unsigned int received; 542 543 if (ourport->rx_enabled) { 544 dev_dbg(port->dev, "stopping rx\n"); 545 switch (ourport->info->type) { 546 case TYPE_S3C6400: 547 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD, 548 S3C64XX_UINTM); 549 break; 550 case TYPE_APPLE_S5L: 551 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON); 552 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON); 553 break; 554 default: 555 disable_irq_nosync(ourport->rx_irq); 556 break; 557 } 558 ourport->rx_enabled = 0; 559 } 560 if (dma && dma->rx_chan) { 561 dmaengine_pause(dma->tx_chan); 562 dma_status = dmaengine_tx_status(dma->rx_chan, 563 dma->rx_cookie, &state); 564 if (dma_status == DMA_IN_PROGRESS || 565 dma_status == DMA_PAUSED) { 566 received = dma->rx_bytes_requested - state.residue; 567 dmaengine_terminate_all(dma->rx_chan); 568 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 569 } 570 } 571 } 572 573 static inline struct s3c24xx_uart_info 574 *s3c24xx_port_to_info(struct uart_port *port) 575 { 576 return to_ourport(port)->info; 577 } 578 579 static inline struct s3c2410_uartcfg 580 *s3c24xx_port_to_cfg(struct uart_port *port) 581 { 582 struct s3c24xx_uart_port *ourport; 583 584 if (port->dev == NULL) 585 return NULL; 586 587 ourport = container_of(port, struct s3c24xx_uart_port, port); 588 return ourport->cfg; 589 } 590 591 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport, 592 unsigned long ufstat) 593 { 594 struct s3c24xx_uart_info *info = ourport->info; 595 596 if (ufstat & info->rx_fifofull) 597 return ourport->port.fifosize; 598 599 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift; 600 } 601 602 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport); 603 static void s3c24xx_serial_rx_dma_complete(void *args) 604 { 605 struct s3c24xx_uart_port *ourport = args; 606 struct uart_port *port = &ourport->port; 607 608 struct s3c24xx_uart_dma *dma = ourport->dma; 609 struct tty_port *t = &port->state->port; 610 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port); 611 612 struct dma_tx_state state; 613 unsigned long flags; 614 int received; 615 616 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state); 617 received = dma->rx_bytes_requested - state.residue; 618 async_tx_ack(dma->rx_desc); 619 620 spin_lock_irqsave(&port->lock, flags); 621 622 if (received) 623 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 624 625 if (tty) { 626 tty_flip_buffer_push(t); 627 tty_kref_put(tty); 628 } 629 630 s3c64xx_start_rx_dma(ourport); 631 632 spin_unlock_irqrestore(&port->lock, flags); 633 } 634 635 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport) 636 { 637 struct s3c24xx_uart_dma *dma = ourport->dma; 638 639 dma_sync_single_for_device(ourport->port.dev, dma->rx_addr, 640 dma->rx_size, DMA_FROM_DEVICE); 641 642 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan, 643 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM, 644 DMA_PREP_INTERRUPT); 645 if (!dma->rx_desc) { 646 dev_err(ourport->port.dev, "Unable to get desc for Rx\n"); 647 return; 648 } 649 650 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete; 651 dma->rx_desc->callback_param = ourport; 652 dma->rx_bytes_requested = dma->rx_size; 653 654 dma->rx_cookie = dmaengine_submit(dma->rx_desc); 655 dma_async_issue_pending(dma->rx_chan); 656 } 657 658 /* ? - where has parity gone?? */ 659 #define S3C2410_UERSTAT_PARITY (0x1000) 660 661 static void enable_rx_dma(struct s3c24xx_uart_port *ourport) 662 { 663 struct uart_port *port = &ourport->port; 664 unsigned int ucon; 665 666 /* set Rx mode to DMA mode */ 667 ucon = rd_regl(port, S3C2410_UCON); 668 ucon &= ~(S3C64XX_UCON_RXBURST_MASK | 669 S3C64XX_UCON_TIMEOUT_MASK | 670 S3C64XX_UCON_EMPTYINT_EN | 671 S3C64XX_UCON_DMASUS_EN | 672 S3C64XX_UCON_TIMEOUT_EN | 673 S3C64XX_UCON_RXMODE_MASK); 674 ucon |= S3C64XX_UCON_RXBURST_16 | 675 0xf << S3C64XX_UCON_TIMEOUT_SHIFT | 676 S3C64XX_UCON_EMPTYINT_EN | 677 S3C64XX_UCON_TIMEOUT_EN | 678 S3C64XX_UCON_RXMODE_DMA; 679 wr_regl(port, S3C2410_UCON, ucon); 680 681 ourport->rx_mode = S3C24XX_RX_DMA; 682 } 683 684 static void enable_rx_pio(struct s3c24xx_uart_port *ourport) 685 { 686 struct uart_port *port = &ourport->port; 687 unsigned int ucon; 688 689 /* set Rx mode to DMA mode */ 690 ucon = rd_regl(port, S3C2410_UCON); 691 ucon &= ~S3C64XX_UCON_RXMODE_MASK; 692 ucon |= S3C64XX_UCON_RXMODE_CPU; 693 694 /* Apple types use these bits for IRQ masks */ 695 if (ourport->info->type != TYPE_APPLE_S5L) { 696 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK | 697 S3C64XX_UCON_EMPTYINT_EN | 698 S3C64XX_UCON_DMASUS_EN | 699 S3C64XX_UCON_TIMEOUT_EN); 700 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT | 701 S3C64XX_UCON_TIMEOUT_EN; 702 } 703 wr_regl(port, S3C2410_UCON, ucon); 704 705 ourport->rx_mode = S3C24XX_RX_PIO; 706 } 707 708 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport); 709 710 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id) 711 { 712 unsigned int utrstat, received; 713 struct s3c24xx_uart_port *ourport = dev_id; 714 struct uart_port *port = &ourport->port; 715 struct s3c24xx_uart_dma *dma = ourport->dma; 716 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port); 717 struct tty_port *t = &port->state->port; 718 unsigned long flags; 719 struct dma_tx_state state; 720 721 utrstat = rd_regl(port, S3C2410_UTRSTAT); 722 rd_regl(port, S3C2410_UFSTAT); 723 724 spin_lock_irqsave(&port->lock, flags); 725 726 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) { 727 s3c64xx_start_rx_dma(ourport); 728 if (ourport->rx_mode == S3C24XX_RX_PIO) 729 enable_rx_dma(ourport); 730 goto finish; 731 } 732 733 if (ourport->rx_mode == S3C24XX_RX_DMA) { 734 dmaengine_pause(dma->rx_chan); 735 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state); 736 dmaengine_terminate_all(dma->rx_chan); 737 received = dma->rx_bytes_requested - state.residue; 738 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 739 740 enable_rx_pio(ourport); 741 } 742 743 s3c24xx_serial_rx_drain_fifo(ourport); 744 745 if (tty) { 746 tty_flip_buffer_push(t); 747 tty_kref_put(tty); 748 } 749 750 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT); 751 752 finish: 753 spin_unlock_irqrestore(&port->lock, flags); 754 755 return IRQ_HANDLED; 756 } 757 758 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport) 759 { 760 struct uart_port *port = &ourport->port; 761 unsigned int ufcon, ch, flag, ufstat, uerstat; 762 unsigned int fifocnt = 0; 763 int max_count = port->fifosize; 764 765 while (max_count-- > 0) { 766 /* 767 * Receive all characters known to be in FIFO 768 * before reading FIFO level again 769 */ 770 if (fifocnt == 0) { 771 ufstat = rd_regl(port, S3C2410_UFSTAT); 772 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat); 773 if (fifocnt == 0) 774 break; 775 } 776 fifocnt--; 777 778 uerstat = rd_regl(port, S3C2410_UERSTAT); 779 ch = rd_reg(port, S3C2410_URXH); 780 781 if (port->flags & UPF_CONS_FLOW) { 782 int txe = s3c24xx_serial_txempty_nofifo(port); 783 784 if (ourport->rx_enabled) { 785 if (!txe) { 786 ourport->rx_enabled = 0; 787 continue; 788 } 789 } else { 790 if (txe) { 791 ufcon = rd_regl(port, S3C2410_UFCON); 792 ufcon |= S3C2410_UFCON_RESETRX; 793 wr_regl(port, S3C2410_UFCON, ufcon); 794 ourport->rx_enabled = 1; 795 return; 796 } 797 continue; 798 } 799 } 800 801 /* insert the character into the buffer */ 802 803 flag = TTY_NORMAL; 804 port->icount.rx++; 805 806 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) { 807 dev_dbg(port->dev, 808 "rxerr: port ch=0x%02x, rxs=0x%08x\n", 809 ch, uerstat); 810 811 /* check for break */ 812 if (uerstat & S3C2410_UERSTAT_BREAK) { 813 dev_dbg(port->dev, "break!\n"); 814 port->icount.brk++; 815 if (uart_handle_break(port)) 816 continue; /* Ignore character */ 817 } 818 819 if (uerstat & S3C2410_UERSTAT_FRAME) 820 port->icount.frame++; 821 if (uerstat & S3C2410_UERSTAT_OVERRUN) 822 port->icount.overrun++; 823 824 uerstat &= port->read_status_mask; 825 826 if (uerstat & S3C2410_UERSTAT_BREAK) 827 flag = TTY_BREAK; 828 else if (uerstat & S3C2410_UERSTAT_PARITY) 829 flag = TTY_PARITY; 830 else if (uerstat & (S3C2410_UERSTAT_FRAME | 831 S3C2410_UERSTAT_OVERRUN)) 832 flag = TTY_FRAME; 833 } 834 835 if (uart_handle_sysrq_char(port, ch)) 836 continue; /* Ignore character */ 837 838 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, 839 ch, flag); 840 } 841 842 tty_flip_buffer_push(&port->state->port); 843 } 844 845 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id) 846 { 847 struct s3c24xx_uart_port *ourport = dev_id; 848 struct uart_port *port = &ourport->port; 849 unsigned long flags; 850 851 spin_lock_irqsave(&port->lock, flags); 852 s3c24xx_serial_rx_drain_fifo(ourport); 853 spin_unlock_irqrestore(&port->lock, flags); 854 855 return IRQ_HANDLED; 856 } 857 858 static irqreturn_t s3c24xx_serial_rx_irq(int irq, void *dev_id) 859 { 860 struct s3c24xx_uart_port *ourport = dev_id; 861 862 if (ourport->dma && ourport->dma->rx_chan) 863 return s3c24xx_serial_rx_chars_dma(dev_id); 864 return s3c24xx_serial_rx_chars_pio(dev_id); 865 } 866 867 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport) 868 { 869 struct uart_port *port = &ourport->port; 870 struct circ_buf *xmit = &port->state->xmit; 871 int count, dma_count = 0; 872 873 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 874 875 if (ourport->dma && ourport->dma->tx_chan && 876 count >= ourport->min_dma_size) { 877 int align = dma_get_cache_alignment() - 878 (xmit->tail & (dma_get_cache_alignment() - 1)); 879 if (count - align >= ourport->min_dma_size) { 880 dma_count = count - align; 881 count = align; 882 } 883 } 884 885 if (port->x_char) { 886 wr_reg(port, S3C2410_UTXH, port->x_char); 887 port->icount.tx++; 888 port->x_char = 0; 889 return; 890 } 891 892 /* if there isn't anything more to transmit, or the uart is now 893 * stopped, disable the uart and exit 894 */ 895 896 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 897 s3c24xx_serial_stop_tx(port); 898 return; 899 } 900 901 /* try and drain the buffer... */ 902 903 if (count > port->fifosize) { 904 count = port->fifosize; 905 dma_count = 0; 906 } 907 908 while (!uart_circ_empty(xmit) && count > 0) { 909 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull) 910 break; 911 912 wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]); 913 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 914 port->icount.tx++; 915 count--; 916 } 917 918 if (!count && dma_count) { 919 s3c24xx_serial_start_tx_dma(ourport, dma_count); 920 return; 921 } 922 923 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) { 924 spin_unlock(&port->lock); 925 uart_write_wakeup(port); 926 spin_lock(&port->lock); 927 } 928 929 if (uart_circ_empty(xmit)) 930 s3c24xx_serial_stop_tx(port); 931 } 932 933 static irqreturn_t s3c24xx_serial_tx_irq(int irq, void *id) 934 { 935 struct s3c24xx_uart_port *ourport = id; 936 struct uart_port *port = &ourport->port; 937 unsigned long flags; 938 939 spin_lock_irqsave(&port->lock, flags); 940 941 s3c24xx_serial_tx_chars(ourport); 942 943 spin_unlock_irqrestore(&port->lock, flags); 944 return IRQ_HANDLED; 945 } 946 947 /* interrupt handler for s3c64xx and later SoC's.*/ 948 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id) 949 { 950 struct s3c24xx_uart_port *ourport = id; 951 struct uart_port *port = &ourport->port; 952 unsigned int pend = rd_regl(port, S3C64XX_UINTP); 953 irqreturn_t ret = IRQ_HANDLED; 954 955 if (pend & S3C64XX_UINTM_RXD_MSK) { 956 ret = s3c24xx_serial_rx_irq(irq, id); 957 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK); 958 } 959 if (pend & S3C64XX_UINTM_TXD_MSK) { 960 ret = s3c24xx_serial_tx_irq(irq, id); 961 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK); 962 } 963 return ret; 964 } 965 966 /* interrupt handler for Apple SoC's.*/ 967 static irqreturn_t apple_serial_handle_irq(int irq, void *id) 968 { 969 struct s3c24xx_uart_port *ourport = id; 970 struct uart_port *port = &ourport->port; 971 unsigned int pend = rd_regl(port, S3C2410_UTRSTAT); 972 irqreturn_t ret = IRQ_NONE; 973 974 if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) { 975 wr_regl(port, S3C2410_UTRSTAT, 976 APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO); 977 ret = s3c24xx_serial_rx_irq(irq, id); 978 } 979 if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) { 980 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH); 981 ret = s3c24xx_serial_tx_irq(irq, id); 982 } 983 984 return ret; 985 } 986 987 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) 988 { 989 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 990 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT); 991 unsigned long ufcon = rd_regl(port, S3C2410_UFCON); 992 993 if (ufcon & S3C2410_UFCON_FIFOMODE) { 994 if ((ufstat & info->tx_fifomask) != 0 || 995 (ufstat & info->tx_fifofull)) 996 return 0; 997 998 return 1; 999 } 1000 1001 return s3c24xx_serial_txempty_nofifo(port); 1002 } 1003 1004 /* no modem control lines */ 1005 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) 1006 { 1007 unsigned int umstat = rd_reg(port, S3C2410_UMSTAT); 1008 1009 if (umstat & S3C2410_UMSTAT_CTS) 1010 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 1011 else 1012 return TIOCM_CAR | TIOCM_DSR; 1013 } 1014 1015 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) 1016 { 1017 unsigned int umcon = rd_regl(port, S3C2410_UMCON); 1018 1019 if (mctrl & TIOCM_RTS) 1020 umcon |= S3C2410_UMCOM_RTS_LOW; 1021 else 1022 umcon &= ~S3C2410_UMCOM_RTS_LOW; 1023 1024 wr_regl(port, S3C2410_UMCON, umcon); 1025 } 1026 1027 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state) 1028 { 1029 unsigned long flags; 1030 unsigned int ucon; 1031 1032 spin_lock_irqsave(&port->lock, flags); 1033 1034 ucon = rd_regl(port, S3C2410_UCON); 1035 1036 if (break_state) 1037 ucon |= S3C2410_UCON_SBREAK; 1038 else 1039 ucon &= ~S3C2410_UCON_SBREAK; 1040 1041 wr_regl(port, S3C2410_UCON, ucon); 1042 1043 spin_unlock_irqrestore(&port->lock, flags); 1044 } 1045 1046 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p) 1047 { 1048 struct s3c24xx_uart_dma *dma = p->dma; 1049 struct dma_slave_caps dma_caps; 1050 const char *reason = NULL; 1051 int ret; 1052 1053 /* Default slave configuration parameters */ 1054 dma->rx_conf.direction = DMA_DEV_TO_MEM; 1055 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1056 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH; 1057 dma->rx_conf.src_maxburst = 1; 1058 1059 dma->tx_conf.direction = DMA_MEM_TO_DEV; 1060 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1061 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH; 1062 dma->tx_conf.dst_maxburst = 1; 1063 1064 dma->rx_chan = dma_request_chan(p->port.dev, "rx"); 1065 1066 if (IS_ERR(dma->rx_chan)) { 1067 reason = "DMA RX channel request failed"; 1068 ret = PTR_ERR(dma->rx_chan); 1069 goto err_warn; 1070 } 1071 1072 ret = dma_get_slave_caps(dma->rx_chan, &dma_caps); 1073 if (ret < 0 || 1074 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) { 1075 reason = "insufficient DMA RX engine capabilities"; 1076 ret = -EOPNOTSUPP; 1077 goto err_release_rx; 1078 } 1079 1080 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf); 1081 1082 dma->tx_chan = dma_request_chan(p->port.dev, "tx"); 1083 if (IS_ERR(dma->tx_chan)) { 1084 reason = "DMA TX channel request failed"; 1085 ret = PTR_ERR(dma->tx_chan); 1086 goto err_release_rx; 1087 } 1088 1089 ret = dma_get_slave_caps(dma->tx_chan, &dma_caps); 1090 if (ret < 0 || 1091 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) { 1092 reason = "insufficient DMA TX engine capabilities"; 1093 ret = -EOPNOTSUPP; 1094 goto err_release_tx; 1095 } 1096 1097 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf); 1098 1099 /* RX buffer */ 1100 dma->rx_size = PAGE_SIZE; 1101 1102 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL); 1103 if (!dma->rx_buf) { 1104 ret = -ENOMEM; 1105 goto err_release_tx; 1106 } 1107 1108 dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf, 1109 dma->rx_size, DMA_FROM_DEVICE); 1110 if (dma_mapping_error(p->port.dev, dma->rx_addr)) { 1111 reason = "DMA mapping error for RX buffer"; 1112 ret = -EIO; 1113 goto err_free_rx; 1114 } 1115 1116 /* TX buffer */ 1117 dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf, 1118 UART_XMIT_SIZE, DMA_TO_DEVICE); 1119 if (dma_mapping_error(p->port.dev, dma->tx_addr)) { 1120 reason = "DMA mapping error for TX buffer"; 1121 ret = -EIO; 1122 goto err_unmap_rx; 1123 } 1124 1125 return 0; 1126 1127 err_unmap_rx: 1128 dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size, 1129 DMA_FROM_DEVICE); 1130 err_free_rx: 1131 kfree(dma->rx_buf); 1132 err_release_tx: 1133 dma_release_channel(dma->tx_chan); 1134 err_release_rx: 1135 dma_release_channel(dma->rx_chan); 1136 err_warn: 1137 if (reason) 1138 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason); 1139 return ret; 1140 } 1141 1142 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p) 1143 { 1144 struct s3c24xx_uart_dma *dma = p->dma; 1145 1146 if (dma->rx_chan) { 1147 dmaengine_terminate_all(dma->rx_chan); 1148 dma_unmap_single(p->port.dev, dma->rx_addr, 1149 dma->rx_size, DMA_FROM_DEVICE); 1150 kfree(dma->rx_buf); 1151 dma_release_channel(dma->rx_chan); 1152 dma->rx_chan = NULL; 1153 } 1154 1155 if (dma->tx_chan) { 1156 dmaengine_terminate_all(dma->tx_chan); 1157 dma_unmap_single(p->port.dev, dma->tx_addr, 1158 UART_XMIT_SIZE, DMA_TO_DEVICE); 1159 dma_release_channel(dma->tx_chan); 1160 dma->tx_chan = NULL; 1161 } 1162 } 1163 1164 static void s3c24xx_serial_shutdown(struct uart_port *port) 1165 { 1166 struct s3c24xx_uart_port *ourport = to_ourport(port); 1167 1168 if (ourport->tx_claimed) { 1169 free_irq(ourport->tx_irq, ourport); 1170 ourport->tx_enabled = 0; 1171 ourport->tx_claimed = 0; 1172 ourport->tx_mode = 0; 1173 } 1174 1175 if (ourport->rx_claimed) { 1176 free_irq(ourport->rx_irq, ourport); 1177 ourport->rx_claimed = 0; 1178 ourport->rx_enabled = 0; 1179 } 1180 1181 if (ourport->dma) 1182 s3c24xx_serial_release_dma(ourport); 1183 1184 ourport->tx_in_progress = 0; 1185 } 1186 1187 static void s3c64xx_serial_shutdown(struct uart_port *port) 1188 { 1189 struct s3c24xx_uart_port *ourport = to_ourport(port); 1190 1191 ourport->tx_enabled = 0; 1192 ourport->tx_mode = 0; 1193 ourport->rx_enabled = 0; 1194 1195 free_irq(port->irq, ourport); 1196 1197 wr_regl(port, S3C64XX_UINTP, 0xf); 1198 wr_regl(port, S3C64XX_UINTM, 0xf); 1199 1200 if (ourport->dma) 1201 s3c24xx_serial_release_dma(ourport); 1202 1203 ourport->tx_in_progress = 0; 1204 } 1205 1206 static void apple_s5l_serial_shutdown(struct uart_port *port) 1207 { 1208 struct s3c24xx_uart_port *ourport = to_ourport(port); 1209 1210 unsigned int ucon; 1211 1212 ucon = rd_regl(port, S3C2410_UCON); 1213 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | 1214 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 1215 APPLE_S5L_UCON_RXTO_ENA_MSK); 1216 wr_regl(port, S3C2410_UCON, ucon); 1217 1218 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS); 1219 1220 free_irq(port->irq, ourport); 1221 1222 ourport->tx_enabled = 0; 1223 ourport->tx_mode = 0; 1224 ourport->rx_enabled = 0; 1225 1226 if (ourport->dma) 1227 s3c24xx_serial_release_dma(ourport); 1228 1229 ourport->tx_in_progress = 0; 1230 } 1231 1232 static int s3c24xx_serial_startup(struct uart_port *port) 1233 { 1234 struct s3c24xx_uart_port *ourport = to_ourport(port); 1235 int ret; 1236 1237 ourport->rx_enabled = 1; 1238 1239 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_irq, 0, 1240 s3c24xx_serial_portname(port), ourport); 1241 1242 if (ret != 0) { 1243 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq); 1244 return ret; 1245 } 1246 1247 ourport->rx_claimed = 1; 1248 1249 dev_dbg(port->dev, "requesting tx irq...\n"); 1250 1251 ourport->tx_enabled = 1; 1252 1253 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_irq, 0, 1254 s3c24xx_serial_portname(port), ourport); 1255 1256 if (ret) { 1257 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq); 1258 goto err; 1259 } 1260 1261 ourport->tx_claimed = 1; 1262 1263 /* the port reset code should have done the correct 1264 * register setup for the port controls 1265 */ 1266 1267 return ret; 1268 1269 err: 1270 s3c24xx_serial_shutdown(port); 1271 return ret; 1272 } 1273 1274 static int s3c64xx_serial_startup(struct uart_port *port) 1275 { 1276 struct s3c24xx_uart_port *ourport = to_ourport(port); 1277 unsigned long flags; 1278 unsigned int ufcon; 1279 int ret; 1280 1281 wr_regl(port, S3C64XX_UINTM, 0xf); 1282 if (ourport->dma) { 1283 ret = s3c24xx_serial_request_dma(ourport); 1284 if (ret < 0) { 1285 devm_kfree(port->dev, ourport->dma); 1286 ourport->dma = NULL; 1287 } 1288 } 1289 1290 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED, 1291 s3c24xx_serial_portname(port), ourport); 1292 if (ret) { 1293 dev_err(port->dev, "cannot get irq %d\n", port->irq); 1294 return ret; 1295 } 1296 1297 /* For compatibility with s3c24xx Soc's */ 1298 ourport->rx_enabled = 1; 1299 ourport->tx_enabled = 0; 1300 1301 spin_lock_irqsave(&port->lock, flags); 1302 1303 ufcon = rd_regl(port, S3C2410_UFCON); 1304 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8; 1305 if (!uart_console(port)) 1306 ufcon |= S3C2410_UFCON_RESETTX; 1307 wr_regl(port, S3C2410_UFCON, ufcon); 1308 1309 enable_rx_pio(ourport); 1310 1311 spin_unlock_irqrestore(&port->lock, flags); 1312 1313 /* Enable Rx Interrupt */ 1314 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM); 1315 1316 return ret; 1317 } 1318 1319 static int apple_s5l_serial_startup(struct uart_port *port) 1320 { 1321 struct s3c24xx_uart_port *ourport = to_ourport(port); 1322 unsigned long flags; 1323 unsigned int ufcon; 1324 int ret; 1325 1326 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS); 1327 1328 ret = request_irq(port->irq, apple_serial_handle_irq, 0, 1329 s3c24xx_serial_portname(port), ourport); 1330 if (ret) { 1331 dev_err(port->dev, "cannot get irq %d\n", port->irq); 1332 return ret; 1333 } 1334 1335 /* For compatibility with s3c24xx Soc's */ 1336 ourport->rx_enabled = 1; 1337 ourport->tx_enabled = 0; 1338 1339 spin_lock_irqsave(&port->lock, flags); 1340 1341 ufcon = rd_regl(port, S3C2410_UFCON); 1342 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8; 1343 if (!uart_console(port)) 1344 ufcon |= S3C2410_UFCON_RESETTX; 1345 wr_regl(port, S3C2410_UFCON, ufcon); 1346 1347 enable_rx_pio(ourport); 1348 1349 spin_unlock_irqrestore(&port->lock, flags); 1350 1351 /* Enable Rx Interrupt */ 1352 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON); 1353 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON); 1354 1355 return ret; 1356 } 1357 1358 /* power power management control */ 1359 1360 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, 1361 unsigned int old) 1362 { 1363 struct s3c24xx_uart_port *ourport = to_ourport(port); 1364 int timeout = 10000; 1365 1366 ourport->pm_level = level; 1367 1368 switch (level) { 1369 case 3: 1370 while (--timeout && !s3c24xx_serial_txempty_nofifo(port)) 1371 udelay(100); 1372 1373 if (!IS_ERR(ourport->baudclk)) 1374 clk_disable_unprepare(ourport->baudclk); 1375 1376 clk_disable_unprepare(ourport->clk); 1377 break; 1378 1379 case 0: 1380 clk_prepare_enable(ourport->clk); 1381 1382 if (!IS_ERR(ourport->baudclk)) 1383 clk_prepare_enable(ourport->baudclk); 1384 1385 break; 1386 default: 1387 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level); 1388 } 1389 } 1390 1391 /* baud rate calculation 1392 * 1393 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number 1394 * of different sources, including the peripheral clock ("pclk") and an 1395 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk") 1396 * with a programmable extra divisor. 1397 * 1398 * The following code goes through the clock sources, and calculates the 1399 * baud clocks (and the resultant actual baud rates) and then tries to 1400 * pick the closest one and select that. 1401 * 1402 */ 1403 1404 #define MAX_CLK_NAME_LENGTH 15 1405 1406 static inline int s3c24xx_serial_getsource(struct uart_port *port) 1407 { 1408 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1409 unsigned int ucon; 1410 1411 if (info->num_clks == 1) 1412 return 0; 1413 1414 ucon = rd_regl(port, S3C2410_UCON); 1415 ucon &= info->clksel_mask; 1416 return ucon >> info->clksel_shift; 1417 } 1418 1419 static void s3c24xx_serial_setsource(struct uart_port *port, 1420 unsigned int clk_sel) 1421 { 1422 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1423 unsigned int ucon; 1424 1425 if (info->num_clks == 1) 1426 return; 1427 1428 ucon = rd_regl(port, S3C2410_UCON); 1429 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel) 1430 return; 1431 1432 ucon &= ~info->clksel_mask; 1433 ucon |= clk_sel << info->clksel_shift; 1434 wr_regl(port, S3C2410_UCON, ucon); 1435 } 1436 1437 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport, 1438 unsigned int req_baud, struct clk **best_clk, 1439 unsigned int *clk_num) 1440 { 1441 struct s3c24xx_uart_info *info = ourport->info; 1442 struct clk *clk; 1443 unsigned long rate; 1444 unsigned int cnt, baud, quot, best_quot = 0; 1445 char clkname[MAX_CLK_NAME_LENGTH]; 1446 int calc_deviation, deviation = (1 << 30) - 1; 1447 1448 for (cnt = 0; cnt < info->num_clks; cnt++) { 1449 /* Keep selected clock if provided */ 1450 if (ourport->cfg->clk_sel && 1451 !(ourport->cfg->clk_sel & (1 << cnt))) 1452 continue; 1453 1454 sprintf(clkname, "clk_uart_baud%d", cnt); 1455 clk = clk_get(ourport->port.dev, clkname); 1456 if (IS_ERR(clk)) 1457 continue; 1458 1459 rate = clk_get_rate(clk); 1460 if (!rate) 1461 continue; 1462 1463 if (ourport->info->has_divslot) { 1464 unsigned long div = rate / req_baud; 1465 1466 /* The UDIVSLOT register on the newer UARTs allows us to 1467 * get a divisor adjustment of 1/16th on the baud clock. 1468 * 1469 * We don't keep the UDIVSLOT value (the 16ths we 1470 * calculated by not multiplying the baud by 16) as it 1471 * is easy enough to recalculate. 1472 */ 1473 1474 quot = div / 16; 1475 baud = rate / div; 1476 } else { 1477 quot = (rate + (8 * req_baud)) / (16 * req_baud); 1478 baud = rate / (quot * 16); 1479 } 1480 quot--; 1481 1482 calc_deviation = req_baud - baud; 1483 if (calc_deviation < 0) 1484 calc_deviation = -calc_deviation; 1485 1486 if (calc_deviation < deviation) { 1487 *best_clk = clk; 1488 best_quot = quot; 1489 *clk_num = cnt; 1490 deviation = calc_deviation; 1491 } 1492 } 1493 1494 return best_quot; 1495 } 1496 1497 /* udivslot_table[] 1498 * 1499 * This table takes the fractional value of the baud divisor and gives 1500 * the recommended setting for the UDIVSLOT register. 1501 */ 1502 static u16 udivslot_table[16] = { 1503 [0] = 0x0000, 1504 [1] = 0x0080, 1505 [2] = 0x0808, 1506 [3] = 0x0888, 1507 [4] = 0x2222, 1508 [5] = 0x4924, 1509 [6] = 0x4A52, 1510 [7] = 0x54AA, 1511 [8] = 0x5555, 1512 [9] = 0xD555, 1513 [10] = 0xD5D5, 1514 [11] = 0xDDD5, 1515 [12] = 0xDDDD, 1516 [13] = 0xDFDD, 1517 [14] = 0xDFDF, 1518 [15] = 0xFFDF, 1519 }; 1520 1521 static void s3c24xx_serial_set_termios(struct uart_port *port, 1522 struct ktermios *termios, 1523 struct ktermios *old) 1524 { 1525 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port); 1526 struct s3c24xx_uart_port *ourport = to_ourport(port); 1527 struct clk *clk = ERR_PTR(-EINVAL); 1528 unsigned long flags; 1529 unsigned int baud, quot, clk_sel = 0; 1530 unsigned int ulcon; 1531 unsigned int umcon; 1532 unsigned int udivslot = 0; 1533 1534 /* 1535 * We don't support modem control lines. 1536 */ 1537 termios->c_cflag &= ~(HUPCL | CMSPAR); 1538 termios->c_cflag |= CLOCAL; 1539 1540 /* 1541 * Ask the core to calculate the divisor for us. 1542 */ 1543 1544 baud = uart_get_baud_rate(port, termios, old, 0, 3000000); 1545 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel); 1546 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) 1547 quot = port->custom_divisor; 1548 if (IS_ERR(clk)) 1549 return; 1550 1551 /* check to see if we need to change clock source */ 1552 1553 if (ourport->baudclk != clk) { 1554 clk_prepare_enable(clk); 1555 1556 s3c24xx_serial_setsource(port, clk_sel); 1557 1558 if (!IS_ERR(ourport->baudclk)) { 1559 clk_disable_unprepare(ourport->baudclk); 1560 ourport->baudclk = ERR_PTR(-EINVAL); 1561 } 1562 1563 ourport->baudclk = clk; 1564 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0; 1565 } 1566 1567 if (ourport->info->has_divslot) { 1568 unsigned int div = ourport->baudclk_rate / baud; 1569 1570 if (cfg->has_fracval) { 1571 udivslot = (div & 15); 1572 dev_dbg(port->dev, "fracval = %04x\n", udivslot); 1573 } else { 1574 udivslot = udivslot_table[div & 15]; 1575 dev_dbg(port->dev, "udivslot = %04x (div %d)\n", 1576 udivslot, div & 15); 1577 } 1578 } 1579 1580 switch (termios->c_cflag & CSIZE) { 1581 case CS5: 1582 dev_dbg(port->dev, "config: 5bits/char\n"); 1583 ulcon = S3C2410_LCON_CS5; 1584 break; 1585 case CS6: 1586 dev_dbg(port->dev, "config: 6bits/char\n"); 1587 ulcon = S3C2410_LCON_CS6; 1588 break; 1589 case CS7: 1590 dev_dbg(port->dev, "config: 7bits/char\n"); 1591 ulcon = S3C2410_LCON_CS7; 1592 break; 1593 case CS8: 1594 default: 1595 dev_dbg(port->dev, "config: 8bits/char\n"); 1596 ulcon = S3C2410_LCON_CS8; 1597 break; 1598 } 1599 1600 /* preserve original lcon IR settings */ 1601 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM); 1602 1603 if (termios->c_cflag & CSTOPB) 1604 ulcon |= S3C2410_LCON_STOPB; 1605 1606 if (termios->c_cflag & PARENB) { 1607 if (termios->c_cflag & PARODD) 1608 ulcon |= S3C2410_LCON_PODD; 1609 else 1610 ulcon |= S3C2410_LCON_PEVEN; 1611 } else { 1612 ulcon |= S3C2410_LCON_PNONE; 1613 } 1614 1615 spin_lock_irqsave(&port->lock, flags); 1616 1617 dev_dbg(port->dev, 1618 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n", 1619 ulcon, quot, udivslot); 1620 1621 wr_regl(port, S3C2410_ULCON, ulcon); 1622 wr_regl(port, S3C2410_UBRDIV, quot); 1623 1624 port->status &= ~UPSTAT_AUTOCTS; 1625 1626 umcon = rd_regl(port, S3C2410_UMCON); 1627 if (termios->c_cflag & CRTSCTS) { 1628 umcon |= S3C2410_UMCOM_AFC; 1629 /* Disable RTS when RX FIFO contains 63 bytes */ 1630 umcon &= ~S3C2412_UMCON_AFC_8; 1631 port->status = UPSTAT_AUTOCTS; 1632 } else { 1633 umcon &= ~S3C2410_UMCOM_AFC; 1634 } 1635 wr_regl(port, S3C2410_UMCON, umcon); 1636 1637 if (ourport->info->has_divslot) 1638 wr_regl(port, S3C2443_DIVSLOT, udivslot); 1639 1640 dev_dbg(port->dev, 1641 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n", 1642 rd_regl(port, S3C2410_ULCON), 1643 rd_regl(port, S3C2410_UCON), 1644 rd_regl(port, S3C2410_UFCON)); 1645 1646 /* 1647 * Update the per-port timeout. 1648 */ 1649 uart_update_timeout(port, termios->c_cflag, baud); 1650 1651 /* 1652 * Which character status flags are we interested in? 1653 */ 1654 port->read_status_mask = S3C2410_UERSTAT_OVERRUN; 1655 if (termios->c_iflag & INPCK) 1656 port->read_status_mask |= S3C2410_UERSTAT_FRAME | 1657 S3C2410_UERSTAT_PARITY; 1658 /* 1659 * Which character status flags should we ignore? 1660 */ 1661 port->ignore_status_mask = 0; 1662 if (termios->c_iflag & IGNPAR) 1663 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN; 1664 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR) 1665 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME; 1666 1667 /* 1668 * Ignore all characters if CREAD is not set. 1669 */ 1670 if ((termios->c_cflag & CREAD) == 0) 1671 port->ignore_status_mask |= RXSTAT_DUMMY_READ; 1672 1673 spin_unlock_irqrestore(&port->lock, flags); 1674 } 1675 1676 static const char *s3c24xx_serial_type(struct uart_port *port) 1677 { 1678 struct s3c24xx_uart_port *ourport = to_ourport(port); 1679 1680 switch (ourport->info->type) { 1681 case TYPE_S3C24XX: 1682 return "S3C24XX"; 1683 case TYPE_S3C6400: 1684 return "S3C6400/10"; 1685 case TYPE_APPLE_S5L: 1686 return "APPLE S5L"; 1687 default: 1688 return NULL; 1689 } 1690 } 1691 1692 static void s3c24xx_serial_config_port(struct uart_port *port, int flags) 1693 { 1694 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1695 1696 if (flags & UART_CONFIG_TYPE) 1697 port->type = info->port_type; 1698 } 1699 1700 /* 1701 * verify the new serial_struct (for TIOCSSERIAL). 1702 */ 1703 static int 1704 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser) 1705 { 1706 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1707 1708 if (ser->type != PORT_UNKNOWN && ser->type != info->port_type) 1709 return -EINVAL; 1710 1711 return 0; 1712 } 1713 1714 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 1715 1716 static struct console s3c24xx_serial_console; 1717 1718 static int __init s3c24xx_serial_console_init(void) 1719 { 1720 register_console(&s3c24xx_serial_console); 1721 return 0; 1722 } 1723 console_initcall(s3c24xx_serial_console_init); 1724 1725 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console 1726 #else 1727 #define S3C24XX_SERIAL_CONSOLE NULL 1728 #endif 1729 1730 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1731 static int s3c24xx_serial_get_poll_char(struct uart_port *port); 1732 static void s3c24xx_serial_put_poll_char(struct uart_port *port, 1733 unsigned char c); 1734 #endif 1735 1736 static const struct uart_ops s3c24xx_serial_ops = { 1737 .pm = s3c24xx_serial_pm, 1738 .tx_empty = s3c24xx_serial_tx_empty, 1739 .get_mctrl = s3c24xx_serial_get_mctrl, 1740 .set_mctrl = s3c24xx_serial_set_mctrl, 1741 .stop_tx = s3c24xx_serial_stop_tx, 1742 .start_tx = s3c24xx_serial_start_tx, 1743 .stop_rx = s3c24xx_serial_stop_rx, 1744 .break_ctl = s3c24xx_serial_break_ctl, 1745 .startup = s3c24xx_serial_startup, 1746 .shutdown = s3c24xx_serial_shutdown, 1747 .set_termios = s3c24xx_serial_set_termios, 1748 .type = s3c24xx_serial_type, 1749 .config_port = s3c24xx_serial_config_port, 1750 .verify_port = s3c24xx_serial_verify_port, 1751 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1752 .poll_get_char = s3c24xx_serial_get_poll_char, 1753 .poll_put_char = s3c24xx_serial_put_poll_char, 1754 #endif 1755 }; 1756 1757 static const struct uart_ops s3c64xx_serial_ops = { 1758 .pm = s3c24xx_serial_pm, 1759 .tx_empty = s3c24xx_serial_tx_empty, 1760 .get_mctrl = s3c24xx_serial_get_mctrl, 1761 .set_mctrl = s3c24xx_serial_set_mctrl, 1762 .stop_tx = s3c24xx_serial_stop_tx, 1763 .start_tx = s3c24xx_serial_start_tx, 1764 .stop_rx = s3c24xx_serial_stop_rx, 1765 .break_ctl = s3c24xx_serial_break_ctl, 1766 .startup = s3c64xx_serial_startup, 1767 .shutdown = s3c64xx_serial_shutdown, 1768 .set_termios = s3c24xx_serial_set_termios, 1769 .type = s3c24xx_serial_type, 1770 .config_port = s3c24xx_serial_config_port, 1771 .verify_port = s3c24xx_serial_verify_port, 1772 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1773 .poll_get_char = s3c24xx_serial_get_poll_char, 1774 .poll_put_char = s3c24xx_serial_put_poll_char, 1775 #endif 1776 }; 1777 1778 static const struct uart_ops apple_s5l_serial_ops = { 1779 .pm = s3c24xx_serial_pm, 1780 .tx_empty = s3c24xx_serial_tx_empty, 1781 .get_mctrl = s3c24xx_serial_get_mctrl, 1782 .set_mctrl = s3c24xx_serial_set_mctrl, 1783 .stop_tx = s3c24xx_serial_stop_tx, 1784 .start_tx = s3c24xx_serial_start_tx, 1785 .stop_rx = s3c24xx_serial_stop_rx, 1786 .break_ctl = s3c24xx_serial_break_ctl, 1787 .startup = apple_s5l_serial_startup, 1788 .shutdown = apple_s5l_serial_shutdown, 1789 .set_termios = s3c24xx_serial_set_termios, 1790 .type = s3c24xx_serial_type, 1791 .config_port = s3c24xx_serial_config_port, 1792 .verify_port = s3c24xx_serial_verify_port, 1793 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1794 .poll_get_char = s3c24xx_serial_get_poll_char, 1795 .poll_put_char = s3c24xx_serial_put_poll_char, 1796 #endif 1797 }; 1798 1799 static struct uart_driver s3c24xx_uart_drv = { 1800 .owner = THIS_MODULE, 1801 .driver_name = "s3c2410_serial", 1802 .nr = CONFIG_SERIAL_SAMSUNG_UARTS, 1803 .cons = S3C24XX_SERIAL_CONSOLE, 1804 .dev_name = S3C24XX_SERIAL_NAME, 1805 .major = S3C24XX_SERIAL_MAJOR, 1806 .minor = S3C24XX_SERIAL_MINOR, 1807 }; 1808 1809 #define __PORT_LOCK_UNLOCKED(i) \ 1810 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock) 1811 static struct s3c24xx_uart_port 1812 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = { 1813 [0] = { 1814 .port = { 1815 .lock = __PORT_LOCK_UNLOCKED(0), 1816 .iotype = UPIO_MEM, 1817 .uartclk = 0, 1818 .fifosize = 16, 1819 .ops = &s3c24xx_serial_ops, 1820 .flags = UPF_BOOT_AUTOCONF, 1821 .line = 0, 1822 } 1823 }, 1824 [1] = { 1825 .port = { 1826 .lock = __PORT_LOCK_UNLOCKED(1), 1827 .iotype = UPIO_MEM, 1828 .uartclk = 0, 1829 .fifosize = 16, 1830 .ops = &s3c24xx_serial_ops, 1831 .flags = UPF_BOOT_AUTOCONF, 1832 .line = 1, 1833 } 1834 }, 1835 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2 1836 [2] = { 1837 .port = { 1838 .lock = __PORT_LOCK_UNLOCKED(2), 1839 .iotype = UPIO_MEM, 1840 .uartclk = 0, 1841 .fifosize = 16, 1842 .ops = &s3c24xx_serial_ops, 1843 .flags = UPF_BOOT_AUTOCONF, 1844 .line = 2, 1845 } 1846 }, 1847 #endif 1848 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3 1849 [3] = { 1850 .port = { 1851 .lock = __PORT_LOCK_UNLOCKED(3), 1852 .iotype = UPIO_MEM, 1853 .uartclk = 0, 1854 .fifosize = 16, 1855 .ops = &s3c24xx_serial_ops, 1856 .flags = UPF_BOOT_AUTOCONF, 1857 .line = 3, 1858 } 1859 } 1860 #endif 1861 }; 1862 #undef __PORT_LOCK_UNLOCKED 1863 1864 /* s3c24xx_serial_resetport 1865 * 1866 * reset the fifos and other the settings. 1867 */ 1868 1869 static void s3c24xx_serial_resetport(struct uart_port *port, 1870 struct s3c2410_uartcfg *cfg) 1871 { 1872 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1873 unsigned long ucon = rd_regl(port, S3C2410_UCON); 1874 1875 ucon &= (info->clksel_mask | info->ucon_mask); 1876 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); 1877 1878 /* reset both fifos */ 1879 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); 1880 wr_regl(port, S3C2410_UFCON, cfg->ufcon); 1881 1882 /* some delay is required after fifo reset */ 1883 udelay(1); 1884 } 1885 1886 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ 1887 1888 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb, 1889 unsigned long val, void *data) 1890 { 1891 struct s3c24xx_uart_port *port; 1892 struct uart_port *uport; 1893 1894 port = container_of(nb, struct s3c24xx_uart_port, freq_transition); 1895 uport = &port->port; 1896 1897 /* check to see if port is enabled */ 1898 1899 if (port->pm_level != 0) 1900 return 0; 1901 1902 /* try and work out if the baudrate is changing, we can detect 1903 * a change in rate, but we do not have support for detecting 1904 * a disturbance in the clock-rate over the change. 1905 */ 1906 1907 if (IS_ERR(port->baudclk)) 1908 goto exit; 1909 1910 if (port->baudclk_rate == clk_get_rate(port->baudclk)) 1911 goto exit; 1912 1913 if (val == CPUFREQ_PRECHANGE) { 1914 /* we should really shut the port down whilst the 1915 * frequency change is in progress. 1916 */ 1917 1918 } else if (val == CPUFREQ_POSTCHANGE) { 1919 struct ktermios *termios; 1920 struct tty_struct *tty; 1921 1922 if (uport->state == NULL) 1923 goto exit; 1924 1925 tty = uport->state->port.tty; 1926 1927 if (tty == NULL) 1928 goto exit; 1929 1930 termios = &tty->termios; 1931 1932 if (termios == NULL) { 1933 dev_warn(uport->dev, "%s: no termios?\n", __func__); 1934 goto exit; 1935 } 1936 1937 s3c24xx_serial_set_termios(uport, termios, NULL); 1938 } 1939 1940 exit: 1941 return 0; 1942 } 1943 1944 static inline int 1945 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) 1946 { 1947 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition; 1948 1949 return cpufreq_register_notifier(&port->freq_transition, 1950 CPUFREQ_TRANSITION_NOTIFIER); 1951 } 1952 1953 static inline void 1954 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) 1955 { 1956 cpufreq_unregister_notifier(&port->freq_transition, 1957 CPUFREQ_TRANSITION_NOTIFIER); 1958 } 1959 1960 #else 1961 static inline int 1962 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) 1963 { 1964 return 0; 1965 } 1966 1967 static inline void 1968 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) 1969 { 1970 } 1971 #endif 1972 1973 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport) 1974 { 1975 struct device *dev = ourport->port.dev; 1976 struct s3c24xx_uart_info *info = ourport->info; 1977 char clk_name[MAX_CLK_NAME_LENGTH]; 1978 unsigned int clk_sel; 1979 struct clk *clk; 1980 int clk_num; 1981 int ret; 1982 1983 clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel; 1984 for (clk_num = 0; clk_num < info->num_clks; clk_num++) { 1985 if (!(clk_sel & (1 << clk_num))) 1986 continue; 1987 1988 sprintf(clk_name, "clk_uart_baud%d", clk_num); 1989 clk = clk_get(dev, clk_name); 1990 if (IS_ERR(clk)) 1991 continue; 1992 1993 ret = clk_prepare_enable(clk); 1994 if (ret) { 1995 clk_put(clk); 1996 continue; 1997 } 1998 1999 ourport->baudclk = clk; 2000 ourport->baudclk_rate = clk_get_rate(clk); 2001 s3c24xx_serial_setsource(&ourport->port, clk_num); 2002 2003 return 0; 2004 } 2005 2006 return -EINVAL; 2007 } 2008 2009 /* s3c24xx_serial_init_port 2010 * 2011 * initialise a single serial port from the platform device given 2012 */ 2013 2014 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, 2015 struct platform_device *platdev) 2016 { 2017 struct uart_port *port = &ourport->port; 2018 struct s3c2410_uartcfg *cfg = ourport->cfg; 2019 struct resource *res; 2020 int ret; 2021 2022 if (platdev == NULL) 2023 return -ENODEV; 2024 2025 if (port->mapbase != 0) 2026 return -EINVAL; 2027 2028 /* setup info for port */ 2029 port->dev = &platdev->dev; 2030 2031 port->uartclk = 1; 2032 2033 if (cfg->uart_flags & UPF_CONS_FLOW) { 2034 dev_dbg(port->dev, "enabling flow control\n"); 2035 port->flags |= UPF_CONS_FLOW; 2036 } 2037 2038 /* sort our the physical and virtual addresses for each UART */ 2039 2040 res = platform_get_resource(platdev, IORESOURCE_MEM, 0); 2041 if (res == NULL) { 2042 dev_err(port->dev, "failed to find memory resource for uart\n"); 2043 return -EINVAL; 2044 } 2045 2046 dev_dbg(port->dev, "resource %pR)\n", res); 2047 2048 port->membase = devm_ioremap_resource(port->dev, res); 2049 if (IS_ERR(port->membase)) { 2050 dev_err(port->dev, "failed to remap controller address\n"); 2051 return -EBUSY; 2052 } 2053 2054 port->mapbase = res->start; 2055 ret = platform_get_irq(platdev, 0); 2056 if (ret < 0) { 2057 port->irq = 0; 2058 } else { 2059 port->irq = ret; 2060 ourport->rx_irq = ret; 2061 ourport->tx_irq = ret + 1; 2062 } 2063 2064 switch (ourport->info->type) { 2065 case TYPE_S3C24XX: 2066 ret = platform_get_irq(platdev, 1); 2067 if (ret > 0) 2068 ourport->tx_irq = ret; 2069 break; 2070 default: 2071 break; 2072 } 2073 2074 /* 2075 * DMA is currently supported only on DT platforms, if DMA properties 2076 * are specified. 2077 */ 2078 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node, 2079 "dmas", NULL)) { 2080 ourport->dma = devm_kzalloc(port->dev, 2081 sizeof(*ourport->dma), 2082 GFP_KERNEL); 2083 if (!ourport->dma) { 2084 ret = -ENOMEM; 2085 goto err; 2086 } 2087 } 2088 2089 ourport->clk = clk_get(&platdev->dev, "uart"); 2090 if (IS_ERR(ourport->clk)) { 2091 pr_err("%s: Controller clock not found\n", 2092 dev_name(&platdev->dev)); 2093 ret = PTR_ERR(ourport->clk); 2094 goto err; 2095 } 2096 2097 ret = clk_prepare_enable(ourport->clk); 2098 if (ret) { 2099 pr_err("uart: clock failed to prepare+enable: %d\n", ret); 2100 clk_put(ourport->clk); 2101 goto err; 2102 } 2103 2104 ret = s3c24xx_serial_enable_baudclk(ourport); 2105 if (ret) 2106 pr_warn("uart: failed to enable baudclk\n"); 2107 2108 /* Keep all interrupts masked and cleared */ 2109 switch (ourport->info->type) { 2110 case TYPE_S3C6400: 2111 wr_regl(port, S3C64XX_UINTM, 0xf); 2112 wr_regl(port, S3C64XX_UINTP, 0xf); 2113 wr_regl(port, S3C64XX_UINTSP, 0xf); 2114 break; 2115 case TYPE_APPLE_S5L: { 2116 unsigned int ucon; 2117 2118 ucon = rd_regl(port, S3C2410_UCON); 2119 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | 2120 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 2121 APPLE_S5L_UCON_RXTO_ENA_MSK); 2122 wr_regl(port, S3C2410_UCON, ucon); 2123 2124 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS); 2125 break; 2126 } 2127 default: 2128 break; 2129 } 2130 2131 dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n", 2132 &port->mapbase, port->membase, port->irq, 2133 ourport->rx_irq, ourport->tx_irq, port->uartclk); 2134 2135 /* reset the fifos (and setup the uart) */ 2136 s3c24xx_serial_resetport(port, cfg); 2137 2138 return 0; 2139 2140 err: 2141 port->mapbase = 0; 2142 return ret; 2143 } 2144 2145 /* Device driver serial port probe */ 2146 2147 #ifdef CONFIG_OF 2148 static const struct of_device_id s3c24xx_uart_dt_match[]; 2149 #endif 2150 2151 static int probe_index; 2152 2153 static inline struct s3c24xx_serial_drv_data * 2154 s3c24xx_get_driver_data(struct platform_device *pdev) 2155 { 2156 #ifdef CONFIG_OF 2157 if (pdev->dev.of_node) { 2158 const struct of_device_id *match; 2159 2160 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node); 2161 return (struct s3c24xx_serial_drv_data *)match->data; 2162 } 2163 #endif 2164 return (struct s3c24xx_serial_drv_data *) 2165 platform_get_device_id(pdev)->driver_data; 2166 } 2167 2168 static int s3c24xx_serial_probe(struct platform_device *pdev) 2169 { 2170 struct device_node *np = pdev->dev.of_node; 2171 struct s3c24xx_uart_port *ourport; 2172 int index = probe_index; 2173 int ret, prop = 0; 2174 2175 if (np) { 2176 ret = of_alias_get_id(np, "serial"); 2177 if (ret >= 0) 2178 index = ret; 2179 } 2180 2181 if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) { 2182 dev_err(&pdev->dev, "serial%d out of range\n", index); 2183 return -EINVAL; 2184 } 2185 ourport = &s3c24xx_serial_ports[index]; 2186 2187 ourport->drv_data = s3c24xx_get_driver_data(pdev); 2188 if (!ourport->drv_data) { 2189 dev_err(&pdev->dev, "could not find driver data\n"); 2190 return -ENODEV; 2191 } 2192 2193 ourport->baudclk = ERR_PTR(-EINVAL); 2194 ourport->info = ourport->drv_data->info; 2195 ourport->cfg = (dev_get_platdata(&pdev->dev)) ? 2196 dev_get_platdata(&pdev->dev) : 2197 ourport->drv_data->def_cfg; 2198 2199 switch (ourport->info->type) { 2200 case TYPE_S3C24XX: 2201 ourport->port.ops = &s3c24xx_serial_ops; 2202 break; 2203 case TYPE_S3C6400: 2204 ourport->port.ops = &s3c64xx_serial_ops; 2205 break; 2206 case TYPE_APPLE_S5L: 2207 ourport->port.ops = &apple_s5l_serial_ops; 2208 break; 2209 } 2210 2211 if (np) { 2212 of_property_read_u32(np, 2213 "samsung,uart-fifosize", &ourport->port.fifosize); 2214 2215 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) { 2216 switch (prop) { 2217 case 1: 2218 ourport->port.iotype = UPIO_MEM; 2219 break; 2220 case 4: 2221 ourport->port.iotype = UPIO_MEM32; 2222 break; 2223 default: 2224 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n", 2225 prop); 2226 ret = -EINVAL; 2227 break; 2228 } 2229 } 2230 } 2231 2232 if (ourport->drv_data->fifosize[index]) 2233 ourport->port.fifosize = ourport->drv_data->fifosize[index]; 2234 else if (ourport->info->fifosize) 2235 ourport->port.fifosize = ourport->info->fifosize; 2236 ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE); 2237 2238 /* 2239 * DMA transfers must be aligned at least to cache line size, 2240 * so find minimal transfer size suitable for DMA mode 2241 */ 2242 ourport->min_dma_size = max_t(int, ourport->port.fifosize, 2243 dma_get_cache_alignment()); 2244 2245 dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport); 2246 2247 ret = s3c24xx_serial_init_port(ourport, pdev); 2248 if (ret < 0) 2249 return ret; 2250 2251 if (!s3c24xx_uart_drv.state) { 2252 ret = uart_register_driver(&s3c24xx_uart_drv); 2253 if (ret < 0) { 2254 pr_err("Failed to register Samsung UART driver\n"); 2255 return ret; 2256 } 2257 } 2258 2259 dev_dbg(&pdev->dev, "%s: adding port\n", __func__); 2260 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port); 2261 platform_set_drvdata(pdev, &ourport->port); 2262 2263 /* 2264 * Deactivate the clock enabled in s3c24xx_serial_init_port here, 2265 * so that a potential re-enablement through the pm-callback overlaps 2266 * and keeps the clock enabled in this case. 2267 */ 2268 clk_disable_unprepare(ourport->clk); 2269 if (!IS_ERR(ourport->baudclk)) 2270 clk_disable_unprepare(ourport->baudclk); 2271 2272 ret = s3c24xx_serial_cpufreq_register(ourport); 2273 if (ret < 0) 2274 dev_err(&pdev->dev, "failed to add cpufreq notifier\n"); 2275 2276 probe_index++; 2277 2278 return 0; 2279 } 2280 2281 static int s3c24xx_serial_remove(struct platform_device *dev) 2282 { 2283 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); 2284 2285 if (port) { 2286 s3c24xx_serial_cpufreq_deregister(to_ourport(port)); 2287 uart_remove_one_port(&s3c24xx_uart_drv, port); 2288 } 2289 2290 uart_unregister_driver(&s3c24xx_uart_drv); 2291 2292 return 0; 2293 } 2294 2295 /* UART power management code */ 2296 #ifdef CONFIG_PM_SLEEP 2297 static int s3c24xx_serial_suspend(struct device *dev) 2298 { 2299 struct uart_port *port = s3c24xx_dev_to_port(dev); 2300 2301 if (port) 2302 uart_suspend_port(&s3c24xx_uart_drv, port); 2303 2304 return 0; 2305 } 2306 2307 static int s3c24xx_serial_resume(struct device *dev) 2308 { 2309 struct uart_port *port = s3c24xx_dev_to_port(dev); 2310 struct s3c24xx_uart_port *ourport = to_ourport(port); 2311 2312 if (port) { 2313 clk_prepare_enable(ourport->clk); 2314 if (!IS_ERR(ourport->baudclk)) 2315 clk_prepare_enable(ourport->baudclk); 2316 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port)); 2317 if (!IS_ERR(ourport->baudclk)) 2318 clk_disable_unprepare(ourport->baudclk); 2319 clk_disable_unprepare(ourport->clk); 2320 2321 uart_resume_port(&s3c24xx_uart_drv, port); 2322 } 2323 2324 return 0; 2325 } 2326 2327 static int s3c24xx_serial_resume_noirq(struct device *dev) 2328 { 2329 struct uart_port *port = s3c24xx_dev_to_port(dev); 2330 struct s3c24xx_uart_port *ourport = to_ourport(port); 2331 2332 if (port) { 2333 /* restore IRQ mask */ 2334 switch (ourport->info->type) { 2335 case TYPE_S3C6400: { 2336 unsigned int uintm = 0xf; 2337 2338 if (ourport->tx_enabled) 2339 uintm &= ~S3C64XX_UINTM_TXD_MSK; 2340 if (ourport->rx_enabled) 2341 uintm &= ~S3C64XX_UINTM_RXD_MSK; 2342 clk_prepare_enable(ourport->clk); 2343 if (!IS_ERR(ourport->baudclk)) 2344 clk_prepare_enable(ourport->baudclk); 2345 wr_regl(port, S3C64XX_UINTM, uintm); 2346 if (!IS_ERR(ourport->baudclk)) 2347 clk_disable_unprepare(ourport->baudclk); 2348 clk_disable_unprepare(ourport->clk); 2349 break; 2350 } 2351 case TYPE_APPLE_S5L: { 2352 unsigned int ucon; 2353 int ret; 2354 2355 ret = clk_prepare_enable(ourport->clk); 2356 if (ret) { 2357 dev_err(dev, "clk_enable clk failed: %d\n", ret); 2358 return ret; 2359 } 2360 if (!IS_ERR(ourport->baudclk)) { 2361 ret = clk_prepare_enable(ourport->baudclk); 2362 if (ret) { 2363 dev_err(dev, "clk_enable baudclk failed: %d\n", ret); 2364 clk_disable_unprepare(ourport->clk); 2365 return ret; 2366 } 2367 } 2368 2369 ucon = rd_regl(port, S3C2410_UCON); 2370 2371 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | 2372 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 2373 APPLE_S5L_UCON_RXTO_ENA_MSK); 2374 2375 if (ourport->tx_enabled) 2376 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK; 2377 if (ourport->rx_enabled) 2378 ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 2379 APPLE_S5L_UCON_RXTO_ENA_MSK; 2380 2381 wr_regl(port, S3C2410_UCON, ucon); 2382 2383 if (!IS_ERR(ourport->baudclk)) 2384 clk_disable_unprepare(ourport->baudclk); 2385 clk_disable_unprepare(ourport->clk); 2386 break; 2387 } 2388 default: 2389 break; 2390 } 2391 } 2392 2393 return 0; 2394 } 2395 2396 static const struct dev_pm_ops s3c24xx_serial_pm_ops = { 2397 .suspend = s3c24xx_serial_suspend, 2398 .resume = s3c24xx_serial_resume, 2399 .resume_noirq = s3c24xx_serial_resume_noirq, 2400 }; 2401 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops) 2402 2403 #else /* !CONFIG_PM_SLEEP */ 2404 2405 #define SERIAL_SAMSUNG_PM_OPS NULL 2406 #endif /* CONFIG_PM_SLEEP */ 2407 2408 /* Console code */ 2409 2410 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 2411 2412 static struct uart_port *cons_uart; 2413 2414 static int 2415 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon) 2416 { 2417 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 2418 unsigned long ufstat, utrstat; 2419 2420 if (ufcon & S3C2410_UFCON_FIFOMODE) { 2421 /* fifo mode - check amount of data in fifo registers... */ 2422 2423 ufstat = rd_regl(port, S3C2410_UFSTAT); 2424 return (ufstat & info->tx_fifofull) ? 0 : 1; 2425 } 2426 2427 /* in non-fifo mode, we go and use the tx buffer empty */ 2428 2429 utrstat = rd_regl(port, S3C2410_UTRSTAT); 2430 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0; 2431 } 2432 2433 static bool 2434 s3c24xx_port_configured(unsigned int ucon) 2435 { 2436 /* consider the serial port configured if the tx/rx mode set */ 2437 return (ucon & 0xf) != 0; 2438 } 2439 2440 #ifdef CONFIG_CONSOLE_POLL 2441 /* 2442 * Console polling routines for writing and reading from the uart while 2443 * in an interrupt or debug context. 2444 */ 2445 2446 static int s3c24xx_serial_get_poll_char(struct uart_port *port) 2447 { 2448 struct s3c24xx_uart_port *ourport = to_ourport(port); 2449 unsigned int ufstat; 2450 2451 ufstat = rd_regl(port, S3C2410_UFSTAT); 2452 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0) 2453 return NO_POLL_CHAR; 2454 2455 return rd_reg(port, S3C2410_URXH); 2456 } 2457 2458 static void s3c24xx_serial_put_poll_char(struct uart_port *port, 2459 unsigned char c) 2460 { 2461 unsigned int ufcon = rd_regl(port, S3C2410_UFCON); 2462 unsigned int ucon = rd_regl(port, S3C2410_UCON); 2463 2464 /* not possible to xmit on unconfigured port */ 2465 if (!s3c24xx_port_configured(ucon)) 2466 return; 2467 2468 while (!s3c24xx_serial_console_txrdy(port, ufcon)) 2469 cpu_relax(); 2470 wr_reg(port, S3C2410_UTXH, c); 2471 } 2472 2473 #endif /* CONFIG_CONSOLE_POLL */ 2474 2475 static void 2476 s3c24xx_serial_console_putchar(struct uart_port *port, int ch) 2477 { 2478 unsigned int ufcon = rd_regl(port, S3C2410_UFCON); 2479 2480 while (!s3c24xx_serial_console_txrdy(port, ufcon)) 2481 cpu_relax(); 2482 wr_reg(port, S3C2410_UTXH, ch); 2483 } 2484 2485 static void 2486 s3c24xx_serial_console_write(struct console *co, const char *s, 2487 unsigned int count) 2488 { 2489 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON); 2490 2491 /* not possible to xmit on unconfigured port */ 2492 if (!s3c24xx_port_configured(ucon)) 2493 return; 2494 2495 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar); 2496 } 2497 2498 static void __init 2499 s3c24xx_serial_get_options(struct uart_port *port, int *baud, 2500 int *parity, int *bits) 2501 { 2502 struct clk *clk; 2503 unsigned int ulcon; 2504 unsigned int ucon; 2505 unsigned int ubrdiv; 2506 unsigned long rate; 2507 unsigned int clk_sel; 2508 char clk_name[MAX_CLK_NAME_LENGTH]; 2509 2510 ulcon = rd_regl(port, S3C2410_ULCON); 2511 ucon = rd_regl(port, S3C2410_UCON); 2512 ubrdiv = rd_regl(port, S3C2410_UBRDIV); 2513 2514 if (s3c24xx_port_configured(ucon)) { 2515 switch (ulcon & S3C2410_LCON_CSMASK) { 2516 case S3C2410_LCON_CS5: 2517 *bits = 5; 2518 break; 2519 case S3C2410_LCON_CS6: 2520 *bits = 6; 2521 break; 2522 case S3C2410_LCON_CS7: 2523 *bits = 7; 2524 break; 2525 case S3C2410_LCON_CS8: 2526 default: 2527 *bits = 8; 2528 break; 2529 } 2530 2531 switch (ulcon & S3C2410_LCON_PMASK) { 2532 case S3C2410_LCON_PEVEN: 2533 *parity = 'e'; 2534 break; 2535 2536 case S3C2410_LCON_PODD: 2537 *parity = 'o'; 2538 break; 2539 2540 case S3C2410_LCON_PNONE: 2541 default: 2542 *parity = 'n'; 2543 } 2544 2545 /* now calculate the baud rate */ 2546 2547 clk_sel = s3c24xx_serial_getsource(port); 2548 sprintf(clk_name, "clk_uart_baud%d", clk_sel); 2549 2550 clk = clk_get(port->dev, clk_name); 2551 if (!IS_ERR(clk)) 2552 rate = clk_get_rate(clk); 2553 else 2554 rate = 1; 2555 2556 *baud = rate / (16 * (ubrdiv + 1)); 2557 dev_dbg(port->dev, "calculated baud %d\n", *baud); 2558 } 2559 } 2560 2561 static int __init 2562 s3c24xx_serial_console_setup(struct console *co, char *options) 2563 { 2564 struct uart_port *port; 2565 int baud = 9600; 2566 int bits = 8; 2567 int parity = 'n'; 2568 int flow = 'n'; 2569 2570 /* is this a valid port */ 2571 2572 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS) 2573 co->index = 0; 2574 2575 port = &s3c24xx_serial_ports[co->index].port; 2576 2577 /* is the port configured? */ 2578 2579 if (port->mapbase == 0x0) 2580 return -ENODEV; 2581 2582 cons_uart = port; 2583 2584 /* 2585 * Check whether an invalid uart number has been specified, and 2586 * if so, search for the first available port that does have 2587 * console support. 2588 */ 2589 if (options) 2590 uart_parse_options(options, &baud, &parity, &bits, &flow); 2591 else 2592 s3c24xx_serial_get_options(port, &baud, &parity, &bits); 2593 2594 dev_dbg(port->dev, "baud %d\n", baud); 2595 2596 return uart_set_options(port, co, baud, parity, bits, flow); 2597 } 2598 2599 static struct console s3c24xx_serial_console = { 2600 .name = S3C24XX_SERIAL_NAME, 2601 .device = uart_console_device, 2602 .flags = CON_PRINTBUFFER, 2603 .index = -1, 2604 .write = s3c24xx_serial_console_write, 2605 .setup = s3c24xx_serial_console_setup, 2606 .data = &s3c24xx_uart_drv, 2607 }; 2608 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */ 2609 2610 #ifdef CONFIG_CPU_S3C2410 2611 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = { 2612 .info = &(struct s3c24xx_uart_info) { 2613 .name = "Samsung S3C2410 UART", 2614 .type = TYPE_S3C24XX, 2615 .port_type = PORT_S3C2410, 2616 .fifosize = 16, 2617 .rx_fifomask = S3C2410_UFSTAT_RXMASK, 2618 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT, 2619 .rx_fifofull = S3C2410_UFSTAT_RXFULL, 2620 .tx_fifofull = S3C2410_UFSTAT_TXFULL, 2621 .tx_fifomask = S3C2410_UFSTAT_TXMASK, 2622 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT, 2623 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2624 .num_clks = 2, 2625 .clksel_mask = S3C2410_UCON_CLKMASK, 2626 .clksel_shift = S3C2410_UCON_CLKSHIFT, 2627 }, 2628 .def_cfg = &(struct s3c2410_uartcfg) { 2629 .ucon = S3C2410_UCON_DEFAULT, 2630 .ufcon = S3C2410_UFCON_DEFAULT, 2631 }, 2632 }; 2633 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data) 2634 #else 2635 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL 2636 #endif 2637 2638 #ifdef CONFIG_CPU_S3C2412 2639 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = { 2640 .info = &(struct s3c24xx_uart_info) { 2641 .name = "Samsung S3C2412 UART", 2642 .type = TYPE_S3C24XX, 2643 .port_type = PORT_S3C2412, 2644 .fifosize = 64, 2645 .has_divslot = 1, 2646 .rx_fifomask = S3C2440_UFSTAT_RXMASK, 2647 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, 2648 .rx_fifofull = S3C2440_UFSTAT_RXFULL, 2649 .tx_fifofull = S3C2440_UFSTAT_TXFULL, 2650 .tx_fifomask = S3C2440_UFSTAT_TXMASK, 2651 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, 2652 .def_clk_sel = S3C2410_UCON_CLKSEL2, 2653 .num_clks = 4, 2654 .clksel_mask = S3C2412_UCON_CLKMASK, 2655 .clksel_shift = S3C2412_UCON_CLKSHIFT, 2656 }, 2657 .def_cfg = &(struct s3c2410_uartcfg) { 2658 .ucon = S3C2410_UCON_DEFAULT, 2659 .ufcon = S3C2410_UFCON_DEFAULT, 2660 }, 2661 }; 2662 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data) 2663 #else 2664 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL 2665 #endif 2666 2667 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \ 2668 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442) 2669 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = { 2670 .info = &(struct s3c24xx_uart_info) { 2671 .name = "Samsung S3C2440 UART", 2672 .type = TYPE_S3C24XX, 2673 .port_type = PORT_S3C2440, 2674 .fifosize = 64, 2675 .has_divslot = 1, 2676 .rx_fifomask = S3C2440_UFSTAT_RXMASK, 2677 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, 2678 .rx_fifofull = S3C2440_UFSTAT_RXFULL, 2679 .tx_fifofull = S3C2440_UFSTAT_TXFULL, 2680 .tx_fifomask = S3C2440_UFSTAT_TXMASK, 2681 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, 2682 .def_clk_sel = S3C2410_UCON_CLKSEL2, 2683 .num_clks = 4, 2684 .clksel_mask = S3C2412_UCON_CLKMASK, 2685 .clksel_shift = S3C2412_UCON_CLKSHIFT, 2686 .ucon_mask = S3C2440_UCON0_DIVMASK, 2687 }, 2688 .def_cfg = &(struct s3c2410_uartcfg) { 2689 .ucon = S3C2410_UCON_DEFAULT, 2690 .ufcon = S3C2410_UFCON_DEFAULT, 2691 }, 2692 }; 2693 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data) 2694 #else 2695 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL 2696 #endif 2697 2698 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) 2699 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = { 2700 .info = &(struct s3c24xx_uart_info) { 2701 .name = "Samsung S3C6400 UART", 2702 .type = TYPE_S3C6400, 2703 .port_type = PORT_S3C6400, 2704 .fifosize = 64, 2705 .has_divslot = 1, 2706 .rx_fifomask = S3C2440_UFSTAT_RXMASK, 2707 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, 2708 .rx_fifofull = S3C2440_UFSTAT_RXFULL, 2709 .tx_fifofull = S3C2440_UFSTAT_TXFULL, 2710 .tx_fifomask = S3C2440_UFSTAT_TXMASK, 2711 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, 2712 .def_clk_sel = S3C2410_UCON_CLKSEL2, 2713 .num_clks = 4, 2714 .clksel_mask = S3C6400_UCON_CLKMASK, 2715 .clksel_shift = S3C6400_UCON_CLKSHIFT, 2716 }, 2717 .def_cfg = &(struct s3c2410_uartcfg) { 2718 .ucon = S3C2410_UCON_DEFAULT, 2719 .ufcon = S3C2410_UFCON_DEFAULT, 2720 }, 2721 }; 2722 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data) 2723 #else 2724 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL 2725 #endif 2726 2727 #ifdef CONFIG_CPU_S5PV210 2728 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { 2729 .info = &(struct s3c24xx_uart_info) { 2730 .name = "Samsung S5PV210 UART", 2731 .type = TYPE_S3C6400, 2732 .port_type = PORT_S3C6400, 2733 .has_divslot = 1, 2734 .rx_fifomask = S5PV210_UFSTAT_RXMASK, 2735 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, 2736 .rx_fifofull = S5PV210_UFSTAT_RXFULL, 2737 .tx_fifofull = S5PV210_UFSTAT_TXFULL, 2738 .tx_fifomask = S5PV210_UFSTAT_TXMASK, 2739 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, 2740 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2741 .num_clks = 2, 2742 .clksel_mask = S5PV210_UCON_CLKMASK, 2743 .clksel_shift = S5PV210_UCON_CLKSHIFT, 2744 }, 2745 .def_cfg = &(struct s3c2410_uartcfg) { 2746 .ucon = S5PV210_UCON_DEFAULT, 2747 .ufcon = S5PV210_UFCON_DEFAULT, 2748 }, 2749 .fifosize = { 256, 64, 16, 16 }, 2750 }; 2751 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data) 2752 #else 2753 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL 2754 #endif 2755 2756 #if defined(CONFIG_ARCH_EXYNOS) 2757 #define EXYNOS_COMMON_SERIAL_DRV_DATA \ 2758 .info = &(struct s3c24xx_uart_info) { \ 2759 .name = "Samsung Exynos UART", \ 2760 .type = TYPE_S3C6400, \ 2761 .port_type = PORT_S3C6400, \ 2762 .has_divslot = 1, \ 2763 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ 2764 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \ 2765 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \ 2766 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \ 2767 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \ 2768 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \ 2769 .def_clk_sel = S3C2410_UCON_CLKSEL0, \ 2770 .num_clks = 1, \ 2771 .clksel_mask = 0, \ 2772 .clksel_shift = 0, \ 2773 }, \ 2774 .def_cfg = &(struct s3c2410_uartcfg) { \ 2775 .ucon = S5PV210_UCON_DEFAULT, \ 2776 .ufcon = S5PV210_UFCON_DEFAULT, \ 2777 .has_fracval = 1, \ 2778 } \ 2779 2780 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = { 2781 EXYNOS_COMMON_SERIAL_DRV_DATA, 2782 .fifosize = { 256, 64, 16, 16 }, 2783 }; 2784 2785 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = { 2786 EXYNOS_COMMON_SERIAL_DRV_DATA, 2787 .fifosize = { 64, 256, 16, 256 }, 2788 }; 2789 2790 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data) 2791 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data) 2792 #else 2793 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL 2794 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL 2795 #endif 2796 2797 #ifdef CONFIG_ARCH_APPLE 2798 static struct s3c24xx_serial_drv_data s5l_serial_drv_data = { 2799 .info = &(struct s3c24xx_uart_info) { 2800 .name = "Apple S5L UART", 2801 .type = TYPE_APPLE_S5L, 2802 .port_type = PORT_8250, 2803 .fifosize = 16, 2804 .rx_fifomask = S3C2410_UFSTAT_RXMASK, 2805 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT, 2806 .rx_fifofull = S3C2410_UFSTAT_RXFULL, 2807 .tx_fifofull = S3C2410_UFSTAT_TXFULL, 2808 .tx_fifomask = S3C2410_UFSTAT_TXMASK, 2809 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT, 2810 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2811 .num_clks = 1, 2812 .clksel_mask = 0, 2813 .clksel_shift = 0, 2814 }, 2815 .def_cfg = &(struct s3c2410_uartcfg) { 2816 .ucon = APPLE_S5L_UCON_DEFAULT, 2817 .ufcon = S3C2410_UFCON_DEFAULT, 2818 }, 2819 }; 2820 #define S5L_SERIAL_DRV_DATA ((kernel_ulong_t)&s5l_serial_drv_data) 2821 #else 2822 #define S5L_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) 2823 #endif 2824 2825 static const struct platform_device_id s3c24xx_serial_driver_ids[] = { 2826 { 2827 .name = "s3c2410-uart", 2828 .driver_data = S3C2410_SERIAL_DRV_DATA, 2829 }, { 2830 .name = "s3c2412-uart", 2831 .driver_data = S3C2412_SERIAL_DRV_DATA, 2832 }, { 2833 .name = "s3c2440-uart", 2834 .driver_data = S3C2440_SERIAL_DRV_DATA, 2835 }, { 2836 .name = "s3c6400-uart", 2837 .driver_data = S3C6400_SERIAL_DRV_DATA, 2838 }, { 2839 .name = "s5pv210-uart", 2840 .driver_data = S5PV210_SERIAL_DRV_DATA, 2841 }, { 2842 .name = "exynos4210-uart", 2843 .driver_data = EXYNOS4210_SERIAL_DRV_DATA, 2844 }, { 2845 .name = "exynos5433-uart", 2846 .driver_data = EXYNOS5433_SERIAL_DRV_DATA, 2847 }, { 2848 .name = "s5l-uart", 2849 .driver_data = S5L_SERIAL_DRV_DATA, 2850 }, 2851 { }, 2852 }; 2853 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids); 2854 2855 #ifdef CONFIG_OF 2856 static const struct of_device_id s3c24xx_uart_dt_match[] = { 2857 { .compatible = "samsung,s3c2410-uart", 2858 .data = (void *)S3C2410_SERIAL_DRV_DATA }, 2859 { .compatible = "samsung,s3c2412-uart", 2860 .data = (void *)S3C2412_SERIAL_DRV_DATA }, 2861 { .compatible = "samsung,s3c2440-uart", 2862 .data = (void *)S3C2440_SERIAL_DRV_DATA }, 2863 { .compatible = "samsung,s3c6400-uart", 2864 .data = (void *)S3C6400_SERIAL_DRV_DATA }, 2865 { .compatible = "samsung,s5pv210-uart", 2866 .data = (void *)S5PV210_SERIAL_DRV_DATA }, 2867 { .compatible = "samsung,exynos4210-uart", 2868 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA }, 2869 { .compatible = "samsung,exynos5433-uart", 2870 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA }, 2871 { .compatible = "apple,s5l-uart", 2872 .data = (void *)S5L_SERIAL_DRV_DATA }, 2873 {}, 2874 }; 2875 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); 2876 #endif 2877 2878 static struct platform_driver samsung_serial_driver = { 2879 .probe = s3c24xx_serial_probe, 2880 .remove = s3c24xx_serial_remove, 2881 .id_table = s3c24xx_serial_driver_ids, 2882 .driver = { 2883 .name = "samsung-uart", 2884 .pm = SERIAL_SAMSUNG_PM_OPS, 2885 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match), 2886 }, 2887 }; 2888 2889 module_platform_driver(samsung_serial_driver); 2890 2891 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 2892 /* 2893 * Early console. 2894 */ 2895 2896 static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val) 2897 { 2898 switch (port->iotype) { 2899 case UPIO_MEM: 2900 writeb(val, portaddr(port, reg)); 2901 break; 2902 case UPIO_MEM32: 2903 writel(val, portaddr(port, reg)); 2904 break; 2905 } 2906 } 2907 2908 struct samsung_early_console_data { 2909 u32 txfull_mask; 2910 }; 2911 2912 static void samsung_early_busyuart(struct uart_port *port) 2913 { 2914 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE)) 2915 ; 2916 } 2917 2918 static void samsung_early_busyuart_fifo(struct uart_port *port) 2919 { 2920 struct samsung_early_console_data *data = port->private_data; 2921 2922 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask) 2923 ; 2924 } 2925 2926 static void samsung_early_putc(struct uart_port *port, int c) 2927 { 2928 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) 2929 samsung_early_busyuart_fifo(port); 2930 else 2931 samsung_early_busyuart(port); 2932 2933 wr_reg_barrier(port, S3C2410_UTXH, c); 2934 } 2935 2936 static void samsung_early_write(struct console *con, const char *s, 2937 unsigned int n) 2938 { 2939 struct earlycon_device *dev = con->data; 2940 2941 uart_console_write(&dev->port, s, n, samsung_early_putc); 2942 } 2943 2944 static int __init samsung_early_console_setup(struct earlycon_device *device, 2945 const char *opt) 2946 { 2947 if (!device->port.membase) 2948 return -ENODEV; 2949 2950 device->con->write = samsung_early_write; 2951 return 0; 2952 } 2953 2954 /* S3C2410 */ 2955 static struct samsung_early_console_data s3c2410_early_console_data = { 2956 .txfull_mask = S3C2410_UFSTAT_TXFULL, 2957 }; 2958 2959 static int __init s3c2410_early_console_setup(struct earlycon_device *device, 2960 const char *opt) 2961 { 2962 device->port.private_data = &s3c2410_early_console_data; 2963 return samsung_early_console_setup(device, opt); 2964 } 2965 2966 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart", 2967 s3c2410_early_console_setup); 2968 2969 /* S3C2412, S3C2440, S3C64xx */ 2970 static struct samsung_early_console_data s3c2440_early_console_data = { 2971 .txfull_mask = S3C2440_UFSTAT_TXFULL, 2972 }; 2973 2974 static int __init s3c2440_early_console_setup(struct earlycon_device *device, 2975 const char *opt) 2976 { 2977 device->port.private_data = &s3c2440_early_console_data; 2978 return samsung_early_console_setup(device, opt); 2979 } 2980 2981 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart", 2982 s3c2440_early_console_setup); 2983 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart", 2984 s3c2440_early_console_setup); 2985 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart", 2986 s3c2440_early_console_setup); 2987 2988 /* S5PV210, Exynos */ 2989 static struct samsung_early_console_data s5pv210_early_console_data = { 2990 .txfull_mask = S5PV210_UFSTAT_TXFULL, 2991 }; 2992 2993 static int __init s5pv210_early_console_setup(struct earlycon_device *device, 2994 const char *opt) 2995 { 2996 device->port.private_data = &s5pv210_early_console_data; 2997 return samsung_early_console_setup(device, opt); 2998 } 2999 3000 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart", 3001 s5pv210_early_console_setup); 3002 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart", 3003 s5pv210_early_console_setup); 3004 3005 /* Apple S5L */ 3006 static int __init apple_s5l_early_console_setup(struct earlycon_device *device, 3007 const char *opt) 3008 { 3009 /* Close enough to S3C2410 for earlycon... */ 3010 device->port.private_data = &s3c2410_early_console_data; 3011 3012 #ifdef CONFIG_ARM64 3013 /* ... but we need to override the existing fixmap entry as nGnRnE */ 3014 __set_fixmap(FIX_EARLYCON_MEM_BASE, device->port.mapbase, 3015 __pgprot(PROT_DEVICE_nGnRnE)); 3016 #endif 3017 return samsung_early_console_setup(device, opt); 3018 } 3019 3020 OF_EARLYCON_DECLARE(s5l, "apple,s5l-uart", apple_s5l_early_console_setup); 3021 #endif 3022 3023 MODULE_ALIAS("platform:samsung-uart"); 3024 MODULE_DESCRIPTION("Samsung SoC Serial port driver"); 3025 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); 3026 MODULE_LICENSE("GPL v2"); 3027