1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver core for Samsung SoC onboard UARTs. 4 * 5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics 6 * http://armlinux.simtec.co.uk/ 7 */ 8 9 /* Note on 2410 error handling 10 * 11 * The s3c2410 manual has a love/hate affair with the contents of the 12 * UERSTAT register in the UART blocks, and keeps marking some of the 13 * error bits as reserved. Having checked with the s3c2410x01, 14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED 15 * feature from the latter versions of the manual. 16 * 17 * If it becomes aparrent that latter versions of the 2410 remove these 18 * bits, then action will have to be taken to differentiate the versions 19 * and change the policy on BREAK 20 * 21 * BJD, 04-Nov-2004 22 */ 23 24 #include <linux/dmaengine.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/slab.h> 27 #include <linux/module.h> 28 #include <linux/ioport.h> 29 #include <linux/io.h> 30 #include <linux/platform_device.h> 31 #include <linux/init.h> 32 #include <linux/sysrq.h> 33 #include <linux/console.h> 34 #include <linux/tty.h> 35 #include <linux/tty_flip.h> 36 #include <linux/serial_core.h> 37 #include <linux/serial.h> 38 #include <linux/serial_s3c.h> 39 #include <linux/delay.h> 40 #include <linux/clk.h> 41 #include <linux/cpufreq.h> 42 #include <linux/of.h> 43 #include <asm/irq.h> 44 45 /* UART name and device definitions */ 46 47 #define S3C24XX_SERIAL_NAME "ttySAC" 48 #define S3C24XX_SERIAL_MAJOR 204 49 #define S3C24XX_SERIAL_MINOR 64 50 51 #define S3C24XX_TX_PIO 1 52 #define S3C24XX_TX_DMA 2 53 #define S3C24XX_RX_PIO 1 54 #define S3C24XX_RX_DMA 2 55 56 /* flag to ignore all characters coming in */ 57 #define RXSTAT_DUMMY_READ (0x10000000) 58 59 enum s3c24xx_port_type { 60 TYPE_S3C24XX, 61 TYPE_S3C6400, 62 TYPE_APPLE_S5L, 63 }; 64 65 struct s3c24xx_uart_info { 66 char *name; 67 enum s3c24xx_port_type type; 68 unsigned int port_type; 69 unsigned int fifosize; 70 unsigned long rx_fifomask; 71 unsigned long rx_fifoshift; 72 unsigned long rx_fifofull; 73 unsigned long tx_fifomask; 74 unsigned long tx_fifoshift; 75 unsigned long tx_fifofull; 76 unsigned int def_clk_sel; 77 unsigned long num_clks; 78 unsigned long clksel_mask; 79 unsigned long clksel_shift; 80 unsigned long ucon_mask; 81 82 /* uart port features */ 83 84 unsigned int has_divslot:1; 85 }; 86 87 struct s3c24xx_serial_drv_data { 88 struct s3c24xx_uart_info *info; 89 struct s3c2410_uartcfg *def_cfg; 90 unsigned int fifosize[CONFIG_SERIAL_SAMSUNG_UARTS]; 91 }; 92 93 struct s3c24xx_uart_dma { 94 unsigned int rx_chan_id; 95 unsigned int tx_chan_id; 96 97 struct dma_slave_config rx_conf; 98 struct dma_slave_config tx_conf; 99 100 struct dma_chan *rx_chan; 101 struct dma_chan *tx_chan; 102 103 dma_addr_t rx_addr; 104 dma_addr_t tx_addr; 105 106 dma_cookie_t rx_cookie; 107 dma_cookie_t tx_cookie; 108 109 char *rx_buf; 110 111 dma_addr_t tx_transfer_addr; 112 113 size_t rx_size; 114 size_t tx_size; 115 116 struct dma_async_tx_descriptor *tx_desc; 117 struct dma_async_tx_descriptor *rx_desc; 118 119 int tx_bytes_requested; 120 int rx_bytes_requested; 121 }; 122 123 struct s3c24xx_uart_port { 124 unsigned char rx_claimed; 125 unsigned char tx_claimed; 126 unsigned char rx_enabled; 127 unsigned char tx_enabled; 128 unsigned int pm_level; 129 unsigned long baudclk_rate; 130 unsigned int min_dma_size; 131 132 unsigned int rx_irq; 133 unsigned int tx_irq; 134 135 unsigned int tx_in_progress; 136 unsigned int tx_mode; 137 unsigned int rx_mode; 138 139 struct s3c24xx_uart_info *info; 140 struct clk *clk; 141 struct clk *baudclk; 142 struct uart_port port; 143 struct s3c24xx_serial_drv_data *drv_data; 144 145 /* reference to platform data */ 146 struct s3c2410_uartcfg *cfg; 147 148 struct s3c24xx_uart_dma *dma; 149 150 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ 151 struct notifier_block freq_transition; 152 #endif 153 }; 154 155 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport); 156 157 /* conversion functions */ 158 159 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev) 160 161 /* register access controls */ 162 163 #define portaddr(port, reg) ((port)->membase + (reg)) 164 #define portaddrl(port, reg) \ 165 ((unsigned long *)(unsigned long)((port)->membase + (reg))) 166 167 static u32 rd_reg(struct uart_port *port, u32 reg) 168 { 169 switch (port->iotype) { 170 case UPIO_MEM: 171 return readb_relaxed(portaddr(port, reg)); 172 case UPIO_MEM32: 173 return readl_relaxed(portaddr(port, reg)); 174 default: 175 return 0; 176 } 177 return 0; 178 } 179 180 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg))) 181 182 static void wr_reg(struct uart_port *port, u32 reg, u32 val) 183 { 184 switch (port->iotype) { 185 case UPIO_MEM: 186 writeb_relaxed(val, portaddr(port, reg)); 187 break; 188 case UPIO_MEM32: 189 writel_relaxed(val, portaddr(port, reg)); 190 break; 191 } 192 } 193 194 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg)) 195 196 /* Byte-order aware bit setting/clearing functions. */ 197 198 static inline void s3c24xx_set_bit(struct uart_port *port, int idx, 199 unsigned int reg) 200 { 201 unsigned long flags; 202 u32 val; 203 204 local_irq_save(flags); 205 val = rd_regl(port, reg); 206 val |= (1 << idx); 207 wr_regl(port, reg, val); 208 local_irq_restore(flags); 209 } 210 211 static inline void s3c24xx_clear_bit(struct uart_port *port, int idx, 212 unsigned int reg) 213 { 214 unsigned long flags; 215 u32 val; 216 217 local_irq_save(flags); 218 val = rd_regl(port, reg); 219 val &= ~(1 << idx); 220 wr_regl(port, reg, val); 221 local_irq_restore(flags); 222 } 223 224 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port) 225 { 226 return container_of(port, struct s3c24xx_uart_port, port); 227 } 228 229 /* translate a port to the device name */ 230 231 static inline const char *s3c24xx_serial_portname(struct uart_port *port) 232 { 233 return to_platform_device(port->dev)->name; 234 } 235 236 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port) 237 { 238 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE; 239 } 240 241 static void s3c24xx_serial_rx_enable(struct uart_port *port) 242 { 243 struct s3c24xx_uart_port *ourport = to_ourport(port); 244 unsigned long flags; 245 unsigned int ucon, ufcon; 246 int count = 10000; 247 248 spin_lock_irqsave(&port->lock, flags); 249 250 while (--count && !s3c24xx_serial_txempty_nofifo(port)) 251 udelay(100); 252 253 ufcon = rd_regl(port, S3C2410_UFCON); 254 ufcon |= S3C2410_UFCON_RESETRX; 255 wr_regl(port, S3C2410_UFCON, ufcon); 256 257 ucon = rd_regl(port, S3C2410_UCON); 258 ucon |= S3C2410_UCON_RXIRQMODE; 259 wr_regl(port, S3C2410_UCON, ucon); 260 261 ourport->rx_enabled = 1; 262 spin_unlock_irqrestore(&port->lock, flags); 263 } 264 265 static void s3c24xx_serial_rx_disable(struct uart_port *port) 266 { 267 struct s3c24xx_uart_port *ourport = to_ourport(port); 268 unsigned long flags; 269 unsigned int ucon; 270 271 spin_lock_irqsave(&port->lock, flags); 272 273 ucon = rd_regl(port, S3C2410_UCON); 274 ucon &= ~S3C2410_UCON_RXIRQMODE; 275 wr_regl(port, S3C2410_UCON, ucon); 276 277 ourport->rx_enabled = 0; 278 spin_unlock_irqrestore(&port->lock, flags); 279 } 280 281 static void s3c24xx_serial_stop_tx(struct uart_port *port) 282 { 283 struct s3c24xx_uart_port *ourport = to_ourport(port); 284 struct s3c24xx_uart_dma *dma = ourport->dma; 285 struct circ_buf *xmit = &port->state->xmit; 286 struct dma_tx_state state; 287 int count; 288 289 if (!ourport->tx_enabled) 290 return; 291 292 switch (ourport->info->type) { 293 case TYPE_S3C6400: 294 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM); 295 break; 296 case TYPE_APPLE_S5L: 297 s3c24xx_clear_bit(port, APPLE_S5L_UCON_TXTHRESH_ENA, S3C2410_UCON); 298 break; 299 default: 300 disable_irq_nosync(ourport->tx_irq); 301 break; 302 } 303 304 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) { 305 dmaengine_pause(dma->tx_chan); 306 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state); 307 dmaengine_terminate_all(dma->tx_chan); 308 dma_sync_single_for_cpu(dma->tx_chan->device->dev, 309 dma->tx_transfer_addr, dma->tx_size, 310 DMA_TO_DEVICE); 311 async_tx_ack(dma->tx_desc); 312 count = dma->tx_bytes_requested - state.residue; 313 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 314 port->icount.tx += count; 315 } 316 317 ourport->tx_enabled = 0; 318 ourport->tx_in_progress = 0; 319 320 if (port->flags & UPF_CONS_FLOW) 321 s3c24xx_serial_rx_enable(port); 322 323 ourport->tx_mode = 0; 324 } 325 326 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport); 327 328 static void s3c24xx_serial_tx_dma_complete(void *args) 329 { 330 struct s3c24xx_uart_port *ourport = args; 331 struct uart_port *port = &ourport->port; 332 struct circ_buf *xmit = &port->state->xmit; 333 struct s3c24xx_uart_dma *dma = ourport->dma; 334 struct dma_tx_state state; 335 unsigned long flags; 336 int count; 337 338 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state); 339 count = dma->tx_bytes_requested - state.residue; 340 async_tx_ack(dma->tx_desc); 341 342 dma_sync_single_for_cpu(dma->tx_chan->device->dev, 343 dma->tx_transfer_addr, dma->tx_size, 344 DMA_TO_DEVICE); 345 346 spin_lock_irqsave(&port->lock, flags); 347 348 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 349 port->icount.tx += count; 350 ourport->tx_in_progress = 0; 351 352 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 353 uart_write_wakeup(port); 354 355 s3c24xx_serial_start_next_tx(ourport); 356 spin_unlock_irqrestore(&port->lock, flags); 357 } 358 359 static void enable_tx_dma(struct s3c24xx_uart_port *ourport) 360 { 361 struct uart_port *port = &ourport->port; 362 u32 ucon; 363 364 /* Mask Tx interrupt */ 365 switch (ourport->info->type) { 366 case TYPE_S3C6400: 367 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM); 368 break; 369 case TYPE_APPLE_S5L: 370 WARN_ON(1); // No DMA 371 break; 372 default: 373 disable_irq_nosync(ourport->tx_irq); 374 break; 375 } 376 377 /* Enable tx dma mode */ 378 ucon = rd_regl(port, S3C2410_UCON); 379 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK); 380 ucon |= (dma_get_cache_alignment() >= 16) ? 381 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1; 382 ucon |= S3C64XX_UCON_TXMODE_DMA; 383 wr_regl(port, S3C2410_UCON, ucon); 384 385 ourport->tx_mode = S3C24XX_TX_DMA; 386 } 387 388 static void enable_tx_pio(struct s3c24xx_uart_port *ourport) 389 { 390 struct uart_port *port = &ourport->port; 391 u32 ucon, ufcon; 392 393 /* Set ufcon txtrig */ 394 ourport->tx_in_progress = S3C24XX_TX_PIO; 395 ufcon = rd_regl(port, S3C2410_UFCON); 396 wr_regl(port, S3C2410_UFCON, ufcon); 397 398 /* Enable tx pio mode */ 399 ucon = rd_regl(port, S3C2410_UCON); 400 ucon &= ~(S3C64XX_UCON_TXMODE_MASK); 401 ucon |= S3C64XX_UCON_TXMODE_CPU; 402 wr_regl(port, S3C2410_UCON, ucon); 403 404 /* Unmask Tx interrupt */ 405 switch (ourport->info->type) { 406 case TYPE_S3C6400: 407 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD, 408 S3C64XX_UINTM); 409 break; 410 case TYPE_APPLE_S5L: 411 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK; 412 wr_regl(port, S3C2410_UCON, ucon); 413 break; 414 default: 415 enable_irq(ourport->tx_irq); 416 break; 417 } 418 419 ourport->tx_mode = S3C24XX_TX_PIO; 420 421 /* 422 * The Apple version only has edge triggered TX IRQs, so we need 423 * to kick off the process by sending some characters here. 424 */ 425 if (ourport->info->type == TYPE_APPLE_S5L) 426 s3c24xx_serial_tx_chars(ourport); 427 } 428 429 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport) 430 { 431 if (ourport->tx_mode != S3C24XX_TX_PIO) 432 enable_tx_pio(ourport); 433 } 434 435 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport, 436 unsigned int count) 437 { 438 struct uart_port *port = &ourport->port; 439 struct circ_buf *xmit = &port->state->xmit; 440 struct s3c24xx_uart_dma *dma = ourport->dma; 441 442 if (ourport->tx_mode != S3C24XX_TX_DMA) 443 enable_tx_dma(ourport); 444 445 dma->tx_size = count & ~(dma_get_cache_alignment() - 1); 446 dma->tx_transfer_addr = dma->tx_addr + xmit->tail; 447 448 dma_sync_single_for_device(dma->tx_chan->device->dev, 449 dma->tx_transfer_addr, dma->tx_size, 450 DMA_TO_DEVICE); 451 452 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan, 453 dma->tx_transfer_addr, dma->tx_size, 454 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 455 if (!dma->tx_desc) { 456 dev_err(ourport->port.dev, "Unable to get desc for Tx\n"); 457 return -EIO; 458 } 459 460 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete; 461 dma->tx_desc->callback_param = ourport; 462 dma->tx_bytes_requested = dma->tx_size; 463 464 ourport->tx_in_progress = S3C24XX_TX_DMA; 465 dma->tx_cookie = dmaengine_submit(dma->tx_desc); 466 dma_async_issue_pending(dma->tx_chan); 467 return 0; 468 } 469 470 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport) 471 { 472 struct uart_port *port = &ourport->port; 473 struct circ_buf *xmit = &port->state->xmit; 474 unsigned long count; 475 476 /* Get data size up to the end of buffer */ 477 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 478 479 if (!count) { 480 s3c24xx_serial_stop_tx(port); 481 return; 482 } 483 484 if (!ourport->dma || !ourport->dma->tx_chan || 485 count < ourport->min_dma_size || 486 xmit->tail & (dma_get_cache_alignment() - 1)) 487 s3c24xx_serial_start_tx_pio(ourport); 488 else 489 s3c24xx_serial_start_tx_dma(ourport, count); 490 } 491 492 static void s3c24xx_serial_start_tx(struct uart_port *port) 493 { 494 struct s3c24xx_uart_port *ourport = to_ourport(port); 495 struct circ_buf *xmit = &port->state->xmit; 496 497 if (!ourport->tx_enabled) { 498 if (port->flags & UPF_CONS_FLOW) 499 s3c24xx_serial_rx_disable(port); 500 501 ourport->tx_enabled = 1; 502 if (!ourport->dma || !ourport->dma->tx_chan) 503 s3c24xx_serial_start_tx_pio(ourport); 504 } 505 506 if (ourport->dma && ourport->dma->tx_chan) { 507 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress) 508 s3c24xx_serial_start_next_tx(ourport); 509 } 510 } 511 512 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport, 513 struct tty_port *tty, int count) 514 { 515 struct s3c24xx_uart_dma *dma = ourport->dma; 516 int copied; 517 518 if (!count) 519 return; 520 521 dma_sync_single_for_cpu(dma->rx_chan->device->dev, dma->rx_addr, 522 dma->rx_size, DMA_FROM_DEVICE); 523 524 ourport->port.icount.rx += count; 525 if (!tty) { 526 dev_err(ourport->port.dev, "No tty port\n"); 527 return; 528 } 529 copied = tty_insert_flip_string(tty, 530 ((unsigned char *)(ourport->dma->rx_buf)), count); 531 if (copied != count) { 532 WARN_ON(1); 533 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n"); 534 } 535 } 536 537 static void s3c24xx_serial_stop_rx(struct uart_port *port) 538 { 539 struct s3c24xx_uart_port *ourport = to_ourport(port); 540 struct s3c24xx_uart_dma *dma = ourport->dma; 541 struct tty_port *t = &port->state->port; 542 struct dma_tx_state state; 543 enum dma_status dma_status; 544 unsigned int received; 545 546 if (ourport->rx_enabled) { 547 dev_dbg(port->dev, "stopping rx\n"); 548 switch (ourport->info->type) { 549 case TYPE_S3C6400: 550 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD, 551 S3C64XX_UINTM); 552 break; 553 case TYPE_APPLE_S5L: 554 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON); 555 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON); 556 break; 557 default: 558 disable_irq_nosync(ourport->rx_irq); 559 break; 560 } 561 ourport->rx_enabled = 0; 562 } 563 if (dma && dma->rx_chan) { 564 dmaengine_pause(dma->tx_chan); 565 dma_status = dmaengine_tx_status(dma->rx_chan, 566 dma->rx_cookie, &state); 567 if (dma_status == DMA_IN_PROGRESS || 568 dma_status == DMA_PAUSED) { 569 received = dma->rx_bytes_requested - state.residue; 570 dmaengine_terminate_all(dma->rx_chan); 571 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 572 } 573 } 574 } 575 576 static inline struct s3c24xx_uart_info 577 *s3c24xx_port_to_info(struct uart_port *port) 578 { 579 return to_ourport(port)->info; 580 } 581 582 static inline struct s3c2410_uartcfg 583 *s3c24xx_port_to_cfg(struct uart_port *port) 584 { 585 struct s3c24xx_uart_port *ourport; 586 587 if (port->dev == NULL) 588 return NULL; 589 590 ourport = container_of(port, struct s3c24xx_uart_port, port); 591 return ourport->cfg; 592 } 593 594 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport, 595 unsigned long ufstat) 596 { 597 struct s3c24xx_uart_info *info = ourport->info; 598 599 if (ufstat & info->rx_fifofull) 600 return ourport->port.fifosize; 601 602 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift; 603 } 604 605 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport); 606 static void s3c24xx_serial_rx_dma_complete(void *args) 607 { 608 struct s3c24xx_uart_port *ourport = args; 609 struct uart_port *port = &ourport->port; 610 611 struct s3c24xx_uart_dma *dma = ourport->dma; 612 struct tty_port *t = &port->state->port; 613 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port); 614 615 struct dma_tx_state state; 616 unsigned long flags; 617 int received; 618 619 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state); 620 received = dma->rx_bytes_requested - state.residue; 621 async_tx_ack(dma->rx_desc); 622 623 spin_lock_irqsave(&port->lock, flags); 624 625 if (received) 626 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 627 628 if (tty) { 629 tty_flip_buffer_push(t); 630 tty_kref_put(tty); 631 } 632 633 s3c64xx_start_rx_dma(ourport); 634 635 spin_unlock_irqrestore(&port->lock, flags); 636 } 637 638 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport) 639 { 640 struct s3c24xx_uart_dma *dma = ourport->dma; 641 642 dma_sync_single_for_device(dma->rx_chan->device->dev, dma->rx_addr, 643 dma->rx_size, DMA_FROM_DEVICE); 644 645 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan, 646 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM, 647 DMA_PREP_INTERRUPT); 648 if (!dma->rx_desc) { 649 dev_err(ourport->port.dev, "Unable to get desc for Rx\n"); 650 return; 651 } 652 653 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete; 654 dma->rx_desc->callback_param = ourport; 655 dma->rx_bytes_requested = dma->rx_size; 656 657 dma->rx_cookie = dmaengine_submit(dma->rx_desc); 658 dma_async_issue_pending(dma->rx_chan); 659 } 660 661 /* ? - where has parity gone?? */ 662 #define S3C2410_UERSTAT_PARITY (0x1000) 663 664 static void enable_rx_dma(struct s3c24xx_uart_port *ourport) 665 { 666 struct uart_port *port = &ourport->port; 667 unsigned int ucon; 668 669 /* set Rx mode to DMA mode */ 670 ucon = rd_regl(port, S3C2410_UCON); 671 ucon &= ~(S3C64XX_UCON_RXBURST_MASK | 672 S3C64XX_UCON_TIMEOUT_MASK | 673 S3C64XX_UCON_EMPTYINT_EN | 674 S3C64XX_UCON_DMASUS_EN | 675 S3C64XX_UCON_TIMEOUT_EN | 676 S3C64XX_UCON_RXMODE_MASK); 677 ucon |= S3C64XX_UCON_RXBURST_16 | 678 0xf << S3C64XX_UCON_TIMEOUT_SHIFT | 679 S3C64XX_UCON_EMPTYINT_EN | 680 S3C64XX_UCON_TIMEOUT_EN | 681 S3C64XX_UCON_RXMODE_DMA; 682 wr_regl(port, S3C2410_UCON, ucon); 683 684 ourport->rx_mode = S3C24XX_RX_DMA; 685 } 686 687 static void enable_rx_pio(struct s3c24xx_uart_port *ourport) 688 { 689 struct uart_port *port = &ourport->port; 690 unsigned int ucon; 691 692 /* set Rx mode to DMA mode */ 693 ucon = rd_regl(port, S3C2410_UCON); 694 ucon &= ~S3C64XX_UCON_RXMODE_MASK; 695 ucon |= S3C64XX_UCON_RXMODE_CPU; 696 697 /* Apple types use these bits for IRQ masks */ 698 if (ourport->info->type != TYPE_APPLE_S5L) { 699 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK | 700 S3C64XX_UCON_EMPTYINT_EN | 701 S3C64XX_UCON_DMASUS_EN | 702 S3C64XX_UCON_TIMEOUT_EN); 703 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT | 704 S3C64XX_UCON_TIMEOUT_EN; 705 } 706 wr_regl(port, S3C2410_UCON, ucon); 707 708 ourport->rx_mode = S3C24XX_RX_PIO; 709 } 710 711 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport); 712 713 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id) 714 { 715 unsigned int utrstat, received; 716 struct s3c24xx_uart_port *ourport = dev_id; 717 struct uart_port *port = &ourport->port; 718 struct s3c24xx_uart_dma *dma = ourport->dma; 719 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port); 720 struct tty_port *t = &port->state->port; 721 struct dma_tx_state state; 722 723 utrstat = rd_regl(port, S3C2410_UTRSTAT); 724 rd_regl(port, S3C2410_UFSTAT); 725 726 spin_lock(&port->lock); 727 728 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) { 729 s3c64xx_start_rx_dma(ourport); 730 if (ourport->rx_mode == S3C24XX_RX_PIO) 731 enable_rx_dma(ourport); 732 goto finish; 733 } 734 735 if (ourport->rx_mode == S3C24XX_RX_DMA) { 736 dmaengine_pause(dma->rx_chan); 737 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state); 738 dmaengine_terminate_all(dma->rx_chan); 739 received = dma->rx_bytes_requested - state.residue; 740 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 741 742 enable_rx_pio(ourport); 743 } 744 745 s3c24xx_serial_rx_drain_fifo(ourport); 746 747 if (tty) { 748 tty_flip_buffer_push(t); 749 tty_kref_put(tty); 750 } 751 752 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT); 753 754 finish: 755 spin_unlock(&port->lock); 756 757 return IRQ_HANDLED; 758 } 759 760 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport) 761 { 762 struct uart_port *port = &ourport->port; 763 unsigned int ufcon, ch, flag, ufstat, uerstat; 764 unsigned int fifocnt = 0; 765 int max_count = port->fifosize; 766 767 while (max_count-- > 0) { 768 /* 769 * Receive all characters known to be in FIFO 770 * before reading FIFO level again 771 */ 772 if (fifocnt == 0) { 773 ufstat = rd_regl(port, S3C2410_UFSTAT); 774 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat); 775 if (fifocnt == 0) 776 break; 777 } 778 fifocnt--; 779 780 uerstat = rd_regl(port, S3C2410_UERSTAT); 781 ch = rd_reg(port, S3C2410_URXH); 782 783 if (port->flags & UPF_CONS_FLOW) { 784 int txe = s3c24xx_serial_txempty_nofifo(port); 785 786 if (ourport->rx_enabled) { 787 if (!txe) { 788 ourport->rx_enabled = 0; 789 continue; 790 } 791 } else { 792 if (txe) { 793 ufcon = rd_regl(port, S3C2410_UFCON); 794 ufcon |= S3C2410_UFCON_RESETRX; 795 wr_regl(port, S3C2410_UFCON, ufcon); 796 ourport->rx_enabled = 1; 797 return; 798 } 799 continue; 800 } 801 } 802 803 /* insert the character into the buffer */ 804 805 flag = TTY_NORMAL; 806 port->icount.rx++; 807 808 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) { 809 dev_dbg(port->dev, 810 "rxerr: port ch=0x%02x, rxs=0x%08x\n", 811 ch, uerstat); 812 813 /* check for break */ 814 if (uerstat & S3C2410_UERSTAT_BREAK) { 815 dev_dbg(port->dev, "break!\n"); 816 port->icount.brk++; 817 if (uart_handle_break(port)) 818 continue; /* Ignore character */ 819 } 820 821 if (uerstat & S3C2410_UERSTAT_FRAME) 822 port->icount.frame++; 823 if (uerstat & S3C2410_UERSTAT_OVERRUN) 824 port->icount.overrun++; 825 826 uerstat &= port->read_status_mask; 827 828 if (uerstat & S3C2410_UERSTAT_BREAK) 829 flag = TTY_BREAK; 830 else if (uerstat & S3C2410_UERSTAT_PARITY) 831 flag = TTY_PARITY; 832 else if (uerstat & (S3C2410_UERSTAT_FRAME | 833 S3C2410_UERSTAT_OVERRUN)) 834 flag = TTY_FRAME; 835 } 836 837 if (uart_handle_sysrq_char(port, ch)) 838 continue; /* Ignore character */ 839 840 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, 841 ch, flag); 842 } 843 844 tty_flip_buffer_push(&port->state->port); 845 } 846 847 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id) 848 { 849 struct s3c24xx_uart_port *ourport = dev_id; 850 struct uart_port *port = &ourport->port; 851 852 spin_lock(&port->lock); 853 s3c24xx_serial_rx_drain_fifo(ourport); 854 spin_unlock(&port->lock); 855 856 return IRQ_HANDLED; 857 } 858 859 static irqreturn_t s3c24xx_serial_rx_irq(int irq, void *dev_id) 860 { 861 struct s3c24xx_uart_port *ourport = dev_id; 862 863 if (ourport->dma && ourport->dma->rx_chan) 864 return s3c24xx_serial_rx_chars_dma(dev_id); 865 return s3c24xx_serial_rx_chars_pio(dev_id); 866 } 867 868 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport) 869 { 870 struct uart_port *port = &ourport->port; 871 struct circ_buf *xmit = &port->state->xmit; 872 int count, dma_count = 0; 873 874 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 875 876 if (ourport->dma && ourport->dma->tx_chan && 877 count >= ourport->min_dma_size) { 878 int align = dma_get_cache_alignment() - 879 (xmit->tail & (dma_get_cache_alignment() - 1)); 880 if (count - align >= ourport->min_dma_size) { 881 dma_count = count - align; 882 count = align; 883 } 884 } 885 886 if (port->x_char) { 887 wr_reg(port, S3C2410_UTXH, port->x_char); 888 port->icount.tx++; 889 port->x_char = 0; 890 return; 891 } 892 893 /* if there isn't anything more to transmit, or the uart is now 894 * stopped, disable the uart and exit 895 */ 896 897 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 898 s3c24xx_serial_stop_tx(port); 899 return; 900 } 901 902 /* try and drain the buffer... */ 903 904 if (count > port->fifosize) { 905 count = port->fifosize; 906 dma_count = 0; 907 } 908 909 while (!uart_circ_empty(xmit) && count > 0) { 910 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull) 911 break; 912 913 wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]); 914 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 915 port->icount.tx++; 916 count--; 917 } 918 919 if (!count && dma_count) { 920 s3c24xx_serial_start_tx_dma(ourport, dma_count); 921 return; 922 } 923 924 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) { 925 spin_unlock(&port->lock); 926 uart_write_wakeup(port); 927 spin_lock(&port->lock); 928 } 929 930 if (uart_circ_empty(xmit)) 931 s3c24xx_serial_stop_tx(port); 932 } 933 934 static irqreturn_t s3c24xx_serial_tx_irq(int irq, void *id) 935 { 936 struct s3c24xx_uart_port *ourport = id; 937 struct uart_port *port = &ourport->port; 938 939 spin_lock(&port->lock); 940 941 s3c24xx_serial_tx_chars(ourport); 942 943 spin_unlock(&port->lock); 944 return IRQ_HANDLED; 945 } 946 947 /* interrupt handler for s3c64xx and later SoC's.*/ 948 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id) 949 { 950 struct s3c24xx_uart_port *ourport = id; 951 struct uart_port *port = &ourport->port; 952 unsigned int pend = rd_regl(port, S3C64XX_UINTP); 953 irqreturn_t ret = IRQ_HANDLED; 954 955 if (pend & S3C64XX_UINTM_RXD_MSK) { 956 ret = s3c24xx_serial_rx_irq(irq, id); 957 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK); 958 } 959 if (pend & S3C64XX_UINTM_TXD_MSK) { 960 ret = s3c24xx_serial_tx_irq(irq, id); 961 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK); 962 } 963 return ret; 964 } 965 966 /* interrupt handler for Apple SoC's.*/ 967 static irqreturn_t apple_serial_handle_irq(int irq, void *id) 968 { 969 struct s3c24xx_uart_port *ourport = id; 970 struct uart_port *port = &ourport->port; 971 unsigned int pend = rd_regl(port, S3C2410_UTRSTAT); 972 irqreturn_t ret = IRQ_NONE; 973 974 if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) { 975 wr_regl(port, S3C2410_UTRSTAT, 976 APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO); 977 ret = s3c24xx_serial_rx_irq(irq, id); 978 } 979 if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) { 980 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH); 981 ret = s3c24xx_serial_tx_irq(irq, id); 982 } 983 984 return ret; 985 } 986 987 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) 988 { 989 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 990 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT); 991 unsigned long ufcon = rd_regl(port, S3C2410_UFCON); 992 993 if (ufcon & S3C2410_UFCON_FIFOMODE) { 994 if ((ufstat & info->tx_fifomask) != 0 || 995 (ufstat & info->tx_fifofull)) 996 return 0; 997 998 return 1; 999 } 1000 1001 return s3c24xx_serial_txempty_nofifo(port); 1002 } 1003 1004 /* no modem control lines */ 1005 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) 1006 { 1007 unsigned int umstat = rd_reg(port, S3C2410_UMSTAT); 1008 1009 if (umstat & S3C2410_UMSTAT_CTS) 1010 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 1011 else 1012 return TIOCM_CAR | TIOCM_DSR; 1013 } 1014 1015 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) 1016 { 1017 unsigned int umcon = rd_regl(port, S3C2410_UMCON); 1018 1019 if (mctrl & TIOCM_RTS) 1020 umcon |= S3C2410_UMCOM_RTS_LOW; 1021 else 1022 umcon &= ~S3C2410_UMCOM_RTS_LOW; 1023 1024 wr_regl(port, S3C2410_UMCON, umcon); 1025 } 1026 1027 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state) 1028 { 1029 unsigned long flags; 1030 unsigned int ucon; 1031 1032 spin_lock_irqsave(&port->lock, flags); 1033 1034 ucon = rd_regl(port, S3C2410_UCON); 1035 1036 if (break_state) 1037 ucon |= S3C2410_UCON_SBREAK; 1038 else 1039 ucon &= ~S3C2410_UCON_SBREAK; 1040 1041 wr_regl(port, S3C2410_UCON, ucon); 1042 1043 spin_unlock_irqrestore(&port->lock, flags); 1044 } 1045 1046 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p) 1047 { 1048 struct s3c24xx_uart_dma *dma = p->dma; 1049 struct dma_slave_caps dma_caps; 1050 const char *reason = NULL; 1051 int ret; 1052 1053 /* Default slave configuration parameters */ 1054 dma->rx_conf.direction = DMA_DEV_TO_MEM; 1055 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1056 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH; 1057 dma->rx_conf.src_maxburst = 1; 1058 1059 dma->tx_conf.direction = DMA_MEM_TO_DEV; 1060 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1061 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH; 1062 dma->tx_conf.dst_maxburst = 1; 1063 1064 dma->rx_chan = dma_request_chan(p->port.dev, "rx"); 1065 1066 if (IS_ERR(dma->rx_chan)) { 1067 reason = "DMA RX channel request failed"; 1068 ret = PTR_ERR(dma->rx_chan); 1069 goto err_warn; 1070 } 1071 1072 ret = dma_get_slave_caps(dma->rx_chan, &dma_caps); 1073 if (ret < 0 || 1074 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) { 1075 reason = "insufficient DMA RX engine capabilities"; 1076 ret = -EOPNOTSUPP; 1077 goto err_release_rx; 1078 } 1079 1080 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf); 1081 1082 dma->tx_chan = dma_request_chan(p->port.dev, "tx"); 1083 if (IS_ERR(dma->tx_chan)) { 1084 reason = "DMA TX channel request failed"; 1085 ret = PTR_ERR(dma->tx_chan); 1086 goto err_release_rx; 1087 } 1088 1089 ret = dma_get_slave_caps(dma->tx_chan, &dma_caps); 1090 if (ret < 0 || 1091 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) { 1092 reason = "insufficient DMA TX engine capabilities"; 1093 ret = -EOPNOTSUPP; 1094 goto err_release_tx; 1095 } 1096 1097 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf); 1098 1099 /* RX buffer */ 1100 dma->rx_size = PAGE_SIZE; 1101 1102 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL); 1103 if (!dma->rx_buf) { 1104 ret = -ENOMEM; 1105 goto err_release_tx; 1106 } 1107 1108 dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf, 1109 dma->rx_size, DMA_FROM_DEVICE); 1110 if (dma_mapping_error(dma->rx_chan->device->dev, dma->rx_addr)) { 1111 reason = "DMA mapping error for RX buffer"; 1112 ret = -EIO; 1113 goto err_free_rx; 1114 } 1115 1116 /* TX buffer */ 1117 dma->tx_addr = dma_map_single(dma->tx_chan->device->dev, 1118 p->port.state->xmit.buf, UART_XMIT_SIZE, 1119 DMA_TO_DEVICE); 1120 if (dma_mapping_error(dma->tx_chan->device->dev, dma->tx_addr)) { 1121 reason = "DMA mapping error for TX buffer"; 1122 ret = -EIO; 1123 goto err_unmap_rx; 1124 } 1125 1126 return 0; 1127 1128 err_unmap_rx: 1129 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr, 1130 dma->rx_size, DMA_FROM_DEVICE); 1131 err_free_rx: 1132 kfree(dma->rx_buf); 1133 err_release_tx: 1134 dma_release_channel(dma->tx_chan); 1135 err_release_rx: 1136 dma_release_channel(dma->rx_chan); 1137 err_warn: 1138 if (reason) 1139 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason); 1140 return ret; 1141 } 1142 1143 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p) 1144 { 1145 struct s3c24xx_uart_dma *dma = p->dma; 1146 1147 if (dma->rx_chan) { 1148 dmaengine_terminate_all(dma->rx_chan); 1149 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr, 1150 dma->rx_size, DMA_FROM_DEVICE); 1151 kfree(dma->rx_buf); 1152 dma_release_channel(dma->rx_chan); 1153 dma->rx_chan = NULL; 1154 } 1155 1156 if (dma->tx_chan) { 1157 dmaengine_terminate_all(dma->tx_chan); 1158 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr, 1159 UART_XMIT_SIZE, DMA_TO_DEVICE); 1160 dma_release_channel(dma->tx_chan); 1161 dma->tx_chan = NULL; 1162 } 1163 } 1164 1165 static void s3c24xx_serial_shutdown(struct uart_port *port) 1166 { 1167 struct s3c24xx_uart_port *ourport = to_ourport(port); 1168 1169 if (ourport->tx_claimed) { 1170 free_irq(ourport->tx_irq, ourport); 1171 ourport->tx_enabled = 0; 1172 ourport->tx_claimed = 0; 1173 ourport->tx_mode = 0; 1174 } 1175 1176 if (ourport->rx_claimed) { 1177 free_irq(ourport->rx_irq, ourport); 1178 ourport->rx_claimed = 0; 1179 ourport->rx_enabled = 0; 1180 } 1181 1182 if (ourport->dma) 1183 s3c24xx_serial_release_dma(ourport); 1184 1185 ourport->tx_in_progress = 0; 1186 } 1187 1188 static void s3c64xx_serial_shutdown(struct uart_port *port) 1189 { 1190 struct s3c24xx_uart_port *ourport = to_ourport(port); 1191 1192 ourport->tx_enabled = 0; 1193 ourport->tx_mode = 0; 1194 ourport->rx_enabled = 0; 1195 1196 free_irq(port->irq, ourport); 1197 1198 wr_regl(port, S3C64XX_UINTP, 0xf); 1199 wr_regl(port, S3C64XX_UINTM, 0xf); 1200 1201 if (ourport->dma) 1202 s3c24xx_serial_release_dma(ourport); 1203 1204 ourport->tx_in_progress = 0; 1205 } 1206 1207 static void apple_s5l_serial_shutdown(struct uart_port *port) 1208 { 1209 struct s3c24xx_uart_port *ourport = to_ourport(port); 1210 1211 unsigned int ucon; 1212 1213 ucon = rd_regl(port, S3C2410_UCON); 1214 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | 1215 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 1216 APPLE_S5L_UCON_RXTO_ENA_MSK); 1217 wr_regl(port, S3C2410_UCON, ucon); 1218 1219 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS); 1220 1221 free_irq(port->irq, ourport); 1222 1223 ourport->tx_enabled = 0; 1224 ourport->tx_mode = 0; 1225 ourport->rx_enabled = 0; 1226 1227 if (ourport->dma) 1228 s3c24xx_serial_release_dma(ourport); 1229 1230 ourport->tx_in_progress = 0; 1231 } 1232 1233 static int s3c24xx_serial_startup(struct uart_port *port) 1234 { 1235 struct s3c24xx_uart_port *ourport = to_ourport(port); 1236 int ret; 1237 1238 ourport->rx_enabled = 1; 1239 1240 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_irq, 0, 1241 s3c24xx_serial_portname(port), ourport); 1242 1243 if (ret != 0) { 1244 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq); 1245 return ret; 1246 } 1247 1248 ourport->rx_claimed = 1; 1249 1250 dev_dbg(port->dev, "requesting tx irq...\n"); 1251 1252 ourport->tx_enabled = 1; 1253 1254 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_irq, 0, 1255 s3c24xx_serial_portname(port), ourport); 1256 1257 if (ret) { 1258 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq); 1259 goto err; 1260 } 1261 1262 ourport->tx_claimed = 1; 1263 1264 /* the port reset code should have done the correct 1265 * register setup for the port controls 1266 */ 1267 1268 return ret; 1269 1270 err: 1271 s3c24xx_serial_shutdown(port); 1272 return ret; 1273 } 1274 1275 static int s3c64xx_serial_startup(struct uart_port *port) 1276 { 1277 struct s3c24xx_uart_port *ourport = to_ourport(port); 1278 unsigned long flags; 1279 unsigned int ufcon; 1280 int ret; 1281 1282 wr_regl(port, S3C64XX_UINTM, 0xf); 1283 if (ourport->dma) { 1284 ret = s3c24xx_serial_request_dma(ourport); 1285 if (ret < 0) { 1286 devm_kfree(port->dev, ourport->dma); 1287 ourport->dma = NULL; 1288 } 1289 } 1290 1291 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED, 1292 s3c24xx_serial_portname(port), ourport); 1293 if (ret) { 1294 dev_err(port->dev, "cannot get irq %d\n", port->irq); 1295 return ret; 1296 } 1297 1298 /* For compatibility with s3c24xx Soc's */ 1299 ourport->rx_enabled = 1; 1300 ourport->tx_enabled = 0; 1301 1302 spin_lock_irqsave(&port->lock, flags); 1303 1304 ufcon = rd_regl(port, S3C2410_UFCON); 1305 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8; 1306 if (!uart_console(port)) 1307 ufcon |= S3C2410_UFCON_RESETTX; 1308 wr_regl(port, S3C2410_UFCON, ufcon); 1309 1310 enable_rx_pio(ourport); 1311 1312 spin_unlock_irqrestore(&port->lock, flags); 1313 1314 /* Enable Rx Interrupt */ 1315 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM); 1316 1317 return ret; 1318 } 1319 1320 static int apple_s5l_serial_startup(struct uart_port *port) 1321 { 1322 struct s3c24xx_uart_port *ourport = to_ourport(port); 1323 unsigned long flags; 1324 unsigned int ufcon; 1325 int ret; 1326 1327 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS); 1328 1329 ret = request_irq(port->irq, apple_serial_handle_irq, 0, 1330 s3c24xx_serial_portname(port), ourport); 1331 if (ret) { 1332 dev_err(port->dev, "cannot get irq %d\n", port->irq); 1333 return ret; 1334 } 1335 1336 /* For compatibility with s3c24xx Soc's */ 1337 ourport->rx_enabled = 1; 1338 ourport->tx_enabled = 0; 1339 1340 spin_lock_irqsave(&port->lock, flags); 1341 1342 ufcon = rd_regl(port, S3C2410_UFCON); 1343 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8; 1344 if (!uart_console(port)) 1345 ufcon |= S3C2410_UFCON_RESETTX; 1346 wr_regl(port, S3C2410_UFCON, ufcon); 1347 1348 enable_rx_pio(ourport); 1349 1350 spin_unlock_irqrestore(&port->lock, flags); 1351 1352 /* Enable Rx Interrupt */ 1353 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON); 1354 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON); 1355 1356 return ret; 1357 } 1358 1359 /* power power management control */ 1360 1361 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, 1362 unsigned int old) 1363 { 1364 struct s3c24xx_uart_port *ourport = to_ourport(port); 1365 int timeout = 10000; 1366 1367 ourport->pm_level = level; 1368 1369 switch (level) { 1370 case 3: 1371 while (--timeout && !s3c24xx_serial_txempty_nofifo(port)) 1372 udelay(100); 1373 1374 if (!IS_ERR(ourport->baudclk)) 1375 clk_disable_unprepare(ourport->baudclk); 1376 1377 clk_disable_unprepare(ourport->clk); 1378 break; 1379 1380 case 0: 1381 clk_prepare_enable(ourport->clk); 1382 1383 if (!IS_ERR(ourport->baudclk)) 1384 clk_prepare_enable(ourport->baudclk); 1385 break; 1386 default: 1387 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level); 1388 } 1389 } 1390 1391 /* baud rate calculation 1392 * 1393 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number 1394 * of different sources, including the peripheral clock ("pclk") and an 1395 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk") 1396 * with a programmable extra divisor. 1397 * 1398 * The following code goes through the clock sources, and calculates the 1399 * baud clocks (and the resultant actual baud rates) and then tries to 1400 * pick the closest one and select that. 1401 * 1402 */ 1403 1404 #define MAX_CLK_NAME_LENGTH 15 1405 1406 static inline int s3c24xx_serial_getsource(struct uart_port *port) 1407 { 1408 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1409 unsigned int ucon; 1410 1411 if (info->num_clks == 1) 1412 return 0; 1413 1414 ucon = rd_regl(port, S3C2410_UCON); 1415 ucon &= info->clksel_mask; 1416 return ucon >> info->clksel_shift; 1417 } 1418 1419 static void s3c24xx_serial_setsource(struct uart_port *port, 1420 unsigned int clk_sel) 1421 { 1422 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1423 unsigned int ucon; 1424 1425 if (info->num_clks == 1) 1426 return; 1427 1428 ucon = rd_regl(port, S3C2410_UCON); 1429 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel) 1430 return; 1431 1432 ucon &= ~info->clksel_mask; 1433 ucon |= clk_sel << info->clksel_shift; 1434 wr_regl(port, S3C2410_UCON, ucon); 1435 } 1436 1437 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport, 1438 unsigned int req_baud, struct clk **best_clk, 1439 unsigned int *clk_num) 1440 { 1441 struct s3c24xx_uart_info *info = ourport->info; 1442 struct clk *clk; 1443 unsigned long rate; 1444 unsigned int cnt, baud, quot, best_quot = 0; 1445 char clkname[MAX_CLK_NAME_LENGTH]; 1446 int calc_deviation, deviation = (1 << 30) - 1; 1447 1448 for (cnt = 0; cnt < info->num_clks; cnt++) { 1449 /* Keep selected clock if provided */ 1450 if (ourport->cfg->clk_sel && 1451 !(ourport->cfg->clk_sel & (1 << cnt))) 1452 continue; 1453 1454 sprintf(clkname, "clk_uart_baud%d", cnt); 1455 clk = clk_get(ourport->port.dev, clkname); 1456 if (IS_ERR(clk)) 1457 continue; 1458 1459 rate = clk_get_rate(clk); 1460 if (!rate) 1461 continue; 1462 1463 if (ourport->info->has_divslot) { 1464 unsigned long div = rate / req_baud; 1465 1466 /* The UDIVSLOT register on the newer UARTs allows us to 1467 * get a divisor adjustment of 1/16th on the baud clock. 1468 * 1469 * We don't keep the UDIVSLOT value (the 16ths we 1470 * calculated by not multiplying the baud by 16) as it 1471 * is easy enough to recalculate. 1472 */ 1473 1474 quot = div / 16; 1475 baud = rate / div; 1476 } else { 1477 quot = (rate + (8 * req_baud)) / (16 * req_baud); 1478 baud = rate / (quot * 16); 1479 } 1480 quot--; 1481 1482 calc_deviation = req_baud - baud; 1483 if (calc_deviation < 0) 1484 calc_deviation = -calc_deviation; 1485 1486 if (calc_deviation < deviation) { 1487 *best_clk = clk; 1488 best_quot = quot; 1489 *clk_num = cnt; 1490 deviation = calc_deviation; 1491 } 1492 } 1493 1494 return best_quot; 1495 } 1496 1497 /* udivslot_table[] 1498 * 1499 * This table takes the fractional value of the baud divisor and gives 1500 * the recommended setting for the UDIVSLOT register. 1501 */ 1502 static u16 udivslot_table[16] = { 1503 [0] = 0x0000, 1504 [1] = 0x0080, 1505 [2] = 0x0808, 1506 [3] = 0x0888, 1507 [4] = 0x2222, 1508 [5] = 0x4924, 1509 [6] = 0x4A52, 1510 [7] = 0x54AA, 1511 [8] = 0x5555, 1512 [9] = 0xD555, 1513 [10] = 0xD5D5, 1514 [11] = 0xDDD5, 1515 [12] = 0xDDDD, 1516 [13] = 0xDFDD, 1517 [14] = 0xDFDF, 1518 [15] = 0xFFDF, 1519 }; 1520 1521 static void s3c24xx_serial_set_termios(struct uart_port *port, 1522 struct ktermios *termios, 1523 struct ktermios *old) 1524 { 1525 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port); 1526 struct s3c24xx_uart_port *ourport = to_ourport(port); 1527 struct clk *clk = ERR_PTR(-EINVAL); 1528 unsigned long flags; 1529 unsigned int baud, quot, clk_sel = 0; 1530 unsigned int ulcon; 1531 unsigned int umcon; 1532 unsigned int udivslot = 0; 1533 1534 /* 1535 * We don't support modem control lines. 1536 */ 1537 termios->c_cflag &= ~(HUPCL | CMSPAR); 1538 termios->c_cflag |= CLOCAL; 1539 1540 /* 1541 * Ask the core to calculate the divisor for us. 1542 */ 1543 1544 baud = uart_get_baud_rate(port, termios, old, 0, 3000000); 1545 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel); 1546 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) 1547 quot = port->custom_divisor; 1548 if (IS_ERR(clk)) 1549 return; 1550 1551 /* check to see if we need to change clock source */ 1552 1553 if (ourport->baudclk != clk) { 1554 clk_prepare_enable(clk); 1555 1556 s3c24xx_serial_setsource(port, clk_sel); 1557 1558 if (!IS_ERR(ourport->baudclk)) { 1559 clk_disable_unprepare(ourport->baudclk); 1560 ourport->baudclk = ERR_PTR(-EINVAL); 1561 } 1562 1563 ourport->baudclk = clk; 1564 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0; 1565 } 1566 1567 if (ourport->info->has_divslot) { 1568 unsigned int div = ourport->baudclk_rate / baud; 1569 1570 if (cfg->has_fracval) { 1571 udivslot = (div & 15); 1572 dev_dbg(port->dev, "fracval = %04x\n", udivslot); 1573 } else { 1574 udivslot = udivslot_table[div & 15]; 1575 dev_dbg(port->dev, "udivslot = %04x (div %d)\n", 1576 udivslot, div & 15); 1577 } 1578 } 1579 1580 switch (termios->c_cflag & CSIZE) { 1581 case CS5: 1582 dev_dbg(port->dev, "config: 5bits/char\n"); 1583 ulcon = S3C2410_LCON_CS5; 1584 break; 1585 case CS6: 1586 dev_dbg(port->dev, "config: 6bits/char\n"); 1587 ulcon = S3C2410_LCON_CS6; 1588 break; 1589 case CS7: 1590 dev_dbg(port->dev, "config: 7bits/char\n"); 1591 ulcon = S3C2410_LCON_CS7; 1592 break; 1593 case CS8: 1594 default: 1595 dev_dbg(port->dev, "config: 8bits/char\n"); 1596 ulcon = S3C2410_LCON_CS8; 1597 break; 1598 } 1599 1600 /* preserve original lcon IR settings */ 1601 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM); 1602 1603 if (termios->c_cflag & CSTOPB) 1604 ulcon |= S3C2410_LCON_STOPB; 1605 1606 if (termios->c_cflag & PARENB) { 1607 if (termios->c_cflag & PARODD) 1608 ulcon |= S3C2410_LCON_PODD; 1609 else 1610 ulcon |= S3C2410_LCON_PEVEN; 1611 } else { 1612 ulcon |= S3C2410_LCON_PNONE; 1613 } 1614 1615 spin_lock_irqsave(&port->lock, flags); 1616 1617 dev_dbg(port->dev, 1618 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n", 1619 ulcon, quot, udivslot); 1620 1621 wr_regl(port, S3C2410_ULCON, ulcon); 1622 wr_regl(port, S3C2410_UBRDIV, quot); 1623 1624 port->status &= ~UPSTAT_AUTOCTS; 1625 1626 umcon = rd_regl(port, S3C2410_UMCON); 1627 if (termios->c_cflag & CRTSCTS) { 1628 umcon |= S3C2410_UMCOM_AFC; 1629 /* Disable RTS when RX FIFO contains 63 bytes */ 1630 umcon &= ~S3C2412_UMCON_AFC_8; 1631 port->status = UPSTAT_AUTOCTS; 1632 } else { 1633 umcon &= ~S3C2410_UMCOM_AFC; 1634 } 1635 wr_regl(port, S3C2410_UMCON, umcon); 1636 1637 if (ourport->info->has_divslot) 1638 wr_regl(port, S3C2443_DIVSLOT, udivslot); 1639 1640 dev_dbg(port->dev, 1641 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n", 1642 rd_regl(port, S3C2410_ULCON), 1643 rd_regl(port, S3C2410_UCON), 1644 rd_regl(port, S3C2410_UFCON)); 1645 1646 /* 1647 * Update the per-port timeout. 1648 */ 1649 uart_update_timeout(port, termios->c_cflag, baud); 1650 1651 /* 1652 * Which character status flags are we interested in? 1653 */ 1654 port->read_status_mask = S3C2410_UERSTAT_OVERRUN; 1655 if (termios->c_iflag & INPCK) 1656 port->read_status_mask |= S3C2410_UERSTAT_FRAME | 1657 S3C2410_UERSTAT_PARITY; 1658 /* 1659 * Which character status flags should we ignore? 1660 */ 1661 port->ignore_status_mask = 0; 1662 if (termios->c_iflag & IGNPAR) 1663 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN; 1664 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR) 1665 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME; 1666 1667 /* 1668 * Ignore all characters if CREAD is not set. 1669 */ 1670 if ((termios->c_cflag & CREAD) == 0) 1671 port->ignore_status_mask |= RXSTAT_DUMMY_READ; 1672 1673 spin_unlock_irqrestore(&port->lock, flags); 1674 } 1675 1676 static const char *s3c24xx_serial_type(struct uart_port *port) 1677 { 1678 struct s3c24xx_uart_port *ourport = to_ourport(port); 1679 1680 switch (ourport->info->type) { 1681 case TYPE_S3C24XX: 1682 return "S3C24XX"; 1683 case TYPE_S3C6400: 1684 return "S3C6400/10"; 1685 case TYPE_APPLE_S5L: 1686 return "APPLE S5L"; 1687 default: 1688 return NULL; 1689 } 1690 } 1691 1692 static void s3c24xx_serial_config_port(struct uart_port *port, int flags) 1693 { 1694 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1695 1696 if (flags & UART_CONFIG_TYPE) 1697 port->type = info->port_type; 1698 } 1699 1700 /* 1701 * verify the new serial_struct (for TIOCSSERIAL). 1702 */ 1703 static int 1704 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser) 1705 { 1706 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1707 1708 if (ser->type != PORT_UNKNOWN && ser->type != info->port_type) 1709 return -EINVAL; 1710 1711 return 0; 1712 } 1713 1714 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 1715 1716 static struct console s3c24xx_serial_console; 1717 1718 static void __init s3c24xx_serial_register_console(void) 1719 { 1720 register_console(&s3c24xx_serial_console); 1721 } 1722 1723 static void s3c24xx_serial_unregister_console(void) 1724 { 1725 if (s3c24xx_serial_console.flags & CON_ENABLED) 1726 unregister_console(&s3c24xx_serial_console); 1727 } 1728 1729 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console 1730 #else 1731 static inline void s3c24xx_serial_register_console(void) { } 1732 static inline void s3c24xx_serial_unregister_console(void) { } 1733 #define S3C24XX_SERIAL_CONSOLE NULL 1734 #endif 1735 1736 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1737 static int s3c24xx_serial_get_poll_char(struct uart_port *port); 1738 static void s3c24xx_serial_put_poll_char(struct uart_port *port, 1739 unsigned char c); 1740 #endif 1741 1742 static const struct uart_ops s3c24xx_serial_ops = { 1743 .pm = s3c24xx_serial_pm, 1744 .tx_empty = s3c24xx_serial_tx_empty, 1745 .get_mctrl = s3c24xx_serial_get_mctrl, 1746 .set_mctrl = s3c24xx_serial_set_mctrl, 1747 .stop_tx = s3c24xx_serial_stop_tx, 1748 .start_tx = s3c24xx_serial_start_tx, 1749 .stop_rx = s3c24xx_serial_stop_rx, 1750 .break_ctl = s3c24xx_serial_break_ctl, 1751 .startup = s3c24xx_serial_startup, 1752 .shutdown = s3c24xx_serial_shutdown, 1753 .set_termios = s3c24xx_serial_set_termios, 1754 .type = s3c24xx_serial_type, 1755 .config_port = s3c24xx_serial_config_port, 1756 .verify_port = s3c24xx_serial_verify_port, 1757 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1758 .poll_get_char = s3c24xx_serial_get_poll_char, 1759 .poll_put_char = s3c24xx_serial_put_poll_char, 1760 #endif 1761 }; 1762 1763 static const struct uart_ops s3c64xx_serial_ops = { 1764 .pm = s3c24xx_serial_pm, 1765 .tx_empty = s3c24xx_serial_tx_empty, 1766 .get_mctrl = s3c24xx_serial_get_mctrl, 1767 .set_mctrl = s3c24xx_serial_set_mctrl, 1768 .stop_tx = s3c24xx_serial_stop_tx, 1769 .start_tx = s3c24xx_serial_start_tx, 1770 .stop_rx = s3c24xx_serial_stop_rx, 1771 .break_ctl = s3c24xx_serial_break_ctl, 1772 .startup = s3c64xx_serial_startup, 1773 .shutdown = s3c64xx_serial_shutdown, 1774 .set_termios = s3c24xx_serial_set_termios, 1775 .type = s3c24xx_serial_type, 1776 .config_port = s3c24xx_serial_config_port, 1777 .verify_port = s3c24xx_serial_verify_port, 1778 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1779 .poll_get_char = s3c24xx_serial_get_poll_char, 1780 .poll_put_char = s3c24xx_serial_put_poll_char, 1781 #endif 1782 }; 1783 1784 static const struct uart_ops apple_s5l_serial_ops = { 1785 .pm = s3c24xx_serial_pm, 1786 .tx_empty = s3c24xx_serial_tx_empty, 1787 .get_mctrl = s3c24xx_serial_get_mctrl, 1788 .set_mctrl = s3c24xx_serial_set_mctrl, 1789 .stop_tx = s3c24xx_serial_stop_tx, 1790 .start_tx = s3c24xx_serial_start_tx, 1791 .stop_rx = s3c24xx_serial_stop_rx, 1792 .break_ctl = s3c24xx_serial_break_ctl, 1793 .startup = apple_s5l_serial_startup, 1794 .shutdown = apple_s5l_serial_shutdown, 1795 .set_termios = s3c24xx_serial_set_termios, 1796 .type = s3c24xx_serial_type, 1797 .config_port = s3c24xx_serial_config_port, 1798 .verify_port = s3c24xx_serial_verify_port, 1799 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1800 .poll_get_char = s3c24xx_serial_get_poll_char, 1801 .poll_put_char = s3c24xx_serial_put_poll_char, 1802 #endif 1803 }; 1804 1805 static struct uart_driver s3c24xx_uart_drv = { 1806 .owner = THIS_MODULE, 1807 .driver_name = "s3c2410_serial", 1808 .nr = CONFIG_SERIAL_SAMSUNG_UARTS, 1809 .cons = S3C24XX_SERIAL_CONSOLE, 1810 .dev_name = S3C24XX_SERIAL_NAME, 1811 .major = S3C24XX_SERIAL_MAJOR, 1812 .minor = S3C24XX_SERIAL_MINOR, 1813 }; 1814 1815 #define __PORT_LOCK_UNLOCKED(i) \ 1816 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock) 1817 static struct s3c24xx_uart_port 1818 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = { 1819 [0] = { 1820 .port = { 1821 .lock = __PORT_LOCK_UNLOCKED(0), 1822 .iotype = UPIO_MEM, 1823 .uartclk = 0, 1824 .fifosize = 16, 1825 .ops = &s3c24xx_serial_ops, 1826 .flags = UPF_BOOT_AUTOCONF, 1827 .line = 0, 1828 } 1829 }, 1830 [1] = { 1831 .port = { 1832 .lock = __PORT_LOCK_UNLOCKED(1), 1833 .iotype = UPIO_MEM, 1834 .uartclk = 0, 1835 .fifosize = 16, 1836 .ops = &s3c24xx_serial_ops, 1837 .flags = UPF_BOOT_AUTOCONF, 1838 .line = 1, 1839 } 1840 }, 1841 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2 1842 [2] = { 1843 .port = { 1844 .lock = __PORT_LOCK_UNLOCKED(2), 1845 .iotype = UPIO_MEM, 1846 .uartclk = 0, 1847 .fifosize = 16, 1848 .ops = &s3c24xx_serial_ops, 1849 .flags = UPF_BOOT_AUTOCONF, 1850 .line = 2, 1851 } 1852 }, 1853 #endif 1854 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3 1855 [3] = { 1856 .port = { 1857 .lock = __PORT_LOCK_UNLOCKED(3), 1858 .iotype = UPIO_MEM, 1859 .uartclk = 0, 1860 .fifosize = 16, 1861 .ops = &s3c24xx_serial_ops, 1862 .flags = UPF_BOOT_AUTOCONF, 1863 .line = 3, 1864 } 1865 } 1866 #endif 1867 }; 1868 #undef __PORT_LOCK_UNLOCKED 1869 1870 /* s3c24xx_serial_resetport 1871 * 1872 * reset the fifos and other the settings. 1873 */ 1874 1875 static void s3c24xx_serial_resetport(struct uart_port *port, 1876 struct s3c2410_uartcfg *cfg) 1877 { 1878 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1879 unsigned long ucon = rd_regl(port, S3C2410_UCON); 1880 1881 ucon &= (info->clksel_mask | info->ucon_mask); 1882 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); 1883 1884 /* reset both fifos */ 1885 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); 1886 wr_regl(port, S3C2410_UFCON, cfg->ufcon); 1887 1888 /* some delay is required after fifo reset */ 1889 udelay(1); 1890 } 1891 1892 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ 1893 1894 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb, 1895 unsigned long val, void *data) 1896 { 1897 struct s3c24xx_uart_port *port; 1898 struct uart_port *uport; 1899 1900 port = container_of(nb, struct s3c24xx_uart_port, freq_transition); 1901 uport = &port->port; 1902 1903 /* check to see if port is enabled */ 1904 1905 if (port->pm_level != 0) 1906 return 0; 1907 1908 /* try and work out if the baudrate is changing, we can detect 1909 * a change in rate, but we do not have support for detecting 1910 * a disturbance in the clock-rate over the change. 1911 */ 1912 1913 if (IS_ERR(port->baudclk)) 1914 goto exit; 1915 1916 if (port->baudclk_rate == clk_get_rate(port->baudclk)) 1917 goto exit; 1918 1919 if (val == CPUFREQ_PRECHANGE) { 1920 /* we should really shut the port down whilst the 1921 * frequency change is in progress. 1922 */ 1923 1924 } else if (val == CPUFREQ_POSTCHANGE) { 1925 struct ktermios *termios; 1926 struct tty_struct *tty; 1927 1928 if (uport->state == NULL) 1929 goto exit; 1930 1931 tty = uport->state->port.tty; 1932 1933 if (tty == NULL) 1934 goto exit; 1935 1936 termios = &tty->termios; 1937 1938 if (termios == NULL) { 1939 dev_warn(uport->dev, "%s: no termios?\n", __func__); 1940 goto exit; 1941 } 1942 1943 s3c24xx_serial_set_termios(uport, termios, NULL); 1944 } 1945 1946 exit: 1947 return 0; 1948 } 1949 1950 static inline int 1951 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) 1952 { 1953 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition; 1954 1955 return cpufreq_register_notifier(&port->freq_transition, 1956 CPUFREQ_TRANSITION_NOTIFIER); 1957 } 1958 1959 static inline void 1960 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) 1961 { 1962 cpufreq_unregister_notifier(&port->freq_transition, 1963 CPUFREQ_TRANSITION_NOTIFIER); 1964 } 1965 1966 #else 1967 static inline int 1968 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) 1969 { 1970 return 0; 1971 } 1972 1973 static inline void 1974 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) 1975 { 1976 } 1977 #endif 1978 1979 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport) 1980 { 1981 struct device *dev = ourport->port.dev; 1982 struct s3c24xx_uart_info *info = ourport->info; 1983 char clk_name[MAX_CLK_NAME_LENGTH]; 1984 unsigned int clk_sel; 1985 struct clk *clk; 1986 int clk_num; 1987 int ret; 1988 1989 clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel; 1990 for (clk_num = 0; clk_num < info->num_clks; clk_num++) { 1991 if (!(clk_sel & (1 << clk_num))) 1992 continue; 1993 1994 sprintf(clk_name, "clk_uart_baud%d", clk_num); 1995 clk = clk_get(dev, clk_name); 1996 if (IS_ERR(clk)) 1997 continue; 1998 1999 ret = clk_prepare_enable(clk); 2000 if (ret) { 2001 clk_put(clk); 2002 continue; 2003 } 2004 2005 ourport->baudclk = clk; 2006 ourport->baudclk_rate = clk_get_rate(clk); 2007 s3c24xx_serial_setsource(&ourport->port, clk_num); 2008 2009 return 0; 2010 } 2011 2012 return -EINVAL; 2013 } 2014 2015 /* s3c24xx_serial_init_port 2016 * 2017 * initialise a single serial port from the platform device given 2018 */ 2019 2020 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, 2021 struct platform_device *platdev) 2022 { 2023 struct uart_port *port = &ourport->port; 2024 struct s3c2410_uartcfg *cfg = ourport->cfg; 2025 struct resource *res; 2026 int ret; 2027 2028 if (platdev == NULL) 2029 return -ENODEV; 2030 2031 if (port->mapbase != 0) 2032 return -EINVAL; 2033 2034 /* setup info for port */ 2035 port->dev = &platdev->dev; 2036 2037 port->uartclk = 1; 2038 2039 if (cfg->uart_flags & UPF_CONS_FLOW) { 2040 dev_dbg(port->dev, "enabling flow control\n"); 2041 port->flags |= UPF_CONS_FLOW; 2042 } 2043 2044 /* sort our the physical and virtual addresses for each UART */ 2045 2046 res = platform_get_resource(platdev, IORESOURCE_MEM, 0); 2047 if (res == NULL) { 2048 dev_err(port->dev, "failed to find memory resource for uart\n"); 2049 return -EINVAL; 2050 } 2051 2052 dev_dbg(port->dev, "resource %pR)\n", res); 2053 2054 port->membase = devm_ioremap_resource(port->dev, res); 2055 if (IS_ERR(port->membase)) { 2056 dev_err(port->dev, "failed to remap controller address\n"); 2057 return -EBUSY; 2058 } 2059 2060 port->mapbase = res->start; 2061 ret = platform_get_irq(platdev, 0); 2062 if (ret < 0) { 2063 port->irq = 0; 2064 } else { 2065 port->irq = ret; 2066 ourport->rx_irq = ret; 2067 ourport->tx_irq = ret + 1; 2068 } 2069 2070 switch (ourport->info->type) { 2071 case TYPE_S3C24XX: 2072 ret = platform_get_irq(platdev, 1); 2073 if (ret > 0) 2074 ourport->tx_irq = ret; 2075 break; 2076 default: 2077 break; 2078 } 2079 2080 /* 2081 * DMA is currently supported only on DT platforms, if DMA properties 2082 * are specified. 2083 */ 2084 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node, 2085 "dmas", NULL)) { 2086 ourport->dma = devm_kzalloc(port->dev, 2087 sizeof(*ourport->dma), 2088 GFP_KERNEL); 2089 if (!ourport->dma) { 2090 ret = -ENOMEM; 2091 goto err; 2092 } 2093 } 2094 2095 ourport->clk = clk_get(&platdev->dev, "uart"); 2096 if (IS_ERR(ourport->clk)) { 2097 pr_err("%s: Controller clock not found\n", 2098 dev_name(&platdev->dev)); 2099 ret = PTR_ERR(ourport->clk); 2100 goto err; 2101 } 2102 2103 ret = clk_prepare_enable(ourport->clk); 2104 if (ret) { 2105 pr_err("uart: clock failed to prepare+enable: %d\n", ret); 2106 clk_put(ourport->clk); 2107 goto err; 2108 } 2109 2110 ret = s3c24xx_serial_enable_baudclk(ourport); 2111 if (ret) 2112 pr_warn("uart: failed to enable baudclk\n"); 2113 2114 /* Keep all interrupts masked and cleared */ 2115 switch (ourport->info->type) { 2116 case TYPE_S3C6400: 2117 wr_regl(port, S3C64XX_UINTM, 0xf); 2118 wr_regl(port, S3C64XX_UINTP, 0xf); 2119 wr_regl(port, S3C64XX_UINTSP, 0xf); 2120 break; 2121 case TYPE_APPLE_S5L: { 2122 unsigned int ucon; 2123 2124 ucon = rd_regl(port, S3C2410_UCON); 2125 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | 2126 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 2127 APPLE_S5L_UCON_RXTO_ENA_MSK); 2128 wr_regl(port, S3C2410_UCON, ucon); 2129 2130 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS); 2131 break; 2132 } 2133 default: 2134 break; 2135 } 2136 2137 dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n", 2138 &port->mapbase, port->membase, port->irq, 2139 ourport->rx_irq, ourport->tx_irq, port->uartclk); 2140 2141 /* reset the fifos (and setup the uart) */ 2142 s3c24xx_serial_resetport(port, cfg); 2143 2144 return 0; 2145 2146 err: 2147 port->mapbase = 0; 2148 return ret; 2149 } 2150 2151 /* Device driver serial port probe */ 2152 2153 #ifdef CONFIG_OF 2154 static const struct of_device_id s3c24xx_uart_dt_match[]; 2155 #endif 2156 2157 static int probe_index; 2158 2159 static inline struct s3c24xx_serial_drv_data * 2160 s3c24xx_get_driver_data(struct platform_device *pdev) 2161 { 2162 #ifdef CONFIG_OF 2163 if (pdev->dev.of_node) { 2164 const struct of_device_id *match; 2165 2166 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node); 2167 return (struct s3c24xx_serial_drv_data *)match->data; 2168 } 2169 #endif 2170 return (struct s3c24xx_serial_drv_data *) 2171 platform_get_device_id(pdev)->driver_data; 2172 } 2173 2174 static int s3c24xx_serial_probe(struct platform_device *pdev) 2175 { 2176 struct device_node *np = pdev->dev.of_node; 2177 struct s3c24xx_uart_port *ourport; 2178 int index = probe_index; 2179 int ret, prop = 0; 2180 2181 if (np) { 2182 ret = of_alias_get_id(np, "serial"); 2183 if (ret >= 0) 2184 index = ret; 2185 } 2186 2187 if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) { 2188 dev_err(&pdev->dev, "serial%d out of range\n", index); 2189 return -EINVAL; 2190 } 2191 ourport = &s3c24xx_serial_ports[index]; 2192 2193 ourport->drv_data = s3c24xx_get_driver_data(pdev); 2194 if (!ourport->drv_data) { 2195 dev_err(&pdev->dev, "could not find driver data\n"); 2196 return -ENODEV; 2197 } 2198 2199 ourport->baudclk = ERR_PTR(-EINVAL); 2200 ourport->info = ourport->drv_data->info; 2201 ourport->cfg = (dev_get_platdata(&pdev->dev)) ? 2202 dev_get_platdata(&pdev->dev) : 2203 ourport->drv_data->def_cfg; 2204 2205 switch (ourport->info->type) { 2206 case TYPE_S3C24XX: 2207 ourport->port.ops = &s3c24xx_serial_ops; 2208 break; 2209 case TYPE_S3C6400: 2210 ourport->port.ops = &s3c64xx_serial_ops; 2211 break; 2212 case TYPE_APPLE_S5L: 2213 ourport->port.ops = &apple_s5l_serial_ops; 2214 break; 2215 } 2216 2217 if (np) { 2218 of_property_read_u32(np, 2219 "samsung,uart-fifosize", &ourport->port.fifosize); 2220 2221 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) { 2222 switch (prop) { 2223 case 1: 2224 ourport->port.iotype = UPIO_MEM; 2225 break; 2226 case 4: 2227 ourport->port.iotype = UPIO_MEM32; 2228 break; 2229 default: 2230 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n", 2231 prop); 2232 return -EINVAL; 2233 } 2234 } 2235 } 2236 2237 if (ourport->drv_data->fifosize[index]) 2238 ourport->port.fifosize = ourport->drv_data->fifosize[index]; 2239 else if (ourport->info->fifosize) 2240 ourport->port.fifosize = ourport->info->fifosize; 2241 ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE); 2242 2243 /* 2244 * DMA transfers must be aligned at least to cache line size, 2245 * so find minimal transfer size suitable for DMA mode 2246 */ 2247 ourport->min_dma_size = max_t(int, ourport->port.fifosize, 2248 dma_get_cache_alignment()); 2249 2250 dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport); 2251 2252 ret = s3c24xx_serial_init_port(ourport, pdev); 2253 if (ret < 0) 2254 return ret; 2255 2256 if (!s3c24xx_uart_drv.state) { 2257 ret = uart_register_driver(&s3c24xx_uart_drv); 2258 if (ret < 0) { 2259 pr_err("Failed to register Samsung UART driver\n"); 2260 return ret; 2261 } 2262 } 2263 2264 dev_dbg(&pdev->dev, "%s: adding port\n", __func__); 2265 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port); 2266 platform_set_drvdata(pdev, &ourport->port); 2267 2268 /* 2269 * Deactivate the clock enabled in s3c24xx_serial_init_port here, 2270 * so that a potential re-enablement through the pm-callback overlaps 2271 * and keeps the clock enabled in this case. 2272 */ 2273 clk_disable_unprepare(ourport->clk); 2274 if (!IS_ERR(ourport->baudclk)) 2275 clk_disable_unprepare(ourport->baudclk); 2276 2277 ret = s3c24xx_serial_cpufreq_register(ourport); 2278 if (ret < 0) 2279 dev_err(&pdev->dev, "failed to add cpufreq notifier\n"); 2280 2281 probe_index++; 2282 2283 return 0; 2284 } 2285 2286 static int s3c24xx_serial_remove(struct platform_device *dev) 2287 { 2288 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); 2289 2290 if (port) { 2291 s3c24xx_serial_cpufreq_deregister(to_ourport(port)); 2292 uart_remove_one_port(&s3c24xx_uart_drv, port); 2293 } 2294 2295 uart_unregister_driver(&s3c24xx_uart_drv); 2296 2297 return 0; 2298 } 2299 2300 /* UART power management code */ 2301 #ifdef CONFIG_PM_SLEEP 2302 static int s3c24xx_serial_suspend(struct device *dev) 2303 { 2304 struct uart_port *port = s3c24xx_dev_to_port(dev); 2305 2306 if (port) 2307 uart_suspend_port(&s3c24xx_uart_drv, port); 2308 2309 return 0; 2310 } 2311 2312 static int s3c24xx_serial_resume(struct device *dev) 2313 { 2314 struct uart_port *port = s3c24xx_dev_to_port(dev); 2315 struct s3c24xx_uart_port *ourport = to_ourport(port); 2316 2317 if (port) { 2318 clk_prepare_enable(ourport->clk); 2319 if (!IS_ERR(ourport->baudclk)) 2320 clk_prepare_enable(ourport->baudclk); 2321 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port)); 2322 if (!IS_ERR(ourport->baudclk)) 2323 clk_disable_unprepare(ourport->baudclk); 2324 clk_disable_unprepare(ourport->clk); 2325 2326 uart_resume_port(&s3c24xx_uart_drv, port); 2327 } 2328 2329 return 0; 2330 } 2331 2332 static int s3c24xx_serial_resume_noirq(struct device *dev) 2333 { 2334 struct uart_port *port = s3c24xx_dev_to_port(dev); 2335 struct s3c24xx_uart_port *ourport = to_ourport(port); 2336 2337 if (port) { 2338 /* restore IRQ mask */ 2339 switch (ourport->info->type) { 2340 case TYPE_S3C6400: { 2341 unsigned int uintm = 0xf; 2342 2343 if (ourport->tx_enabled) 2344 uintm &= ~S3C64XX_UINTM_TXD_MSK; 2345 if (ourport->rx_enabled) 2346 uintm &= ~S3C64XX_UINTM_RXD_MSK; 2347 clk_prepare_enable(ourport->clk); 2348 if (!IS_ERR(ourport->baudclk)) 2349 clk_prepare_enable(ourport->baudclk); 2350 wr_regl(port, S3C64XX_UINTM, uintm); 2351 if (!IS_ERR(ourport->baudclk)) 2352 clk_disable_unprepare(ourport->baudclk); 2353 clk_disable_unprepare(ourport->clk); 2354 break; 2355 } 2356 case TYPE_APPLE_S5L: { 2357 unsigned int ucon; 2358 int ret; 2359 2360 ret = clk_prepare_enable(ourport->clk); 2361 if (ret) { 2362 dev_err(dev, "clk_enable clk failed: %d\n", ret); 2363 return ret; 2364 } 2365 if (!IS_ERR(ourport->baudclk)) { 2366 ret = clk_prepare_enable(ourport->baudclk); 2367 if (ret) { 2368 dev_err(dev, "clk_enable baudclk failed: %d\n", ret); 2369 clk_disable_unprepare(ourport->clk); 2370 return ret; 2371 } 2372 } 2373 2374 ucon = rd_regl(port, S3C2410_UCON); 2375 2376 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | 2377 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 2378 APPLE_S5L_UCON_RXTO_ENA_MSK); 2379 2380 if (ourport->tx_enabled) 2381 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK; 2382 if (ourport->rx_enabled) 2383 ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 2384 APPLE_S5L_UCON_RXTO_ENA_MSK; 2385 2386 wr_regl(port, S3C2410_UCON, ucon); 2387 2388 if (!IS_ERR(ourport->baudclk)) 2389 clk_disable_unprepare(ourport->baudclk); 2390 clk_disable_unprepare(ourport->clk); 2391 break; 2392 } 2393 default: 2394 break; 2395 } 2396 } 2397 2398 return 0; 2399 } 2400 2401 static const struct dev_pm_ops s3c24xx_serial_pm_ops = { 2402 .suspend = s3c24xx_serial_suspend, 2403 .resume = s3c24xx_serial_resume, 2404 .resume_noirq = s3c24xx_serial_resume_noirq, 2405 }; 2406 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops) 2407 2408 #else /* !CONFIG_PM_SLEEP */ 2409 2410 #define SERIAL_SAMSUNG_PM_OPS NULL 2411 #endif /* CONFIG_PM_SLEEP */ 2412 2413 /* Console code */ 2414 2415 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 2416 2417 static struct uart_port *cons_uart; 2418 2419 static int 2420 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon) 2421 { 2422 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 2423 unsigned long ufstat, utrstat; 2424 2425 if (ufcon & S3C2410_UFCON_FIFOMODE) { 2426 /* fifo mode - check amount of data in fifo registers... */ 2427 2428 ufstat = rd_regl(port, S3C2410_UFSTAT); 2429 return (ufstat & info->tx_fifofull) ? 0 : 1; 2430 } 2431 2432 /* in non-fifo mode, we go and use the tx buffer empty */ 2433 2434 utrstat = rd_regl(port, S3C2410_UTRSTAT); 2435 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0; 2436 } 2437 2438 static bool 2439 s3c24xx_port_configured(unsigned int ucon) 2440 { 2441 /* consider the serial port configured if the tx/rx mode set */ 2442 return (ucon & 0xf) != 0; 2443 } 2444 2445 #ifdef CONFIG_CONSOLE_POLL 2446 /* 2447 * Console polling routines for writing and reading from the uart while 2448 * in an interrupt or debug context. 2449 */ 2450 2451 static int s3c24xx_serial_get_poll_char(struct uart_port *port) 2452 { 2453 struct s3c24xx_uart_port *ourport = to_ourport(port); 2454 unsigned int ufstat; 2455 2456 ufstat = rd_regl(port, S3C2410_UFSTAT); 2457 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0) 2458 return NO_POLL_CHAR; 2459 2460 return rd_reg(port, S3C2410_URXH); 2461 } 2462 2463 static void s3c24xx_serial_put_poll_char(struct uart_port *port, 2464 unsigned char c) 2465 { 2466 unsigned int ufcon = rd_regl(port, S3C2410_UFCON); 2467 unsigned int ucon = rd_regl(port, S3C2410_UCON); 2468 2469 /* not possible to xmit on unconfigured port */ 2470 if (!s3c24xx_port_configured(ucon)) 2471 return; 2472 2473 while (!s3c24xx_serial_console_txrdy(port, ufcon)) 2474 cpu_relax(); 2475 wr_reg(port, S3C2410_UTXH, c); 2476 } 2477 2478 #endif /* CONFIG_CONSOLE_POLL */ 2479 2480 static void 2481 s3c24xx_serial_console_putchar(struct uart_port *port, int ch) 2482 { 2483 unsigned int ufcon = rd_regl(port, S3C2410_UFCON); 2484 2485 while (!s3c24xx_serial_console_txrdy(port, ufcon)) 2486 cpu_relax(); 2487 wr_reg(port, S3C2410_UTXH, ch); 2488 } 2489 2490 static void 2491 s3c24xx_serial_console_write(struct console *co, const char *s, 2492 unsigned int count) 2493 { 2494 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON); 2495 2496 /* not possible to xmit on unconfigured port */ 2497 if (!s3c24xx_port_configured(ucon)) 2498 return; 2499 2500 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar); 2501 } 2502 2503 /* Shouldn't be __init, as it can be instantiated from other module */ 2504 static void 2505 s3c24xx_serial_get_options(struct uart_port *port, int *baud, 2506 int *parity, int *bits) 2507 { 2508 struct clk *clk; 2509 unsigned int ulcon; 2510 unsigned int ucon; 2511 unsigned int ubrdiv; 2512 unsigned long rate; 2513 unsigned int clk_sel; 2514 char clk_name[MAX_CLK_NAME_LENGTH]; 2515 2516 ulcon = rd_regl(port, S3C2410_ULCON); 2517 ucon = rd_regl(port, S3C2410_UCON); 2518 ubrdiv = rd_regl(port, S3C2410_UBRDIV); 2519 2520 if (s3c24xx_port_configured(ucon)) { 2521 switch (ulcon & S3C2410_LCON_CSMASK) { 2522 case S3C2410_LCON_CS5: 2523 *bits = 5; 2524 break; 2525 case S3C2410_LCON_CS6: 2526 *bits = 6; 2527 break; 2528 case S3C2410_LCON_CS7: 2529 *bits = 7; 2530 break; 2531 case S3C2410_LCON_CS8: 2532 default: 2533 *bits = 8; 2534 break; 2535 } 2536 2537 switch (ulcon & S3C2410_LCON_PMASK) { 2538 case S3C2410_LCON_PEVEN: 2539 *parity = 'e'; 2540 break; 2541 2542 case S3C2410_LCON_PODD: 2543 *parity = 'o'; 2544 break; 2545 2546 case S3C2410_LCON_PNONE: 2547 default: 2548 *parity = 'n'; 2549 } 2550 2551 /* now calculate the baud rate */ 2552 2553 clk_sel = s3c24xx_serial_getsource(port); 2554 sprintf(clk_name, "clk_uart_baud%d", clk_sel); 2555 2556 clk = clk_get(port->dev, clk_name); 2557 if (!IS_ERR(clk)) 2558 rate = clk_get_rate(clk); 2559 else 2560 rate = 1; 2561 2562 *baud = rate / (16 * (ubrdiv + 1)); 2563 dev_dbg(port->dev, "calculated baud %d\n", *baud); 2564 } 2565 } 2566 2567 /* Shouldn't be __init, as it can be instantiated from other module */ 2568 static int 2569 s3c24xx_serial_console_setup(struct console *co, char *options) 2570 { 2571 struct uart_port *port; 2572 int baud = 9600; 2573 int bits = 8; 2574 int parity = 'n'; 2575 int flow = 'n'; 2576 2577 /* is this a valid port */ 2578 2579 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS) 2580 co->index = 0; 2581 2582 port = &s3c24xx_serial_ports[co->index].port; 2583 2584 /* is the port configured? */ 2585 2586 if (port->mapbase == 0x0) 2587 return -ENODEV; 2588 2589 cons_uart = port; 2590 2591 /* 2592 * Check whether an invalid uart number has been specified, and 2593 * if so, search for the first available port that does have 2594 * console support. 2595 */ 2596 if (options) 2597 uart_parse_options(options, &baud, &parity, &bits, &flow); 2598 else 2599 s3c24xx_serial_get_options(port, &baud, &parity, &bits); 2600 2601 dev_dbg(port->dev, "baud %d\n", baud); 2602 2603 return uart_set_options(port, co, baud, parity, bits, flow); 2604 } 2605 2606 static struct console s3c24xx_serial_console = { 2607 .name = S3C24XX_SERIAL_NAME, 2608 .device = uart_console_device, 2609 .flags = CON_PRINTBUFFER, 2610 .index = -1, 2611 .write = s3c24xx_serial_console_write, 2612 .setup = s3c24xx_serial_console_setup, 2613 .data = &s3c24xx_uart_drv, 2614 }; 2615 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */ 2616 2617 #ifdef CONFIG_CPU_S3C2410 2618 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = { 2619 .info = &(struct s3c24xx_uart_info) { 2620 .name = "Samsung S3C2410 UART", 2621 .type = TYPE_S3C24XX, 2622 .port_type = PORT_S3C2410, 2623 .fifosize = 16, 2624 .rx_fifomask = S3C2410_UFSTAT_RXMASK, 2625 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT, 2626 .rx_fifofull = S3C2410_UFSTAT_RXFULL, 2627 .tx_fifofull = S3C2410_UFSTAT_TXFULL, 2628 .tx_fifomask = S3C2410_UFSTAT_TXMASK, 2629 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT, 2630 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2631 .num_clks = 2, 2632 .clksel_mask = S3C2410_UCON_CLKMASK, 2633 .clksel_shift = S3C2410_UCON_CLKSHIFT, 2634 }, 2635 .def_cfg = &(struct s3c2410_uartcfg) { 2636 .ucon = S3C2410_UCON_DEFAULT, 2637 .ufcon = S3C2410_UFCON_DEFAULT, 2638 }, 2639 }; 2640 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data) 2641 #else 2642 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL 2643 #endif 2644 2645 #ifdef CONFIG_CPU_S3C2412 2646 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = { 2647 .info = &(struct s3c24xx_uart_info) { 2648 .name = "Samsung S3C2412 UART", 2649 .type = TYPE_S3C24XX, 2650 .port_type = PORT_S3C2412, 2651 .fifosize = 64, 2652 .has_divslot = 1, 2653 .rx_fifomask = S3C2440_UFSTAT_RXMASK, 2654 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, 2655 .rx_fifofull = S3C2440_UFSTAT_RXFULL, 2656 .tx_fifofull = S3C2440_UFSTAT_TXFULL, 2657 .tx_fifomask = S3C2440_UFSTAT_TXMASK, 2658 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, 2659 .def_clk_sel = S3C2410_UCON_CLKSEL2, 2660 .num_clks = 4, 2661 .clksel_mask = S3C2412_UCON_CLKMASK, 2662 .clksel_shift = S3C2412_UCON_CLKSHIFT, 2663 }, 2664 .def_cfg = &(struct s3c2410_uartcfg) { 2665 .ucon = S3C2410_UCON_DEFAULT, 2666 .ufcon = S3C2410_UFCON_DEFAULT, 2667 }, 2668 }; 2669 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data) 2670 #else 2671 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL 2672 #endif 2673 2674 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \ 2675 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442) 2676 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = { 2677 .info = &(struct s3c24xx_uart_info) { 2678 .name = "Samsung S3C2440 UART", 2679 .type = TYPE_S3C24XX, 2680 .port_type = PORT_S3C2440, 2681 .fifosize = 64, 2682 .has_divslot = 1, 2683 .rx_fifomask = S3C2440_UFSTAT_RXMASK, 2684 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, 2685 .rx_fifofull = S3C2440_UFSTAT_RXFULL, 2686 .tx_fifofull = S3C2440_UFSTAT_TXFULL, 2687 .tx_fifomask = S3C2440_UFSTAT_TXMASK, 2688 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, 2689 .def_clk_sel = S3C2410_UCON_CLKSEL2, 2690 .num_clks = 4, 2691 .clksel_mask = S3C2412_UCON_CLKMASK, 2692 .clksel_shift = S3C2412_UCON_CLKSHIFT, 2693 .ucon_mask = S3C2440_UCON0_DIVMASK, 2694 }, 2695 .def_cfg = &(struct s3c2410_uartcfg) { 2696 .ucon = S3C2410_UCON_DEFAULT, 2697 .ufcon = S3C2410_UFCON_DEFAULT, 2698 }, 2699 }; 2700 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data) 2701 #else 2702 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL 2703 #endif 2704 2705 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) 2706 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = { 2707 .info = &(struct s3c24xx_uart_info) { 2708 .name = "Samsung S3C6400 UART", 2709 .type = TYPE_S3C6400, 2710 .port_type = PORT_S3C6400, 2711 .fifosize = 64, 2712 .has_divslot = 1, 2713 .rx_fifomask = S3C2440_UFSTAT_RXMASK, 2714 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, 2715 .rx_fifofull = S3C2440_UFSTAT_RXFULL, 2716 .tx_fifofull = S3C2440_UFSTAT_TXFULL, 2717 .tx_fifomask = S3C2440_UFSTAT_TXMASK, 2718 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, 2719 .def_clk_sel = S3C2410_UCON_CLKSEL2, 2720 .num_clks = 4, 2721 .clksel_mask = S3C6400_UCON_CLKMASK, 2722 .clksel_shift = S3C6400_UCON_CLKSHIFT, 2723 }, 2724 .def_cfg = &(struct s3c2410_uartcfg) { 2725 .ucon = S3C2410_UCON_DEFAULT, 2726 .ufcon = S3C2410_UFCON_DEFAULT, 2727 }, 2728 }; 2729 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data) 2730 #else 2731 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL 2732 #endif 2733 2734 #ifdef CONFIG_CPU_S5PV210 2735 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { 2736 .info = &(struct s3c24xx_uart_info) { 2737 .name = "Samsung S5PV210 UART", 2738 .type = TYPE_S3C6400, 2739 .port_type = PORT_S3C6400, 2740 .has_divslot = 1, 2741 .rx_fifomask = S5PV210_UFSTAT_RXMASK, 2742 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, 2743 .rx_fifofull = S5PV210_UFSTAT_RXFULL, 2744 .tx_fifofull = S5PV210_UFSTAT_TXFULL, 2745 .tx_fifomask = S5PV210_UFSTAT_TXMASK, 2746 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, 2747 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2748 .num_clks = 2, 2749 .clksel_mask = S5PV210_UCON_CLKMASK, 2750 .clksel_shift = S5PV210_UCON_CLKSHIFT, 2751 }, 2752 .def_cfg = &(struct s3c2410_uartcfg) { 2753 .ucon = S5PV210_UCON_DEFAULT, 2754 .ufcon = S5PV210_UFCON_DEFAULT, 2755 }, 2756 .fifosize = { 256, 64, 16, 16 }, 2757 }; 2758 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data) 2759 #else 2760 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL 2761 #endif 2762 2763 #if defined(CONFIG_ARCH_EXYNOS) 2764 #define EXYNOS_COMMON_SERIAL_DRV_DATA() \ 2765 .info = &(struct s3c24xx_uart_info) { \ 2766 .name = "Samsung Exynos UART", \ 2767 .type = TYPE_S3C6400, \ 2768 .port_type = PORT_S3C6400, \ 2769 .has_divslot = 1, \ 2770 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ 2771 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \ 2772 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \ 2773 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \ 2774 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \ 2775 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \ 2776 .def_clk_sel = S3C2410_UCON_CLKSEL0, \ 2777 .num_clks = 1, \ 2778 .clksel_mask = 0, \ 2779 .clksel_shift = 0, \ 2780 }, \ 2781 .def_cfg = &(struct s3c2410_uartcfg) { \ 2782 .ucon = S5PV210_UCON_DEFAULT, \ 2783 .ufcon = S5PV210_UFCON_DEFAULT, \ 2784 .has_fracval = 1, \ 2785 } \ 2786 2787 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = { 2788 EXYNOS_COMMON_SERIAL_DRV_DATA(), 2789 .fifosize = { 256, 64, 16, 16 }, 2790 }; 2791 2792 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = { 2793 EXYNOS_COMMON_SERIAL_DRV_DATA(), 2794 .fifosize = { 64, 256, 16, 256 }, 2795 }; 2796 2797 static struct s3c24xx_serial_drv_data exynos850_serial_drv_data = { 2798 EXYNOS_COMMON_SERIAL_DRV_DATA(), 2799 .fifosize = { 256, 64, 64, 64 }, 2800 }; 2801 2802 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data) 2803 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data) 2804 #define EXYNOS850_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos850_serial_drv_data) 2805 2806 #else 2807 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) 2808 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) 2809 #define EXYNOS850_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) 2810 #endif 2811 2812 #ifdef CONFIG_ARCH_APPLE 2813 static struct s3c24xx_serial_drv_data s5l_serial_drv_data = { 2814 .info = &(struct s3c24xx_uart_info) { 2815 .name = "Apple S5L UART", 2816 .type = TYPE_APPLE_S5L, 2817 .port_type = PORT_8250, 2818 .fifosize = 16, 2819 .rx_fifomask = S3C2410_UFSTAT_RXMASK, 2820 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT, 2821 .rx_fifofull = S3C2410_UFSTAT_RXFULL, 2822 .tx_fifofull = S3C2410_UFSTAT_TXFULL, 2823 .tx_fifomask = S3C2410_UFSTAT_TXMASK, 2824 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT, 2825 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2826 .num_clks = 1, 2827 .clksel_mask = 0, 2828 .clksel_shift = 0, 2829 }, 2830 .def_cfg = &(struct s3c2410_uartcfg) { 2831 .ucon = APPLE_S5L_UCON_DEFAULT, 2832 .ufcon = S3C2410_UFCON_DEFAULT, 2833 }, 2834 }; 2835 #define S5L_SERIAL_DRV_DATA ((kernel_ulong_t)&s5l_serial_drv_data) 2836 #else 2837 #define S5L_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) 2838 #endif 2839 2840 static const struct platform_device_id s3c24xx_serial_driver_ids[] = { 2841 { 2842 .name = "s3c2410-uart", 2843 .driver_data = S3C2410_SERIAL_DRV_DATA, 2844 }, { 2845 .name = "s3c2412-uart", 2846 .driver_data = S3C2412_SERIAL_DRV_DATA, 2847 }, { 2848 .name = "s3c2440-uart", 2849 .driver_data = S3C2440_SERIAL_DRV_DATA, 2850 }, { 2851 .name = "s3c6400-uart", 2852 .driver_data = S3C6400_SERIAL_DRV_DATA, 2853 }, { 2854 .name = "s5pv210-uart", 2855 .driver_data = S5PV210_SERIAL_DRV_DATA, 2856 }, { 2857 .name = "exynos4210-uart", 2858 .driver_data = EXYNOS4210_SERIAL_DRV_DATA, 2859 }, { 2860 .name = "exynos5433-uart", 2861 .driver_data = EXYNOS5433_SERIAL_DRV_DATA, 2862 }, { 2863 .name = "s5l-uart", 2864 .driver_data = S5L_SERIAL_DRV_DATA, 2865 }, { 2866 .name = "exynos850-uart", 2867 .driver_data = EXYNOS850_SERIAL_DRV_DATA, 2868 }, 2869 { }, 2870 }; 2871 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids); 2872 2873 #ifdef CONFIG_OF 2874 static const struct of_device_id s3c24xx_uart_dt_match[] = { 2875 { .compatible = "samsung,s3c2410-uart", 2876 .data = (void *)S3C2410_SERIAL_DRV_DATA }, 2877 { .compatible = "samsung,s3c2412-uart", 2878 .data = (void *)S3C2412_SERIAL_DRV_DATA }, 2879 { .compatible = "samsung,s3c2440-uart", 2880 .data = (void *)S3C2440_SERIAL_DRV_DATA }, 2881 { .compatible = "samsung,s3c6400-uart", 2882 .data = (void *)S3C6400_SERIAL_DRV_DATA }, 2883 { .compatible = "samsung,s5pv210-uart", 2884 .data = (void *)S5PV210_SERIAL_DRV_DATA }, 2885 { .compatible = "samsung,exynos4210-uart", 2886 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA }, 2887 { .compatible = "samsung,exynos5433-uart", 2888 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA }, 2889 { .compatible = "apple,s5l-uart", 2890 .data = (void *)S5L_SERIAL_DRV_DATA }, 2891 { .compatible = "samsung,exynos850-uart", 2892 .data = (void *)EXYNOS850_SERIAL_DRV_DATA }, 2893 {}, 2894 }; 2895 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); 2896 #endif 2897 2898 static struct platform_driver samsung_serial_driver = { 2899 .probe = s3c24xx_serial_probe, 2900 .remove = s3c24xx_serial_remove, 2901 .id_table = s3c24xx_serial_driver_ids, 2902 .driver = { 2903 .name = "samsung-uart", 2904 .pm = SERIAL_SAMSUNG_PM_OPS, 2905 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match), 2906 }, 2907 }; 2908 2909 static int __init samsung_serial_init(void) 2910 { 2911 int ret; 2912 2913 s3c24xx_serial_register_console(); 2914 2915 ret = platform_driver_register(&samsung_serial_driver); 2916 if (ret) { 2917 s3c24xx_serial_unregister_console(); 2918 return ret; 2919 } 2920 2921 return 0; 2922 } 2923 2924 static void __exit samsung_serial_exit(void) 2925 { 2926 platform_driver_unregister(&samsung_serial_driver); 2927 s3c24xx_serial_unregister_console(); 2928 } 2929 2930 module_init(samsung_serial_init); 2931 module_exit(samsung_serial_exit); 2932 2933 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 2934 /* 2935 * Early console. 2936 */ 2937 2938 static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val) 2939 { 2940 switch (port->iotype) { 2941 case UPIO_MEM: 2942 writeb(val, portaddr(port, reg)); 2943 break; 2944 case UPIO_MEM32: 2945 writel(val, portaddr(port, reg)); 2946 break; 2947 } 2948 } 2949 2950 struct samsung_early_console_data { 2951 u32 txfull_mask; 2952 }; 2953 2954 static void samsung_early_busyuart(struct uart_port *port) 2955 { 2956 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE)) 2957 ; 2958 } 2959 2960 static void samsung_early_busyuart_fifo(struct uart_port *port) 2961 { 2962 struct samsung_early_console_data *data = port->private_data; 2963 2964 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask) 2965 ; 2966 } 2967 2968 static void samsung_early_putc(struct uart_port *port, int c) 2969 { 2970 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) 2971 samsung_early_busyuart_fifo(port); 2972 else 2973 samsung_early_busyuart(port); 2974 2975 wr_reg_barrier(port, S3C2410_UTXH, c); 2976 } 2977 2978 static void samsung_early_write(struct console *con, const char *s, 2979 unsigned int n) 2980 { 2981 struct earlycon_device *dev = con->data; 2982 2983 uart_console_write(&dev->port, s, n, samsung_early_putc); 2984 } 2985 2986 static int __init samsung_early_console_setup(struct earlycon_device *device, 2987 const char *opt) 2988 { 2989 if (!device->port.membase) 2990 return -ENODEV; 2991 2992 device->con->write = samsung_early_write; 2993 return 0; 2994 } 2995 2996 /* S3C2410 */ 2997 static struct samsung_early_console_data s3c2410_early_console_data = { 2998 .txfull_mask = S3C2410_UFSTAT_TXFULL, 2999 }; 3000 3001 static int __init s3c2410_early_console_setup(struct earlycon_device *device, 3002 const char *opt) 3003 { 3004 device->port.private_data = &s3c2410_early_console_data; 3005 return samsung_early_console_setup(device, opt); 3006 } 3007 3008 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart", 3009 s3c2410_early_console_setup); 3010 3011 /* S3C2412, S3C2440, S3C64xx */ 3012 static struct samsung_early_console_data s3c2440_early_console_data = { 3013 .txfull_mask = S3C2440_UFSTAT_TXFULL, 3014 }; 3015 3016 static int __init s3c2440_early_console_setup(struct earlycon_device *device, 3017 const char *opt) 3018 { 3019 device->port.private_data = &s3c2440_early_console_data; 3020 return samsung_early_console_setup(device, opt); 3021 } 3022 3023 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart", 3024 s3c2440_early_console_setup); 3025 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart", 3026 s3c2440_early_console_setup); 3027 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart", 3028 s3c2440_early_console_setup); 3029 3030 /* S5PV210, Exynos */ 3031 static struct samsung_early_console_data s5pv210_early_console_data = { 3032 .txfull_mask = S5PV210_UFSTAT_TXFULL, 3033 }; 3034 3035 static int __init s5pv210_early_console_setup(struct earlycon_device *device, 3036 const char *opt) 3037 { 3038 device->port.private_data = &s5pv210_early_console_data; 3039 return samsung_early_console_setup(device, opt); 3040 } 3041 3042 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart", 3043 s5pv210_early_console_setup); 3044 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart", 3045 s5pv210_early_console_setup); 3046 3047 /* Apple S5L */ 3048 static int __init apple_s5l_early_console_setup(struct earlycon_device *device, 3049 const char *opt) 3050 { 3051 /* Close enough to S3C2410 for earlycon... */ 3052 device->port.private_data = &s3c2410_early_console_data; 3053 3054 #ifdef CONFIG_ARM64 3055 /* ... but we need to override the existing fixmap entry as nGnRnE */ 3056 __set_fixmap(FIX_EARLYCON_MEM_BASE, device->port.mapbase, 3057 __pgprot(PROT_DEVICE_nGnRnE)); 3058 #endif 3059 return samsung_early_console_setup(device, opt); 3060 } 3061 3062 OF_EARLYCON_DECLARE(s5l, "apple,s5l-uart", apple_s5l_early_console_setup); 3063 #endif 3064 3065 MODULE_ALIAS("platform:samsung-uart"); 3066 MODULE_DESCRIPTION("Samsung SoC Serial port driver"); 3067 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); 3068 MODULE_LICENSE("GPL v2"); 3069