1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver core for Samsung SoC onboard UARTs. 4 * 5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics 6 * http://armlinux.simtec.co.uk/ 7 */ 8 9 /* Note on 2410 error handling 10 * 11 * The s3c2410 manual has a love/hate affair with the contents of the 12 * UERSTAT register in the UART blocks, and keeps marking some of the 13 * error bits as reserved. Having checked with the s3c2410x01, 14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED 15 * feature from the latter versions of the manual. 16 * 17 * If it becomes aparrent that latter versions of the 2410 remove these 18 * bits, then action will have to be taken to differentiate the versions 19 * and change the policy on BREAK 20 * 21 * BJD, 04-Nov-2004 22 */ 23 24 #include <linux/console.h> 25 #include <linux/clk.h> 26 #include <linux/cpufreq.h> 27 #include <linux/delay.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/dmaengine.h> 30 #include <linux/init.h> 31 #include <linux/io.h> 32 #include <linux/ioport.h> 33 #include <linux/math.h> 34 #include <linux/module.h> 35 #include <linux/of.h> 36 #include <linux/platform_device.h> 37 #include <linux/serial.h> 38 #include <linux/serial_core.h> 39 #include <linux/serial_s3c.h> 40 #include <linux/slab.h> 41 #include <linux/sysrq.h> 42 #include <linux/tty.h> 43 #include <linux/tty_flip.h> 44 #include <linux/types.h> 45 46 #include <asm/irq.h> 47 48 /* UART name and device definitions */ 49 50 #define S3C24XX_SERIAL_NAME "ttySAC" 51 #define S3C24XX_SERIAL_MAJOR 204 52 #define S3C24XX_SERIAL_MINOR 64 53 54 #ifdef CONFIG_ARM64 55 #define UART_NR 12 56 #else 57 #define UART_NR CONFIG_SERIAL_SAMSUNG_UARTS 58 #endif 59 60 #define S3C24XX_TX_PIO 1 61 #define S3C24XX_TX_DMA 2 62 #define S3C24XX_RX_PIO 1 63 #define S3C24XX_RX_DMA 2 64 65 /* flag to ignore all characters coming in */ 66 #define RXSTAT_DUMMY_READ (0x10000000) 67 68 enum s3c24xx_port_type { 69 TYPE_S3C6400, 70 TYPE_APPLE_S5L, 71 }; 72 73 struct s3c24xx_uart_info { 74 const char *name; 75 enum s3c24xx_port_type type; 76 unsigned int port_type; 77 unsigned int fifosize; 78 u32 rx_fifomask; 79 u32 rx_fifoshift; 80 u32 rx_fifofull; 81 u32 tx_fifomask; 82 u32 tx_fifoshift; 83 u32 tx_fifofull; 84 u32 clksel_mask; 85 u32 clksel_shift; 86 u32 ucon_mask; 87 u8 def_clk_sel; 88 u8 num_clks; 89 u8 iotype; 90 91 /* uart port features */ 92 bool has_divslot; 93 }; 94 95 struct s3c24xx_serial_drv_data { 96 const struct s3c24xx_uart_info info; 97 const struct s3c2410_uartcfg def_cfg; 98 const unsigned int fifosize[UART_NR]; 99 }; 100 101 struct s3c24xx_uart_dma { 102 unsigned int rx_chan_id; 103 unsigned int tx_chan_id; 104 105 struct dma_slave_config rx_conf; 106 struct dma_slave_config tx_conf; 107 108 struct dma_chan *rx_chan; 109 struct dma_chan *tx_chan; 110 111 dma_addr_t rx_addr; 112 dma_addr_t tx_addr; 113 114 dma_cookie_t rx_cookie; 115 dma_cookie_t tx_cookie; 116 117 char *rx_buf; 118 119 dma_addr_t tx_transfer_addr; 120 121 size_t rx_size; 122 size_t tx_size; 123 124 struct dma_async_tx_descriptor *tx_desc; 125 struct dma_async_tx_descriptor *rx_desc; 126 127 int tx_bytes_requested; 128 int rx_bytes_requested; 129 }; 130 131 struct s3c24xx_uart_port { 132 unsigned char rx_enabled; 133 unsigned char tx_enabled; 134 unsigned int pm_level; 135 unsigned long baudclk_rate; 136 unsigned int min_dma_size; 137 138 unsigned int rx_irq; 139 unsigned int tx_irq; 140 141 unsigned int tx_in_progress; 142 unsigned int tx_mode; 143 unsigned int rx_mode; 144 145 const struct s3c24xx_uart_info *info; 146 struct clk *clk; 147 struct clk *baudclk; 148 struct uart_port port; 149 const struct s3c24xx_serial_drv_data *drv_data; 150 151 /* reference to platform data */ 152 const struct s3c2410_uartcfg *cfg; 153 154 struct s3c24xx_uart_dma *dma; 155 }; 156 157 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport); 158 159 /* conversion functions */ 160 161 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev) 162 163 /* register access controls */ 164 165 #define portaddr(port, reg) ((port)->membase + (reg)) 166 #define portaddrl(port, reg) \ 167 ((unsigned long *)(unsigned long)((port)->membase + (reg))) 168 169 static u32 rd_reg(const struct uart_port *port, u32 reg) 170 { 171 switch (port->iotype) { 172 case UPIO_MEM: 173 return readb_relaxed(portaddr(port, reg)); 174 case UPIO_MEM32: 175 return readl_relaxed(portaddr(port, reg)); 176 default: 177 return 0; 178 } 179 return 0; 180 } 181 182 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg))) 183 184 static void wr_reg(const struct uart_port *port, u32 reg, u32 val) 185 { 186 switch (port->iotype) { 187 case UPIO_MEM: 188 writeb_relaxed(val, portaddr(port, reg)); 189 break; 190 case UPIO_MEM32: 191 writel_relaxed(val, portaddr(port, reg)); 192 break; 193 } 194 } 195 196 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg)) 197 198 /* Byte-order aware bit setting/clearing functions. */ 199 200 static inline void s3c24xx_set_bit(const struct uart_port *port, int idx, 201 u32 reg) 202 { 203 unsigned long flags; 204 u32 val; 205 206 local_irq_save(flags); 207 val = rd_regl(port, reg); 208 val |= (1 << idx); 209 wr_regl(port, reg, val); 210 local_irq_restore(flags); 211 } 212 213 static inline void s3c24xx_clear_bit(const struct uart_port *port, int idx, 214 u32 reg) 215 { 216 unsigned long flags; 217 u32 val; 218 219 local_irq_save(flags); 220 val = rd_regl(port, reg); 221 val &= ~(1 << idx); 222 wr_regl(port, reg, val); 223 local_irq_restore(flags); 224 } 225 226 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port) 227 { 228 return container_of(port, struct s3c24xx_uart_port, port); 229 } 230 231 /* translate a port to the device name */ 232 233 static inline const char *s3c24xx_serial_portname(const struct uart_port *port) 234 { 235 return to_platform_device(port->dev)->name; 236 } 237 238 static bool s3c24xx_serial_txempty_nofifo(const struct uart_port *port) 239 { 240 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE; 241 } 242 243 static void s3c24xx_serial_rx_enable(struct uart_port *port) 244 { 245 struct s3c24xx_uart_port *ourport = to_ourport(port); 246 unsigned long flags; 247 int count = 10000; 248 u32 ucon, ufcon; 249 250 uart_port_lock_irqsave(port, &flags); 251 252 while (--count && !s3c24xx_serial_txempty_nofifo(port)) 253 udelay(100); 254 255 ufcon = rd_regl(port, S3C2410_UFCON); 256 ufcon |= S3C2410_UFCON_RESETRX; 257 wr_regl(port, S3C2410_UFCON, ufcon); 258 259 ucon = rd_regl(port, S3C2410_UCON); 260 ucon |= S3C2410_UCON_RXIRQMODE; 261 wr_regl(port, S3C2410_UCON, ucon); 262 263 ourport->rx_enabled = 1; 264 uart_port_unlock_irqrestore(port, flags); 265 } 266 267 static void s3c24xx_serial_rx_disable(struct uart_port *port) 268 { 269 struct s3c24xx_uart_port *ourport = to_ourport(port); 270 unsigned long flags; 271 u32 ucon; 272 273 uart_port_lock_irqsave(port, &flags); 274 275 ucon = rd_regl(port, S3C2410_UCON); 276 ucon &= ~S3C2410_UCON_RXIRQMODE; 277 wr_regl(port, S3C2410_UCON, ucon); 278 279 ourport->rx_enabled = 0; 280 uart_port_unlock_irqrestore(port, flags); 281 } 282 283 static void s3c24xx_serial_stop_tx(struct uart_port *port) 284 { 285 struct s3c24xx_uart_port *ourport = to_ourport(port); 286 struct s3c24xx_uart_dma *dma = ourport->dma; 287 struct dma_tx_state state; 288 int count; 289 290 if (!ourport->tx_enabled) 291 return; 292 293 switch (ourport->info->type) { 294 case TYPE_S3C6400: 295 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM); 296 break; 297 case TYPE_APPLE_S5L: 298 s3c24xx_clear_bit(port, APPLE_S5L_UCON_TXTHRESH_ENA, S3C2410_UCON); 299 break; 300 default: 301 disable_irq_nosync(ourport->tx_irq); 302 break; 303 } 304 305 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) { 306 dmaengine_pause(dma->tx_chan); 307 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state); 308 dmaengine_terminate_all(dma->tx_chan); 309 dma_sync_single_for_cpu(dma->tx_chan->device->dev, 310 dma->tx_transfer_addr, dma->tx_size, 311 DMA_TO_DEVICE); 312 async_tx_ack(dma->tx_desc); 313 count = dma->tx_bytes_requested - state.residue; 314 uart_xmit_advance(port, count); 315 } 316 317 ourport->tx_enabled = 0; 318 ourport->tx_in_progress = 0; 319 320 if (port->flags & UPF_CONS_FLOW) 321 s3c24xx_serial_rx_enable(port); 322 323 ourport->tx_mode = 0; 324 } 325 326 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport); 327 328 static void s3c24xx_serial_tx_dma_complete(void *args) 329 { 330 struct s3c24xx_uart_port *ourport = args; 331 struct uart_port *port = &ourport->port; 332 struct circ_buf *xmit = &port->state->xmit; 333 struct s3c24xx_uart_dma *dma = ourport->dma; 334 struct dma_tx_state state; 335 unsigned long flags; 336 int count; 337 338 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state); 339 count = dma->tx_bytes_requested - state.residue; 340 async_tx_ack(dma->tx_desc); 341 342 dma_sync_single_for_cpu(dma->tx_chan->device->dev, 343 dma->tx_transfer_addr, dma->tx_size, 344 DMA_TO_DEVICE); 345 346 uart_port_lock_irqsave(port, &flags); 347 348 uart_xmit_advance(port, count); 349 ourport->tx_in_progress = 0; 350 351 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 352 uart_write_wakeup(port); 353 354 s3c24xx_serial_start_next_tx(ourport); 355 uart_port_unlock_irqrestore(port, flags); 356 } 357 358 static void enable_tx_dma(struct s3c24xx_uart_port *ourport) 359 { 360 const struct uart_port *port = &ourport->port; 361 u32 ucon; 362 363 /* Mask Tx interrupt */ 364 switch (ourport->info->type) { 365 case TYPE_S3C6400: 366 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM); 367 break; 368 case TYPE_APPLE_S5L: 369 WARN_ON(1); // No DMA 370 break; 371 default: 372 disable_irq_nosync(ourport->tx_irq); 373 break; 374 } 375 376 /* Enable tx dma mode */ 377 ucon = rd_regl(port, S3C2410_UCON); 378 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK); 379 ucon |= S3C64XX_UCON_TXBURST_1; 380 ucon |= S3C64XX_UCON_TXMODE_DMA; 381 wr_regl(port, S3C2410_UCON, ucon); 382 383 ourport->tx_mode = S3C24XX_TX_DMA; 384 } 385 386 static void enable_tx_pio(struct s3c24xx_uart_port *ourport) 387 { 388 const struct uart_port *port = &ourport->port; 389 u32 ucon, ufcon; 390 391 /* Set ufcon txtrig */ 392 ourport->tx_in_progress = S3C24XX_TX_PIO; 393 ufcon = rd_regl(port, S3C2410_UFCON); 394 wr_regl(port, S3C2410_UFCON, ufcon); 395 396 /* Enable tx pio mode */ 397 ucon = rd_regl(port, S3C2410_UCON); 398 ucon &= ~(S3C64XX_UCON_TXMODE_MASK); 399 ucon |= S3C64XX_UCON_TXMODE_CPU; 400 wr_regl(port, S3C2410_UCON, ucon); 401 402 /* Unmask Tx interrupt */ 403 switch (ourport->info->type) { 404 case TYPE_S3C6400: 405 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD, 406 S3C64XX_UINTM); 407 break; 408 case TYPE_APPLE_S5L: 409 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK; 410 wr_regl(port, S3C2410_UCON, ucon); 411 break; 412 default: 413 enable_irq(ourport->tx_irq); 414 break; 415 } 416 417 ourport->tx_mode = S3C24XX_TX_PIO; 418 419 /* 420 * The Apple version only has edge triggered TX IRQs, so we need 421 * to kick off the process by sending some characters here. 422 */ 423 if (ourport->info->type == TYPE_APPLE_S5L) 424 s3c24xx_serial_tx_chars(ourport); 425 } 426 427 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport) 428 { 429 if (ourport->tx_mode != S3C24XX_TX_PIO) 430 enable_tx_pio(ourport); 431 } 432 433 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport, 434 unsigned int count) 435 { 436 struct uart_port *port = &ourport->port; 437 struct circ_buf *xmit = &port->state->xmit; 438 struct s3c24xx_uart_dma *dma = ourport->dma; 439 440 if (ourport->tx_mode != S3C24XX_TX_DMA) 441 enable_tx_dma(ourport); 442 443 dma->tx_size = count & ~(dma_get_cache_alignment() - 1); 444 dma->tx_transfer_addr = dma->tx_addr + xmit->tail; 445 446 dma_sync_single_for_device(dma->tx_chan->device->dev, 447 dma->tx_transfer_addr, dma->tx_size, 448 DMA_TO_DEVICE); 449 450 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan, 451 dma->tx_transfer_addr, dma->tx_size, 452 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 453 if (!dma->tx_desc) { 454 dev_err(ourport->port.dev, "Unable to get desc for Tx\n"); 455 return -EIO; 456 } 457 458 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete; 459 dma->tx_desc->callback_param = ourport; 460 dma->tx_bytes_requested = dma->tx_size; 461 462 ourport->tx_in_progress = S3C24XX_TX_DMA; 463 dma->tx_cookie = dmaengine_submit(dma->tx_desc); 464 dma_async_issue_pending(dma->tx_chan); 465 return 0; 466 } 467 468 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport) 469 { 470 struct uart_port *port = &ourport->port; 471 struct circ_buf *xmit = &port->state->xmit; 472 unsigned long count; 473 474 /* Get data size up to the end of buffer */ 475 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 476 477 if (!count) { 478 s3c24xx_serial_stop_tx(port); 479 return; 480 } 481 482 if (!ourport->dma || !ourport->dma->tx_chan || 483 count < ourport->min_dma_size || 484 xmit->tail & (dma_get_cache_alignment() - 1)) 485 s3c24xx_serial_start_tx_pio(ourport); 486 else 487 s3c24xx_serial_start_tx_dma(ourport, count); 488 } 489 490 static void s3c24xx_serial_start_tx(struct uart_port *port) 491 { 492 struct s3c24xx_uart_port *ourport = to_ourport(port); 493 struct circ_buf *xmit = &port->state->xmit; 494 495 if (!ourport->tx_enabled) { 496 if (port->flags & UPF_CONS_FLOW) 497 s3c24xx_serial_rx_disable(port); 498 499 ourport->tx_enabled = 1; 500 if (!ourport->dma || !ourport->dma->tx_chan) 501 s3c24xx_serial_start_tx_pio(ourport); 502 } 503 504 if (ourport->dma && ourport->dma->tx_chan) { 505 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress) 506 s3c24xx_serial_start_next_tx(ourport); 507 } 508 } 509 510 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport, 511 struct tty_port *tty, int count) 512 { 513 struct s3c24xx_uart_dma *dma = ourport->dma; 514 int copied; 515 516 if (!count) 517 return; 518 519 dma_sync_single_for_cpu(dma->rx_chan->device->dev, dma->rx_addr, 520 dma->rx_size, DMA_FROM_DEVICE); 521 522 ourport->port.icount.rx += count; 523 if (!tty) { 524 dev_err(ourport->port.dev, "No tty port\n"); 525 return; 526 } 527 copied = tty_insert_flip_string(tty, 528 ((unsigned char *)(ourport->dma->rx_buf)), count); 529 if (copied != count) { 530 WARN_ON(1); 531 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n"); 532 } 533 } 534 535 static void s3c24xx_serial_stop_rx(struct uart_port *port) 536 { 537 struct s3c24xx_uart_port *ourport = to_ourport(port); 538 struct s3c24xx_uart_dma *dma = ourport->dma; 539 struct tty_port *t = &port->state->port; 540 struct dma_tx_state state; 541 enum dma_status dma_status; 542 unsigned int received; 543 544 if (ourport->rx_enabled) { 545 dev_dbg(port->dev, "stopping rx\n"); 546 switch (ourport->info->type) { 547 case TYPE_S3C6400: 548 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD, 549 S3C64XX_UINTM); 550 break; 551 case TYPE_APPLE_S5L: 552 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON); 553 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON); 554 break; 555 default: 556 disable_irq_nosync(ourport->rx_irq); 557 break; 558 } 559 ourport->rx_enabled = 0; 560 } 561 if (dma && dma->rx_chan) { 562 dmaengine_pause(dma->tx_chan); 563 dma_status = dmaengine_tx_status(dma->rx_chan, 564 dma->rx_cookie, &state); 565 if (dma_status == DMA_IN_PROGRESS || 566 dma_status == DMA_PAUSED) { 567 received = dma->rx_bytes_requested - state.residue; 568 dmaengine_terminate_all(dma->rx_chan); 569 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 570 } 571 } 572 } 573 574 static inline const struct s3c24xx_uart_info 575 *s3c24xx_port_to_info(struct uart_port *port) 576 { 577 return to_ourport(port)->info; 578 } 579 580 static inline const struct s3c2410_uartcfg 581 *s3c24xx_port_to_cfg(const struct uart_port *port) 582 { 583 const struct s3c24xx_uart_port *ourport; 584 585 if (port->dev == NULL) 586 return NULL; 587 588 ourport = container_of(port, struct s3c24xx_uart_port, port); 589 return ourport->cfg; 590 } 591 592 static unsigned int 593 s3c24xx_serial_rx_fifocnt(const struct s3c24xx_uart_port *ourport, u32 ufstat) 594 { 595 const struct s3c24xx_uart_info *info = ourport->info; 596 597 if (ufstat & info->rx_fifofull) 598 return ourport->port.fifosize; 599 600 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift; 601 } 602 603 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport); 604 static void s3c24xx_serial_rx_dma_complete(void *args) 605 { 606 struct s3c24xx_uart_port *ourport = args; 607 struct uart_port *port = &ourport->port; 608 609 struct s3c24xx_uart_dma *dma = ourport->dma; 610 struct tty_port *t = &port->state->port; 611 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port); 612 613 struct dma_tx_state state; 614 unsigned long flags; 615 int received; 616 617 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state); 618 received = dma->rx_bytes_requested - state.residue; 619 async_tx_ack(dma->rx_desc); 620 621 uart_port_lock_irqsave(port, &flags); 622 623 if (received) 624 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 625 626 if (tty) { 627 tty_flip_buffer_push(t); 628 tty_kref_put(tty); 629 } 630 631 s3c64xx_start_rx_dma(ourport); 632 633 uart_port_unlock_irqrestore(port, flags); 634 } 635 636 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport) 637 { 638 struct s3c24xx_uart_dma *dma = ourport->dma; 639 640 dma_sync_single_for_device(dma->rx_chan->device->dev, dma->rx_addr, 641 dma->rx_size, DMA_FROM_DEVICE); 642 643 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan, 644 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM, 645 DMA_PREP_INTERRUPT); 646 if (!dma->rx_desc) { 647 dev_err(ourport->port.dev, "Unable to get desc for Rx\n"); 648 return; 649 } 650 651 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete; 652 dma->rx_desc->callback_param = ourport; 653 dma->rx_bytes_requested = dma->rx_size; 654 655 dma->rx_cookie = dmaengine_submit(dma->rx_desc); 656 dma_async_issue_pending(dma->rx_chan); 657 } 658 659 /* ? - where has parity gone?? */ 660 #define S3C2410_UERSTAT_PARITY (0x1000) 661 662 static void enable_rx_dma(struct s3c24xx_uart_port *ourport) 663 { 664 struct uart_port *port = &ourport->port; 665 u32 ucon; 666 667 /* set Rx mode to DMA mode */ 668 ucon = rd_regl(port, S3C2410_UCON); 669 ucon &= ~(S3C64XX_UCON_RXBURST_MASK | 670 S3C64XX_UCON_TIMEOUT_MASK | 671 S3C64XX_UCON_EMPTYINT_EN | 672 S3C64XX_UCON_DMASUS_EN | 673 S3C64XX_UCON_TIMEOUT_EN | 674 S3C64XX_UCON_RXMODE_MASK); 675 ucon |= S3C64XX_UCON_RXBURST_1 | 676 0xf << S3C64XX_UCON_TIMEOUT_SHIFT | 677 S3C64XX_UCON_EMPTYINT_EN | 678 S3C64XX_UCON_TIMEOUT_EN | 679 S3C64XX_UCON_RXMODE_DMA; 680 wr_regl(port, S3C2410_UCON, ucon); 681 682 ourport->rx_mode = S3C24XX_RX_DMA; 683 } 684 685 static void enable_rx_pio(struct s3c24xx_uart_port *ourport) 686 { 687 struct uart_port *port = &ourport->port; 688 u32 ucon; 689 690 /* set Rx mode to DMA mode */ 691 ucon = rd_regl(port, S3C2410_UCON); 692 ucon &= ~S3C64XX_UCON_RXMODE_MASK; 693 ucon |= S3C64XX_UCON_RXMODE_CPU; 694 695 /* Apple types use these bits for IRQ masks */ 696 if (ourport->info->type != TYPE_APPLE_S5L) { 697 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK | 698 S3C64XX_UCON_EMPTYINT_EN | 699 S3C64XX_UCON_DMASUS_EN | 700 S3C64XX_UCON_TIMEOUT_EN); 701 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT | 702 S3C64XX_UCON_TIMEOUT_EN; 703 } 704 wr_regl(port, S3C2410_UCON, ucon); 705 706 ourport->rx_mode = S3C24XX_RX_PIO; 707 } 708 709 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport); 710 711 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id) 712 { 713 struct s3c24xx_uart_port *ourport = dev_id; 714 struct uart_port *port = &ourport->port; 715 struct s3c24xx_uart_dma *dma = ourport->dma; 716 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port); 717 struct tty_port *t = &port->state->port; 718 struct dma_tx_state state; 719 unsigned int received; 720 u32 utrstat; 721 722 utrstat = rd_regl(port, S3C2410_UTRSTAT); 723 rd_regl(port, S3C2410_UFSTAT); 724 725 uart_port_lock(port); 726 727 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) { 728 s3c64xx_start_rx_dma(ourport); 729 if (ourport->rx_mode == S3C24XX_RX_PIO) 730 enable_rx_dma(ourport); 731 goto finish; 732 } 733 734 if (ourport->rx_mode == S3C24XX_RX_DMA) { 735 dmaengine_pause(dma->rx_chan); 736 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state); 737 dmaengine_terminate_all(dma->rx_chan); 738 received = dma->rx_bytes_requested - state.residue; 739 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 740 741 enable_rx_pio(ourport); 742 } 743 744 s3c24xx_serial_rx_drain_fifo(ourport); 745 746 if (tty) { 747 tty_flip_buffer_push(t); 748 tty_kref_put(tty); 749 } 750 751 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT); 752 753 finish: 754 uart_port_unlock(port); 755 756 return IRQ_HANDLED; 757 } 758 759 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport) 760 { 761 struct uart_port *port = &ourport->port; 762 unsigned int max_count = port->fifosize; 763 unsigned int fifocnt = 0; 764 u32 ufcon, ufstat, uerstat; 765 u8 ch, flag; 766 767 while (max_count-- > 0) { 768 /* 769 * Receive all characters known to be in FIFO 770 * before reading FIFO level again 771 */ 772 if (fifocnt == 0) { 773 ufstat = rd_regl(port, S3C2410_UFSTAT); 774 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat); 775 if (fifocnt == 0) 776 break; 777 } 778 fifocnt--; 779 780 uerstat = rd_regl(port, S3C2410_UERSTAT); 781 ch = rd_reg(port, S3C2410_URXH); 782 783 if (port->flags & UPF_CONS_FLOW) { 784 bool txe = s3c24xx_serial_txempty_nofifo(port); 785 786 if (ourport->rx_enabled) { 787 if (!txe) { 788 ourport->rx_enabled = 0; 789 continue; 790 } 791 } else { 792 if (txe) { 793 ufcon = rd_regl(port, S3C2410_UFCON); 794 ufcon |= S3C2410_UFCON_RESETRX; 795 wr_regl(port, S3C2410_UFCON, ufcon); 796 ourport->rx_enabled = 1; 797 return; 798 } 799 continue; 800 } 801 } 802 803 /* insert the character into the buffer */ 804 805 flag = TTY_NORMAL; 806 port->icount.rx++; 807 808 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) { 809 dev_dbg(port->dev, 810 "rxerr: port ch=0x%02x, rxs=0x%08x\n", 811 ch, uerstat); 812 813 /* check for break */ 814 if (uerstat & S3C2410_UERSTAT_BREAK) { 815 dev_dbg(port->dev, "break!\n"); 816 port->icount.brk++; 817 if (uart_handle_break(port)) 818 continue; /* Ignore character */ 819 } 820 821 if (uerstat & S3C2410_UERSTAT_FRAME) 822 port->icount.frame++; 823 if (uerstat & S3C2410_UERSTAT_OVERRUN) 824 port->icount.overrun++; 825 826 uerstat &= port->read_status_mask; 827 828 if (uerstat & S3C2410_UERSTAT_BREAK) 829 flag = TTY_BREAK; 830 else if (uerstat & S3C2410_UERSTAT_PARITY) 831 flag = TTY_PARITY; 832 else if (uerstat & (S3C2410_UERSTAT_FRAME | 833 S3C2410_UERSTAT_OVERRUN)) 834 flag = TTY_FRAME; 835 } 836 837 if (uart_handle_sysrq_char(port, ch)) 838 continue; /* Ignore character */ 839 840 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, 841 ch, flag); 842 } 843 844 tty_flip_buffer_push(&port->state->port); 845 } 846 847 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id) 848 { 849 struct s3c24xx_uart_port *ourport = dev_id; 850 struct uart_port *port = &ourport->port; 851 852 uart_port_lock(port); 853 s3c24xx_serial_rx_drain_fifo(ourport); 854 uart_port_unlock(port); 855 856 return IRQ_HANDLED; 857 } 858 859 static irqreturn_t s3c24xx_serial_rx_irq(int irq, void *dev_id) 860 { 861 struct s3c24xx_uart_port *ourport = dev_id; 862 863 if (ourport->dma && ourport->dma->rx_chan) 864 return s3c24xx_serial_rx_chars_dma(dev_id); 865 return s3c24xx_serial_rx_chars_pio(dev_id); 866 } 867 868 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport) 869 { 870 struct uart_port *port = &ourport->port; 871 struct circ_buf *xmit = &port->state->xmit; 872 int count, dma_count = 0; 873 874 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 875 876 if (ourport->dma && ourport->dma->tx_chan && 877 count >= ourport->min_dma_size) { 878 int align = dma_get_cache_alignment() - 879 (xmit->tail & (dma_get_cache_alignment() - 1)); 880 if (count - align >= ourport->min_dma_size) { 881 dma_count = count - align; 882 count = align; 883 } 884 } 885 886 if (port->x_char) { 887 wr_reg(port, S3C2410_UTXH, port->x_char); 888 port->icount.tx++; 889 port->x_char = 0; 890 return; 891 } 892 893 /* if there isn't anything more to transmit, or the uart is now 894 * stopped, disable the uart and exit 895 */ 896 897 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 898 s3c24xx_serial_stop_tx(port); 899 return; 900 } 901 902 /* try and drain the buffer... */ 903 904 if (count > port->fifosize) { 905 count = port->fifosize; 906 dma_count = 0; 907 } 908 909 while (!uart_circ_empty(xmit) && count > 0) { 910 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull) 911 break; 912 913 wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]); 914 uart_xmit_advance(port, 1); 915 count--; 916 } 917 918 if (!count && dma_count) { 919 s3c24xx_serial_start_tx_dma(ourport, dma_count); 920 return; 921 } 922 923 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 924 uart_write_wakeup(port); 925 926 if (uart_circ_empty(xmit)) 927 s3c24xx_serial_stop_tx(port); 928 } 929 930 static irqreturn_t s3c24xx_serial_tx_irq(int irq, void *id) 931 { 932 struct s3c24xx_uart_port *ourport = id; 933 struct uart_port *port = &ourport->port; 934 935 uart_port_lock(port); 936 937 s3c24xx_serial_tx_chars(ourport); 938 939 uart_port_unlock(port); 940 return IRQ_HANDLED; 941 } 942 943 /* interrupt handler for s3c64xx and later SoC's.*/ 944 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id) 945 { 946 const struct s3c24xx_uart_port *ourport = id; 947 const struct uart_port *port = &ourport->port; 948 u32 pend = rd_regl(port, S3C64XX_UINTP); 949 irqreturn_t ret = IRQ_HANDLED; 950 951 if (pend & S3C64XX_UINTM_RXD_MSK) { 952 ret = s3c24xx_serial_rx_irq(irq, id); 953 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK); 954 } 955 if (pend & S3C64XX_UINTM_TXD_MSK) { 956 ret = s3c24xx_serial_tx_irq(irq, id); 957 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK); 958 } 959 return ret; 960 } 961 962 /* interrupt handler for Apple SoC's.*/ 963 static irqreturn_t apple_serial_handle_irq(int irq, void *id) 964 { 965 const struct s3c24xx_uart_port *ourport = id; 966 const struct uart_port *port = &ourport->port; 967 u32 pend = rd_regl(port, S3C2410_UTRSTAT); 968 irqreturn_t ret = IRQ_NONE; 969 970 if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) { 971 wr_regl(port, S3C2410_UTRSTAT, 972 APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO); 973 ret = s3c24xx_serial_rx_irq(irq, id); 974 } 975 if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) { 976 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH); 977 ret = s3c24xx_serial_tx_irq(irq, id); 978 } 979 980 return ret; 981 } 982 983 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) 984 { 985 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 986 u32 ufstat = rd_regl(port, S3C2410_UFSTAT); 987 u32 ufcon = rd_regl(port, S3C2410_UFCON); 988 989 if (ufcon & S3C2410_UFCON_FIFOMODE) { 990 if ((ufstat & info->tx_fifomask) || 991 (ufstat & info->tx_fifofull)) 992 return 0; 993 return TIOCSER_TEMT; 994 } 995 996 return s3c24xx_serial_txempty_nofifo(port) ? TIOCSER_TEMT : 0; 997 } 998 999 /* no modem control lines */ 1000 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) 1001 { 1002 u32 umstat = rd_reg(port, S3C2410_UMSTAT); 1003 1004 if (umstat & S3C2410_UMSTAT_CTS) 1005 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 1006 else 1007 return TIOCM_CAR | TIOCM_DSR; 1008 } 1009 1010 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) 1011 { 1012 u32 umcon = rd_regl(port, S3C2410_UMCON); 1013 u32 ucon = rd_regl(port, S3C2410_UCON); 1014 1015 if (mctrl & TIOCM_RTS) 1016 umcon |= S3C2410_UMCOM_RTS_LOW; 1017 else 1018 umcon &= ~S3C2410_UMCOM_RTS_LOW; 1019 1020 wr_regl(port, S3C2410_UMCON, umcon); 1021 1022 if (mctrl & TIOCM_LOOP) 1023 ucon |= S3C2410_UCON_LOOPBACK; 1024 else 1025 ucon &= ~S3C2410_UCON_LOOPBACK; 1026 1027 wr_regl(port, S3C2410_UCON, ucon); 1028 } 1029 1030 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state) 1031 { 1032 unsigned long flags; 1033 u32 ucon; 1034 1035 uart_port_lock_irqsave(port, &flags); 1036 1037 ucon = rd_regl(port, S3C2410_UCON); 1038 1039 if (break_state) 1040 ucon |= S3C2410_UCON_SBREAK; 1041 else 1042 ucon &= ~S3C2410_UCON_SBREAK; 1043 1044 wr_regl(port, S3C2410_UCON, ucon); 1045 1046 uart_port_unlock_irqrestore(port, flags); 1047 } 1048 1049 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p) 1050 { 1051 struct s3c24xx_uart_dma *dma = p->dma; 1052 struct dma_slave_caps dma_caps; 1053 const char *reason = NULL; 1054 int ret; 1055 1056 /* Default slave configuration parameters */ 1057 dma->rx_conf.direction = DMA_DEV_TO_MEM; 1058 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1059 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH; 1060 dma->rx_conf.src_maxburst = 1; 1061 1062 dma->tx_conf.direction = DMA_MEM_TO_DEV; 1063 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1064 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH; 1065 dma->tx_conf.dst_maxburst = 1; 1066 1067 dma->rx_chan = dma_request_chan(p->port.dev, "rx"); 1068 1069 if (IS_ERR(dma->rx_chan)) { 1070 reason = "DMA RX channel request failed"; 1071 ret = PTR_ERR(dma->rx_chan); 1072 goto err_warn; 1073 } 1074 1075 ret = dma_get_slave_caps(dma->rx_chan, &dma_caps); 1076 if (ret < 0 || 1077 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) { 1078 reason = "insufficient DMA RX engine capabilities"; 1079 ret = -EOPNOTSUPP; 1080 goto err_release_rx; 1081 } 1082 1083 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf); 1084 1085 dma->tx_chan = dma_request_chan(p->port.dev, "tx"); 1086 if (IS_ERR(dma->tx_chan)) { 1087 reason = "DMA TX channel request failed"; 1088 ret = PTR_ERR(dma->tx_chan); 1089 goto err_release_rx; 1090 } 1091 1092 ret = dma_get_slave_caps(dma->tx_chan, &dma_caps); 1093 if (ret < 0 || 1094 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) { 1095 reason = "insufficient DMA TX engine capabilities"; 1096 ret = -EOPNOTSUPP; 1097 goto err_release_tx; 1098 } 1099 1100 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf); 1101 1102 /* RX buffer */ 1103 dma->rx_size = PAGE_SIZE; 1104 1105 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL); 1106 if (!dma->rx_buf) { 1107 ret = -ENOMEM; 1108 goto err_release_tx; 1109 } 1110 1111 dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf, 1112 dma->rx_size, DMA_FROM_DEVICE); 1113 if (dma_mapping_error(dma->rx_chan->device->dev, dma->rx_addr)) { 1114 reason = "DMA mapping error for RX buffer"; 1115 ret = -EIO; 1116 goto err_free_rx; 1117 } 1118 1119 /* TX buffer */ 1120 dma->tx_addr = dma_map_single(dma->tx_chan->device->dev, 1121 p->port.state->xmit.buf, UART_XMIT_SIZE, 1122 DMA_TO_DEVICE); 1123 if (dma_mapping_error(dma->tx_chan->device->dev, dma->tx_addr)) { 1124 reason = "DMA mapping error for TX buffer"; 1125 ret = -EIO; 1126 goto err_unmap_rx; 1127 } 1128 1129 return 0; 1130 1131 err_unmap_rx: 1132 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr, 1133 dma->rx_size, DMA_FROM_DEVICE); 1134 err_free_rx: 1135 kfree(dma->rx_buf); 1136 err_release_tx: 1137 dma_release_channel(dma->tx_chan); 1138 err_release_rx: 1139 dma_release_channel(dma->rx_chan); 1140 err_warn: 1141 if (reason) 1142 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason); 1143 return ret; 1144 } 1145 1146 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p) 1147 { 1148 struct s3c24xx_uart_dma *dma = p->dma; 1149 1150 if (dma->rx_chan) { 1151 dmaengine_terminate_all(dma->rx_chan); 1152 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr, 1153 dma->rx_size, DMA_FROM_DEVICE); 1154 kfree(dma->rx_buf); 1155 dma_release_channel(dma->rx_chan); 1156 dma->rx_chan = NULL; 1157 } 1158 1159 if (dma->tx_chan) { 1160 dmaengine_terminate_all(dma->tx_chan); 1161 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr, 1162 UART_XMIT_SIZE, DMA_TO_DEVICE); 1163 dma_release_channel(dma->tx_chan); 1164 dma->tx_chan = NULL; 1165 } 1166 } 1167 1168 static void s3c64xx_serial_shutdown(struct uart_port *port) 1169 { 1170 struct s3c24xx_uart_port *ourport = to_ourport(port); 1171 1172 ourport->tx_enabled = 0; 1173 ourport->tx_mode = 0; 1174 ourport->rx_enabled = 0; 1175 1176 free_irq(port->irq, ourport); 1177 1178 wr_regl(port, S3C64XX_UINTP, 0xf); 1179 wr_regl(port, S3C64XX_UINTM, 0xf); 1180 1181 if (ourport->dma) 1182 s3c24xx_serial_release_dma(ourport); 1183 1184 ourport->tx_in_progress = 0; 1185 } 1186 1187 static void apple_s5l_serial_shutdown(struct uart_port *port) 1188 { 1189 struct s3c24xx_uart_port *ourport = to_ourport(port); 1190 1191 u32 ucon; 1192 1193 ucon = rd_regl(port, S3C2410_UCON); 1194 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | 1195 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 1196 APPLE_S5L_UCON_RXTO_ENA_MSK); 1197 wr_regl(port, S3C2410_UCON, ucon); 1198 1199 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS); 1200 1201 free_irq(port->irq, ourport); 1202 1203 ourport->tx_enabled = 0; 1204 ourport->tx_mode = 0; 1205 ourport->rx_enabled = 0; 1206 1207 if (ourport->dma) 1208 s3c24xx_serial_release_dma(ourport); 1209 1210 ourport->tx_in_progress = 0; 1211 } 1212 1213 static int s3c64xx_serial_startup(struct uart_port *port) 1214 { 1215 struct s3c24xx_uart_port *ourport = to_ourport(port); 1216 unsigned long flags; 1217 u32 ufcon; 1218 int ret; 1219 1220 wr_regl(port, S3C64XX_UINTM, 0xf); 1221 if (ourport->dma) { 1222 ret = s3c24xx_serial_request_dma(ourport); 1223 if (ret < 0) { 1224 devm_kfree(port->dev, ourport->dma); 1225 ourport->dma = NULL; 1226 } 1227 } 1228 1229 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED, 1230 s3c24xx_serial_portname(port), ourport); 1231 if (ret) { 1232 dev_err(port->dev, "cannot get irq %d\n", port->irq); 1233 return ret; 1234 } 1235 1236 /* For compatibility with s3c24xx Soc's */ 1237 ourport->rx_enabled = 1; 1238 ourport->tx_enabled = 0; 1239 1240 uart_port_lock_irqsave(port, &flags); 1241 1242 ufcon = rd_regl(port, S3C2410_UFCON); 1243 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8; 1244 if (!uart_console(port)) 1245 ufcon |= S3C2410_UFCON_RESETTX; 1246 wr_regl(port, S3C2410_UFCON, ufcon); 1247 1248 enable_rx_pio(ourport); 1249 1250 uart_port_unlock_irqrestore(port, flags); 1251 1252 /* Enable Rx Interrupt */ 1253 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM); 1254 1255 return ret; 1256 } 1257 1258 static int apple_s5l_serial_startup(struct uart_port *port) 1259 { 1260 struct s3c24xx_uart_port *ourport = to_ourport(port); 1261 unsigned long flags; 1262 u32 ufcon; 1263 int ret; 1264 1265 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS); 1266 1267 ret = request_irq(port->irq, apple_serial_handle_irq, 0, 1268 s3c24xx_serial_portname(port), ourport); 1269 if (ret) { 1270 dev_err(port->dev, "cannot get irq %d\n", port->irq); 1271 return ret; 1272 } 1273 1274 /* For compatibility with s3c24xx Soc's */ 1275 ourport->rx_enabled = 1; 1276 ourport->tx_enabled = 0; 1277 1278 uart_port_lock_irqsave(port, &flags); 1279 1280 ufcon = rd_regl(port, S3C2410_UFCON); 1281 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8; 1282 if (!uart_console(port)) 1283 ufcon |= S3C2410_UFCON_RESETTX; 1284 wr_regl(port, S3C2410_UFCON, ufcon); 1285 1286 enable_rx_pio(ourport); 1287 1288 uart_port_unlock_irqrestore(port, flags); 1289 1290 /* Enable Rx Interrupt */ 1291 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON); 1292 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON); 1293 1294 return ret; 1295 } 1296 1297 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, 1298 unsigned int old) 1299 { 1300 struct s3c24xx_uart_port *ourport = to_ourport(port); 1301 int timeout = 10000; 1302 1303 ourport->pm_level = level; 1304 1305 switch (level) { 1306 case 3: 1307 while (--timeout && !s3c24xx_serial_txempty_nofifo(port)) 1308 udelay(100); 1309 1310 if (!IS_ERR(ourport->baudclk)) 1311 clk_disable_unprepare(ourport->baudclk); 1312 1313 clk_disable_unprepare(ourport->clk); 1314 break; 1315 1316 case 0: 1317 clk_prepare_enable(ourport->clk); 1318 1319 if (!IS_ERR(ourport->baudclk)) 1320 clk_prepare_enable(ourport->baudclk); 1321 break; 1322 default: 1323 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level); 1324 } 1325 } 1326 1327 /* baud rate calculation 1328 * 1329 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number 1330 * of different sources, including the peripheral clock ("pclk") and an 1331 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk") 1332 * with a programmable extra divisor. 1333 * 1334 * The following code goes through the clock sources, and calculates the 1335 * baud clocks (and the resultant actual baud rates) and then tries to 1336 * pick the closest one and select that. 1337 * 1338 */ 1339 1340 #define MAX_CLK_NAME_LENGTH 15 1341 1342 static inline u8 s3c24xx_serial_getsource(struct uart_port *port) 1343 { 1344 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1345 u32 ucon; 1346 1347 if (info->num_clks == 1) 1348 return 0; 1349 1350 ucon = rd_regl(port, S3C2410_UCON); 1351 ucon &= info->clksel_mask; 1352 return ucon >> info->clksel_shift; 1353 } 1354 1355 static void s3c24xx_serial_setsource(struct uart_port *port, u8 clk_sel) 1356 { 1357 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1358 u32 ucon; 1359 1360 if (info->num_clks == 1) 1361 return; 1362 1363 ucon = rd_regl(port, S3C2410_UCON); 1364 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel) 1365 return; 1366 1367 ucon &= ~info->clksel_mask; 1368 ucon |= clk_sel << info->clksel_shift; 1369 wr_regl(port, S3C2410_UCON, ucon); 1370 } 1371 1372 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport, 1373 unsigned int req_baud, struct clk **best_clk, 1374 u8 *clk_num) 1375 { 1376 const struct s3c24xx_uart_info *info = ourport->info; 1377 struct clk *clk; 1378 unsigned long rate; 1379 unsigned int baud, quot, best_quot = 0; 1380 char clkname[MAX_CLK_NAME_LENGTH]; 1381 int calc_deviation, deviation = (1 << 30) - 1; 1382 u8 cnt; 1383 1384 for (cnt = 0; cnt < info->num_clks; cnt++) { 1385 /* Keep selected clock if provided */ 1386 if (ourport->cfg->clk_sel && 1387 !(ourport->cfg->clk_sel & (1 << cnt))) 1388 continue; 1389 1390 sprintf(clkname, "clk_uart_baud%d", cnt); 1391 clk = clk_get(ourport->port.dev, clkname); 1392 if (IS_ERR(clk)) 1393 continue; 1394 1395 rate = clk_get_rate(clk); 1396 if (!rate) { 1397 dev_err(ourport->port.dev, 1398 "Failed to get clock rate for %s.\n", clkname); 1399 clk_put(clk); 1400 continue; 1401 } 1402 1403 if (ourport->info->has_divslot) { 1404 unsigned long div = rate / req_baud; 1405 1406 /* The UDIVSLOT register on the newer UARTs allows us to 1407 * get a divisor adjustment of 1/16th on the baud clock. 1408 * 1409 * We don't keep the UDIVSLOT value (the 16ths we 1410 * calculated by not multiplying the baud by 16) as it 1411 * is easy enough to recalculate. 1412 */ 1413 1414 quot = div / 16; 1415 baud = rate / div; 1416 } else { 1417 quot = (rate + (8 * req_baud)) / (16 * req_baud); 1418 baud = rate / (quot * 16); 1419 } 1420 quot--; 1421 1422 calc_deviation = abs(req_baud - baud); 1423 1424 if (calc_deviation < deviation) { 1425 /* 1426 * If we find a better clk, release the previous one, if 1427 * any. 1428 */ 1429 if (!IS_ERR(*best_clk)) 1430 clk_put(*best_clk); 1431 *best_clk = clk; 1432 best_quot = quot; 1433 *clk_num = cnt; 1434 deviation = calc_deviation; 1435 } else { 1436 clk_put(clk); 1437 } 1438 } 1439 1440 return best_quot; 1441 } 1442 1443 /* udivslot_table[] 1444 * 1445 * This table takes the fractional value of the baud divisor and gives 1446 * the recommended setting for the UDIVSLOT register. 1447 */ 1448 static const u16 udivslot_table[16] = { 1449 [0] = 0x0000, 1450 [1] = 0x0080, 1451 [2] = 0x0808, 1452 [3] = 0x0888, 1453 [4] = 0x2222, 1454 [5] = 0x4924, 1455 [6] = 0x4A52, 1456 [7] = 0x54AA, 1457 [8] = 0x5555, 1458 [9] = 0xD555, 1459 [10] = 0xD5D5, 1460 [11] = 0xDDD5, 1461 [12] = 0xDDDD, 1462 [13] = 0xDFDD, 1463 [14] = 0xDFDF, 1464 [15] = 0xFFDF, 1465 }; 1466 1467 static void s3c24xx_serial_set_termios(struct uart_port *port, 1468 struct ktermios *termios, 1469 const struct ktermios *old) 1470 { 1471 const struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port); 1472 struct s3c24xx_uart_port *ourport = to_ourport(port); 1473 struct clk *clk = ERR_PTR(-EINVAL); 1474 unsigned long flags; 1475 unsigned int baud, quot; 1476 unsigned int udivslot = 0; 1477 u32 ulcon, umcon; 1478 u8 clk_sel = 0; 1479 1480 /* 1481 * We don't support modem control lines. 1482 */ 1483 termios->c_cflag &= ~(HUPCL | CMSPAR); 1484 termios->c_cflag |= CLOCAL; 1485 1486 /* 1487 * Ask the core to calculate the divisor for us. 1488 */ 1489 1490 baud = uart_get_baud_rate(port, termios, old, 0, 3000000); 1491 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel); 1492 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) 1493 quot = port->custom_divisor; 1494 if (IS_ERR(clk)) 1495 return; 1496 1497 /* check to see if we need to change clock source */ 1498 1499 if (ourport->baudclk != clk) { 1500 clk_prepare_enable(clk); 1501 1502 s3c24xx_serial_setsource(port, clk_sel); 1503 1504 if (!IS_ERR(ourport->baudclk)) { 1505 clk_disable_unprepare(ourport->baudclk); 1506 ourport->baudclk = ERR_PTR(-EINVAL); 1507 } 1508 1509 ourport->baudclk = clk; 1510 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0; 1511 } 1512 1513 if (ourport->info->has_divslot) { 1514 unsigned int div = ourport->baudclk_rate / baud; 1515 1516 if (cfg->has_fracval) { 1517 udivslot = (div & 15); 1518 dev_dbg(port->dev, "fracval = %04x\n", udivslot); 1519 } else { 1520 udivslot = udivslot_table[div & 15]; 1521 dev_dbg(port->dev, "udivslot = %04x (div %d)\n", 1522 udivslot, div & 15); 1523 } 1524 } 1525 1526 switch (termios->c_cflag & CSIZE) { 1527 case CS5: 1528 dev_dbg(port->dev, "config: 5bits/char\n"); 1529 ulcon = S3C2410_LCON_CS5; 1530 break; 1531 case CS6: 1532 dev_dbg(port->dev, "config: 6bits/char\n"); 1533 ulcon = S3C2410_LCON_CS6; 1534 break; 1535 case CS7: 1536 dev_dbg(port->dev, "config: 7bits/char\n"); 1537 ulcon = S3C2410_LCON_CS7; 1538 break; 1539 case CS8: 1540 default: 1541 dev_dbg(port->dev, "config: 8bits/char\n"); 1542 ulcon = S3C2410_LCON_CS8; 1543 break; 1544 } 1545 1546 /* preserve original lcon IR settings */ 1547 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM); 1548 1549 if (termios->c_cflag & CSTOPB) 1550 ulcon |= S3C2410_LCON_STOPB; 1551 1552 if (termios->c_cflag & PARENB) { 1553 if (termios->c_cflag & PARODD) 1554 ulcon |= S3C2410_LCON_PODD; 1555 else 1556 ulcon |= S3C2410_LCON_PEVEN; 1557 } else { 1558 ulcon |= S3C2410_LCON_PNONE; 1559 } 1560 1561 uart_port_lock_irqsave(port, &flags); 1562 1563 dev_dbg(port->dev, 1564 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n", 1565 ulcon, quot, udivslot); 1566 1567 wr_regl(port, S3C2410_ULCON, ulcon); 1568 wr_regl(port, S3C2410_UBRDIV, quot); 1569 1570 port->status &= ~UPSTAT_AUTOCTS; 1571 1572 umcon = rd_regl(port, S3C2410_UMCON); 1573 if (termios->c_cflag & CRTSCTS) { 1574 umcon |= S3C2410_UMCOM_AFC; 1575 /* Disable RTS when RX FIFO contains 63 bytes */ 1576 umcon &= ~S3C2412_UMCON_AFC_8; 1577 port->status = UPSTAT_AUTOCTS; 1578 } else { 1579 umcon &= ~S3C2410_UMCOM_AFC; 1580 } 1581 wr_regl(port, S3C2410_UMCON, umcon); 1582 1583 if (ourport->info->has_divslot) 1584 wr_regl(port, S3C2443_DIVSLOT, udivslot); 1585 1586 dev_dbg(port->dev, 1587 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n", 1588 rd_regl(port, S3C2410_ULCON), 1589 rd_regl(port, S3C2410_UCON), 1590 rd_regl(port, S3C2410_UFCON)); 1591 1592 /* 1593 * Update the per-port timeout. 1594 */ 1595 uart_update_timeout(port, termios->c_cflag, baud); 1596 1597 /* 1598 * Which character status flags are we interested in? 1599 */ 1600 port->read_status_mask = S3C2410_UERSTAT_OVERRUN; 1601 if (termios->c_iflag & INPCK) 1602 port->read_status_mask |= S3C2410_UERSTAT_FRAME | 1603 S3C2410_UERSTAT_PARITY; 1604 /* 1605 * Which character status flags should we ignore? 1606 */ 1607 port->ignore_status_mask = 0; 1608 if (termios->c_iflag & IGNPAR) 1609 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN; 1610 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR) 1611 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME; 1612 1613 /* 1614 * Ignore all characters if CREAD is not set. 1615 */ 1616 if ((termios->c_cflag & CREAD) == 0) 1617 port->ignore_status_mask |= RXSTAT_DUMMY_READ; 1618 1619 uart_port_unlock_irqrestore(port, flags); 1620 } 1621 1622 static const char *s3c24xx_serial_type(struct uart_port *port) 1623 { 1624 const struct s3c24xx_uart_port *ourport = to_ourport(port); 1625 1626 switch (ourport->info->type) { 1627 case TYPE_S3C6400: 1628 return "S3C6400/10"; 1629 case TYPE_APPLE_S5L: 1630 return "APPLE S5L"; 1631 default: 1632 return NULL; 1633 } 1634 } 1635 1636 static void s3c24xx_serial_config_port(struct uart_port *port, int flags) 1637 { 1638 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1639 1640 if (flags & UART_CONFIG_TYPE) 1641 port->type = info->port_type; 1642 } 1643 1644 /* 1645 * verify the new serial_struct (for TIOCSSERIAL). 1646 */ 1647 static int 1648 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser) 1649 { 1650 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1651 1652 if (ser->type != PORT_UNKNOWN && ser->type != info->port_type) 1653 return -EINVAL; 1654 1655 return 0; 1656 } 1657 1658 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 1659 1660 static struct console s3c24xx_serial_console; 1661 1662 static void __init s3c24xx_serial_register_console(void) 1663 { 1664 register_console(&s3c24xx_serial_console); 1665 } 1666 1667 static void s3c24xx_serial_unregister_console(void) 1668 { 1669 if (console_is_registered(&s3c24xx_serial_console)) 1670 unregister_console(&s3c24xx_serial_console); 1671 } 1672 1673 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console 1674 #else 1675 static inline void s3c24xx_serial_register_console(void) { } 1676 static inline void s3c24xx_serial_unregister_console(void) { } 1677 #define S3C24XX_SERIAL_CONSOLE NULL 1678 #endif 1679 1680 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1681 static int s3c24xx_serial_get_poll_char(struct uart_port *port); 1682 static void s3c24xx_serial_put_poll_char(struct uart_port *port, 1683 unsigned char c); 1684 #endif 1685 1686 static const struct uart_ops s3c64xx_serial_ops = { 1687 .pm = s3c24xx_serial_pm, 1688 .tx_empty = s3c24xx_serial_tx_empty, 1689 .get_mctrl = s3c24xx_serial_get_mctrl, 1690 .set_mctrl = s3c24xx_serial_set_mctrl, 1691 .stop_tx = s3c24xx_serial_stop_tx, 1692 .start_tx = s3c24xx_serial_start_tx, 1693 .stop_rx = s3c24xx_serial_stop_rx, 1694 .break_ctl = s3c24xx_serial_break_ctl, 1695 .startup = s3c64xx_serial_startup, 1696 .shutdown = s3c64xx_serial_shutdown, 1697 .set_termios = s3c24xx_serial_set_termios, 1698 .type = s3c24xx_serial_type, 1699 .config_port = s3c24xx_serial_config_port, 1700 .verify_port = s3c24xx_serial_verify_port, 1701 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1702 .poll_get_char = s3c24xx_serial_get_poll_char, 1703 .poll_put_char = s3c24xx_serial_put_poll_char, 1704 #endif 1705 }; 1706 1707 static const struct uart_ops apple_s5l_serial_ops = { 1708 .pm = s3c24xx_serial_pm, 1709 .tx_empty = s3c24xx_serial_tx_empty, 1710 .get_mctrl = s3c24xx_serial_get_mctrl, 1711 .set_mctrl = s3c24xx_serial_set_mctrl, 1712 .stop_tx = s3c24xx_serial_stop_tx, 1713 .start_tx = s3c24xx_serial_start_tx, 1714 .stop_rx = s3c24xx_serial_stop_rx, 1715 .break_ctl = s3c24xx_serial_break_ctl, 1716 .startup = apple_s5l_serial_startup, 1717 .shutdown = apple_s5l_serial_shutdown, 1718 .set_termios = s3c24xx_serial_set_termios, 1719 .type = s3c24xx_serial_type, 1720 .config_port = s3c24xx_serial_config_port, 1721 .verify_port = s3c24xx_serial_verify_port, 1722 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1723 .poll_get_char = s3c24xx_serial_get_poll_char, 1724 .poll_put_char = s3c24xx_serial_put_poll_char, 1725 #endif 1726 }; 1727 1728 static struct uart_driver s3c24xx_uart_drv = { 1729 .owner = THIS_MODULE, 1730 .driver_name = "s3c2410_serial", 1731 .nr = UART_NR, 1732 .cons = S3C24XX_SERIAL_CONSOLE, 1733 .dev_name = S3C24XX_SERIAL_NAME, 1734 .major = S3C24XX_SERIAL_MAJOR, 1735 .minor = S3C24XX_SERIAL_MINOR, 1736 }; 1737 1738 static struct s3c24xx_uart_port s3c24xx_serial_ports[UART_NR]; 1739 1740 static void s3c24xx_serial_init_port_default(int index) 1741 { 1742 struct uart_port *port = &s3c24xx_serial_ports[index].port; 1743 1744 spin_lock_init(&port->lock); 1745 1746 port->uartclk = 0; 1747 port->fifosize = 16; 1748 port->flags = UPF_BOOT_AUTOCONF; 1749 port->line = index; 1750 } 1751 1752 /* s3c24xx_serial_resetport 1753 * 1754 * reset the fifos and other the settings. 1755 */ 1756 1757 static void s3c24xx_serial_resetport(struct uart_port *port, 1758 const struct s3c2410_uartcfg *cfg) 1759 { 1760 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1761 u32 ucon = rd_regl(port, S3C2410_UCON); 1762 1763 ucon &= (info->clksel_mask | info->ucon_mask); 1764 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); 1765 1766 /* reset both fifos */ 1767 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); 1768 wr_regl(port, S3C2410_UFCON, cfg->ufcon); 1769 1770 /* some delay is required after fifo reset */ 1771 udelay(1); 1772 } 1773 1774 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport) 1775 { 1776 struct device *dev = ourport->port.dev; 1777 const struct s3c24xx_uart_info *info = ourport->info; 1778 char clk_name[MAX_CLK_NAME_LENGTH]; 1779 struct clk *clk; 1780 int ret; 1781 u8 clk_sel, clk_num; 1782 1783 clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel; 1784 for (clk_num = 0; clk_num < info->num_clks; clk_num++) { 1785 if (!(clk_sel & (1 << clk_num))) 1786 continue; 1787 1788 sprintf(clk_name, "clk_uart_baud%d", clk_num); 1789 clk = clk_get(dev, clk_name); 1790 if (IS_ERR(clk)) 1791 continue; 1792 1793 ret = clk_prepare_enable(clk); 1794 if (ret) { 1795 clk_put(clk); 1796 continue; 1797 } 1798 1799 ourport->baudclk = clk; 1800 ourport->baudclk_rate = clk_get_rate(clk); 1801 s3c24xx_serial_setsource(&ourport->port, clk_num); 1802 1803 return 0; 1804 } 1805 1806 return -EINVAL; 1807 } 1808 1809 /* s3c24xx_serial_init_port 1810 * 1811 * initialise a single serial port from the platform device given 1812 */ 1813 1814 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, 1815 struct platform_device *platdev) 1816 { 1817 struct uart_port *port = &ourport->port; 1818 const struct s3c2410_uartcfg *cfg = ourport->cfg; 1819 struct resource *res; 1820 int ret; 1821 1822 if (platdev == NULL) 1823 return -ENODEV; 1824 1825 if (port->mapbase != 0) 1826 return -EINVAL; 1827 1828 /* setup info for port */ 1829 port->dev = &platdev->dev; 1830 1831 port->uartclk = 1; 1832 1833 if (cfg->uart_flags & UPF_CONS_FLOW) { 1834 dev_dbg(port->dev, "enabling flow control\n"); 1835 port->flags |= UPF_CONS_FLOW; 1836 } 1837 1838 /* sort our the physical and virtual addresses for each UART */ 1839 1840 res = platform_get_resource(platdev, IORESOURCE_MEM, 0); 1841 if (res == NULL) { 1842 dev_err(port->dev, "failed to find memory resource for uart\n"); 1843 return -EINVAL; 1844 } 1845 1846 dev_dbg(port->dev, "resource %pR)\n", res); 1847 1848 port->membase = devm_ioremap_resource(port->dev, res); 1849 if (IS_ERR(port->membase)) { 1850 dev_err(port->dev, "failed to remap controller address\n"); 1851 return -EBUSY; 1852 } 1853 1854 port->mapbase = res->start; 1855 ret = platform_get_irq(platdev, 0); 1856 if (ret < 0) { 1857 port->irq = 0; 1858 } else { 1859 port->irq = ret; 1860 ourport->rx_irq = ret; 1861 ourport->tx_irq = ret + 1; 1862 } 1863 1864 /* 1865 * DMA is currently supported only on DT platforms, if DMA properties 1866 * are specified. 1867 */ 1868 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node, 1869 "dmas", NULL)) { 1870 ourport->dma = devm_kzalloc(port->dev, 1871 sizeof(*ourport->dma), 1872 GFP_KERNEL); 1873 if (!ourport->dma) { 1874 ret = -ENOMEM; 1875 goto err; 1876 } 1877 } 1878 1879 ourport->clk = clk_get(&platdev->dev, "uart"); 1880 if (IS_ERR(ourport->clk)) { 1881 pr_err("%s: Controller clock not found\n", 1882 dev_name(&platdev->dev)); 1883 ret = PTR_ERR(ourport->clk); 1884 goto err; 1885 } 1886 1887 ret = clk_prepare_enable(ourport->clk); 1888 if (ret) { 1889 pr_err("uart: clock failed to prepare+enable: %d\n", ret); 1890 clk_put(ourport->clk); 1891 goto err; 1892 } 1893 1894 ret = s3c24xx_serial_enable_baudclk(ourport); 1895 if (ret) 1896 pr_warn("uart: failed to enable baudclk\n"); 1897 1898 /* Keep all interrupts masked and cleared */ 1899 switch (ourport->info->type) { 1900 case TYPE_S3C6400: 1901 wr_regl(port, S3C64XX_UINTM, 0xf); 1902 wr_regl(port, S3C64XX_UINTP, 0xf); 1903 wr_regl(port, S3C64XX_UINTSP, 0xf); 1904 break; 1905 case TYPE_APPLE_S5L: { 1906 u32 ucon; 1907 1908 ucon = rd_regl(port, S3C2410_UCON); 1909 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | 1910 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 1911 APPLE_S5L_UCON_RXTO_ENA_MSK); 1912 wr_regl(port, S3C2410_UCON, ucon); 1913 1914 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS); 1915 break; 1916 } 1917 default: 1918 break; 1919 } 1920 1921 dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n", 1922 &port->mapbase, port->membase, port->irq, 1923 ourport->rx_irq, ourport->tx_irq, port->uartclk); 1924 1925 /* reset the fifos (and setup the uart) */ 1926 s3c24xx_serial_resetport(port, cfg); 1927 1928 return 0; 1929 1930 err: 1931 port->mapbase = 0; 1932 return ret; 1933 } 1934 1935 /* Device driver serial port probe */ 1936 1937 static int probe_index; 1938 1939 static inline const struct s3c24xx_serial_drv_data * 1940 s3c24xx_get_driver_data(struct platform_device *pdev) 1941 { 1942 if (dev_of_node(&pdev->dev)) 1943 return of_device_get_match_data(&pdev->dev); 1944 1945 return (struct s3c24xx_serial_drv_data *) 1946 platform_get_device_id(pdev)->driver_data; 1947 } 1948 1949 static int s3c24xx_serial_probe(struct platform_device *pdev) 1950 { 1951 struct device_node *np = pdev->dev.of_node; 1952 struct s3c24xx_uart_port *ourport; 1953 int index = probe_index; 1954 int ret, prop = 0, fifosize_prop = 1; 1955 1956 if (np) { 1957 ret = of_alias_get_id(np, "serial"); 1958 if (ret >= 0) 1959 index = ret; 1960 } 1961 1962 if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) { 1963 dev_err(&pdev->dev, "serial%d out of range\n", index); 1964 return -EINVAL; 1965 } 1966 ourport = &s3c24xx_serial_ports[index]; 1967 1968 s3c24xx_serial_init_port_default(index); 1969 1970 ourport->drv_data = s3c24xx_get_driver_data(pdev); 1971 if (!ourport->drv_data) { 1972 dev_err(&pdev->dev, "could not find driver data\n"); 1973 return -ENODEV; 1974 } 1975 1976 ourport->baudclk = ERR_PTR(-EINVAL); 1977 ourport->info = &ourport->drv_data->info; 1978 ourport->cfg = (dev_get_platdata(&pdev->dev)) ? 1979 dev_get_platdata(&pdev->dev) : 1980 &ourport->drv_data->def_cfg; 1981 1982 switch (ourport->info->type) { 1983 case TYPE_S3C6400: 1984 ourport->port.ops = &s3c64xx_serial_ops; 1985 break; 1986 case TYPE_APPLE_S5L: 1987 ourport->port.ops = &apple_s5l_serial_ops; 1988 break; 1989 } 1990 1991 ourport->port.iotype = ourport->info->iotype; 1992 1993 if (np) { 1994 fifosize_prop = of_property_read_u32(np, "samsung,uart-fifosize", 1995 &ourport->port.fifosize); 1996 1997 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) { 1998 switch (prop) { 1999 case 1: 2000 ourport->port.iotype = UPIO_MEM; 2001 break; 2002 case 4: 2003 ourport->port.iotype = UPIO_MEM32; 2004 break; 2005 default: 2006 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n", 2007 prop); 2008 return -EINVAL; 2009 } 2010 } 2011 } 2012 2013 if (fifosize_prop) { 2014 if (ourport->drv_data->fifosize[index]) 2015 ourport->port.fifosize = ourport->drv_data->fifosize[index]; 2016 else if (ourport->info->fifosize) 2017 ourport->port.fifosize = ourport->info->fifosize; 2018 } 2019 2020 ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE); 2021 2022 /* 2023 * DMA transfers must be aligned at least to cache line size, 2024 * so find minimal transfer size suitable for DMA mode 2025 */ 2026 ourport->min_dma_size = max_t(int, ourport->port.fifosize, 2027 dma_get_cache_alignment()); 2028 2029 dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport); 2030 2031 ret = s3c24xx_serial_init_port(ourport, pdev); 2032 if (ret < 0) 2033 return ret; 2034 2035 if (!s3c24xx_uart_drv.state) { 2036 ret = uart_register_driver(&s3c24xx_uart_drv); 2037 if (ret < 0) { 2038 pr_err("Failed to register Samsung UART driver\n"); 2039 return ret; 2040 } 2041 } 2042 2043 dev_dbg(&pdev->dev, "%s: adding port\n", __func__); 2044 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port); 2045 platform_set_drvdata(pdev, &ourport->port); 2046 2047 /* 2048 * Deactivate the clock enabled in s3c24xx_serial_init_port here, 2049 * so that a potential re-enablement through the pm-callback overlaps 2050 * and keeps the clock enabled in this case. 2051 */ 2052 clk_disable_unprepare(ourport->clk); 2053 if (!IS_ERR(ourport->baudclk)) 2054 clk_disable_unprepare(ourport->baudclk); 2055 2056 probe_index++; 2057 2058 return 0; 2059 } 2060 2061 static void s3c24xx_serial_remove(struct platform_device *dev) 2062 { 2063 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); 2064 2065 if (port) 2066 uart_remove_one_port(&s3c24xx_uart_drv, port); 2067 2068 uart_unregister_driver(&s3c24xx_uart_drv); 2069 } 2070 2071 /* UART power management code */ 2072 #ifdef CONFIG_PM_SLEEP 2073 static int s3c24xx_serial_suspend(struct device *dev) 2074 { 2075 struct uart_port *port = s3c24xx_dev_to_port(dev); 2076 2077 if (port) 2078 uart_suspend_port(&s3c24xx_uart_drv, port); 2079 2080 return 0; 2081 } 2082 2083 static int s3c24xx_serial_resume(struct device *dev) 2084 { 2085 struct uart_port *port = s3c24xx_dev_to_port(dev); 2086 struct s3c24xx_uart_port *ourport = to_ourport(port); 2087 2088 if (port) { 2089 clk_prepare_enable(ourport->clk); 2090 if (!IS_ERR(ourport->baudclk)) 2091 clk_prepare_enable(ourport->baudclk); 2092 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port)); 2093 if (!IS_ERR(ourport->baudclk)) 2094 clk_disable_unprepare(ourport->baudclk); 2095 clk_disable_unprepare(ourport->clk); 2096 2097 uart_resume_port(&s3c24xx_uart_drv, port); 2098 } 2099 2100 return 0; 2101 } 2102 2103 static int s3c24xx_serial_resume_noirq(struct device *dev) 2104 { 2105 struct uart_port *port = s3c24xx_dev_to_port(dev); 2106 struct s3c24xx_uart_port *ourport = to_ourport(port); 2107 2108 if (port) { 2109 /* restore IRQ mask */ 2110 switch (ourport->info->type) { 2111 case TYPE_S3C6400: { 2112 u32 uintm = 0xf; 2113 2114 if (ourport->tx_enabled) 2115 uintm &= ~S3C64XX_UINTM_TXD_MSK; 2116 if (ourport->rx_enabled) 2117 uintm &= ~S3C64XX_UINTM_RXD_MSK; 2118 clk_prepare_enable(ourport->clk); 2119 if (!IS_ERR(ourport->baudclk)) 2120 clk_prepare_enable(ourport->baudclk); 2121 wr_regl(port, S3C64XX_UINTM, uintm); 2122 if (!IS_ERR(ourport->baudclk)) 2123 clk_disable_unprepare(ourport->baudclk); 2124 clk_disable_unprepare(ourport->clk); 2125 break; 2126 } 2127 case TYPE_APPLE_S5L: { 2128 u32 ucon; 2129 int ret; 2130 2131 ret = clk_prepare_enable(ourport->clk); 2132 if (ret) { 2133 dev_err(dev, "clk_enable clk failed: %d\n", ret); 2134 return ret; 2135 } 2136 if (!IS_ERR(ourport->baudclk)) { 2137 ret = clk_prepare_enable(ourport->baudclk); 2138 if (ret) { 2139 dev_err(dev, "clk_enable baudclk failed: %d\n", ret); 2140 clk_disable_unprepare(ourport->clk); 2141 return ret; 2142 } 2143 } 2144 2145 ucon = rd_regl(port, S3C2410_UCON); 2146 2147 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | 2148 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 2149 APPLE_S5L_UCON_RXTO_ENA_MSK); 2150 2151 if (ourport->tx_enabled) 2152 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK; 2153 if (ourport->rx_enabled) 2154 ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 2155 APPLE_S5L_UCON_RXTO_ENA_MSK; 2156 2157 wr_regl(port, S3C2410_UCON, ucon); 2158 2159 if (!IS_ERR(ourport->baudclk)) 2160 clk_disable_unprepare(ourport->baudclk); 2161 clk_disable_unprepare(ourport->clk); 2162 break; 2163 } 2164 default: 2165 break; 2166 } 2167 } 2168 2169 return 0; 2170 } 2171 2172 static const struct dev_pm_ops s3c24xx_serial_pm_ops = { 2173 SET_SYSTEM_SLEEP_PM_OPS(s3c24xx_serial_suspend, s3c24xx_serial_resume) 2174 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, s3c24xx_serial_resume_noirq) 2175 }; 2176 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops) 2177 2178 #else /* !CONFIG_PM_SLEEP */ 2179 2180 #define SERIAL_SAMSUNG_PM_OPS NULL 2181 #endif /* CONFIG_PM_SLEEP */ 2182 2183 /* Console code */ 2184 2185 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 2186 2187 static struct uart_port *cons_uart; 2188 2189 static bool 2190 s3c24xx_serial_console_txrdy(struct uart_port *port, u32 ufcon) 2191 { 2192 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 2193 u32 ufstat, utrstat; 2194 2195 if (ufcon & S3C2410_UFCON_FIFOMODE) { 2196 /* fifo mode - check amount of data in fifo registers... */ 2197 2198 ufstat = rd_regl(port, S3C2410_UFSTAT); 2199 return !(ufstat & info->tx_fifofull); 2200 } 2201 2202 /* in non-fifo mode, we go and use the tx buffer empty */ 2203 2204 utrstat = rd_regl(port, S3C2410_UTRSTAT); 2205 return utrstat & S3C2410_UTRSTAT_TXE; 2206 } 2207 2208 static bool 2209 s3c24xx_port_configured(u32 ucon) 2210 { 2211 /* consider the serial port configured if the tx/rx mode set */ 2212 return (ucon & 0xf) != 0; 2213 } 2214 2215 #ifdef CONFIG_CONSOLE_POLL 2216 /* 2217 * Console polling routines for writing and reading from the uart while 2218 * in an interrupt or debug context. 2219 */ 2220 2221 static int s3c24xx_serial_get_poll_char(struct uart_port *port) 2222 { 2223 const struct s3c24xx_uart_port *ourport = to_ourport(port); 2224 u32 ufstat; 2225 2226 ufstat = rd_regl(port, S3C2410_UFSTAT); 2227 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0) 2228 return NO_POLL_CHAR; 2229 2230 return rd_reg(port, S3C2410_URXH); 2231 } 2232 2233 static void s3c24xx_serial_put_poll_char(struct uart_port *port, 2234 unsigned char c) 2235 { 2236 u32 ufcon = rd_regl(port, S3C2410_UFCON); 2237 u32 ucon = rd_regl(port, S3C2410_UCON); 2238 2239 /* not possible to xmit on unconfigured port */ 2240 if (!s3c24xx_port_configured(ucon)) 2241 return; 2242 2243 while (!s3c24xx_serial_console_txrdy(port, ufcon)) 2244 cpu_relax(); 2245 wr_reg(port, S3C2410_UTXH, c); 2246 } 2247 2248 #endif /* CONFIG_CONSOLE_POLL */ 2249 2250 static void 2251 s3c24xx_serial_console_putchar(struct uart_port *port, unsigned char ch) 2252 { 2253 u32 ufcon = rd_regl(port, S3C2410_UFCON); 2254 2255 while (!s3c24xx_serial_console_txrdy(port, ufcon)) 2256 cpu_relax(); 2257 wr_reg(port, S3C2410_UTXH, ch); 2258 } 2259 2260 static void 2261 s3c24xx_serial_console_write(struct console *co, const char *s, 2262 unsigned int count) 2263 { 2264 u32 ucon = rd_regl(cons_uart, S3C2410_UCON); 2265 unsigned long flags; 2266 bool locked = true; 2267 2268 /* not possible to xmit on unconfigured port */ 2269 if (!s3c24xx_port_configured(ucon)) 2270 return; 2271 2272 if (cons_uart->sysrq) 2273 locked = false; 2274 else if (oops_in_progress) 2275 locked = uart_port_trylock_irqsave(cons_uart, &flags); 2276 else 2277 uart_port_lock_irqsave(cons_uart, &flags); 2278 2279 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar); 2280 2281 if (locked) 2282 uart_port_unlock_irqrestore(cons_uart, flags); 2283 } 2284 2285 /* Shouldn't be __init, as it can be instantiated from other module */ 2286 static void 2287 s3c24xx_serial_get_options(struct uart_port *port, int *baud, 2288 int *parity, int *bits) 2289 { 2290 struct clk *clk; 2291 unsigned long rate; 2292 u32 ulcon, ucon, ubrdiv; 2293 char clk_name[MAX_CLK_NAME_LENGTH]; 2294 u8 clk_sel; 2295 2296 ulcon = rd_regl(port, S3C2410_ULCON); 2297 ucon = rd_regl(port, S3C2410_UCON); 2298 ubrdiv = rd_regl(port, S3C2410_UBRDIV); 2299 2300 if (s3c24xx_port_configured(ucon)) { 2301 switch (ulcon & S3C2410_LCON_CSMASK) { 2302 case S3C2410_LCON_CS5: 2303 *bits = 5; 2304 break; 2305 case S3C2410_LCON_CS6: 2306 *bits = 6; 2307 break; 2308 case S3C2410_LCON_CS7: 2309 *bits = 7; 2310 break; 2311 case S3C2410_LCON_CS8: 2312 default: 2313 *bits = 8; 2314 break; 2315 } 2316 2317 switch (ulcon & S3C2410_LCON_PMASK) { 2318 case S3C2410_LCON_PEVEN: 2319 *parity = 'e'; 2320 break; 2321 2322 case S3C2410_LCON_PODD: 2323 *parity = 'o'; 2324 break; 2325 2326 case S3C2410_LCON_PNONE: 2327 default: 2328 *parity = 'n'; 2329 } 2330 2331 /* now calculate the baud rate */ 2332 2333 clk_sel = s3c24xx_serial_getsource(port); 2334 sprintf(clk_name, "clk_uart_baud%d", clk_sel); 2335 2336 clk = clk_get(port->dev, clk_name); 2337 if (!IS_ERR(clk)) 2338 rate = clk_get_rate(clk); 2339 else 2340 rate = 1; 2341 2342 *baud = rate / (16 * (ubrdiv + 1)); 2343 dev_dbg(port->dev, "calculated baud %d\n", *baud); 2344 } 2345 } 2346 2347 /* Shouldn't be __init, as it can be instantiated from other module */ 2348 static int 2349 s3c24xx_serial_console_setup(struct console *co, char *options) 2350 { 2351 struct uart_port *port; 2352 int baud = 9600; 2353 int bits = 8; 2354 int parity = 'n'; 2355 int flow = 'n'; 2356 2357 /* is this a valid port */ 2358 2359 if (co->index == -1 || co->index >= UART_NR) 2360 co->index = 0; 2361 2362 port = &s3c24xx_serial_ports[co->index].port; 2363 2364 /* is the port configured? */ 2365 2366 if (port->mapbase == 0x0) 2367 return -ENODEV; 2368 2369 cons_uart = port; 2370 2371 /* 2372 * Check whether an invalid uart number has been specified, and 2373 * if so, search for the first available port that does have 2374 * console support. 2375 */ 2376 if (options) 2377 uart_parse_options(options, &baud, &parity, &bits, &flow); 2378 else 2379 s3c24xx_serial_get_options(port, &baud, &parity, &bits); 2380 2381 dev_dbg(port->dev, "baud %d\n", baud); 2382 2383 return uart_set_options(port, co, baud, parity, bits, flow); 2384 } 2385 2386 static struct console s3c24xx_serial_console = { 2387 .name = S3C24XX_SERIAL_NAME, 2388 .device = uart_console_device, 2389 .flags = CON_PRINTBUFFER, 2390 .index = -1, 2391 .write = s3c24xx_serial_console_write, 2392 .setup = s3c24xx_serial_console_setup, 2393 .data = &s3c24xx_uart_drv, 2394 }; 2395 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */ 2396 2397 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) 2398 static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = { 2399 .info = { 2400 .name = "Samsung S3C6400 UART", 2401 .type = TYPE_S3C6400, 2402 .port_type = PORT_S3C6400, 2403 .iotype = UPIO_MEM, 2404 .fifosize = 64, 2405 .has_divslot = true, 2406 .rx_fifomask = S3C2440_UFSTAT_RXMASK, 2407 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, 2408 .rx_fifofull = S3C2440_UFSTAT_RXFULL, 2409 .tx_fifofull = S3C2440_UFSTAT_TXFULL, 2410 .tx_fifomask = S3C2440_UFSTAT_TXMASK, 2411 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, 2412 .def_clk_sel = S3C2410_UCON_CLKSEL2, 2413 .num_clks = 4, 2414 .clksel_mask = S3C6400_UCON_CLKMASK, 2415 .clksel_shift = S3C6400_UCON_CLKSHIFT, 2416 }, 2417 .def_cfg = { 2418 .ucon = S3C2410_UCON_DEFAULT, 2419 .ufcon = S3C2410_UFCON_DEFAULT, 2420 }, 2421 }; 2422 #define S3C6400_SERIAL_DRV_DATA (&s3c6400_serial_drv_data) 2423 #else 2424 #define S3C6400_SERIAL_DRV_DATA NULL 2425 #endif 2426 2427 #ifdef CONFIG_CPU_S5PV210 2428 static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { 2429 .info = { 2430 .name = "Samsung S5PV210 UART", 2431 .type = TYPE_S3C6400, 2432 .port_type = PORT_S3C6400, 2433 .iotype = UPIO_MEM, 2434 .has_divslot = true, 2435 .rx_fifomask = S5PV210_UFSTAT_RXMASK, 2436 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, 2437 .rx_fifofull = S5PV210_UFSTAT_RXFULL, 2438 .tx_fifofull = S5PV210_UFSTAT_TXFULL, 2439 .tx_fifomask = S5PV210_UFSTAT_TXMASK, 2440 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, 2441 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2442 .num_clks = 2, 2443 .clksel_mask = S5PV210_UCON_CLKMASK, 2444 .clksel_shift = S5PV210_UCON_CLKSHIFT, 2445 }, 2446 .def_cfg = { 2447 .ucon = S5PV210_UCON_DEFAULT, 2448 .ufcon = S5PV210_UFCON_DEFAULT, 2449 }, 2450 .fifosize = { 256, 64, 16, 16 }, 2451 }; 2452 #define S5PV210_SERIAL_DRV_DATA (&s5pv210_serial_drv_data) 2453 #else 2454 #define S5PV210_SERIAL_DRV_DATA NULL 2455 #endif 2456 2457 #if defined(CONFIG_ARCH_EXYNOS) 2458 #define EXYNOS_COMMON_SERIAL_DRV_DATA \ 2459 .info = { \ 2460 .name = "Samsung Exynos UART", \ 2461 .type = TYPE_S3C6400, \ 2462 .port_type = PORT_S3C6400, \ 2463 .iotype = UPIO_MEM, \ 2464 .has_divslot = true, \ 2465 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ 2466 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \ 2467 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \ 2468 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \ 2469 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \ 2470 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \ 2471 .def_clk_sel = S3C2410_UCON_CLKSEL0, \ 2472 .num_clks = 1, \ 2473 .clksel_mask = 0, \ 2474 .clksel_shift = 0, \ 2475 }, \ 2476 .def_cfg = { \ 2477 .ucon = S5PV210_UCON_DEFAULT, \ 2478 .ufcon = S5PV210_UFCON_DEFAULT, \ 2479 .has_fracval = 1, \ 2480 } \ 2481 2482 static const struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = { 2483 EXYNOS_COMMON_SERIAL_DRV_DATA, 2484 .fifosize = { 256, 64, 16, 16 }, 2485 }; 2486 2487 static const struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = { 2488 EXYNOS_COMMON_SERIAL_DRV_DATA, 2489 .fifosize = { 64, 256, 16, 256 }, 2490 }; 2491 2492 static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = { 2493 EXYNOS_COMMON_SERIAL_DRV_DATA, 2494 .fifosize = { 256, 64, 64, 64 }, 2495 }; 2496 2497 static const struct s3c24xx_serial_drv_data gs101_serial_drv_data = { 2498 .info = { 2499 .name = "Google GS101 UART", 2500 .type = TYPE_S3C6400, 2501 .port_type = PORT_S3C6400, 2502 .iotype = UPIO_MEM32, 2503 .has_divslot = true, 2504 .rx_fifomask = S5PV210_UFSTAT_RXMASK, 2505 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, 2506 .rx_fifofull = S5PV210_UFSTAT_RXFULL, 2507 .tx_fifofull = S5PV210_UFSTAT_TXFULL, 2508 .tx_fifomask = S5PV210_UFSTAT_TXMASK, 2509 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, 2510 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2511 .num_clks = 1, 2512 .clksel_mask = 0, 2513 .clksel_shift = 0, 2514 }, 2515 .def_cfg = { 2516 .ucon = S5PV210_UCON_DEFAULT, 2517 .ufcon = S5PV210_UFCON_DEFAULT, 2518 .has_fracval = 1, 2519 }, 2520 /* samsung,uart-fifosize must be specified in the device tree. */ 2521 .fifosize = { 0 }, 2522 }; 2523 2524 #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data) 2525 #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data) 2526 #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data) 2527 #define GS101_SERIAL_DRV_DATA (&gs101_serial_drv_data) 2528 2529 #else 2530 #define EXYNOS4210_SERIAL_DRV_DATA NULL 2531 #define EXYNOS5433_SERIAL_DRV_DATA NULL 2532 #define EXYNOS850_SERIAL_DRV_DATA NULL 2533 #define GS101_SERIAL_DRV_DATA NULL 2534 #endif 2535 2536 #ifdef CONFIG_ARCH_APPLE 2537 static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = { 2538 .info = { 2539 .name = "Apple S5L UART", 2540 .type = TYPE_APPLE_S5L, 2541 .port_type = PORT_8250, 2542 .iotype = UPIO_MEM, 2543 .fifosize = 16, 2544 .rx_fifomask = S3C2410_UFSTAT_RXMASK, 2545 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT, 2546 .rx_fifofull = S3C2410_UFSTAT_RXFULL, 2547 .tx_fifofull = S3C2410_UFSTAT_TXFULL, 2548 .tx_fifomask = S3C2410_UFSTAT_TXMASK, 2549 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT, 2550 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2551 .num_clks = 1, 2552 .clksel_mask = 0, 2553 .clksel_shift = 0, 2554 .ucon_mask = APPLE_S5L_UCON_MASK, 2555 }, 2556 .def_cfg = { 2557 .ucon = APPLE_S5L_UCON_DEFAULT, 2558 .ufcon = S3C2410_UFCON_DEFAULT, 2559 }, 2560 }; 2561 #define S5L_SERIAL_DRV_DATA (&s5l_serial_drv_data) 2562 #else 2563 #define S5L_SERIAL_DRV_DATA NULL 2564 #endif 2565 2566 #if defined(CONFIG_ARCH_ARTPEC) 2567 static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = { 2568 .info = { 2569 .name = "Axis ARTPEC-8 UART", 2570 .type = TYPE_S3C6400, 2571 .port_type = PORT_S3C6400, 2572 .iotype = UPIO_MEM, 2573 .fifosize = 64, 2574 .has_divslot = true, 2575 .rx_fifomask = S5PV210_UFSTAT_RXMASK, 2576 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, 2577 .rx_fifofull = S5PV210_UFSTAT_RXFULL, 2578 .tx_fifofull = S5PV210_UFSTAT_TXFULL, 2579 .tx_fifomask = S5PV210_UFSTAT_TXMASK, 2580 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, 2581 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2582 .num_clks = 1, 2583 .clksel_mask = 0, 2584 .clksel_shift = 0, 2585 }, 2586 .def_cfg = { 2587 .ucon = S5PV210_UCON_DEFAULT, 2588 .ufcon = S5PV210_UFCON_DEFAULT, 2589 .has_fracval = 1, 2590 } 2591 }; 2592 #define ARTPEC8_SERIAL_DRV_DATA (&artpec8_serial_drv_data) 2593 #else 2594 #define ARTPEC8_SERIAL_DRV_DATA (NULL) 2595 #endif 2596 2597 static const struct platform_device_id s3c24xx_serial_driver_ids[] = { 2598 { 2599 .name = "s3c6400-uart", 2600 .driver_data = (kernel_ulong_t)S3C6400_SERIAL_DRV_DATA, 2601 }, { 2602 .name = "s5pv210-uart", 2603 .driver_data = (kernel_ulong_t)S5PV210_SERIAL_DRV_DATA, 2604 }, { 2605 .name = "exynos4210-uart", 2606 .driver_data = (kernel_ulong_t)EXYNOS4210_SERIAL_DRV_DATA, 2607 }, { 2608 .name = "exynos5433-uart", 2609 .driver_data = (kernel_ulong_t)EXYNOS5433_SERIAL_DRV_DATA, 2610 }, { 2611 .name = "s5l-uart", 2612 .driver_data = (kernel_ulong_t)S5L_SERIAL_DRV_DATA, 2613 }, { 2614 .name = "exynos850-uart", 2615 .driver_data = (kernel_ulong_t)EXYNOS850_SERIAL_DRV_DATA, 2616 }, { 2617 .name = "artpec8-uart", 2618 .driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA, 2619 }, { 2620 .name = "gs101-uart", 2621 .driver_data = (kernel_ulong_t)GS101_SERIAL_DRV_DATA, 2622 }, 2623 { }, 2624 }; 2625 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids); 2626 2627 #ifdef CONFIG_OF 2628 static const struct of_device_id s3c24xx_uart_dt_match[] = { 2629 { .compatible = "samsung,s3c6400-uart", 2630 .data = S3C6400_SERIAL_DRV_DATA }, 2631 { .compatible = "samsung,s5pv210-uart", 2632 .data = S5PV210_SERIAL_DRV_DATA }, 2633 { .compatible = "samsung,exynos4210-uart", 2634 .data = EXYNOS4210_SERIAL_DRV_DATA }, 2635 { .compatible = "samsung,exynos5433-uart", 2636 .data = EXYNOS5433_SERIAL_DRV_DATA }, 2637 { .compatible = "apple,s5l-uart", 2638 .data = S5L_SERIAL_DRV_DATA }, 2639 { .compatible = "samsung,exynos850-uart", 2640 .data = EXYNOS850_SERIAL_DRV_DATA }, 2641 { .compatible = "axis,artpec8-uart", 2642 .data = ARTPEC8_SERIAL_DRV_DATA }, 2643 { .compatible = "google,gs101-uart", 2644 .data = GS101_SERIAL_DRV_DATA }, 2645 {}, 2646 }; 2647 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); 2648 #endif 2649 2650 static struct platform_driver samsung_serial_driver = { 2651 .probe = s3c24xx_serial_probe, 2652 .remove_new = s3c24xx_serial_remove, 2653 .id_table = s3c24xx_serial_driver_ids, 2654 .driver = { 2655 .name = "samsung-uart", 2656 .pm = SERIAL_SAMSUNG_PM_OPS, 2657 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match), 2658 }, 2659 }; 2660 2661 static int __init samsung_serial_init(void) 2662 { 2663 int ret; 2664 2665 s3c24xx_serial_register_console(); 2666 2667 ret = platform_driver_register(&samsung_serial_driver); 2668 if (ret) { 2669 s3c24xx_serial_unregister_console(); 2670 return ret; 2671 } 2672 2673 return 0; 2674 } 2675 2676 static void __exit samsung_serial_exit(void) 2677 { 2678 platform_driver_unregister(&samsung_serial_driver); 2679 s3c24xx_serial_unregister_console(); 2680 } 2681 2682 module_init(samsung_serial_init); 2683 module_exit(samsung_serial_exit); 2684 2685 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 2686 /* 2687 * Early console. 2688 */ 2689 2690 static void wr_reg_barrier(const struct uart_port *port, u32 reg, u32 val) 2691 { 2692 switch (port->iotype) { 2693 case UPIO_MEM: 2694 writeb(val, portaddr(port, reg)); 2695 break; 2696 case UPIO_MEM32: 2697 writel(val, portaddr(port, reg)); 2698 break; 2699 } 2700 } 2701 2702 struct samsung_early_console_data { 2703 u32 txfull_mask; 2704 u32 rxfifo_mask; 2705 }; 2706 2707 static void samsung_early_busyuart(const struct uart_port *port) 2708 { 2709 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE)) 2710 ; 2711 } 2712 2713 static void samsung_early_busyuart_fifo(const struct uart_port *port) 2714 { 2715 const struct samsung_early_console_data *data = port->private_data; 2716 2717 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask) 2718 ; 2719 } 2720 2721 static void samsung_early_putc(struct uart_port *port, unsigned char c) 2722 { 2723 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) 2724 samsung_early_busyuart_fifo(port); 2725 else 2726 samsung_early_busyuart(port); 2727 2728 wr_reg_barrier(port, S3C2410_UTXH, c); 2729 } 2730 2731 static void samsung_early_write(struct console *con, const char *s, 2732 unsigned int n) 2733 { 2734 struct earlycon_device *dev = con->data; 2735 2736 uart_console_write(&dev->port, s, n, samsung_early_putc); 2737 } 2738 2739 static int samsung_early_read(struct console *con, char *s, unsigned int n) 2740 { 2741 struct earlycon_device *dev = con->data; 2742 const struct samsung_early_console_data *data = dev->port.private_data; 2743 int num_read = 0; 2744 u32 ch, ufstat; 2745 2746 while (num_read < n) { 2747 ufstat = rd_regl(&dev->port, S3C2410_UFSTAT); 2748 if (!(ufstat & data->rxfifo_mask)) 2749 break; 2750 ch = rd_reg(&dev->port, S3C2410_URXH); 2751 if (ch == NO_POLL_CHAR) 2752 break; 2753 2754 s[num_read++] = ch; 2755 } 2756 2757 return num_read; 2758 } 2759 2760 static int __init samsung_early_console_setup(struct earlycon_device *device, 2761 const char *opt) 2762 { 2763 if (!device->port.membase) 2764 return -ENODEV; 2765 2766 device->con->write = samsung_early_write; 2767 device->con->read = samsung_early_read; 2768 return 0; 2769 } 2770 2771 /* S3C2410 */ 2772 static struct samsung_early_console_data s3c2410_early_console_data = { 2773 .txfull_mask = S3C2410_UFSTAT_TXFULL, 2774 .rxfifo_mask = S3C2410_UFSTAT_RXFULL | S3C2410_UFSTAT_RXMASK, 2775 }; 2776 2777 /* S3C64xx */ 2778 static struct samsung_early_console_data s3c2440_early_console_data = { 2779 .txfull_mask = S3C2440_UFSTAT_TXFULL, 2780 .rxfifo_mask = S3C2440_UFSTAT_RXFULL | S3C2440_UFSTAT_RXMASK, 2781 }; 2782 2783 static int __init s3c2440_early_console_setup(struct earlycon_device *device, 2784 const char *opt) 2785 { 2786 device->port.private_data = &s3c2440_early_console_data; 2787 return samsung_early_console_setup(device, opt); 2788 } 2789 2790 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart", 2791 s3c2440_early_console_setup); 2792 2793 /* S5PV210, Exynos */ 2794 static struct samsung_early_console_data s5pv210_early_console_data = { 2795 .txfull_mask = S5PV210_UFSTAT_TXFULL, 2796 .rxfifo_mask = S5PV210_UFSTAT_RXFULL | S5PV210_UFSTAT_RXMASK, 2797 }; 2798 2799 static int __init s5pv210_early_console_setup(struct earlycon_device *device, 2800 const char *opt) 2801 { 2802 device->port.private_data = &s5pv210_early_console_data; 2803 return samsung_early_console_setup(device, opt); 2804 } 2805 2806 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart", 2807 s5pv210_early_console_setup); 2808 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart", 2809 s5pv210_early_console_setup); 2810 OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart", 2811 s5pv210_early_console_setup); 2812 2813 static int __init gs101_early_console_setup(struct earlycon_device *device, 2814 const char *opt) 2815 { 2816 /* gs101 always expects MMIO32 register accesses. */ 2817 device->port.iotype = UPIO_MEM32; 2818 2819 return s5pv210_early_console_setup(device, opt); 2820 } 2821 2822 OF_EARLYCON_DECLARE(gs101, "google,gs101-uart", gs101_early_console_setup); 2823 2824 /* Apple S5L */ 2825 static int __init apple_s5l_early_console_setup(struct earlycon_device *device, 2826 const char *opt) 2827 { 2828 /* Close enough to S3C2410 for earlycon... */ 2829 device->port.private_data = &s3c2410_early_console_data; 2830 2831 #ifdef CONFIG_ARM64 2832 /* ... but we need to override the existing fixmap entry as nGnRnE */ 2833 __set_fixmap(FIX_EARLYCON_MEM_BASE, device->port.mapbase, 2834 __pgprot(PROT_DEVICE_nGnRnE)); 2835 #endif 2836 return samsung_early_console_setup(device, opt); 2837 } 2838 2839 OF_EARLYCON_DECLARE(s5l, "apple,s5l-uart", apple_s5l_early_console_setup); 2840 #endif 2841 2842 MODULE_ALIAS("platform:samsung-uart"); 2843 MODULE_DESCRIPTION("Samsung SoC Serial port driver"); 2844 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); 2845 MODULE_LICENSE("GPL v2"); 2846