1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2025 Renesas Electronics Corp. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/bitops.h> 8 #include <linux/io.h> 9 #include <linux/iopoll.h> 10 #include <linux/module.h> 11 #include <linux/serial_core.h> 12 #include <linux/serial_sci.h> 13 #include <linux/tty_flip.h> 14 15 #include "serial_mctrl_gpio.h" 16 #include "rsci.h" 17 18 MODULE_IMPORT_NS("SH_SCI"); 19 20 /* RSCI registers */ 21 #define RDR 0x00 22 #define TDR 0x04 23 #define CCR0 0x08 24 #define CCR1 0x0C 25 #define CCR2 0x10 26 #define CCR3 0x14 27 #define CCR4 0x18 28 #define FCR 0x24 29 #define CSR 0x48 30 #define FRSR 0x50 31 #define FTSR 0x54 32 #define CFCLR 0x68 33 #define FFCLR 0x70 34 35 /* RDR (Receive Data Register) */ 36 #define RDR_FFER BIT(12) /* FIFO Framing Error */ 37 #define RDR_FPER BIT(11) /* FIFO Parity Error */ 38 #define RDR_RDAT_MSK GENMASK(8, 0) 39 40 /* CCR0 (Common Control Register 0) */ 41 #define CCR0_SSE BIT(24) /* SSn# Pin Function Enable */ 42 #define CCR0_TEIE BIT(21) /* Transmit End Interrupt Enable */ 43 #define CCR0_TIE BIT(20) /* Transmit Interrupt Enable */ 44 #define CCR0_RIE BIT(16) /* Receive Interrupt Enable */ 45 #define CCR0_IDSEL BIT(10) /* ID Frame Select */ 46 #define CCR0_DCME BIT(9) /* Data Compare Match Enable */ 47 #define CCR0_MPIE BIT(8) /* Multiprocessor Interrupt Enable */ 48 #define CCR0_TE BIT(4) /* Transmit Enable */ 49 #define CCR0_RE BIT(0) /* Receive Enable */ 50 51 /* CCR1 (Common Control Register 1) */ 52 #define CCR1_NFEN BIT(28) /* Digital Noise Filter Function */ 53 #define CCR1_SHARPS BIT(20) /* Half -duplex Communication Select */ 54 #define CCR1_SPLP BIT(16) /* Loopback Control */ 55 #define CCR1_RINV BIT(13) /* RxD invert */ 56 #define CCR1_TINV BIT(12) /* TxD invert */ 57 #define CCR1_PM BIT(9) /* Parity Mode */ 58 #define CCR1_PE BIT(8) /* Parity Enable */ 59 #define CCR1_SPB2IO BIT(5) /* Serial Port Break I/O */ 60 #define CCR1_SPB2DT BIT(4) /* Serial Port Break Data Select */ 61 #define CCR1_CTSPEN BIT(1) /* CTS External Pin Enable */ 62 #define CCR1_CTSE BIT(0) /* CTS Enable */ 63 64 /* CCR2 (Common Control Register 2) */ 65 #define CCR2_INIT 0xFF000004 66 #define CCR2_CKS_TCLK (0) /* TCLK clock */ 67 #define CCR2_CKS_TCLK_DIV4 BIT(20) /* TCLK/4 clock */ 68 #define CCR2_CKS_TCLK_DIV16 BIT(21) /* TCLK16 clock */ 69 #define CCR2_CKS_TCLK_DIV64 (BIT(21) | BIT(20)) /* TCLK/64 clock */ 70 #define CCR2_BRME BIT(16) /* Bitrate Modulation Enable */ 71 #define CCR2_ABCSE BIT(6) /* Asynchronous Mode Extended Base Clock Select */ 72 #define CCR2_ABCS BIT(5) /* Asynchronous Mode Base Clock Select */ 73 #define CCR2_BGDM BIT(4) /* Baud Rate Generator Double-Speed Mode Select */ 74 75 /* CCR3 (Common Control Register 3) */ 76 #define CCR3_INIT 0x1203 77 #define CCR3_BLK BIT(29) /* Block Transfer Mode */ 78 #define CCR3_GM BIT(28) /* GSM Mode */ 79 #define CCR3_CKE1 BIT(25) /* Clock Enable 1 */ 80 #define CCR3_CKE0 BIT(24) /* Clock Enable 0 */ 81 #define CCR3_DEN BIT(21) /* Driver Enabled */ 82 #define CCR3_FM BIT(20) /* FIFO Mode Select */ 83 #define CCR3_MP BIT(19) /* Multi-Processor Mode */ 84 #define CCR3_MOD_ASYNC 0 /* Asynchronous mode (Multi-processor mode) */ 85 #define CCR3_MOD_IRDA BIT(16) /* Smart card interface mode */ 86 #define CCR3_MOD_CLK_SYNC BIT(17) /* Clock synchronous mode */ 87 #define CCR3_MOD_SPI (BIT(17) | BIT(16)) /* Simple SPI mode */ 88 #define CCR3_MOD_I2C BIT(18) /* Simple I2C mode */ 89 #define CCR3_RXDESEL BIT(15) /* Asynchronous Start Bit Edge Detection Select */ 90 #define CCR3_STP BIT(14) /* Stop bit Length */ 91 #define CCR3_SINV BIT(13) /* Transmitted/Received Data Invert */ 92 #define CCR3_LSBF BIT(12) /* LSB First select */ 93 #define CCR3_CHR1 BIT(9) /* Character Length */ 94 #define CCR3_CHR0 BIT(8) /* Character Length */ 95 #define CCR3_BPEN BIT(7) /* Synchronizer Bypass Enable */ 96 #define CCR3_CPOL BIT(1) /* Clock Polarity Select */ 97 #define CCR3_CPHA BIT(0) /* Clock Phase Select */ 98 99 /* FCR (FIFO Control Register) */ 100 #define FCR_RFRST BIT(23) /* Receive FIFO Data Register Reset */ 101 #define FCR_TFRST BIT(15) /* Transmit FIFO Data Register Reset */ 102 #define FCR_DRES BIT(0) /* Incoming Data Ready Error Select */ 103 #define FCR_RTRG4_0 GENMASK(20, 16) 104 #define FCR_TTRG GENMASK(12, 8) 105 106 /* CSR (Common Status Register) */ 107 #define CSR_RDRF BIT(31) /* Receive Data Full */ 108 #define CSR_TEND BIT(30) /* Transmit End Flag */ 109 #define CSR_TDRE BIT(29) /* Transmit Data Empty */ 110 #define CSR_FER BIT(28) /* Framing Error */ 111 #define CSR_PER BIT(27) /* Parity Error */ 112 #define CSR_MFF BIT(26) /* Mode Fault Error */ 113 #define CSR_ORER BIT(24) /* Overrun Error */ 114 #define CSR_DFER BIT(18) /* Data Compare Match Framing Error */ 115 #define CSR_DPER BIT(17) /* Data Compare Match Parity Error */ 116 #define CSR_DCMF BIT(16) /* Data Compare Match */ 117 #define CSR_RXDMON BIT(15) /* Serial Input Data Monitor */ 118 #define CSR_ERS BIT(4) /* Error Signal Status */ 119 120 #define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask) 121 #define SCxSR_ERROR_CLEAR(port) (to_sci_port(port)->params->error_clear) 122 123 #define RSCI_DEFAULT_ERROR_MASK (CSR_PER | CSR_FER) 124 125 #define RSCI_RDxF_CLEAR (CFCLR_RDRFC) 126 #define RSCI_ERROR_CLEAR (CFCLR_PERC | CFCLR_FERC) 127 #define RSCI_TDxE_CLEAR (CFCLR_TDREC) 128 #define RSCI_BREAK_CLEAR (CFCLR_PERC | CFCLR_FERC | CFCLR_ORERC) 129 130 /* FRSR (FIFO Receive Status Register) */ 131 #define FRSR_R5_0 GENMASK(13, 8) /* Receive FIFO Data Count */ 132 #define FRSR_DR BIT(0) /* Receive Data Ready */ 133 134 /* CFCLR (Common Flag CLear Register) */ 135 #define CFCLR_RDRFC BIT(31) /* RDRF Clear */ 136 #define CFCLR_TDREC BIT(29) /* TDRE Clear */ 137 #define CFCLR_FERC BIT(28) /* FER Clear */ 138 #define CFCLR_PERC BIT(27) /* PER Clear */ 139 #define CFCLR_MFFC BIT(26) /* MFF Clear */ 140 #define CFCLR_ORERC BIT(24) /* ORER Clear */ 141 #define CFCLR_DFERC BIT(18) /* DFER Clear */ 142 #define CFCLR_DPERC BIT(17) /* DPER Clear */ 143 #define CFCLR_DCMFC BIT(16) /* DCMF Clear */ 144 #define CFCLR_ERSC BIT(4) /* ERS Clear */ 145 #define CFCLR_CLRFLAG (CFCLR_RDRFC | CFCLR_FERC | CFCLR_PERC | \ 146 CFCLR_MFFC | CFCLR_ORERC | CFCLR_DFERC | \ 147 CFCLR_DPERC | CFCLR_DCMFC | CFCLR_ERSC) 148 149 /* FFCLR (FIFO Flag CLear Register) */ 150 #define FFCLR_DRC BIT(0) /* DR Clear */ 151 152 static u32 rsci_serial_in(struct uart_port *p, int offset) 153 { 154 return readl(p->membase + offset); 155 } 156 157 static void rsci_serial_out(struct uart_port *p, int offset, int value) 158 { 159 writel(value, p->membase + offset); 160 } 161 162 static void rsci_clear_DRxC(struct uart_port *port) 163 { 164 rsci_serial_out(port, CFCLR, CFCLR_RDRFC); 165 rsci_serial_out(port, FFCLR, FFCLR_DRC); 166 } 167 168 169 static void rsci_start_rx(struct uart_port *port) 170 { 171 unsigned int ctrl; 172 173 ctrl = rsci_serial_in(port, CCR0); 174 ctrl |= CCR0_RIE; 175 rsci_serial_out(port, CCR0, ctrl); 176 } 177 178 static void rsci_enable_ms(struct uart_port *port) 179 { 180 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 181 } 182 183 static void rsci_init_pins(struct uart_port *port, unsigned int cflag) 184 { 185 struct sci_port *s = to_sci_port(port); 186 187 /* Use port-specific handler if provided */ 188 if (s->cfg->ops && s->cfg->ops->init_pins) { 189 s->cfg->ops->init_pins(port, cflag); 190 return; 191 } 192 193 if (!s->has_rtscts) 194 return; 195 196 if (s->autorts) 197 rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | 198 CCR1_CTSE | CCR1_CTSPEN); 199 } 200 201 static int rsci_scif_set_rtrg(struct uart_port *port, int rx_trig) 202 { 203 u32 fcr = rsci_serial_in(port, FCR); 204 205 if (rx_trig >= port->fifosize) 206 rx_trig = port->fifosize - 1; 207 else if (rx_trig < 1) 208 rx_trig = 0; 209 210 FIELD_MODIFY(FCR_RTRG4_0, &fcr, rx_trig); 211 rsci_serial_out(port, FCR, fcr); 212 213 return rx_trig; 214 } 215 216 static void rsci_set_termios(struct uart_port *port, struct ktermios *termios, 217 const struct ktermios *old) 218 { 219 unsigned int ccr2_val = CCR2_INIT, ccr3_val = CCR3_INIT; 220 unsigned int ccr0_val = 0, ccr1_val = 0, ccr4_val = 0; 221 unsigned int brr1 = 255, cks1 = 0, srr1 = 15; 222 struct sci_port *s = to_sci_port(port); 223 unsigned int brr = 255, cks = 0; 224 int min_err = INT_MAX, err; 225 unsigned long max_freq = 0; 226 unsigned int baud, i; 227 unsigned long flags; 228 unsigned int ctrl; 229 int best_clk = -1; 230 231 if ((termios->c_cflag & CSIZE) == CS7) { 232 ccr3_val |= CCR3_CHR0; 233 } else { 234 termios->c_cflag &= ~CSIZE; 235 termios->c_cflag |= CS8; 236 } 237 238 if (termios->c_cflag & PARENB) 239 ccr1_val |= CCR1_PE; 240 241 if (termios->c_cflag & PARODD) 242 ccr1_val |= (CCR1_PE | CCR1_PM); 243 244 if (termios->c_cflag & CSTOPB) 245 ccr3_val |= CCR3_STP; 246 247 /* Enable noise filter function */ 248 ccr1_val |= CCR1_NFEN; 249 250 /* 251 * earlyprintk comes here early on with port->uartclk set to zero. 252 * the clock framework is not up and running at this point so here 253 * we assume that 115200 is the maximum baud rate. please note that 254 * the baud rate is not programmed during earlyprintk - it is assumed 255 * that the previous boot loader has enabled required clocks and 256 * setup the baud rate generator hardware for us already. 257 */ 258 if (!port->uartclk) { 259 max_freq = 115200; 260 } else { 261 for (i = 0; i < SCI_NUM_CLKS; i++) 262 max_freq = max(max_freq, s->clk_rates[i]); 263 264 max_freq /= min_sr(s); 265 } 266 267 baud = uart_get_baud_rate(port, termios, old, 0, max_freq); 268 269 /* Divided Functional Clock using standard Bit Rate Register */ 270 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 271 if (abs(err) < abs(min_err)) { 272 best_clk = SCI_FCK; 273 ccr0_val = 0; 274 min_err = err; 275 brr = brr1; 276 cks = cks1; 277 } 278 279 if (best_clk >= 0) 280 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 281 s->clks[best_clk], baud, min_err); 282 283 sci_port_enable(s); 284 uart_port_lock_irqsave(port, &flags); 285 286 uart_update_timeout(port, termios->c_cflag, baud); 287 288 rsci_serial_out(port, CCR0, ccr0_val); 289 290 ccr3_val |= CCR3_FM; 291 rsci_serial_out(port, CCR3, ccr3_val); 292 293 ccr2_val |= (cks << 20) | (brr << 8); 294 rsci_serial_out(port, CCR2, ccr2_val); 295 296 rsci_serial_out(port, CCR1, ccr1_val); 297 rsci_serial_out(port, CCR4, ccr4_val); 298 299 ctrl = rsci_serial_in(port, FCR); 300 ctrl |= (FCR_RFRST | FCR_TFRST); 301 rsci_serial_out(port, FCR, ctrl); 302 303 if (s->rx_trigger > 1) 304 rsci_scif_set_rtrg(port, s->rx_trigger); 305 306 port->status &= ~UPSTAT_AUTOCTS; 307 s->autorts = false; 308 309 if ((port->flags & UPF_HARD_FLOW) && (termios->c_cflag & CRTSCTS)) { 310 port->status |= UPSTAT_AUTOCTS; 311 s->autorts = true; 312 } 313 314 rsci_init_pins(port, termios->c_cflag); 315 rsci_serial_out(port, CFCLR, CFCLR_CLRFLAG); 316 rsci_serial_out(port, FFCLR, FFCLR_DRC); 317 318 ccr0_val |= CCR0_RE; 319 rsci_serial_out(port, CCR0, ccr0_val); 320 321 if ((termios->c_cflag & CREAD) != 0) 322 rsci_start_rx(port); 323 324 uart_port_unlock_irqrestore(port, flags); 325 sci_port_disable(s); 326 327 if (UART_ENABLE_MS(port, termios->c_cflag)) 328 rsci_enable_ms(port); 329 } 330 331 static int rsci_txfill(struct uart_port *port) 332 { 333 return rsci_serial_in(port, FTSR); 334 } 335 336 static int rsci_rxfill(struct uart_port *port) 337 { 338 u32 val = rsci_serial_in(port, FRSR); 339 340 return FIELD_GET(FRSR_R5_0, val); 341 } 342 343 static unsigned int rsci_tx_empty(struct uart_port *port) 344 { 345 unsigned int status = rsci_serial_in(port, CSR); 346 unsigned int in_tx_fifo = rsci_txfill(port); 347 348 return (status & CSR_TEND) && !in_tx_fifo ? TIOCSER_TEMT : 0; 349 } 350 351 static void rsci_set_mctrl(struct uart_port *port, unsigned int mctrl) 352 { 353 if (mctrl & TIOCM_LOOP) { 354 /* Standard loopback mode */ 355 rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | CCR1_SPLP); 356 } 357 } 358 359 static unsigned int rsci_get_mctrl(struct uart_port *port) 360 { 361 struct sci_port *s = to_sci_port(port); 362 struct mctrl_gpios *gpios = s->gpios; 363 unsigned int mctrl = 0; 364 365 mctrl_gpio_get(gpios, &mctrl); 366 367 /* 368 * CTS/RTS is handled in hardware when supported, while nothing 369 * else is wired up. 370 */ 371 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) 372 mctrl |= TIOCM_CTS; 373 374 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 375 mctrl |= TIOCM_DSR; 376 377 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 378 mctrl |= TIOCM_CAR; 379 380 return mctrl; 381 } 382 383 static void rsci_clear_CFC(struct uart_port *port, unsigned int mask) 384 { 385 rsci_serial_out(port, CFCLR, mask); 386 } 387 388 static void rsci_start_tx(struct uart_port *port) 389 { 390 struct sci_port *sp = to_sci_port(port); 391 u32 ctrl; 392 393 if (sp->chan_tx) 394 return; 395 396 /* 397 * TE (Transmit Enable) must be set after setting TIE 398 * (Transmit Interrupt Enable) or in the same instruction 399 * to start the transmit process. 400 */ 401 ctrl = rsci_serial_in(port, CCR0); 402 ctrl |= CCR0_TIE | CCR0_TE; 403 rsci_serial_out(port, CCR0, ctrl); 404 } 405 406 static void rsci_stop_tx(struct uart_port *port) 407 { 408 u32 ctrl; 409 410 ctrl = rsci_serial_in(port, CCR0); 411 ctrl &= ~CCR0_TIE; 412 rsci_serial_out(port, CCR0, ctrl); 413 } 414 415 static void rsci_stop_rx(struct uart_port *port) 416 { 417 u32 ctrl; 418 419 ctrl = rsci_serial_in(port, CCR0); 420 ctrl &= ~CCR0_RIE; 421 rsci_serial_out(port, CCR0, ctrl); 422 } 423 424 static int rsci_txroom(struct uart_port *port) 425 { 426 return port->fifosize - rsci_txfill(port); 427 } 428 429 static void rsci_transmit_chars(struct uart_port *port) 430 { 431 unsigned int stopped = uart_tx_stopped(port); 432 struct tty_port *tport = &port->state->port; 433 u32 status, ctrl; 434 int count; 435 436 status = rsci_serial_in(port, CSR); 437 if (!(status & CSR_TDRE)) { 438 ctrl = rsci_serial_in(port, CCR0); 439 if (kfifo_is_empty(&tport->xmit_fifo)) 440 ctrl &= ~CCR0_TIE; 441 else 442 ctrl |= CCR0_TIE; 443 rsci_serial_out(port, CCR0, ctrl); 444 return; 445 } 446 447 count = rsci_txroom(port); 448 449 do { 450 unsigned char c; 451 452 if (port->x_char) { 453 c = port->x_char; 454 port->x_char = 0; 455 } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) { 456 break; 457 } 458 459 rsci_clear_CFC(port, CFCLR_TDREC); 460 rsci_serial_out(port, TDR, c); 461 462 port->icount.tx++; 463 } while (--count > 0); 464 465 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 466 uart_write_wakeup(port); 467 468 if (kfifo_is_empty(&tport->xmit_fifo)) { 469 ctrl = rsci_serial_in(port, CCR0); 470 ctrl &= ~CCR0_TIE; 471 ctrl |= CCR0_TEIE; 472 rsci_serial_out(port, CCR0, ctrl); 473 } 474 } 475 476 static void rsci_receive_chars(struct uart_port *port) 477 { 478 struct tty_port *tport = &port->state->port; 479 u32 rdat, status, frsr_status = 0; 480 int i, count, copied = 0; 481 unsigned char flag; 482 483 status = rsci_serial_in(port, CSR); 484 frsr_status = rsci_serial_in(port, FRSR); 485 486 if (!(status & CSR_RDRF) && !(frsr_status & FRSR_DR)) 487 return; 488 489 while (1) { 490 /* Don't copy more bytes than there is room for in the buffer */ 491 count = tty_buffer_request_room(tport, rsci_rxfill(port)); 492 493 /* If for any reason we can't copy more data, we're done! */ 494 if (count == 0) 495 break; 496 497 for (i = 0; i < count; i++) { 498 char c; 499 500 rdat = rsci_serial_in(port, RDR); 501 /* 9-bits data is not supported yet */ 502 c = rdat & RDR_RDAT_MSK; 503 504 if (uart_handle_sysrq_char(port, c)) { 505 count--; 506 i--; 507 continue; 508 } 509 510 /* 511 * Store data and status. 512 * Non FIFO mode is not supported 513 */ 514 if (rdat & RDR_FFER) { 515 flag = TTY_FRAME; 516 port->icount.frame++; 517 } else if (rdat & RDR_FPER) { 518 flag = TTY_PARITY; 519 port->icount.parity++; 520 } else { 521 flag = TTY_NORMAL; 522 } 523 524 tty_insert_flip_char(tport, c, flag); 525 } 526 527 rsci_serial_in(port, CSR); /* dummy read */ 528 rsci_clear_DRxC(port); 529 530 copied += count; 531 port->icount.rx += count; 532 } 533 534 if (copied) { 535 /* Tell the rest of the system the news. New characters! */ 536 tty_flip_buffer_push(tport); 537 } else { 538 /* TTY buffers full; read from RX reg to prevent lockup */ 539 rsci_serial_in(port, RDR); 540 rsci_serial_in(port, CSR); /* dummy read */ 541 rsci_clear_DRxC(port); 542 } 543 } 544 545 static void rsci_break_ctl(struct uart_port *port, int break_state) 546 { 547 unsigned short ccr0_val, ccr1_val; 548 unsigned long flags; 549 550 uart_port_lock_irqsave(port, &flags); 551 ccr1_val = rsci_serial_in(port, CCR1); 552 ccr0_val = rsci_serial_in(port, CCR0); 553 554 if (break_state == -1) { 555 ccr1_val = (ccr1_val | CCR1_SPB2IO) & ~CCR1_SPB2DT; 556 ccr0_val &= ~CCR0_TE; 557 } else { 558 ccr1_val = (ccr1_val | CCR1_SPB2DT) & ~CCR1_SPB2IO; 559 ccr0_val |= CCR0_TE; 560 } 561 562 rsci_serial_out(port, CCR1, ccr1_val); 563 rsci_serial_out(port, CCR0, ccr0_val); 564 uart_port_unlock_irqrestore(port, flags); 565 } 566 567 static void rsci_poll_put_char(struct uart_port *port, unsigned char c) 568 { 569 u32 status; 570 int ret; 571 572 ret = readl_relaxed_poll_timeout_atomic(port->membase + CSR, status, 573 (status & CSR_TDRE), 100, 574 USEC_PER_SEC); 575 if (ret != 0) { 576 dev_err(port->dev, 577 "Error while sending data in UART TX : %d\n", ret); 578 goto done; 579 } 580 rsci_serial_out(port, TDR, c); 581 done: 582 rsci_clear_CFC(port, CFCLR_TDREC); 583 } 584 585 static void rsci_prepare_console_write(struct uart_port *port, u32 ctrl) 586 { 587 struct sci_port *s = to_sci_port(port); 588 u32 ctrl_temp = s->params->param_bits->rxtx_enable; 589 590 if (s->type == RSCI_PORT_SCIF16) 591 ctrl_temp |= CCR0_TIE | s->hscif_tot; 592 593 rsci_serial_out(port, CCR0, ctrl_temp); 594 } 595 596 static void rsci_finish_console_write(struct uart_port *port, u32 ctrl) 597 { 598 /* First set TE = 0 and then restore the CCR0 value */ 599 rsci_serial_out(port, CCR0, ctrl & ~CCR0_TE); 600 rsci_serial_out(port, CCR0, ctrl); 601 } 602 603 static const char *rsci_type(struct uart_port *port) 604 { 605 return "rsci"; 606 } 607 608 static size_t rsci_suspend_regs_size(void) 609 { 610 return 0; 611 } 612 613 static void rsci_shutdown_complete(struct uart_port *port) 614 { 615 /* 616 * Stop RX and TX, disable related interrupts, keep clock source 617 */ 618 rsci_serial_out(port, CCR0, 0); 619 } 620 621 static const struct sci_common_regs rsci_common_regs = { 622 .status = CSR, 623 .control = CCR0, 624 }; 625 626 static const struct sci_port_params_bits rsci_port_param_bits = { 627 .rxtx_enable = CCR0_RE | CCR0_TE, 628 .te_clear = CCR0_TE | CCR0_TEIE, 629 .poll_sent_bits = CSR_TDRE | CSR_TEND, 630 }; 631 632 static const struct sci_port_params rsci_rzg3e_port_params = { 633 .fifosize = 32, 634 .overrun_reg = CSR, 635 .overrun_mask = CSR_ORER, 636 .sampling_rate_mask = SCI_SR(32), 637 .error_mask = RSCI_DEFAULT_ERROR_MASK, 638 .error_clear = RSCI_ERROR_CLEAR, 639 .param_bits = &rsci_port_param_bits, 640 .common_regs = &rsci_common_regs, 641 }; 642 643 static const struct sci_port_params rsci_rzt2h_port_params = { 644 .fifosize = 16, 645 .overrun_reg = CSR, 646 .overrun_mask = CSR_ORER, 647 .sampling_rate_mask = SCI_SR(32), 648 .error_mask = RSCI_DEFAULT_ERROR_MASK, 649 .error_clear = RSCI_ERROR_CLEAR, 650 .param_bits = &rsci_port_param_bits, 651 .common_regs = &rsci_common_regs, 652 }; 653 654 static const struct uart_ops rsci_uart_ops = { 655 .tx_empty = rsci_tx_empty, 656 .set_mctrl = rsci_set_mctrl, 657 .get_mctrl = rsci_get_mctrl, 658 .start_tx = rsci_start_tx, 659 .stop_tx = rsci_stop_tx, 660 .stop_rx = rsci_stop_rx, 661 .enable_ms = rsci_enable_ms, 662 .break_ctl = rsci_break_ctl, 663 .startup = sci_startup, 664 .shutdown = sci_shutdown, 665 .set_termios = rsci_set_termios, 666 .pm = sci_pm, 667 .type = rsci_type, 668 .release_port = sci_release_port, 669 .request_port = sci_request_port, 670 .config_port = sci_config_port, 671 .verify_port = sci_verify_port, 672 }; 673 674 static const struct sci_port_ops rsci_port_ops = { 675 .read_reg = rsci_serial_in, 676 .write_reg = rsci_serial_out, 677 .clear_SCxSR = rsci_clear_CFC, 678 .transmit_chars = rsci_transmit_chars, 679 .receive_chars = rsci_receive_chars, 680 .poll_put_char = rsci_poll_put_char, 681 .prepare_console_write = rsci_prepare_console_write, 682 .finish_console_write = rsci_finish_console_write, 683 .suspend_regs_size = rsci_suspend_regs_size, 684 .set_rtrg = rsci_scif_set_rtrg, 685 .shutdown_complete = rsci_shutdown_complete, 686 }; 687 688 struct sci_of_data of_rsci_rzg3e_data = { 689 .type = RSCI_PORT_SCIF32, 690 .ops = &rsci_port_ops, 691 .uart_ops = &rsci_uart_ops, 692 .params = &rsci_rzg3e_port_params, 693 }; 694 695 struct sci_of_data of_rsci_rzg3l_data = { 696 .type = RSCI_PORT_SCIF32_SINGLE_TCLK, 697 .ops = &rsci_port_ops, 698 .uart_ops = &rsci_uart_ops, 699 .params = &rsci_rzg3e_port_params, 700 }; 701 702 struct sci_of_data of_rsci_rzt2h_data = { 703 .type = RSCI_PORT_SCIF16, 704 .ops = &rsci_port_ops, 705 .uart_ops = &rsci_uart_ops, 706 .params = &rsci_rzt2h_port_params, 707 }; 708 709 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 710 static int __init rsci_rzg3l_early_console_setup(struct earlycon_device *device, 711 const char *opt) 712 { 713 return scix_early_console_setup(device, &of_rsci_rzg3l_data); 714 } 715 716 static int __init rsci_rzg3e_early_console_setup(struct earlycon_device *device, 717 const char *opt) 718 { 719 return scix_early_console_setup(device, &of_rsci_rzg3e_data); 720 } 721 722 static int __init rsci_rzt2h_early_console_setup(struct earlycon_device *device, 723 const char *opt) 724 { 725 return scix_early_console_setup(device, &of_rsci_rzt2h_data); 726 } 727 728 OF_EARLYCON_DECLARE(rsci, "renesas,r9a08g046-rsci", rsci_rzg3l_early_console_setup); 729 OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rsci", rsci_rzg3e_early_console_setup); 730 OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_rzt2h_early_console_setup); 731 732 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 733 734 MODULE_LICENSE("GPL"); 735 MODULE_DESCRIPTION("RSCI serial driver"); 736