1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2025 Renesas Electronics Corp. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/bitops.h> 8 #include <linux/io.h> 9 #include <linux/iopoll.h> 10 #include <linux/module.h> 11 #include <linux/serial_core.h> 12 #include <linux/serial_sci.h> 13 #include <linux/tty_flip.h> 14 15 #include "serial_mctrl_gpio.h" 16 #include "rsci.h" 17 18 MODULE_IMPORT_NS("SH_SCI"); 19 20 /* RSCI registers */ 21 #define RDR 0x00 22 #define TDR 0x04 23 #define CCR0 0x08 24 #define CCR1 0x0C 25 #define CCR2 0x10 26 #define CCR3 0x14 27 #define CCR4 0x18 28 #define FCR 0x24 29 #define CSR 0x48 30 #define FRSR 0x50 31 #define FTSR 0x54 32 #define CFCLR 0x68 33 #define FFCLR 0x70 34 35 /* RDR (Receive Data Register) */ 36 #define RDR_FFER BIT(12) /* FIFO Framing Error */ 37 #define RDR_FPER BIT(11) /* FIFO Parity Error */ 38 #define RDR_RDAT_MSK GENMASK(8, 0) 39 40 /* CCR0 (Common Control Register 0) */ 41 #define CCR0_SSE BIT(24) /* SSn# Pin Function Enable */ 42 #define CCR0_TEIE BIT(21) /* Transmit End Interrupt Enable */ 43 #define CCR0_TIE BIT(20) /* Transmit Interrupt Enable */ 44 #define CCR0_RIE BIT(16) /* Receive Interrupt Enable */ 45 #define CCR0_IDSEL BIT(10) /* ID Frame Select */ 46 #define CCR0_DCME BIT(9) /* Data Compare Match Enable */ 47 #define CCR0_MPIE BIT(8) /* Multiprocessor Interrupt Enable */ 48 #define CCR0_TE BIT(4) /* Transmit Enable */ 49 #define CCR0_RE BIT(0) /* Receive Enable */ 50 51 /* CCR1 (Common Control Register 1) */ 52 #define CCR1_NFEN BIT(28) /* Digital Noise Filter Function */ 53 #define CCR1_SHARPS BIT(20) /* Half -duplex Communication Select */ 54 #define CCR1_SPLP BIT(16) /* Loopback Control */ 55 #define CCR1_RINV BIT(13) /* RxD invert */ 56 #define CCR1_TINV BIT(12) /* TxD invert */ 57 #define CCR1_PM BIT(9) /* Parity Mode */ 58 #define CCR1_PE BIT(8) /* Parity Enable */ 59 #define CCR1_SPB2IO BIT(5) /* Serial Port Break I/O */ 60 #define CCR1_SPB2DT BIT(4) /* Serial Port Break Data Select */ 61 #define CCR1_CTSPEN BIT(1) /* CTS External Pin Enable */ 62 #define CCR1_CTSE BIT(0) /* CTS Enable */ 63 64 /* CCR2 (Common Control Register 2) */ 65 #define CCR2_INIT 0xFF000004 66 #define CCR2_CKS_TCLK (0) /* TCLK clock */ 67 #define CCR2_CKS_TCLK_DIV4 BIT(20) /* TCLK/4 clock */ 68 #define CCR2_CKS_TCLK_DIV16 BIT(21) /* TCLK16 clock */ 69 #define CCR2_CKS_TCLK_DIV64 (BIT(21) | BIT(20)) /* TCLK/64 clock */ 70 #define CCR2_BRME BIT(16) /* Bitrate Modulation Enable */ 71 #define CCR2_ABCSE BIT(6) /* Asynchronous Mode Extended Base Clock Select */ 72 #define CCR2_ABCS BIT(5) /* Asynchronous Mode Base Clock Select */ 73 #define CCR2_BGDM BIT(4) /* Baud Rate Generator Double-Speed Mode Select */ 74 75 /* CCR3 (Common Control Register 3) */ 76 #define CCR3_INIT 0x1203 77 #define CCR3_BLK BIT(29) /* Block Transfer Mode */ 78 #define CCR3_GM BIT(28) /* GSM Mode */ 79 #define CCR3_CKE1 BIT(25) /* Clock Enable 1 */ 80 #define CCR3_CKE0 BIT(24) /* Clock Enable 0 */ 81 #define CCR3_DEN BIT(21) /* Driver Enabled */ 82 #define CCR3_FM BIT(20) /* FIFO Mode Select */ 83 #define CCR3_MP BIT(19) /* Multi-Processor Mode */ 84 #define CCR3_MOD_ASYNC 0 /* Asynchronous mode (Multi-processor mode) */ 85 #define CCR3_MOD_IRDA BIT(16) /* Smart card interface mode */ 86 #define CCR3_MOD_CLK_SYNC BIT(17) /* Clock synchronous mode */ 87 #define CCR3_MOD_SPI (BIT(17) | BIT(16)) /* Simple SPI mode */ 88 #define CCR3_MOD_I2C BIT(18) /* Simple I2C mode */ 89 #define CCR3_RXDESEL BIT(15) /* Asynchronous Start Bit Edge Detection Select */ 90 #define CCR3_STP BIT(14) /* Stop bit Length */ 91 #define CCR3_SINV BIT(13) /* Transmitted/Received Data Invert */ 92 #define CCR3_LSBF BIT(12) /* LSB First select */ 93 #define CCR3_CHR1 BIT(9) /* Character Length */ 94 #define CCR3_CHR0 BIT(8) /* Character Length */ 95 #define CCR3_BPEN BIT(7) /* Synchronizer Bypass Enable */ 96 #define CCR3_CPOL BIT(1) /* Clock Polarity Select */ 97 #define CCR3_CPHA BIT(0) /* Clock Phase Select */ 98 99 /* FCR (FIFO Control Register) */ 100 #define FCR_RFRST BIT(23) /* Receive FIFO Data Register Reset */ 101 #define FCR_TFRST BIT(15) /* Transmit FIFO Data Register Reset */ 102 #define FCR_DRES BIT(0) /* Incoming Data Ready Error Select */ 103 #define FCR_RTRG4_0 GENMASK(20, 16) 104 #define FCR_TTRG GENMASK(12, 8) 105 106 /* CSR (Common Status Register) */ 107 #define CSR_RDRF BIT(31) /* Receive Data Full */ 108 #define CSR_TEND BIT(30) /* Transmit End Flag */ 109 #define CSR_TDRE BIT(29) /* Transmit Data Empty */ 110 #define CSR_FER BIT(28) /* Framing Error */ 111 #define CSR_PER BIT(27) /* Parity Error */ 112 #define CSR_MFF BIT(26) /* Mode Fault Error */ 113 #define CSR_ORER BIT(24) /* Overrun Error */ 114 #define CSR_DFER BIT(18) /* Data Compare Match Framing Error */ 115 #define CSR_DPER BIT(17) /* Data Compare Match Parity Error */ 116 #define CSR_DCMF BIT(16) /* Data Compare Match */ 117 #define CSR_RXDMON BIT(15) /* Serial Input Data Monitor */ 118 #define CSR_ERS BIT(4) /* Error Signal Status */ 119 120 #define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask) 121 #define SCxSR_ERROR_CLEAR(port) (to_sci_port(port)->params->error_clear) 122 123 #define RSCI_DEFAULT_ERROR_MASK (CSR_PER | CSR_FER) 124 125 #define RSCI_RDxF_CLEAR (CFCLR_RDRFC) 126 #define RSCI_ERROR_CLEAR (CFCLR_PERC | CFCLR_FERC) 127 #define RSCI_TDxE_CLEAR (CFCLR_TDREC) 128 #define RSCI_BREAK_CLEAR (CFCLR_PERC | CFCLR_FERC | CFCLR_ORERC) 129 130 /* FRSR (FIFO Receive Status Register) */ 131 #define FRSR_R5_0 GENMASK(13, 8) /* Receive FIFO Data Count */ 132 #define FRSR_DR BIT(0) /* Receive Data Ready */ 133 134 /* CFCLR (Common Flag CLear Register) */ 135 #define CFCLR_RDRFC BIT(31) /* RDRF Clear */ 136 #define CFCLR_TDREC BIT(29) /* TDRE Clear */ 137 #define CFCLR_FERC BIT(28) /* FER Clear */ 138 #define CFCLR_PERC BIT(27) /* PER Clear */ 139 #define CFCLR_MFFC BIT(26) /* MFF Clear */ 140 #define CFCLR_ORERC BIT(24) /* ORER Clear */ 141 #define CFCLR_DFERC BIT(18) /* DFER Clear */ 142 #define CFCLR_DPERC BIT(17) /* DPER Clear */ 143 #define CFCLR_DCMFC BIT(16) /* DCMF Clear */ 144 #define CFCLR_ERSC BIT(4) /* ERS Clear */ 145 #define CFCLR_CLRFLAG (CFCLR_RDRFC | CFCLR_FERC | CFCLR_PERC | \ 146 CFCLR_MFFC | CFCLR_ORERC | CFCLR_DFERC | \ 147 CFCLR_DPERC | CFCLR_DCMFC | CFCLR_ERSC) 148 149 /* FFCLR (FIFO Flag CLear Register) */ 150 #define FFCLR_DRC BIT(0) /* DR Clear */ 151 152 static u32 rsci_serial_in(struct uart_port *p, int offset) 153 { 154 return readl(p->membase + offset); 155 } 156 157 static void rsci_serial_out(struct uart_port *p, int offset, int value) 158 { 159 writel(value, p->membase + offset); 160 } 161 162 static void rsci_clear_DRxC(struct uart_port *port) 163 { 164 rsci_serial_out(port, CFCLR, CFCLR_RDRFC); 165 rsci_serial_out(port, FFCLR, FFCLR_DRC); 166 } 167 168 169 static void rsci_start_rx(struct uart_port *port) 170 { 171 unsigned int ctrl; 172 173 ctrl = rsci_serial_in(port, CCR0); 174 ctrl |= CCR0_RIE; 175 rsci_serial_out(port, CCR0, ctrl); 176 } 177 178 static void rsci_enable_ms(struct uart_port *port) 179 { 180 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 181 } 182 183 static void rsci_init_pins(struct uart_port *port, unsigned int cflag) 184 { 185 struct sci_port *s = to_sci_port(port); 186 187 /* Use port-specific handler if provided */ 188 if (s->cfg->ops && s->cfg->ops->init_pins) { 189 s->cfg->ops->init_pins(port, cflag); 190 return; 191 } 192 193 if (!s->has_rtscts) 194 return; 195 196 if (s->autorts) 197 rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | 198 CCR1_CTSE | CCR1_CTSPEN); 199 } 200 201 static int rsci_scif_set_rtrg(struct uart_port *port, int rx_trig) 202 { 203 u32 fcr = rsci_serial_in(port, FCR); 204 205 if (rx_trig >= port->fifosize) 206 rx_trig = port->fifosize - 1; 207 else if (rx_trig < 1) 208 rx_trig = 0; 209 210 fcr &= ~FCR_RTRG4_0; 211 fcr |= field_prep(FCR_RTRG4_0, rx_trig); 212 rsci_serial_out(port, FCR, fcr); 213 214 return rx_trig; 215 } 216 217 static void rsci_set_termios(struct uart_port *port, struct ktermios *termios, 218 const struct ktermios *old) 219 { 220 unsigned int ccr2_val = CCR2_INIT, ccr3_val = CCR3_INIT; 221 unsigned int ccr0_val = 0, ccr1_val = 0, ccr4_val = 0; 222 unsigned int brr1 = 255, cks1 = 0, srr1 = 15; 223 struct sci_port *s = to_sci_port(port); 224 unsigned int brr = 255, cks = 0; 225 int min_err = INT_MAX, err; 226 unsigned long max_freq = 0; 227 unsigned int baud, i; 228 unsigned long flags; 229 unsigned int ctrl; 230 int best_clk = -1; 231 232 if ((termios->c_cflag & CSIZE) == CS7) { 233 ccr3_val |= CCR3_CHR0; 234 } else { 235 termios->c_cflag &= ~CSIZE; 236 termios->c_cflag |= CS8; 237 } 238 239 if (termios->c_cflag & PARENB) 240 ccr1_val |= CCR1_PE; 241 242 if (termios->c_cflag & PARODD) 243 ccr1_val |= (CCR1_PE | CCR1_PM); 244 245 if (termios->c_cflag & CSTOPB) 246 ccr3_val |= CCR3_STP; 247 248 /* Enable noise filter function */ 249 ccr1_val |= CCR1_NFEN; 250 251 /* 252 * earlyprintk comes here early on with port->uartclk set to zero. 253 * the clock framework is not up and running at this point so here 254 * we assume that 115200 is the maximum baud rate. please note that 255 * the baud rate is not programmed during earlyprintk - it is assumed 256 * that the previous boot loader has enabled required clocks and 257 * setup the baud rate generator hardware for us already. 258 */ 259 if (!port->uartclk) { 260 max_freq = 115200; 261 } else { 262 for (i = 0; i < SCI_NUM_CLKS; i++) 263 max_freq = max(max_freq, s->clk_rates[i]); 264 265 max_freq /= min_sr(s); 266 } 267 268 baud = uart_get_baud_rate(port, termios, old, 0, max_freq); 269 if (!baud) 270 goto done; 271 272 /* Divided Functional Clock using standard Bit Rate Register */ 273 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 274 if (abs(err) < abs(min_err)) { 275 best_clk = SCI_FCK; 276 ccr0_val = 0; 277 min_err = err; 278 brr = brr1; 279 cks = cks1; 280 } 281 282 done: 283 if (best_clk >= 0) 284 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 285 s->clks[best_clk], baud, min_err); 286 287 sci_port_enable(s); 288 uart_port_lock_irqsave(port, &flags); 289 290 uart_update_timeout(port, termios->c_cflag, baud); 291 292 rsci_serial_out(port, CCR0, ccr0_val); 293 294 ccr3_val |= CCR3_FM; 295 rsci_serial_out(port, CCR3, ccr3_val); 296 297 ccr2_val |= (cks << 20) | (brr << 8); 298 rsci_serial_out(port, CCR2, ccr2_val); 299 300 rsci_serial_out(port, CCR1, ccr1_val); 301 rsci_serial_out(port, CCR4, ccr4_val); 302 303 ctrl = rsci_serial_in(port, FCR); 304 ctrl |= (FCR_RFRST | FCR_TFRST); 305 rsci_serial_out(port, FCR, ctrl); 306 307 if (s->rx_trigger > 1) 308 rsci_scif_set_rtrg(port, s->rx_trigger); 309 310 port->status &= ~UPSTAT_AUTOCTS; 311 s->autorts = false; 312 313 if ((port->flags & UPF_HARD_FLOW) && (termios->c_cflag & CRTSCTS)) { 314 port->status |= UPSTAT_AUTOCTS; 315 s->autorts = true; 316 } 317 318 rsci_init_pins(port, termios->c_cflag); 319 rsci_serial_out(port, CFCLR, CFCLR_CLRFLAG); 320 rsci_serial_out(port, FFCLR, FFCLR_DRC); 321 322 ccr0_val |= CCR0_RE; 323 rsci_serial_out(port, CCR0, ccr0_val); 324 325 if ((termios->c_cflag & CREAD) != 0) 326 rsci_start_rx(port); 327 328 uart_port_unlock_irqrestore(port, flags); 329 sci_port_disable(s); 330 331 if (UART_ENABLE_MS(port, termios->c_cflag)) 332 rsci_enable_ms(port); 333 } 334 335 static int rsci_txfill(struct uart_port *port) 336 { 337 return rsci_serial_in(port, FTSR); 338 } 339 340 static int rsci_rxfill(struct uart_port *port) 341 { 342 u32 val = rsci_serial_in(port, FRSR); 343 344 return FIELD_GET(FRSR_R5_0, val); 345 } 346 347 static unsigned int rsci_tx_empty(struct uart_port *port) 348 { 349 unsigned int status = rsci_serial_in(port, CSR); 350 unsigned int in_tx_fifo = rsci_txfill(port); 351 352 return (status & CSR_TEND) && !in_tx_fifo ? TIOCSER_TEMT : 0; 353 } 354 355 static void rsci_set_mctrl(struct uart_port *port, unsigned int mctrl) 356 { 357 if (mctrl & TIOCM_LOOP) { 358 /* Standard loopback mode */ 359 rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | CCR1_SPLP); 360 } 361 } 362 363 static unsigned int rsci_get_mctrl(struct uart_port *port) 364 { 365 struct sci_port *s = to_sci_port(port); 366 struct mctrl_gpios *gpios = s->gpios; 367 unsigned int mctrl = 0; 368 369 mctrl_gpio_get(gpios, &mctrl); 370 371 /* 372 * CTS/RTS is handled in hardware when supported, while nothing 373 * else is wired up. 374 */ 375 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) 376 mctrl |= TIOCM_CTS; 377 378 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 379 mctrl |= TIOCM_DSR; 380 381 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 382 mctrl |= TIOCM_CAR; 383 384 return mctrl; 385 } 386 387 static void rsci_clear_CFC(struct uart_port *port, unsigned int mask) 388 { 389 rsci_serial_out(port, CFCLR, mask); 390 } 391 392 static void rsci_start_tx(struct uart_port *port) 393 { 394 struct sci_port *sp = to_sci_port(port); 395 u32 ctrl; 396 397 if (sp->chan_tx) 398 return; 399 400 /* 401 * TE (Transmit Enable) must be set after setting TIE 402 * (Transmit Interrupt Enable) or in the same instruction 403 * to start the transmit process. 404 */ 405 ctrl = rsci_serial_in(port, CCR0); 406 ctrl |= CCR0_TIE | CCR0_TE; 407 rsci_serial_out(port, CCR0, ctrl); 408 } 409 410 static void rsci_stop_tx(struct uart_port *port) 411 { 412 u32 ctrl; 413 414 ctrl = rsci_serial_in(port, CCR0); 415 ctrl &= ~CCR0_TIE; 416 rsci_serial_out(port, CCR0, ctrl); 417 } 418 419 static void rsci_stop_rx(struct uart_port *port) 420 { 421 u32 ctrl; 422 423 ctrl = rsci_serial_in(port, CCR0); 424 ctrl &= ~CCR0_RIE; 425 rsci_serial_out(port, CCR0, ctrl); 426 } 427 428 static int rsci_txroom(struct uart_port *port) 429 { 430 return port->fifosize - rsci_txfill(port); 431 } 432 433 static void rsci_transmit_chars(struct uart_port *port) 434 { 435 unsigned int stopped = uart_tx_stopped(port); 436 struct tty_port *tport = &port->state->port; 437 u32 status, ctrl; 438 int count; 439 440 status = rsci_serial_in(port, CSR); 441 if (!(status & CSR_TDRE)) { 442 ctrl = rsci_serial_in(port, CCR0); 443 if (kfifo_is_empty(&tport->xmit_fifo)) 444 ctrl &= ~CCR0_TIE; 445 else 446 ctrl |= CCR0_TIE; 447 rsci_serial_out(port, CCR0, ctrl); 448 return; 449 } 450 451 count = rsci_txroom(port); 452 453 do { 454 unsigned char c; 455 456 if (port->x_char) { 457 c = port->x_char; 458 port->x_char = 0; 459 } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) { 460 break; 461 } 462 463 rsci_clear_CFC(port, CFCLR_TDREC); 464 rsci_serial_out(port, TDR, c); 465 466 port->icount.tx++; 467 } while (--count > 0); 468 469 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 470 uart_write_wakeup(port); 471 472 if (kfifo_is_empty(&tport->xmit_fifo)) { 473 ctrl = rsci_serial_in(port, CCR0); 474 ctrl &= ~CCR0_TIE; 475 ctrl |= CCR0_TEIE; 476 rsci_serial_out(port, CCR0, ctrl); 477 } 478 } 479 480 static void rsci_receive_chars(struct uart_port *port) 481 { 482 struct tty_port *tport = &port->state->port; 483 u32 rdat, status, frsr_status = 0; 484 int i, count, copied = 0; 485 unsigned char flag; 486 487 status = rsci_serial_in(port, CSR); 488 frsr_status = rsci_serial_in(port, FRSR); 489 490 if (!(status & CSR_RDRF) && !(frsr_status & FRSR_DR)) 491 return; 492 493 while (1) { 494 /* Don't copy more bytes than there is room for in the buffer */ 495 count = tty_buffer_request_room(tport, rsci_rxfill(port)); 496 497 /* If for any reason we can't copy more data, we're done! */ 498 if (count == 0) 499 break; 500 501 for (i = 0; i < count; i++) { 502 char c; 503 504 rdat = rsci_serial_in(port, RDR); 505 /* 9-bits data is not supported yet */ 506 c = rdat & RDR_RDAT_MSK; 507 508 if (uart_handle_sysrq_char(port, c)) { 509 count--; 510 i--; 511 continue; 512 } 513 514 /* 515 * Store data and status. 516 * Non FIFO mode is not supported 517 */ 518 if (rdat & RDR_FFER) { 519 flag = TTY_FRAME; 520 port->icount.frame++; 521 } else if (rdat & RDR_FPER) { 522 flag = TTY_PARITY; 523 port->icount.parity++; 524 } else { 525 flag = TTY_NORMAL; 526 } 527 528 tty_insert_flip_char(tport, c, flag); 529 } 530 531 rsci_serial_in(port, CSR); /* dummy read */ 532 rsci_clear_DRxC(port); 533 534 copied += count; 535 port->icount.rx += count; 536 } 537 538 if (copied) { 539 /* Tell the rest of the system the news. New characters! */ 540 tty_flip_buffer_push(tport); 541 } else { 542 /* TTY buffers full; read from RX reg to prevent lockup */ 543 rsci_serial_in(port, RDR); 544 rsci_serial_in(port, CSR); /* dummy read */ 545 rsci_clear_DRxC(port); 546 } 547 } 548 549 static void rsci_break_ctl(struct uart_port *port, int break_state) 550 { 551 unsigned short ccr0_val, ccr1_val; 552 unsigned long flags; 553 554 uart_port_lock_irqsave(port, &flags); 555 ccr1_val = rsci_serial_in(port, CCR1); 556 ccr0_val = rsci_serial_in(port, CCR0); 557 558 if (break_state == -1) { 559 ccr1_val = (ccr1_val | CCR1_SPB2IO) & ~CCR1_SPB2DT; 560 ccr0_val &= ~CCR0_TE; 561 } else { 562 ccr1_val = (ccr1_val | CCR1_SPB2DT) & ~CCR1_SPB2IO; 563 ccr0_val |= CCR0_TE; 564 } 565 566 rsci_serial_out(port, CCR1, ccr1_val); 567 rsci_serial_out(port, CCR0, ccr0_val); 568 uart_port_unlock_irqrestore(port, flags); 569 } 570 571 static void rsci_poll_put_char(struct uart_port *port, unsigned char c) 572 { 573 u32 status; 574 int ret; 575 576 ret = readl_relaxed_poll_timeout_atomic(port->membase + CSR, status, 577 (status & CSR_TDRE), 100, 578 USEC_PER_SEC); 579 if (ret != 0) { 580 dev_err(port->dev, 581 "Error while sending data in UART TX : %d\n", ret); 582 goto done; 583 } 584 rsci_serial_out(port, TDR, c); 585 done: 586 rsci_clear_CFC(port, CFCLR_TDREC); 587 } 588 589 static void rsci_prepare_console_write(struct uart_port *port, u32 ctrl) 590 { 591 struct sci_port *s = to_sci_port(port); 592 u32 ctrl_temp = s->params->param_bits->rxtx_enable; 593 594 if (s->type == RSCI_PORT_SCIF16) 595 ctrl_temp |= CCR0_TIE | s->hscif_tot; 596 597 rsci_serial_out(port, CCR0, ctrl_temp); 598 } 599 600 static void rsci_finish_console_write(struct uart_port *port, u32 ctrl) 601 { 602 /* First set TE = 0 and then restore the CCR0 value */ 603 rsci_serial_out(port, CCR0, ctrl & ~CCR0_TE); 604 rsci_serial_out(port, CCR0, ctrl); 605 } 606 607 static const char *rsci_type(struct uart_port *port) 608 { 609 return "rsci"; 610 } 611 612 static size_t rsci_suspend_regs_size(void) 613 { 614 return 0; 615 } 616 617 static void rsci_shutdown_complete(struct uart_port *port) 618 { 619 /* 620 * Stop RX and TX, disable related interrupts, keep clock source 621 */ 622 rsci_serial_out(port, CCR0, 0); 623 } 624 625 static const struct sci_common_regs rsci_common_regs = { 626 .status = CSR, 627 .control = CCR0, 628 }; 629 630 static const struct sci_port_params_bits rsci_port_param_bits = { 631 .rxtx_enable = CCR0_RE | CCR0_TE, 632 .te_clear = CCR0_TE | CCR0_TEIE, 633 .poll_sent_bits = CSR_TDRE | CSR_TEND, 634 }; 635 636 static const struct sci_port_params rsci_rzg3e_port_params = { 637 .fifosize = 32, 638 .overrun_reg = CSR, 639 .overrun_mask = CSR_ORER, 640 .sampling_rate_mask = SCI_SR(32), 641 .error_mask = RSCI_DEFAULT_ERROR_MASK, 642 .error_clear = RSCI_ERROR_CLEAR, 643 .param_bits = &rsci_port_param_bits, 644 .common_regs = &rsci_common_regs, 645 }; 646 647 static const struct sci_port_params rsci_rzt2h_port_params = { 648 .fifosize = 16, 649 .overrun_reg = CSR, 650 .overrun_mask = CSR_ORER, 651 .sampling_rate_mask = SCI_SR(32), 652 .error_mask = RSCI_DEFAULT_ERROR_MASK, 653 .error_clear = RSCI_ERROR_CLEAR, 654 .param_bits = &rsci_port_param_bits, 655 .common_regs = &rsci_common_regs, 656 }; 657 658 static const struct uart_ops rsci_uart_ops = { 659 .tx_empty = rsci_tx_empty, 660 .set_mctrl = rsci_set_mctrl, 661 .get_mctrl = rsci_get_mctrl, 662 .start_tx = rsci_start_tx, 663 .stop_tx = rsci_stop_tx, 664 .stop_rx = rsci_stop_rx, 665 .enable_ms = rsci_enable_ms, 666 .break_ctl = rsci_break_ctl, 667 .startup = sci_startup, 668 .shutdown = sci_shutdown, 669 .set_termios = rsci_set_termios, 670 .pm = sci_pm, 671 .type = rsci_type, 672 .release_port = sci_release_port, 673 .request_port = sci_request_port, 674 .config_port = sci_config_port, 675 .verify_port = sci_verify_port, 676 }; 677 678 static const struct sci_port_ops rsci_port_ops = { 679 .read_reg = rsci_serial_in, 680 .write_reg = rsci_serial_out, 681 .clear_SCxSR = rsci_clear_CFC, 682 .transmit_chars = rsci_transmit_chars, 683 .receive_chars = rsci_receive_chars, 684 .poll_put_char = rsci_poll_put_char, 685 .prepare_console_write = rsci_prepare_console_write, 686 .finish_console_write = rsci_finish_console_write, 687 .suspend_regs_size = rsci_suspend_regs_size, 688 .set_rtrg = rsci_scif_set_rtrg, 689 .shutdown_complete = rsci_shutdown_complete, 690 }; 691 692 struct sci_of_data of_rsci_rzg3e_data = { 693 .type = RSCI_PORT_SCIF32, 694 .ops = &rsci_port_ops, 695 .uart_ops = &rsci_uart_ops, 696 .params = &rsci_rzg3e_port_params, 697 }; 698 699 struct sci_of_data of_rsci_rzt2h_data = { 700 .type = RSCI_PORT_SCIF16, 701 .ops = &rsci_port_ops, 702 .uart_ops = &rsci_uart_ops, 703 .params = &rsci_rzt2h_port_params, 704 }; 705 706 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 707 708 static int __init rsci_rzg3e_early_console_setup(struct earlycon_device *device, 709 const char *opt) 710 { 711 return scix_early_console_setup(device, &of_rsci_rzg3e_data); 712 } 713 714 static int __init rsci_rzt2h_early_console_setup(struct earlycon_device *device, 715 const char *opt) 716 { 717 return scix_early_console_setup(device, &of_rsci_rzt2h_data); 718 } 719 720 OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rsci", rsci_rzg3e_early_console_setup); 721 OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_rzt2h_early_console_setup); 722 723 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 724 725 MODULE_LICENSE("GPL"); 726 MODULE_DESCRIPTION("RSCI serial driver"); 727