1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2025 Renesas Electronics Corp. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/bitops.h> 8 #include <linux/io.h> 9 #include <linux/iopoll.h> 10 #include <linux/module.h> 11 #include <linux/serial_core.h> 12 #include <linux/serial_sci.h> 13 #include <linux/tty_flip.h> 14 #include "rsci.h" 15 16 MODULE_IMPORT_NS("SH_SCI"); 17 18 /* RSCI registers */ 19 #define RDR 0x00 20 #define TDR 0x04 21 #define CCR0 0x08 22 #define CCR1 0x0C 23 #define CCR2 0x10 24 #define CCR3 0x14 25 #define CCR4 0x18 26 #define FCR 0x24 27 #define DCR 0x30 28 #define CSR 0x48 29 #define FRSR 0x50 30 #define FTSR 0x54 31 #define CFCLR 0x68 32 #define FFCLR 0x70 33 34 /* RDR (Receive Data Register) */ 35 #define RDR_FFER BIT(12) /* FIFO Framing Error */ 36 #define RDR_FPER BIT(11) /* FIFO Parity Error */ 37 #define RDR_RDAT_MSK GENMASK(8, 0) 38 39 /* TDR (Transmit Data Register) */ 40 #define TDR_MPBT BIT(9) /* Multiprocessor Transfer */ 41 #define TDR_TDAT_9BIT_LSHIFT 0 42 #define TDR_TDAT_9BIT_VAL 0x1FF 43 #define TDR_TDAT_9BIT_MSK (TDR_TDAT_9BIT_VAL << TDR_TDAT_9BIT_LSHIFT) 44 45 /* CCR0 (Common Control Register 0) */ 46 #define CCR0_SSE BIT(24) /* SSn# Pin Function Enable */ 47 #define CCR0_TEIE BIT(21) /* Transmit End Interrupt Enable */ 48 #define CCR0_TIE BIT(20) /* Transmit Interrupt Enable */ 49 #define CCR0_RIE BIT(16) /* Receive Interrupt Enable */ 50 #define CCR0_IDSEL BIT(10) /* ID Frame Select */ 51 #define CCR0_DCME BIT(9) /* Data Compare Match Enable */ 52 #define CCR0_MPIE BIT(8) /* Multiprocessor Interrupt Enable */ 53 #define CCR0_TE BIT(4) /* Transmit Enable */ 54 #define CCR0_RE BIT(0) /* Receive Enable */ 55 56 /* CCR1 (Common Control Register 1) */ 57 #define CCR1_NFEN BIT(28) /* Digital Noise Filter Function */ 58 #define CCR1_SHARPS BIT(20) /* Half -duplex Communication Select */ 59 #define CCR1_SPLP BIT(16) /* Loopback Control */ 60 #define CCR1_RINV BIT(13) /* RxD invert */ 61 #define CCR1_TINV BIT(12) /* TxD invert */ 62 #define CCR1_PM BIT(9) /* Parity Mode */ 63 #define CCR1_PE BIT(8) /* Parity Enable */ 64 #define CCR1_SPB2IO BIT(5) /* Serial Port Break I/O */ 65 #define CCR1_SPB2DT BIT(4) /* Serial Port Break Data Select */ 66 #define CCR1_CTSPEN BIT(1) /* CTS External Pin Enable */ 67 #define CCR1_CTSE BIT(0) /* CTS Enable */ 68 69 /* FCR (FIFO Control Register) */ 70 #define FCR_RFRST BIT(23) /* Receive FIFO Data Register Reset */ 71 #define FCR_TFRST BIT(15) /* Transmit FIFO Data Register Reset */ 72 #define FCR_DRES BIT(0) /* Incoming Data Ready Error Select */ 73 #define FCR_RTRG4_0 GENMASK(20, 16) 74 #define FCR_TTRG GENMASK(12, 8) 75 76 /* CSR (Common Status Register) */ 77 #define CSR_RDRF BIT(31) /* Receive Data Full */ 78 #define CSR_TEND BIT(30) /* Transmit End Flag */ 79 #define CSR_TDRE BIT(29) /* Transmit Data Empty */ 80 #define CSR_FER BIT(28) /* Framing Error */ 81 #define CSR_PER BIT(27) /* Parity Error */ 82 #define CSR_MFF BIT(26) /* Mode Fault Error */ 83 #define CSR_ORER BIT(24) /* Overrun Error */ 84 #define CSR_DFER BIT(18) /* Data Compare Match Framing Error */ 85 #define CSR_DPER BIT(17) /* Data Compare Match Parity Error */ 86 #define CSR_DCMF BIT(16) /* Data Compare Match */ 87 #define CSR_RXDMON BIT(15) /* Serial Input Data Monitor */ 88 #define CSR_ERS BIT(4) /* Error Signal Status */ 89 90 #define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask) 91 #define SCxSR_ERROR_CLEAR(port) (to_sci_port(port)->params->error_clear) 92 93 #define RSCI_DEFAULT_ERROR_MASK (CSR_PER | CSR_FER) 94 95 #define RSCI_RDxF_CLEAR (CFCLR_RDRFC) 96 #define RSCI_ERROR_CLEAR (CFCLR_PERC | CFCLR_FERC) 97 #define RSCI_TDxE_CLEAR (CFCLR_TDREC) 98 #define RSCI_BREAK_CLEAR (CFCLR_PERC | CFCLR_FERC | CFCLR_ORERC) 99 100 /* FRSR (FIFO Receive Status Register) */ 101 #define FRSR_R5_0 GENMASK(13, 8) /* Receive FIFO Data Count */ 102 #define FRSR_DR BIT(0) /* Receive Data Ready */ 103 104 /* CFCLR (Common Flag CLear Register) */ 105 #define CFCLR_RDRFC BIT(31) /* RDRF Clear */ 106 #define CFCLR_TDREC BIT(29) /* TDRE Clear */ 107 #define CFCLR_FERC BIT(28) /* FER Clear */ 108 #define CFCLR_PERC BIT(27) /* PER Clear */ 109 #define CFCLR_MFFC BIT(26) /* MFF Clear */ 110 #define CFCLR_ORERC BIT(24) /* ORER Clear */ 111 #define CFCLR_DFERC BIT(18) /* DFER Clear */ 112 #define CFCLR_DPERC BIT(17) /* DPER Clear */ 113 #define CFCLR_DCMFC BIT(16) /* DCMF Clear */ 114 #define CFCLR_ERSC BIT(4) /* ERS Clear */ 115 #define CFCLR_CLRFLAG (CFCLR_RDRFC | CFCLR_FERC | CFCLR_PERC | \ 116 CFCLR_MFFC | CFCLR_ORERC | CFCLR_DFERC | \ 117 CFCLR_DPERC | CFCLR_DCMFC | CFCLR_ERSC) 118 119 /* FFCLR (FIFO Flag CLear Register) */ 120 #define FFCLR_DRC BIT(0) /* DR Clear */ 121 122 #define DCR_DEPOL BIT(0) 123 124 static u32 rsci_serial_in(struct uart_port *p, int offset) 125 { 126 return readl(p->membase + offset); 127 } 128 129 static void rsci_serial_out(struct uart_port *p, int offset, int value) 130 { 131 writel(value, p->membase + offset); 132 } 133 134 static void rsci_clear_DRxC(struct uart_port *port) 135 { 136 rsci_serial_out(port, CFCLR, CFCLR_RDRFC); 137 rsci_serial_out(port, FFCLR, FFCLR_DRC); 138 } 139 140 static void rsci_clear_SCxSR(struct uart_port *port, unsigned int mask) 141 { 142 rsci_serial_out(port, CFCLR, mask); 143 } 144 145 static void rsci_start_rx(struct uart_port *port) 146 { 147 unsigned int ctrl; 148 149 ctrl = rsci_serial_in(port, CCR0); 150 ctrl |= CCR0_RIE; 151 rsci_serial_out(port, CCR0, ctrl); 152 } 153 154 static void rsci_set_termios(struct uart_port *port, struct ktermios *termios, 155 const struct ktermios *old) 156 { 157 struct sci_port *s = to_sci_port(port); 158 unsigned long flags; 159 160 sci_port_enable(s); 161 uart_port_lock_irqsave(port, &flags); 162 163 /* For now, only RX enabling is supported */ 164 if (termios->c_cflag & CREAD) 165 rsci_start_rx(port); 166 167 uart_port_unlock_irqrestore(port, flags); 168 sci_port_disable(s); 169 } 170 171 static int rsci_txfill(struct uart_port *port) 172 { 173 return rsci_serial_in(port, FTSR); 174 } 175 176 static int rsci_rxfill(struct uart_port *port) 177 { 178 u32 val = rsci_serial_in(port, FRSR); 179 180 return FIELD_GET(FRSR_R5_0, val); 181 } 182 183 static unsigned int rsci_tx_empty(struct uart_port *port) 184 { 185 unsigned int status = rsci_serial_in(port, CSR); 186 unsigned int in_tx_fifo = rsci_txfill(port); 187 188 return (status & CSR_TEND) && !in_tx_fifo ? TIOCSER_TEMT : 0; 189 } 190 191 static void rsci_set_mctrl(struct uart_port *port, unsigned int mctrl) 192 { 193 /* Not supported yet */ 194 } 195 196 static unsigned int rsci_get_mctrl(struct uart_port *port) 197 { 198 /* Not supported yet */ 199 return 0; 200 } 201 202 static void rsci_clear_CFC(struct uart_port *port, unsigned int mask) 203 { 204 rsci_serial_out(port, CFCLR, mask); 205 } 206 207 static void rsci_start_tx(struct uart_port *port) 208 { 209 struct sci_port *sp = to_sci_port(port); 210 u32 ctrl; 211 212 if (sp->chan_tx) 213 return; 214 215 /* 216 * TE (Transmit Enable) must be set after setting TIE 217 * (Transmit Interrupt Enable) or in the same instruction 218 * to start the transmit process. 219 */ 220 ctrl = rsci_serial_in(port, CCR0); 221 ctrl |= CCR0_TIE | CCR0_TE; 222 rsci_serial_out(port, CCR0, ctrl); 223 } 224 225 static void rsci_stop_tx(struct uart_port *port) 226 { 227 u32 ctrl; 228 229 ctrl = rsci_serial_in(port, CCR0); 230 ctrl &= ~CCR0_TIE; 231 rsci_serial_out(port, CCR0, ctrl); 232 } 233 234 static void rsci_stop_rx(struct uart_port *port) 235 { 236 u32 ctrl; 237 238 ctrl = rsci_serial_in(port, CCR0); 239 ctrl &= ~CCR0_RIE; 240 rsci_serial_out(port, CCR0, ctrl); 241 } 242 243 static int rsci_txroom(struct uart_port *port) 244 { 245 return port->fifosize - rsci_txfill(port); 246 } 247 248 static void rsci_transmit_chars(struct uart_port *port) 249 { 250 unsigned int stopped = uart_tx_stopped(port); 251 struct tty_port *tport = &port->state->port; 252 u32 status, ctrl; 253 int count; 254 255 status = rsci_serial_in(port, CSR); 256 if (!(status & CSR_TDRE)) { 257 ctrl = rsci_serial_in(port, CCR0); 258 if (kfifo_is_empty(&tport->xmit_fifo)) 259 ctrl &= ~CCR0_TIE; 260 else 261 ctrl |= CCR0_TIE; 262 rsci_serial_out(port, CCR0, ctrl); 263 return; 264 } 265 266 count = rsci_txroom(port); 267 268 do { 269 unsigned char c; 270 271 if (port->x_char) { 272 c = port->x_char; 273 port->x_char = 0; 274 } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) { 275 break; 276 } 277 278 rsci_clear_CFC(port, CFCLR_TDREC); 279 rsci_serial_out(port, TDR, c); 280 281 port->icount.tx++; 282 } while (--count > 0); 283 284 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 285 uart_write_wakeup(port); 286 287 if (kfifo_is_empty(&tport->xmit_fifo)) { 288 ctrl = rsci_serial_in(port, CCR0); 289 ctrl &= ~CCR0_TIE; 290 ctrl |= CCR0_TEIE; 291 rsci_serial_out(port, CCR0, ctrl); 292 } 293 } 294 295 static void rsci_receive_chars(struct uart_port *port) 296 { 297 struct tty_port *tport = &port->state->port; 298 u32 rdat, status, frsr_status = 0; 299 int i, count, copied = 0; 300 unsigned char flag; 301 302 status = rsci_serial_in(port, CSR); 303 frsr_status = rsci_serial_in(port, FRSR); 304 305 if (!(status & CSR_RDRF) && !(frsr_status & FRSR_DR)) 306 return; 307 308 while (1) { 309 /* Don't copy more bytes than there is room for in the buffer */ 310 count = tty_buffer_request_room(tport, rsci_rxfill(port)); 311 312 /* If for any reason we can't copy more data, we're done! */ 313 if (count == 0) 314 break; 315 316 for (i = 0; i < count; i++) { 317 char c; 318 319 rdat = rsci_serial_in(port, RDR); 320 /* 9-bits data is not supported yet */ 321 c = rdat & RDR_RDAT_MSK; 322 323 if (uart_handle_sysrq_char(port, c)) { 324 count--; 325 i--; 326 continue; 327 } 328 329 /* Store data and status. 330 * Non FIFO mode is not supported 331 */ 332 if (rdat & RDR_FFER) { 333 flag = TTY_FRAME; 334 port->icount.frame++; 335 } else if (rdat & RDR_FPER) { 336 flag = TTY_PARITY; 337 port->icount.parity++; 338 } else { 339 flag = TTY_NORMAL; 340 } 341 342 tty_insert_flip_char(tport, c, flag); 343 } 344 345 rsci_serial_in(port, CSR); /* dummy read */ 346 rsci_clear_DRxC(port); 347 348 copied += count; 349 port->icount.rx += count; 350 } 351 352 if (copied) { 353 /* Tell the rest of the system the news. New characters! */ 354 tty_flip_buffer_push(tport); 355 } else { 356 /* TTY buffers full; read from RX reg to prevent lockup */ 357 rsci_serial_in(port, RDR); 358 rsci_serial_in(port, CSR); /* dummy read */ 359 rsci_clear_DRxC(port); 360 } 361 } 362 363 static void rsci_poll_put_char(struct uart_port *port, unsigned char c) 364 { 365 u32 status; 366 int ret; 367 368 ret = readl_relaxed_poll_timeout_atomic(port->membase + CSR, status, 369 (status & CSR_TDRE), 100, 370 USEC_PER_SEC); 371 if (ret != 0) { 372 dev_err(port->dev, 373 "Error while sending data in UART TX : %d\n", ret); 374 goto done; 375 } 376 rsci_serial_out(port, TDR, c); 377 done: 378 rsci_clear_SCxSR(port, CFCLR_TDREC); 379 } 380 381 static void rsci_prepare_console_write(struct uart_port *port, u32 ctrl) 382 { 383 struct sci_port *s = to_sci_port(port); 384 u32 ctrl_temp = 385 s->params->param_bits->rxtx_enable | CCR0_TIE | 386 s->hscif_tot; 387 rsci_serial_out(port, CCR0, ctrl_temp); 388 } 389 390 static const char *rsci_type(struct uart_port *port) 391 { 392 return "rsci"; 393 } 394 395 static size_t rsci_suspend_regs_size(void) 396 { 397 return 0; 398 } 399 400 static void rsci_shutdown_complete(struct uart_port *port) 401 { 402 /* 403 * Stop RX and TX, disable related interrupts, keep clock source 404 */ 405 rsci_serial_out(port, CCR0, 0); 406 } 407 408 static const struct sci_common_regs rsci_common_regs = { 409 .status = CSR, 410 .control = CCR0, 411 }; 412 413 static const struct sci_port_params_bits rsci_port_param_bits = { 414 .rxtx_enable = CCR0_RE | CCR0_TE, 415 .te_clear = CCR0_TE | CCR0_TEIE, 416 .poll_sent_bits = CSR_TDRE | CSR_TEND, 417 }; 418 419 static const struct sci_port_params rsci_port_params = { 420 .fifosize = 16, 421 .overrun_reg = CSR, 422 .overrun_mask = CSR_ORER, 423 .sampling_rate_mask = SCI_SR(32), 424 .error_mask = RSCI_DEFAULT_ERROR_MASK, 425 .error_clear = RSCI_ERROR_CLEAR, 426 .param_bits = &rsci_port_param_bits, 427 .common_regs = &rsci_common_regs, 428 }; 429 430 static const struct uart_ops rsci_uart_ops = { 431 .tx_empty = rsci_tx_empty, 432 .set_mctrl = rsci_set_mctrl, 433 .get_mctrl = rsci_get_mctrl, 434 .start_tx = rsci_start_tx, 435 .stop_tx = rsci_stop_tx, 436 .stop_rx = rsci_stop_rx, 437 .startup = sci_startup, 438 .shutdown = sci_shutdown, 439 .set_termios = rsci_set_termios, 440 .pm = sci_pm, 441 .type = rsci_type, 442 .release_port = sci_release_port, 443 .request_port = sci_request_port, 444 .config_port = sci_config_port, 445 .verify_port = sci_verify_port, 446 }; 447 448 static const struct sci_port_ops rsci_port_ops = { 449 .read_reg = rsci_serial_in, 450 .write_reg = rsci_serial_out, 451 .clear_SCxSR = rsci_clear_SCxSR, 452 .transmit_chars = rsci_transmit_chars, 453 .receive_chars = rsci_receive_chars, 454 .poll_put_char = rsci_poll_put_char, 455 .prepare_console_write = rsci_prepare_console_write, 456 .suspend_regs_size = rsci_suspend_regs_size, 457 .shutdown_complete = rsci_shutdown_complete, 458 }; 459 460 struct sci_of_data of_sci_rsci_data = { 461 .type = SCI_PORT_RSCI, 462 .ops = &rsci_port_ops, 463 .uart_ops = &rsci_uart_ops, 464 .params = &rsci_port_params, 465 }; 466 467 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 468 469 static int __init rsci_early_console_setup(struct earlycon_device *device, 470 const char *opt) 471 { 472 return scix_early_console_setup(device, &of_sci_rsci_data); 473 } 474 475 OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_early_console_setup); 476 477 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 478 479 MODULE_LICENSE("GPL"); 480 MODULE_DESCRIPTION("RSCI serial driver"); 481