1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */ 5 #define __DISABLE_TRACE_MMIO__ 6 7 #include <linux/clk.h> 8 #include <linux/console.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/irq.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/pm_domain.h> 15 #include <linux/pm_opp.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/pm_wakeirq.h> 19 #include <linux/soc/qcom/geni-se.h> 20 #include <linux/serial.h> 21 #include <linux/serial_core.h> 22 #include <linux/slab.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <dt-bindings/interconnect/qcom,icc.h> 26 27 /* UART specific GENI registers */ 28 #define SE_UART_LOOPBACK_CFG 0x22c 29 #define SE_UART_IO_MACRO_CTRL 0x240 30 #define SE_UART_TX_TRANS_CFG 0x25c 31 #define SE_UART_TX_WORD_LEN 0x268 32 #define SE_UART_TX_STOP_BIT_LEN 0x26c 33 #define SE_UART_TX_TRANS_LEN 0x270 34 #define SE_UART_RX_TRANS_CFG 0x280 35 #define SE_UART_RX_WORD_LEN 0x28c 36 #define SE_UART_RX_STALE_CNT 0x294 37 #define SE_UART_TX_PARITY_CFG 0x2a4 38 #define SE_UART_RX_PARITY_CFG 0x2a8 39 #define SE_UART_MANUAL_RFR 0x2ac 40 41 /* SE_UART_TRANS_CFG */ 42 #define UART_TX_PAR_EN BIT(0) 43 #define UART_CTS_MASK BIT(1) 44 45 /* SE_UART_TX_STOP_BIT_LEN */ 46 #define TX_STOP_BIT_LEN_1 0 47 #define TX_STOP_BIT_LEN_2 2 48 49 /* SE_UART_RX_TRANS_CFG */ 50 #define UART_RX_PAR_EN BIT(3) 51 52 /* SE_UART_RX_WORD_LEN */ 53 #define RX_WORD_LEN_MASK GENMASK(9, 0) 54 55 /* SE_UART_RX_STALE_CNT */ 56 #define RX_STALE_CNT GENMASK(23, 0) 57 58 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ 59 #define PAR_CALC_EN BIT(0) 60 #define PAR_EVEN 0x00 61 #define PAR_ODD 0x01 62 #define PAR_SPACE 0x10 63 64 /* SE_UART_MANUAL_RFR register fields */ 65 #define UART_MANUAL_RFR_EN BIT(31) 66 #define UART_RFR_NOT_READY BIT(1) 67 #define UART_RFR_READY BIT(0) 68 69 /* UART M_CMD OP codes */ 70 #define UART_START_TX 0x1 71 /* UART S_CMD OP codes */ 72 #define UART_START_READ 0x1 73 #define UART_PARAM 0x1 74 #define UART_PARAM_RFR_OPEN BIT(7) 75 76 #define UART_OVERSAMPLING 32 77 #define STALE_TIMEOUT 16 78 #define DEFAULT_BITS_PER_CHAR 10 79 #define GENI_UART_CONS_PORTS 1 80 #define GENI_UART_PORTS 3 81 #define DEF_FIFO_DEPTH_WORDS 16 82 #define DEF_TX_WM 2 83 #define DEF_FIFO_WIDTH_BITS 32 84 #define UART_RX_WM 2 85 86 /* SE_UART_LOOPBACK_CFG */ 87 #define RX_TX_SORTED BIT(0) 88 #define CTS_RTS_SORTED BIT(1) 89 #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) 90 91 /* UART pin swap value */ 92 #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) 93 #define IO_MACRO_IO0_SEL 0x3 94 #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) 95 #define IO_MACRO_IO2_IO3_SWAP 0x4640 96 97 /* We always configure 4 bytes per FIFO word */ 98 #define BYTES_PER_FIFO_WORD 4U 99 100 #define DMA_RX_BUF_SIZE 2048 101 102 static DEFINE_IDA(port_ida); 103 #define DOMAIN_IDX_POWER 0 104 #define DOMAIN_IDX_PERF 1 105 106 struct qcom_geni_device_data { 107 bool console; 108 enum geni_se_xfer_mode mode; 109 struct dev_pm_domain_attach_data pd_data; 110 int (*resources_init)(struct uart_port *uport); 111 int (*set_rate)(struct uart_port *uport, unsigned int baud); 112 int (*power_state)(struct uart_port *uport, bool state); 113 }; 114 115 struct qcom_geni_private_data { 116 /* NOTE: earlycon port will have NULL here */ 117 struct uart_driver *drv; 118 119 u32 poll_cached_bytes; 120 unsigned int poll_cached_bytes_cnt; 121 122 u32 write_cached_bytes; 123 unsigned int write_cached_bytes_cnt; 124 }; 125 126 struct qcom_geni_serial_port { 127 struct uart_port uport; 128 struct geni_se se; 129 const char *name; 130 u32 tx_fifo_depth; 131 u32 tx_fifo_width; 132 u32 rx_fifo_depth; 133 dma_addr_t tx_dma_addr; 134 dma_addr_t rx_dma_addr; 135 bool setup; 136 unsigned long poll_timeout_us; 137 unsigned long clk_rate; 138 void *rx_buf; 139 u32 loopback; 140 bool brk; 141 142 unsigned int tx_remaining; 143 unsigned int tx_queued; 144 int wakeup_irq; 145 bool rx_tx_swap; 146 bool cts_rts_swap; 147 148 struct qcom_geni_private_data private_data; 149 const struct qcom_geni_device_data *dev_data; 150 struct dev_pm_domain_list *pd_list; 151 }; 152 153 static const struct uart_ops qcom_geni_console_pops; 154 static const struct uart_ops qcom_geni_uart_pops; 155 static struct uart_driver qcom_geni_console_driver; 156 static struct uart_driver qcom_geni_uart_driver; 157 158 static void __qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport); 159 static void qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport); 160 static int qcom_geni_serial_port_setup(struct uart_port *uport); 161 162 static inline struct qcom_geni_serial_port *to_dev_port(struct uart_port *uport) 163 { 164 return container_of(uport, struct qcom_geni_serial_port, uport); 165 } 166 167 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = { 168 [0] = { 169 .uport = { 170 .iotype = UPIO_MEM, 171 .ops = &qcom_geni_uart_pops, 172 .flags = UPF_BOOT_AUTOCONF, 173 .line = 0, 174 }, 175 }, 176 [1] = { 177 .uport = { 178 .iotype = UPIO_MEM, 179 .ops = &qcom_geni_uart_pops, 180 .flags = UPF_BOOT_AUTOCONF, 181 .line = 1, 182 }, 183 }, 184 [2] = { 185 .uport = { 186 .iotype = UPIO_MEM, 187 .ops = &qcom_geni_uart_pops, 188 .flags = UPF_BOOT_AUTOCONF, 189 .line = 2, 190 }, 191 }, 192 }; 193 194 static struct qcom_geni_serial_port qcom_geni_console_port = { 195 .uport = { 196 .iotype = UPIO_MEM, 197 .ops = &qcom_geni_console_pops, 198 .flags = UPF_BOOT_AUTOCONF, 199 .line = 0, 200 }, 201 }; 202 203 static const struct serial_rs485 qcom_geni_rs485_supported = { 204 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND | SER_RS485_RTS_ON_SEND, 205 }; 206 207 /** 208 * qcom_geni_set_rs485_mode - Set RTS pin state for RS485 mode 209 * @uport: UART port 210 * @flag: RS485 flag to determine RTS polarity 211 * 212 * Enables manual RTS control for RS485. Sets RTS to READY or NOT_READY 213 * based on the specified flag if RS485 mode is enabled. 214 */ 215 static void qcom_geni_set_rs485_mode(struct uart_port *uport, u32 flag) 216 { 217 if (!(uport->rs485.flags & SER_RS485_ENABLED)) 218 return; 219 220 u32 rfr = UART_MANUAL_RFR_EN; 221 222 if (uport->rs485.flags & flag) 223 rfr |= UART_RFR_NOT_READY; 224 else 225 rfr |= UART_RFR_READY; 226 227 writel(rfr, uport->membase + SE_UART_MANUAL_RFR); 228 } 229 230 static int qcom_geni_serial_request_port(struct uart_port *uport) 231 { 232 struct platform_device *pdev = to_platform_device(uport->dev); 233 struct qcom_geni_serial_port *port = to_dev_port(uport); 234 235 uport->membase = devm_platform_ioremap_resource(pdev, 0); 236 if (IS_ERR(uport->membase)) 237 return PTR_ERR(uport->membase); 238 port->se.base = uport->membase; 239 return 0; 240 } 241 242 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags) 243 { 244 if (cfg_flags & UART_CONFIG_TYPE) { 245 uport->type = PORT_MSM; 246 qcom_geni_serial_request_port(uport); 247 } 248 } 249 250 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport) 251 { 252 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR; 253 u32 geni_ios; 254 255 if (uart_console(uport)) { 256 mctrl |= TIOCM_CTS; 257 } else { 258 geni_ios = readl(uport->membase + SE_GENI_IOS); 259 if (!(geni_ios & IO2_DATA_IN)) 260 mctrl |= TIOCM_CTS; 261 } 262 263 return mctrl; 264 } 265 266 static void qcom_geni_serial_set_mctrl(struct uart_port *uport, 267 unsigned int mctrl) 268 { 269 u32 uart_manual_rfr = 0; 270 struct qcom_geni_serial_port *port = to_dev_port(uport); 271 272 if (uart_console(uport)) 273 return; 274 275 if (mctrl & TIOCM_LOOP) 276 port->loopback = RX_TX_CTS_RTS_SORTED; 277 278 if (!(mctrl & TIOCM_RTS) && !uport->suspended) 279 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; 280 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); 281 } 282 283 static const char *qcom_geni_serial_get_type(struct uart_port *uport) 284 { 285 return "MSM"; 286 } 287 288 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console) 289 { 290 struct qcom_geni_serial_port *port; 291 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS; 292 293 if (console) { 294 if (line < 0 || line >= nr_ports) 295 return ERR_PTR(-ENXIO); 296 297 port = &qcom_geni_console_port; 298 } else { 299 int max_alias_num = of_alias_get_highest_id("serial"); 300 301 if (line < 0 || line >= nr_ports) 302 line = ida_alloc_range(&port_ida, max_alias_num + 1, nr_ports, GFP_KERNEL); 303 else 304 line = ida_alloc_range(&port_ida, line, nr_ports, GFP_KERNEL); 305 306 if (line < 0) 307 return ERR_PTR(-ENXIO); 308 309 port = &qcom_geni_uart_ports[line]; 310 } 311 return port; 312 } 313 314 static bool qcom_geni_serial_main_active(struct uart_port *uport) 315 { 316 return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE; 317 } 318 319 static bool qcom_geni_serial_secondary_active(struct uart_port *uport) 320 { 321 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE; 322 } 323 324 static bool qcom_geni_serial_poll_bitfield(struct uart_port *uport, 325 unsigned int offset, u32 field, u32 val) 326 { 327 u32 reg; 328 struct qcom_geni_serial_port *port; 329 unsigned long timeout_us = 20000; 330 struct qcom_geni_private_data *private_data = uport->private_data; 331 332 if (private_data->drv) { 333 port = to_dev_port(uport); 334 if (port->poll_timeout_us) 335 timeout_us = port->poll_timeout_us; 336 } 337 338 /* 339 * Use custom implementation instead of readl_poll_atomic since ktimer 340 * is not ready at the time of early console. 341 */ 342 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; 343 while (timeout_us) { 344 reg = readl(uport->membase + offset); 345 if ((reg & field) == val) 346 return true; 347 udelay(10); 348 timeout_us -= 10; 349 } 350 return false; 351 } 352 353 static bool qcom_geni_serial_poll_bit(struct uart_port *uport, 354 unsigned int offset, u32 field, bool set) 355 { 356 return qcom_geni_serial_poll_bitfield(uport, offset, field, set ? field : 0); 357 } 358 359 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size) 360 { 361 u32 m_cmd; 362 363 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); 364 m_cmd = UART_START_TX << M_OPCODE_SHFT; 365 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); 366 } 367 368 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport) 369 { 370 int done; 371 372 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 373 M_CMD_DONE_EN, true); 374 if (!done) { 375 writel(M_GENI_CMD_ABORT, uport->membase + 376 SE_GENI_M_CMD_CTRL_REG); 377 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 378 M_CMD_ABORT_EN, true); 379 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 380 } 381 } 382 383 static void qcom_geni_serial_abort_rx(struct uart_port *uport) 384 { 385 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN; 386 387 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); 388 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, 389 S_GENI_CMD_ABORT, false); 390 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); 391 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); 392 } 393 394 #ifdef CONFIG_CONSOLE_POLL 395 static int qcom_geni_serial_get_char(struct uart_port *uport) 396 { 397 struct qcom_geni_private_data *private_data = uport->private_data; 398 u32 status; 399 u32 word_cnt; 400 int ret; 401 402 if (!private_data->poll_cached_bytes_cnt) { 403 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 404 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR); 405 406 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 407 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR); 408 409 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 410 word_cnt = status & RX_FIFO_WC_MSK; 411 if (!word_cnt) 412 return NO_POLL_CHAR; 413 414 if (word_cnt == 1 && (status & RX_LAST)) 415 /* 416 * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be 417 * treated as if it was BYTES_PER_FIFO_WORD. 418 */ 419 private_data->poll_cached_bytes_cnt = 420 (status & RX_LAST_BYTE_VALID_MSK) >> 421 RX_LAST_BYTE_VALID_SHFT; 422 423 if (private_data->poll_cached_bytes_cnt == 0) 424 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD; 425 426 private_data->poll_cached_bytes = 427 readl(uport->membase + SE_GENI_RX_FIFOn); 428 } 429 430 private_data->poll_cached_bytes_cnt--; 431 ret = private_data->poll_cached_bytes & 0xff; 432 private_data->poll_cached_bytes >>= 8; 433 434 return ret; 435 } 436 437 static void qcom_geni_serial_poll_put_char(struct uart_port *uport, 438 unsigned char c) 439 { 440 if (qcom_geni_serial_main_active(uport)) { 441 qcom_geni_serial_poll_tx_done(uport); 442 __qcom_geni_serial_cancel_tx_cmd(uport); 443 } 444 445 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 446 qcom_geni_serial_setup_tx(uport, 1); 447 writel(c, uport->membase + SE_GENI_TX_FIFOn); 448 qcom_geni_serial_poll_tx_done(uport); 449 } 450 451 static int qcom_geni_serial_poll_init(struct uart_port *uport) 452 { 453 struct qcom_geni_serial_port *port = to_dev_port(uport); 454 int ret; 455 456 if (!port->setup) { 457 ret = qcom_geni_serial_port_setup(uport); 458 if (ret) 459 return ret; 460 } 461 462 if (!qcom_geni_serial_secondary_active(uport)) 463 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); 464 465 return 0; 466 } 467 #endif 468 469 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 470 static void qcom_geni_serial_drain_fifo(struct uart_port *uport) 471 { 472 struct qcom_geni_serial_port *port = to_dev_port(uport); 473 474 qcom_geni_serial_poll_bitfield(uport, SE_GENI_M_GP_LENGTH, GP_LENGTH, 475 port->tx_queued); 476 } 477 478 static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch) 479 { 480 struct qcom_geni_private_data *private_data = uport->private_data; 481 482 private_data->write_cached_bytes = 483 (private_data->write_cached_bytes >> 8) | (ch << 24); 484 private_data->write_cached_bytes_cnt++; 485 486 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) { 487 writel(private_data->write_cached_bytes, 488 uport->membase + SE_GENI_TX_FIFOn); 489 private_data->write_cached_bytes_cnt = 0; 490 } 491 } 492 493 static void 494 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s, 495 unsigned int count) 496 { 497 struct qcom_geni_private_data *private_data = uport->private_data; 498 499 int i; 500 u32 bytes_to_send = count; 501 502 for (i = 0; i < count; i++) { 503 /* 504 * uart_console_write() adds a carriage return for each newline. 505 * Account for additional bytes to be written. 506 */ 507 if (s[i] == '\n') 508 bytes_to_send++; 509 } 510 511 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 512 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 513 qcom_geni_serial_setup_tx(uport, bytes_to_send); 514 for (i = 0; i < count; ) { 515 size_t chars_to_write = 0; 516 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; 517 518 /* 519 * If the WM bit never set, then the Tx state machine is not 520 * in a valid state, so break, cancel/abort any existing 521 * command. Unfortunately the current data being written is 522 * lost. 523 */ 524 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 525 M_TX_FIFO_WATERMARK_EN, true)) 526 break; 527 chars_to_write = min_t(size_t, count - i, avail / 2); 528 uart_console_write(uport, s + i, chars_to_write, 529 qcom_geni_serial_wr_char); 530 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + 531 SE_GENI_M_IRQ_CLEAR); 532 i += chars_to_write; 533 } 534 535 if (private_data->write_cached_bytes_cnt) { 536 private_data->write_cached_bytes >>= BITS_PER_BYTE * 537 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt); 538 writel(private_data->write_cached_bytes, 539 uport->membase + SE_GENI_TX_FIFOn); 540 private_data->write_cached_bytes_cnt = 0; 541 } 542 543 qcom_geni_serial_poll_tx_done(uport); 544 } 545 546 static void qcom_geni_serial_console_write(struct console *co, const char *s, 547 unsigned int count) 548 { 549 struct uart_port *uport; 550 struct qcom_geni_serial_port *port; 551 u32 m_irq_en, s_irq_en; 552 bool locked = true; 553 unsigned long flags; 554 555 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); 556 557 port = get_port_from_line(co->index, true); 558 if (IS_ERR(port)) 559 return; 560 561 uport = &port->uport; 562 if (oops_in_progress) 563 locked = uart_port_trylock_irqsave(uport, &flags); 564 else 565 uart_port_lock_irqsave(uport, &flags); 566 567 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 568 s_irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 569 writel(0, uport->membase + SE_GENI_M_IRQ_EN); 570 writel(0, uport->membase + SE_GENI_S_IRQ_EN); 571 572 if (qcom_geni_serial_main_active(uport)) { 573 /* Wait for completion or drain FIFO */ 574 if (!locked || port->tx_remaining == 0) 575 qcom_geni_serial_poll_tx_done(uport); 576 else 577 qcom_geni_serial_drain_fifo(uport); 578 579 qcom_geni_serial_cancel_tx_cmd(uport); 580 } 581 582 __qcom_geni_serial_console_write(uport, s, count); 583 584 writel(m_irq_en, uport->membase + SE_GENI_M_IRQ_EN); 585 writel(s_irq_en, uport->membase + SE_GENI_S_IRQ_EN); 586 587 if (locked) 588 uart_port_unlock_irqrestore(uport, flags); 589 } 590 591 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 592 { 593 u32 i; 594 unsigned char buf[sizeof(u32)]; 595 struct tty_port *tport; 596 struct qcom_geni_serial_port *port = to_dev_port(uport); 597 598 tport = &uport->state->port; 599 for (i = 0; i < bytes; ) { 600 int c; 601 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD); 602 603 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); 604 i += chunk; 605 if (drop) 606 continue; 607 608 for (c = 0; c < chunk; c++) { 609 int sysrq; 610 611 uport->icount.rx++; 612 if (port->brk && buf[c] == 0) { 613 port->brk = false; 614 if (uart_handle_break(uport)) 615 continue; 616 } 617 618 sysrq = uart_prepare_sysrq_char(uport, buf[c]); 619 620 if (!sysrq) 621 tty_insert_flip_char(tport, buf[c], TTY_NORMAL); 622 } 623 } 624 if (!drop) 625 tty_flip_buffer_push(tport); 626 } 627 #else 628 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 629 { 630 631 } 632 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 633 634 static void handle_rx_uart(struct uart_port *uport, u32 bytes) 635 { 636 struct qcom_geni_serial_port *port = to_dev_port(uport); 637 struct tty_port *tport = &uport->state->port; 638 int ret; 639 640 ret = tty_insert_flip_string(tport, port->rx_buf, bytes); 641 if (ret != bytes) { 642 dev_err_ratelimited(uport->dev, "failed to push data (%d < %u)\n", 643 ret, bytes); 644 } 645 uport->icount.rx += ret; 646 tty_flip_buffer_push(tport); 647 } 648 649 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport) 650 { 651 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 652 } 653 654 static void qcom_geni_serial_stop_tx_dma(struct uart_port *uport) 655 { 656 struct qcom_geni_serial_port *port = to_dev_port(uport); 657 bool done; 658 659 if (!qcom_geni_serial_main_active(uport)) 660 return; 661 662 if (port->tx_dma_addr) { 663 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, 664 port->tx_remaining); 665 port->tx_dma_addr = 0; 666 port->tx_remaining = 0; 667 } 668 669 geni_se_cancel_m_cmd(&port->se); 670 671 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 672 M_CMD_CANCEL_EN, true); 673 if (!done) { 674 geni_se_abort_m_cmd(&port->se); 675 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 676 M_CMD_ABORT_EN, true); 677 if (!done) 678 dev_err_ratelimited(uport->dev, "M_CMD_ABORT_EN not set"); 679 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 680 } 681 682 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 683 } 684 685 static void qcom_geni_serial_start_tx_dma(struct uart_port *uport) 686 { 687 struct qcom_geni_serial_port *port = to_dev_port(uport); 688 struct tty_port *tport = &uport->state->port; 689 unsigned int xmit_size; 690 u8 *tail; 691 int ret; 692 693 if (port->tx_dma_addr) 694 return; 695 696 if (kfifo_is_empty(&tport->xmit_fifo)) 697 return; 698 699 xmit_size = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, 700 UART_XMIT_SIZE); 701 702 qcom_geni_set_rs485_mode(uport, SER_RS485_RTS_ON_SEND); 703 704 qcom_geni_serial_setup_tx(uport, xmit_size); 705 706 ret = geni_se_tx_dma_prep(&port->se, tail, xmit_size, 707 &port->tx_dma_addr); 708 if (ret) { 709 dev_err(uport->dev, "unable to start TX SE DMA: %d\n", ret); 710 qcom_geni_serial_stop_tx_dma(uport); 711 return; 712 } 713 714 port->tx_remaining = xmit_size; 715 } 716 717 static void qcom_geni_serial_start_tx_fifo(struct uart_port *uport) 718 { 719 unsigned char c; 720 u32 irq_en; 721 722 /* 723 * Start a new transfer in case the previous command was cancelled and 724 * left data in the FIFO which may prevent the watermark interrupt 725 * from triggering. Note that the stale data is discarded. 726 */ 727 if (!qcom_geni_serial_main_active(uport) && 728 !qcom_geni_serial_tx_empty(uport)) { 729 if (uart_fifo_out(uport, &c, 1) == 1) { 730 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 731 qcom_geni_serial_setup_tx(uport, 1); 732 writel(c, uport->membase + SE_GENI_TX_FIFOn); 733 } 734 } 735 736 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 737 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; 738 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 739 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 740 } 741 742 static void qcom_geni_serial_stop_tx_fifo(struct uart_port *uport) 743 { 744 u32 irq_en; 745 746 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 747 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 748 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); 749 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 750 } 751 752 static void __qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport) 753 { 754 struct qcom_geni_serial_port *port = to_dev_port(uport); 755 756 geni_se_cancel_m_cmd(&port->se); 757 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 758 M_CMD_CANCEL_EN, true)) { 759 geni_se_abort_m_cmd(&port->se); 760 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 761 M_CMD_ABORT_EN, true); 762 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 763 } 764 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 765 } 766 767 static void qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport) 768 { 769 struct qcom_geni_serial_port *port = to_dev_port(uport); 770 771 if (!qcom_geni_serial_main_active(uport)) 772 return; 773 774 __qcom_geni_serial_cancel_tx_cmd(uport); 775 776 port->tx_remaining = 0; 777 port->tx_queued = 0; 778 } 779 780 static void qcom_geni_serial_handle_rx_fifo(struct uart_port *uport, bool drop) 781 { 782 u32 status; 783 u32 word_cnt; 784 u32 last_word_byte_cnt; 785 u32 last_word_partial; 786 u32 total_bytes; 787 788 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 789 word_cnt = status & RX_FIFO_WC_MSK; 790 last_word_partial = status & RX_LAST; 791 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >> 792 RX_LAST_BYTE_VALID_SHFT; 793 794 if (!word_cnt) 795 return; 796 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1); 797 if (last_word_partial && last_word_byte_cnt) 798 total_bytes += last_word_byte_cnt; 799 else 800 total_bytes += BYTES_PER_FIFO_WORD; 801 handle_rx_console(uport, total_bytes, drop); 802 } 803 804 static void qcom_geni_serial_stop_rx_fifo(struct uart_port *uport) 805 { 806 u32 irq_en; 807 struct qcom_geni_serial_port *port = to_dev_port(uport); 808 u32 s_irq_status; 809 810 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 811 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); 812 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 813 814 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 815 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 816 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 817 818 if (!qcom_geni_serial_secondary_active(uport)) 819 return; 820 821 geni_se_cancel_s_cmd(&port->se); 822 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 823 S_CMD_CANCEL_EN, true); 824 /* 825 * If timeout occurs secondary engine remains active 826 * and Abort sequence is executed. 827 */ 828 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 829 /* Flush the Rx buffer */ 830 if (s_irq_status & S_RX_FIFO_LAST_EN) 831 qcom_geni_serial_handle_rx_fifo(uport, true); 832 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 833 834 if (qcom_geni_serial_secondary_active(uport)) 835 qcom_geni_serial_abort_rx(uport); 836 } 837 838 static void qcom_geni_serial_start_rx_fifo(struct uart_port *uport) 839 { 840 u32 irq_en; 841 struct qcom_geni_serial_port *port = to_dev_port(uport); 842 843 if (qcom_geni_serial_secondary_active(uport)) 844 qcom_geni_serial_stop_rx_fifo(uport); 845 846 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); 847 848 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 849 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; 850 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 851 852 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 853 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 854 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 855 } 856 857 static void qcom_geni_serial_stop_rx_dma(struct uart_port *uport) 858 { 859 struct qcom_geni_serial_port *port = to_dev_port(uport); 860 bool done; 861 862 if (!qcom_geni_serial_secondary_active(uport)) 863 return; 864 865 geni_se_cancel_s_cmd(&port->se); 866 done = qcom_geni_serial_poll_bit(uport, SE_DMA_RX_IRQ_STAT, 867 RX_EOT, true); 868 if (done) { 869 writel(RX_EOT | RX_DMA_DONE, 870 uport->membase + SE_DMA_RX_IRQ_CLR); 871 } else { 872 qcom_geni_serial_abort_rx(uport); 873 874 writel(1, uport->membase + SE_DMA_RX_FSM_RST); 875 qcom_geni_serial_poll_bit(uport, SE_DMA_RX_IRQ_STAT, 876 RX_RESET_DONE, true); 877 writel(RX_RESET_DONE | RX_DMA_DONE, 878 uport->membase + SE_DMA_RX_IRQ_CLR); 879 } 880 881 if (port->rx_dma_addr) { 882 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, 883 DMA_RX_BUF_SIZE); 884 port->rx_dma_addr = 0; 885 } 886 } 887 888 static void qcom_geni_serial_start_rx_dma(struct uart_port *uport) 889 { 890 struct qcom_geni_serial_port *port = to_dev_port(uport); 891 int ret; 892 893 if (qcom_geni_serial_secondary_active(uport)) 894 qcom_geni_serial_stop_rx_dma(uport); 895 896 geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN); 897 898 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, 899 DMA_RX_BUF_SIZE, 900 &port->rx_dma_addr); 901 if (ret) { 902 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); 903 qcom_geni_serial_stop_rx_dma(uport); 904 } 905 } 906 907 static void qcom_geni_serial_handle_rx_dma(struct uart_port *uport, bool drop) 908 { 909 struct qcom_geni_serial_port *port = to_dev_port(uport); 910 u32 rx_in; 911 int ret; 912 913 if (!qcom_geni_serial_secondary_active(uport)) 914 return; 915 916 if (!port->rx_dma_addr) 917 return; 918 919 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE); 920 port->rx_dma_addr = 0; 921 922 rx_in = readl(uport->membase + SE_DMA_RX_LEN_IN); 923 if (!rx_in) { 924 dev_warn(uport->dev, "serial engine reports 0 RX bytes in!\n"); 925 return; 926 } 927 928 if (!drop) 929 handle_rx_uart(uport, rx_in); 930 931 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, 932 DMA_RX_BUF_SIZE, 933 &port->rx_dma_addr); 934 if (ret) { 935 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); 936 qcom_geni_serial_stop_rx_dma(uport); 937 } 938 } 939 940 static void qcom_geni_serial_start_rx(struct uart_port *uport) 941 { 942 uport->ops->start_rx(uport); 943 } 944 945 static void qcom_geni_serial_stop_rx(struct uart_port *uport) 946 { 947 uport->ops->stop_rx(uport); 948 } 949 950 static void qcom_geni_serial_stop_tx(struct uart_port *uport) 951 { 952 uport->ops->stop_tx(uport); 953 } 954 955 static void qcom_geni_serial_send_chunk_fifo(struct uart_port *uport, 956 unsigned int chunk) 957 { 958 struct qcom_geni_serial_port *port = to_dev_port(uport); 959 unsigned int tx_bytes, remaining = chunk; 960 u8 buf[BYTES_PER_FIFO_WORD]; 961 962 while (remaining) { 963 memset(buf, 0, sizeof(buf)); 964 tx_bytes = min(remaining, BYTES_PER_FIFO_WORD); 965 966 uart_fifo_out(uport, buf, tx_bytes); 967 968 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); 969 970 remaining -= tx_bytes; 971 port->tx_remaining -= tx_bytes; 972 } 973 } 974 975 static void qcom_geni_serial_handle_tx_fifo(struct uart_port *uport, 976 bool done, bool active) 977 { 978 struct qcom_geni_serial_port *port = to_dev_port(uport); 979 struct tty_port *tport = &uport->state->port; 980 size_t avail; 981 size_t pending; 982 u32 status; 983 u32 irq_en; 984 unsigned int chunk; 985 986 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 987 988 /* Complete the current tx command before taking newly added data */ 989 if (active) 990 pending = port->tx_remaining; 991 else 992 pending = kfifo_len(&tport->xmit_fifo); 993 994 /* All data has been transmitted or command has been cancelled */ 995 if (!pending && done) { 996 qcom_geni_serial_stop_tx_fifo(uport); 997 goto out_write_wakeup; 998 } 999 1000 if (active) 1001 avail = port->tx_fifo_depth - (status & TX_FIFO_WC); 1002 else 1003 avail = port->tx_fifo_depth; 1004 1005 avail *= BYTES_PER_FIFO_WORD; 1006 1007 chunk = min(avail, pending); 1008 if (!chunk) 1009 goto out_write_wakeup; 1010 1011 if (!active) { 1012 qcom_geni_serial_setup_tx(uport, pending); 1013 port->tx_remaining = pending; 1014 port->tx_queued = 0; 1015 1016 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 1017 if (!(irq_en & M_TX_FIFO_WATERMARK_EN)) 1018 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 1019 uport->membase + SE_GENI_M_IRQ_EN); 1020 } 1021 1022 qcom_geni_serial_send_chunk_fifo(uport, chunk); 1023 port->tx_queued += chunk; 1024 1025 /* 1026 * The tx fifo watermark is level triggered and latched. Though we had 1027 * cleared it in qcom_geni_serial_isr it will have already reasserted 1028 * so we must clear it again here after our writes. 1029 */ 1030 writel(M_TX_FIFO_WATERMARK_EN, 1031 uport->membase + SE_GENI_M_IRQ_CLEAR); 1032 1033 out_write_wakeup: 1034 if (!port->tx_remaining) { 1035 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 1036 if (irq_en & M_TX_FIFO_WATERMARK_EN) 1037 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN, 1038 uport->membase + SE_GENI_M_IRQ_EN); 1039 } 1040 1041 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1042 uart_write_wakeup(uport); 1043 } 1044 1045 static void qcom_geni_serial_handle_tx_dma(struct uart_port *uport) 1046 { 1047 struct qcom_geni_serial_port *port = to_dev_port(uport); 1048 struct tty_port *tport = &uport->state->port; 1049 1050 uart_xmit_advance(uport, port->tx_remaining); 1051 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining); 1052 port->tx_dma_addr = 0; 1053 port->tx_remaining = 0; 1054 1055 if (!kfifo_is_empty(&tport->xmit_fifo)) 1056 qcom_geni_serial_start_tx_dma(uport); 1057 1058 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1059 uart_write_wakeup(uport); 1060 } 1061 1062 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) 1063 { 1064 u32 m_irq_en; 1065 u32 m_irq_status; 1066 u32 s_irq_status; 1067 u32 geni_status; 1068 u32 dma; 1069 u32 dma_tx_status; 1070 u32 dma_rx_status; 1071 struct uart_port *uport = dev; 1072 bool drop_rx = false; 1073 struct tty_port *tport = &uport->state->port; 1074 struct qcom_geni_serial_port *port = to_dev_port(uport); 1075 1076 if (uport->suspended) 1077 return IRQ_NONE; 1078 1079 uart_port_lock(uport); 1080 1081 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 1082 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 1083 dma_tx_status = readl(uport->membase + SE_DMA_TX_IRQ_STAT); 1084 dma_rx_status = readl(uport->membase + SE_DMA_RX_IRQ_STAT); 1085 geni_status = readl(uport->membase + SE_GENI_STATUS); 1086 dma = readl(uport->membase + SE_GENI_DMA_MODE_EN); 1087 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 1088 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); 1089 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 1090 writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR); 1091 writel(dma_rx_status, uport->membase + SE_DMA_RX_IRQ_CLR); 1092 1093 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN)) 1094 goto out_unlock; 1095 1096 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) { 1097 uport->icount.overrun++; 1098 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 1099 } 1100 1101 if (s_irq_status & (S_GP_IRQ_0_EN | S_GP_IRQ_1_EN)) { 1102 if (s_irq_status & S_GP_IRQ_0_EN) 1103 uport->icount.parity++; 1104 drop_rx = true; 1105 } else if (s_irq_status & (S_GP_IRQ_2_EN | S_GP_IRQ_3_EN)) { 1106 uport->icount.brk++; 1107 port->brk = true; 1108 } 1109 1110 if (dma) { 1111 if (dma_tx_status & TX_DMA_DONE) { 1112 qcom_geni_serial_handle_tx_dma(uport); 1113 qcom_geni_set_rs485_mode(uport, SER_RS485_RTS_AFTER_SEND); 1114 } 1115 1116 if (dma_rx_status) { 1117 if (dma_rx_status & RX_RESET_DONE) 1118 goto out_unlock; 1119 1120 if (dma_rx_status & RX_DMA_PARITY_ERR) { 1121 uport->icount.parity++; 1122 drop_rx = true; 1123 } 1124 1125 if (dma_rx_status & RX_DMA_BREAK) 1126 uport->icount.brk++; 1127 1128 if (dma_rx_status & (RX_DMA_DONE | RX_EOT)) 1129 qcom_geni_serial_handle_rx_dma(uport, drop_rx); 1130 } 1131 } else { 1132 if (m_irq_status & m_irq_en & 1133 (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) 1134 qcom_geni_serial_handle_tx_fifo(uport, 1135 m_irq_status & M_CMD_DONE_EN, 1136 geni_status & M_GENI_CMD_ACTIVE); 1137 1138 if (s_irq_status & (S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN)) 1139 qcom_geni_serial_handle_rx_fifo(uport, drop_rx); 1140 } 1141 1142 out_unlock: 1143 uart_unlock_and_check_sysrq(uport); 1144 1145 return IRQ_HANDLED; 1146 } 1147 1148 static int setup_fifos(struct qcom_geni_serial_port *port) 1149 { 1150 struct uart_port *uport; 1151 u32 old_rx_fifo_depth = port->rx_fifo_depth; 1152 1153 uport = &port->uport; 1154 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); 1155 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); 1156 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); 1157 uport->fifosize = 1158 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; 1159 1160 if (port->rx_buf && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) { 1161 /* 1162 * Use krealloc rather than krealloc_array because rx_buf is 1163 * accessed as 1 byte entries as well as 4 byte entries so it's 1164 * not necessarily an array. 1165 */ 1166 port->rx_buf = devm_krealloc(uport->dev, port->rx_buf, 1167 port->rx_fifo_depth * sizeof(u32), 1168 GFP_KERNEL); 1169 if (!port->rx_buf) 1170 return -ENOMEM; 1171 } 1172 1173 return 0; 1174 } 1175 1176 1177 static void qcom_geni_serial_shutdown(struct uart_port *uport) 1178 { 1179 disable_irq(uport->irq); 1180 1181 uart_port_lock_irq(uport); 1182 qcom_geni_serial_stop_tx(uport); 1183 qcom_geni_serial_stop_rx(uport); 1184 1185 qcom_geni_serial_cancel_tx_cmd(uport); 1186 uart_port_unlock_irq(uport); 1187 } 1188 1189 static void qcom_geni_serial_flush_buffer(struct uart_port *uport) 1190 { 1191 qcom_geni_serial_cancel_tx_cmd(uport); 1192 } 1193 1194 static int qcom_geni_serial_port_setup(struct uart_port *uport) 1195 { 1196 struct qcom_geni_serial_port *port = to_dev_port(uport); 1197 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT; 1198 u32 proto; 1199 u32 pin_swap; 1200 int ret; 1201 1202 proto = geni_se_read_proto(&port->se); 1203 if (proto != GENI_SE_UART) { 1204 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); 1205 return -ENXIO; 1206 } 1207 1208 qcom_geni_serial_stop_rx(uport); 1209 1210 ret = setup_fifos(port); 1211 if (ret) 1212 return ret; 1213 1214 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); 1215 1216 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL); 1217 if (port->rx_tx_swap) { 1218 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK; 1219 pin_swap |= IO_MACRO_IO2_IO3_SWAP; 1220 } 1221 if (port->cts_rts_swap) { 1222 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK; 1223 pin_swap |= IO_MACRO_IO0_SEL; 1224 } 1225 /* Configure this register if RX-TX, CTS-RTS pins are swapped */ 1226 if (port->rx_tx_swap || port->cts_rts_swap) 1227 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL); 1228 1229 /* 1230 * Make an unconditional cancel on the main sequencer to reset 1231 * it else we could end up in data loss scenarios. 1232 */ 1233 if (uart_console(uport)) 1234 qcom_geni_serial_poll_tx_done(uport); 1235 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1236 false, true, true); 1237 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); 1238 geni_se_select_mode(&port->se, port->dev_data->mode); 1239 port->setup = true; 1240 1241 return 0; 1242 } 1243 1244 static int qcom_geni_serial_startup(struct uart_port *uport) 1245 { 1246 int ret; 1247 struct qcom_geni_serial_port *port = to_dev_port(uport); 1248 1249 if (!port->setup) { 1250 ret = qcom_geni_serial_port_setup(uport); 1251 if (ret) 1252 return ret; 1253 } 1254 1255 uart_port_lock_irq(uport); 1256 qcom_geni_serial_start_rx(uport); 1257 uart_port_unlock_irq(uport); 1258 1259 enable_irq(uport->irq); 1260 1261 return 0; 1262 } 1263 1264 static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int desired_clk, 1265 unsigned int *clk_div, unsigned int percent_tol) 1266 { 1267 unsigned long freq; 1268 unsigned long div, maxdiv; 1269 u64 mult; 1270 unsigned long offset, abs_tol, achieved; 1271 1272 abs_tol = div_u64((u64)desired_clk * percent_tol, 100); 1273 maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT; 1274 div = 1; 1275 while (div <= maxdiv) { 1276 mult = (u64)div * desired_clk; 1277 if (mult != (unsigned long)mult) 1278 break; 1279 1280 offset = div * abs_tol; 1281 freq = clk_round_rate(clk, mult - offset); 1282 1283 /* Can only get lower if we're done */ 1284 if (freq < mult - offset) 1285 break; 1286 1287 /* 1288 * Re-calculate div in case rounding skipped rates but we 1289 * ended up at a good one, then check for a match. 1290 */ 1291 div = DIV_ROUND_CLOSEST(freq, desired_clk); 1292 achieved = DIV_ROUND_CLOSEST(freq, div); 1293 if (achieved <= desired_clk + abs_tol && 1294 achieved >= desired_clk - abs_tol) { 1295 *clk_div = div; 1296 return freq; 1297 } 1298 1299 div = DIV_ROUND_UP(freq, desired_clk); 1300 } 1301 1302 return 0; 1303 } 1304 1305 static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud, 1306 unsigned int sampling_rate, unsigned int *clk_div) 1307 { 1308 unsigned long ser_clk; 1309 unsigned long desired_clk; 1310 1311 desired_clk = baud * sampling_rate; 1312 if (!desired_clk) 1313 return 0; 1314 1315 /* 1316 * try to find a clock rate within 2% tolerance, then within 5% 1317 */ 1318 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2); 1319 if (!ser_clk) 1320 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5); 1321 1322 return ser_clk; 1323 } 1324 1325 static int geni_serial_set_rate(struct uart_port *uport, unsigned int baud) 1326 { 1327 struct qcom_geni_serial_port *port = to_dev_port(uport); 1328 unsigned long clk_rate; 1329 unsigned int avg_bw_core; 1330 unsigned int clk_div; 1331 u32 ver, sampling_rate; 1332 u32 ser_clk_cfg; 1333 1334 sampling_rate = UART_OVERSAMPLING; 1335 /* Sampling rate is halved for IP versions >= 2.5 */ 1336 ver = geni_se_get_qup_hw_version(&port->se); 1337 if (ver >= QUP_SE_VERSION_2_5) 1338 sampling_rate /= 2; 1339 1340 clk_rate = get_clk_div_rate(port->se.clk, baud, 1341 sampling_rate, &clk_div); 1342 if (!clk_rate) { 1343 dev_err(port->se.dev, 1344 "Couldn't find suitable clock rate for %u\n", 1345 baud * sampling_rate); 1346 return -EINVAL; 1347 } 1348 1349 dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n", 1350 baud * sampling_rate, clk_rate, clk_div); 1351 1352 uport->uartclk = clk_rate; 1353 port->clk_rate = clk_rate; 1354 dev_pm_opp_set_rate(uport->dev, clk_rate); 1355 ser_clk_cfg = SER_CLK_EN; 1356 ser_clk_cfg |= clk_div << CLK_DIV_SHFT; 1357 1358 /* 1359 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode 1360 * only. 1361 */ 1362 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ) 1363 : GENI_DEFAULT_BW; 1364 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core; 1365 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); 1366 geni_icc_set_bw(&port->se); 1367 1368 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); 1369 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); 1370 return 0; 1371 } 1372 1373 static int geni_serial_set_level(struct uart_port *uport, unsigned int baud) 1374 { 1375 struct qcom_geni_serial_port *port = to_dev_port(uport); 1376 struct device *perf_dev = port->pd_list->pd_devs[DOMAIN_IDX_PERF]; 1377 1378 /* 1379 * The performance protocol sets UART communication 1380 * speeds by selecting different performance levels 1381 * through the OPP framework. 1382 * 1383 * Supported perf levels for baudrates in firmware are below 1384 * +---------------------+--------------------+ 1385 * | Perf level value | Baudrate values | 1386 * +---------------------+--------------------+ 1387 * | 300 | 300 | 1388 * | 1200 | 1200 | 1389 * | 2400 | 2400 | 1390 * | 4800 | 4800 | 1391 * | 9600 | 9600 | 1392 * | 19200 | 19200 | 1393 * | 38400 | 38400 | 1394 * | 57600 | 57600 | 1395 * | 115200 | 115200 | 1396 * | 230400 | 230400 | 1397 * | 460800 | 460800 | 1398 * | 921600 | 921600 | 1399 * | 2000000 | 2000000 | 1400 * | 3000000 | 3000000 | 1401 * | 3200000 | 3200000 | 1402 * | 4000000 | 4000000 | 1403 * +---------------------+--------------------+ 1404 */ 1405 1406 return dev_pm_opp_set_level(perf_dev, baud); 1407 } 1408 1409 static void qcom_geni_serial_set_termios(struct uart_port *uport, 1410 struct ktermios *termios, 1411 const struct ktermios *old) 1412 { 1413 struct qcom_geni_serial_port *port = to_dev_port(uport); 1414 unsigned int baud; 1415 unsigned long timeout; 1416 u32 bits_per_char; 1417 u32 tx_trans_cfg; 1418 u32 tx_parity_cfg; 1419 u32 rx_trans_cfg; 1420 u32 rx_parity_cfg; 1421 u32 stop_bit_len; 1422 int ret = 0; 1423 1424 /* baud rate */ 1425 baud = uart_get_baud_rate(uport, termios, old, 300, 8000000); 1426 1427 ret = port->dev_data->set_rate(uport, baud); 1428 if (ret) 1429 return; 1430 1431 /* parity */ 1432 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); 1433 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); 1434 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG); 1435 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG); 1436 if (termios->c_cflag & PARENB) { 1437 tx_trans_cfg |= UART_TX_PAR_EN; 1438 rx_trans_cfg |= UART_RX_PAR_EN; 1439 tx_parity_cfg |= PAR_CALC_EN; 1440 rx_parity_cfg |= PAR_CALC_EN; 1441 if (termios->c_cflag & PARODD) { 1442 tx_parity_cfg |= PAR_ODD; 1443 rx_parity_cfg |= PAR_ODD; 1444 } else if (termios->c_cflag & CMSPAR) { 1445 tx_parity_cfg |= PAR_SPACE; 1446 rx_parity_cfg |= PAR_SPACE; 1447 } else { 1448 tx_parity_cfg |= PAR_EVEN; 1449 rx_parity_cfg |= PAR_EVEN; 1450 } 1451 } else { 1452 tx_trans_cfg &= ~UART_TX_PAR_EN; 1453 rx_trans_cfg &= ~UART_RX_PAR_EN; 1454 tx_parity_cfg &= ~PAR_CALC_EN; 1455 rx_parity_cfg &= ~PAR_CALC_EN; 1456 } 1457 1458 /* bits per char */ 1459 bits_per_char = tty_get_char_size(termios->c_cflag); 1460 1461 /* stop bits */ 1462 if (termios->c_cflag & CSTOPB) 1463 stop_bit_len = TX_STOP_BIT_LEN_2; 1464 else 1465 stop_bit_len = TX_STOP_BIT_LEN_1; 1466 1467 /* flow control, clear the CTS_MASK bit if using flow control. */ 1468 if (termios->c_cflag & CRTSCTS) 1469 tx_trans_cfg &= ~UART_CTS_MASK; 1470 else 1471 tx_trans_cfg |= UART_CTS_MASK; 1472 1473 if (baud) { 1474 uart_update_timeout(uport, termios->c_cflag, baud); 1475 1476 /* 1477 * Make sure that qcom_geni_serial_poll_bitfield() waits for 1478 * the FIFO, two-word intermediate transfer register and shift 1479 * register to clear. 1480 * 1481 * Note that uart_fifo_timeout() also adds a 20 ms margin. 1482 */ 1483 timeout = jiffies_to_usecs(uart_fifo_timeout(uport)); 1484 timeout += 3 * timeout / port->tx_fifo_depth; 1485 WRITE_ONCE(port->poll_timeout_us, timeout); 1486 } 1487 1488 if (!uart_console(uport)) 1489 writel(port->loopback, 1490 uport->membase + SE_UART_LOOPBACK_CFG); 1491 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1492 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1493 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1494 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1495 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1496 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1497 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1498 } 1499 1500 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 1501 static int qcom_geni_console_setup(struct console *co, char *options) 1502 { 1503 struct uart_port *uport; 1504 struct qcom_geni_serial_port *port; 1505 int baud = 115200; 1506 int bits = 8; 1507 int parity = 'n'; 1508 int flow = 'n'; 1509 int ret; 1510 1511 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) 1512 return -ENXIO; 1513 1514 port = get_port_from_line(co->index, true); 1515 if (IS_ERR(port)) { 1516 pr_err("Invalid line %d\n", co->index); 1517 return PTR_ERR(port); 1518 } 1519 1520 uport = &port->uport; 1521 1522 if (unlikely(!uport->membase)) 1523 return -ENXIO; 1524 1525 if (!port->setup) { 1526 ret = qcom_geni_serial_port_setup(uport); 1527 if (ret) 1528 return ret; 1529 } 1530 1531 if (options) 1532 uart_parse_options(options, &baud, &parity, &bits, &flow); 1533 1534 return uart_set_options(uport, co, baud, parity, bits, flow); 1535 } 1536 1537 static void qcom_geni_serial_earlycon_write(struct console *con, 1538 const char *s, unsigned int n) 1539 { 1540 struct earlycon_device *dev = con->data; 1541 1542 __qcom_geni_serial_console_write(&dev->port, s, n); 1543 } 1544 1545 #ifdef CONFIG_CONSOLE_POLL 1546 static int qcom_geni_serial_earlycon_read(struct console *con, 1547 char *s, unsigned int n) 1548 { 1549 struct earlycon_device *dev = con->data; 1550 struct uart_port *uport = &dev->port; 1551 int num_read = 0; 1552 int ch; 1553 1554 while (num_read < n) { 1555 ch = qcom_geni_serial_get_char(uport); 1556 if (ch == NO_POLL_CHAR) 1557 break; 1558 s[num_read++] = ch; 1559 } 1560 1561 return num_read; 1562 } 1563 1564 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se, 1565 struct console *con) 1566 { 1567 geni_se_setup_s_cmd(se, UART_START_READ, 0); 1568 con->read = qcom_geni_serial_earlycon_read; 1569 } 1570 #else 1571 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se, 1572 struct console *con) { } 1573 #endif 1574 1575 static struct qcom_geni_private_data earlycon_private_data; 1576 1577 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev, 1578 const char *opt) 1579 { 1580 struct uart_port *uport = &dev->port; 1581 u32 tx_trans_cfg; 1582 u32 tx_parity_cfg = 0; /* Disable Tx Parity */ 1583 u32 rx_trans_cfg = 0; 1584 u32 rx_parity_cfg = 0; /* Disable Rx Parity */ 1585 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ 1586 u32 bits_per_char; 1587 struct geni_se se; 1588 1589 if (!uport->membase) 1590 return -EINVAL; 1591 1592 uport->private_data = &earlycon_private_data; 1593 1594 memset(&se, 0, sizeof(se)); 1595 se.base = uport->membase; 1596 if (geni_se_read_proto(&se) != GENI_SE_UART) 1597 return -ENXIO; 1598 /* 1599 * Ignore Flow control. 1600 * n = 8. 1601 */ 1602 tx_trans_cfg = UART_CTS_MASK; 1603 bits_per_char = BITS_PER_BYTE; 1604 1605 /* 1606 * Make an unconditional cancel on the main sequencer to reset 1607 * it else we could end up in data loss scenarios. 1608 */ 1609 qcom_geni_serial_poll_tx_done(uport); 1610 qcom_geni_serial_abort_rx(uport); 1611 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1612 false, true, true); 1613 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); 1614 geni_se_select_mode(&se, GENI_SE_FIFO); 1615 1616 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1617 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1618 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1619 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1620 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1621 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1622 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1623 1624 dev->con->write = qcom_geni_serial_earlycon_write; 1625 dev->con->setup = NULL; 1626 qcom_geni_serial_enable_early_read(&se, dev->con); 1627 1628 return 0; 1629 } 1630 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart", 1631 qcom_geni_serial_earlycon_setup); 1632 1633 static int __init console_register(struct uart_driver *drv) 1634 { 1635 return uart_register_driver(drv); 1636 } 1637 1638 static void console_unregister(struct uart_driver *drv) 1639 { 1640 uart_unregister_driver(drv); 1641 } 1642 1643 static struct console cons_ops = { 1644 .name = "ttyMSM", 1645 .write = qcom_geni_serial_console_write, 1646 .device = uart_console_device, 1647 .setup = qcom_geni_console_setup, 1648 .flags = CON_PRINTBUFFER, 1649 .index = -1, 1650 .data = &qcom_geni_console_driver, 1651 }; 1652 1653 static struct uart_driver qcom_geni_console_driver = { 1654 .owner = THIS_MODULE, 1655 .driver_name = "qcom_geni_console", 1656 .dev_name = "ttyMSM", 1657 .nr = GENI_UART_CONS_PORTS, 1658 .cons = &cons_ops, 1659 }; 1660 #else 1661 static int console_register(struct uart_driver *drv) 1662 { 1663 return 0; 1664 } 1665 1666 static void console_unregister(struct uart_driver *drv) 1667 { 1668 } 1669 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 1670 1671 static struct uart_driver qcom_geni_uart_driver = { 1672 .owner = THIS_MODULE, 1673 .driver_name = "qcom_geni_uart", 1674 .dev_name = "ttyHS", 1675 .nr = GENI_UART_PORTS, 1676 }; 1677 1678 static int geni_serial_resources_on(struct uart_port *uport) 1679 { 1680 struct qcom_geni_serial_port *port = to_dev_port(uport); 1681 int ret; 1682 1683 ret = geni_icc_enable(&port->se); 1684 if (ret) 1685 return ret; 1686 1687 ret = geni_se_resources_on(&port->se); 1688 if (ret) { 1689 geni_icc_disable(&port->se); 1690 return ret; 1691 } 1692 1693 if (port->clk_rate) 1694 dev_pm_opp_set_rate(uport->dev, port->clk_rate); 1695 1696 return 0; 1697 } 1698 1699 static int geni_serial_resources_off(struct uart_port *uport) 1700 { 1701 struct qcom_geni_serial_port *port = to_dev_port(uport); 1702 int ret; 1703 1704 dev_pm_opp_set_rate(uport->dev, 0); 1705 ret = geni_se_resources_off(&port->se); 1706 if (ret) 1707 return ret; 1708 1709 geni_icc_disable(&port->se); 1710 1711 return 0; 1712 } 1713 1714 static int geni_serial_resource_state(struct uart_port *uport, bool power_on) 1715 { 1716 return power_on ? geni_serial_resources_on(uport) : geni_serial_resources_off(uport); 1717 } 1718 1719 static int geni_serial_pwr_init(struct uart_port *uport) 1720 { 1721 struct qcom_geni_serial_port *port = to_dev_port(uport); 1722 int ret; 1723 1724 ret = dev_pm_domain_attach_list(port->se.dev, 1725 &port->dev_data->pd_data, &port->pd_list); 1726 if (ret <= 0) 1727 return -EINVAL; 1728 1729 return 0; 1730 } 1731 1732 static int geni_serial_resource_init(struct uart_port *uport) 1733 { 1734 struct qcom_geni_serial_port *port = to_dev_port(uport); 1735 int ret; 1736 1737 port->se.clk = devm_clk_get(port->se.dev, "se"); 1738 if (IS_ERR(port->se.clk)) { 1739 ret = PTR_ERR(port->se.clk); 1740 dev_err(port->se.dev, "Err getting SE Core clk %d\n", ret); 1741 return ret; 1742 } 1743 1744 ret = geni_icc_get(&port->se, NULL); 1745 if (ret) 1746 return ret; 1747 1748 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; 1749 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 1750 1751 /* Set BW for register access */ 1752 ret = geni_icc_set_bw(&port->se); 1753 if (ret) 1754 return ret; 1755 1756 ret = devm_pm_opp_set_clkname(port->se.dev, "se"); 1757 if (ret) 1758 return ret; 1759 1760 /* OPP table is optional */ 1761 ret = devm_pm_opp_of_add_table(port->se.dev); 1762 if (ret && ret != -ENODEV) { 1763 dev_err(port->se.dev, "invalid OPP table in device tree\n"); 1764 return ret; 1765 } 1766 1767 return 0; 1768 } 1769 1770 static void qcom_geni_serial_pm(struct uart_port *uport, 1771 unsigned int new_state, unsigned int old_state) 1772 { 1773 1774 /* If we've never been called, treat it as off */ 1775 if (old_state == UART_PM_STATE_UNDEFINED) 1776 old_state = UART_PM_STATE_OFF; 1777 1778 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) 1779 pm_runtime_resume_and_get(uport->dev); 1780 else if (new_state == UART_PM_STATE_OFF && 1781 old_state == UART_PM_STATE_ON) 1782 pm_runtime_put_sync(uport->dev); 1783 1784 } 1785 1786 /** 1787 * qcom_geni_rs485_config - Configure RS485 settings for the UART port 1788 * @uport: Pointer to the UART port structure 1789 * @termios: Pointer to the termios structure 1790 * @rs485: Pointer to the RS485 configuration structure 1791 * This function configures the RTS (Request to Send) pin behavior for RS485 mode. 1792 * When RS485 mode is enabled, the RTS pin is kept in default ACTIVE HIGH state. 1793 * Return: Always returns 0. 1794 */ 1795 1796 static int qcom_geni_rs485_config(struct uart_port *uport, 1797 struct ktermios *termios, struct serial_rs485 *rs485) 1798 { 1799 qcom_geni_set_rs485_mode(uport, SER_RS485_ENABLED); 1800 1801 return 0; 1802 } 1803 1804 static const struct uart_ops qcom_geni_console_pops = { 1805 .tx_empty = qcom_geni_serial_tx_empty, 1806 .stop_tx = qcom_geni_serial_stop_tx_fifo, 1807 .start_tx = qcom_geni_serial_start_tx_fifo, 1808 .stop_rx = qcom_geni_serial_stop_rx_fifo, 1809 .start_rx = qcom_geni_serial_start_rx_fifo, 1810 .set_termios = qcom_geni_serial_set_termios, 1811 .startup = qcom_geni_serial_startup, 1812 .request_port = qcom_geni_serial_request_port, 1813 .config_port = qcom_geni_serial_config_port, 1814 .shutdown = qcom_geni_serial_shutdown, 1815 .flush_buffer = qcom_geni_serial_flush_buffer, 1816 .type = qcom_geni_serial_get_type, 1817 .set_mctrl = qcom_geni_serial_set_mctrl, 1818 .get_mctrl = qcom_geni_serial_get_mctrl, 1819 #ifdef CONFIG_CONSOLE_POLL 1820 .poll_get_char = qcom_geni_serial_get_char, 1821 .poll_put_char = qcom_geni_serial_poll_put_char, 1822 .poll_init = qcom_geni_serial_poll_init, 1823 #endif 1824 .pm = qcom_geni_serial_pm, 1825 }; 1826 1827 static const struct uart_ops qcom_geni_uart_pops = { 1828 .tx_empty = qcom_geni_serial_tx_empty, 1829 .stop_tx = qcom_geni_serial_stop_tx_dma, 1830 .start_tx = qcom_geni_serial_start_tx_dma, 1831 .start_rx = qcom_geni_serial_start_rx_dma, 1832 .stop_rx = qcom_geni_serial_stop_rx_dma, 1833 .set_termios = qcom_geni_serial_set_termios, 1834 .startup = qcom_geni_serial_startup, 1835 .request_port = qcom_geni_serial_request_port, 1836 .config_port = qcom_geni_serial_config_port, 1837 .shutdown = qcom_geni_serial_shutdown, 1838 .type = qcom_geni_serial_get_type, 1839 .set_mctrl = qcom_geni_serial_set_mctrl, 1840 .get_mctrl = qcom_geni_serial_get_mctrl, 1841 .pm = qcom_geni_serial_pm, 1842 }; 1843 1844 static int qcom_geni_serial_probe(struct platform_device *pdev) 1845 { 1846 int ret = 0; 1847 int line; 1848 struct qcom_geni_serial_port *port; 1849 struct uart_port *uport; 1850 struct resource *res; 1851 int irq; 1852 struct uart_driver *drv; 1853 const struct qcom_geni_device_data *data; 1854 1855 data = of_device_get_match_data(&pdev->dev); 1856 if (!data) 1857 return -EINVAL; 1858 1859 if (data->console) { 1860 drv = &qcom_geni_console_driver; 1861 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1862 } else { 1863 drv = &qcom_geni_uart_driver; 1864 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1865 if (line == -ENODEV) /* compat with non-standard aliases */ 1866 line = of_alias_get_id(pdev->dev.of_node, "hsuart"); 1867 } 1868 1869 port = get_port_from_line(line, data->console); 1870 if (IS_ERR(port)) { 1871 dev_err(&pdev->dev, "Invalid line %d\n", line); 1872 return PTR_ERR(port); 1873 } 1874 1875 uport = &port->uport; 1876 /* Don't allow 2 drivers to access the same port */ 1877 if (uport->private_data) 1878 return -ENODEV; 1879 1880 uport->dev = &pdev->dev; 1881 port->dev_data = data; 1882 port->se.dev = &pdev->dev; 1883 port->se.wrapper = dev_get_drvdata(pdev->dev.parent); 1884 1885 ret = port->dev_data->resources_init(uport); 1886 if (ret) 1887 return ret; 1888 1889 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1890 if (!res) { 1891 ret = -EINVAL; 1892 goto error; 1893 } 1894 1895 uport->mapbase = res->start; 1896 1897 uport->rs485_config = qcom_geni_rs485_config; 1898 uport->rs485_supported = qcom_geni_rs485_supported; 1899 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1900 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1901 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; 1902 1903 if (!data->console) { 1904 port->rx_buf = devm_kzalloc(uport->dev, 1905 DMA_RX_BUF_SIZE, GFP_KERNEL); 1906 if (!port->rx_buf) { 1907 ret = -ENOMEM; 1908 goto error; 1909 } 1910 } 1911 1912 port->name = devm_kasprintf(uport->dev, GFP_KERNEL, 1913 "qcom_geni_serial_%s%d", 1914 uart_console(uport) ? "console" : "uart", uport->line); 1915 if (!port->name) { 1916 ret = -ENOMEM; 1917 goto error; 1918 } 1919 1920 irq = platform_get_irq(pdev, 0); 1921 if (irq < 0) { 1922 ret = irq; 1923 goto error; 1924 } 1925 1926 uport->irq = irq; 1927 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); 1928 1929 if (!data->console) 1930 port->wakeup_irq = platform_get_irq_optional(pdev, 1); 1931 1932 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap")) 1933 port->rx_tx_swap = true; 1934 1935 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) 1936 port->cts_rts_swap = true; 1937 1938 port->private_data.drv = drv; 1939 uport->private_data = &port->private_data; 1940 platform_set_drvdata(pdev, port); 1941 1942 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); 1943 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, 1944 IRQF_TRIGGER_HIGH, port->name, uport); 1945 if (ret) { 1946 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); 1947 goto error; 1948 } 1949 1950 ret = uart_get_rs485_mode(uport); 1951 if (ret) 1952 return ret; 1953 1954 devm_pm_runtime_enable(port->se.dev); 1955 1956 ret = uart_add_one_port(drv, uport); 1957 if (ret) 1958 goto error; 1959 1960 if (port->wakeup_irq > 0) { 1961 device_init_wakeup(&pdev->dev, true); 1962 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1963 port->wakeup_irq); 1964 if (ret) { 1965 device_init_wakeup(&pdev->dev, false); 1966 ida_free(&port_ida, uport->line); 1967 uart_remove_one_port(drv, uport); 1968 goto error; 1969 } 1970 } 1971 1972 return 0; 1973 1974 error: 1975 dev_pm_domain_detach_list(port->pd_list); 1976 return ret; 1977 } 1978 1979 static void qcom_geni_serial_remove(struct platform_device *pdev) 1980 { 1981 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); 1982 struct uart_port *uport = &port->uport; 1983 struct uart_driver *drv = port->private_data.drv; 1984 1985 dev_pm_clear_wake_irq(&pdev->dev); 1986 device_init_wakeup(&pdev->dev, false); 1987 ida_free(&port_ida, uport->line); 1988 uart_remove_one_port(drv, &port->uport); 1989 dev_pm_domain_detach_list(port->pd_list); 1990 } 1991 1992 static int __maybe_unused qcom_geni_serial_runtime_suspend(struct device *dev) 1993 { 1994 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1995 struct uart_port *uport = &port->uport; 1996 int ret = 0; 1997 1998 if (port->dev_data->power_state) 1999 ret = port->dev_data->power_state(uport, false); 2000 2001 return ret; 2002 } 2003 2004 static int __maybe_unused qcom_geni_serial_runtime_resume(struct device *dev) 2005 { 2006 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 2007 struct uart_port *uport = &port->uport; 2008 int ret = 0; 2009 2010 if (port->dev_data->power_state) 2011 ret = port->dev_data->power_state(uport, true); 2012 2013 return ret; 2014 } 2015 2016 static int qcom_geni_serial_suspend(struct device *dev) 2017 { 2018 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 2019 struct uart_port *uport = &port->uport; 2020 struct qcom_geni_private_data *private_data = uport->private_data; 2021 2022 /* 2023 * This is done so we can hit the lowest possible state in suspend 2024 * even with no_console_suspend 2025 */ 2026 if (uart_console(uport)) { 2027 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY); 2028 geni_icc_set_bw(&port->se); 2029 } 2030 return uart_suspend_port(private_data->drv, uport); 2031 } 2032 2033 static int qcom_geni_serial_resume(struct device *dev) 2034 { 2035 int ret; 2036 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 2037 struct uart_port *uport = &port->uport; 2038 struct qcom_geni_private_data *private_data = uport->private_data; 2039 2040 ret = uart_resume_port(private_data->drv, uport); 2041 if (uart_console(uport)) { 2042 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); 2043 geni_icc_set_bw(&port->se); 2044 } 2045 return ret; 2046 } 2047 2048 static const struct qcom_geni_device_data qcom_geni_console_data = { 2049 .console = true, 2050 .mode = GENI_SE_FIFO, 2051 .resources_init = geni_serial_resource_init, 2052 .set_rate = geni_serial_set_rate, 2053 .power_state = geni_serial_resource_state, 2054 }; 2055 2056 static const struct qcom_geni_device_data qcom_geni_uart_data = { 2057 .console = false, 2058 .mode = GENI_SE_DMA, 2059 .resources_init = geni_serial_resource_init, 2060 .set_rate = geni_serial_set_rate, 2061 .power_state = geni_serial_resource_state, 2062 }; 2063 2064 static const struct qcom_geni_device_data sa8255p_qcom_geni_console_data = { 2065 .console = true, 2066 .mode = GENI_SE_FIFO, 2067 .pd_data = { 2068 .pd_flags = PD_FLAG_DEV_LINK_ON, 2069 .pd_names = (const char*[]) { "power", "perf" }, 2070 .num_pd_names = 2, 2071 }, 2072 .resources_init = geni_serial_pwr_init, 2073 .set_rate = geni_serial_set_level, 2074 }; 2075 2076 static const struct qcom_geni_device_data sa8255p_qcom_geni_uart_data = { 2077 .console = false, 2078 .mode = GENI_SE_DMA, 2079 .pd_data = { 2080 .pd_flags = PD_FLAG_DEV_LINK_ON, 2081 .pd_names = (const char*[]) { "power", "perf" }, 2082 .num_pd_names = 2, 2083 }, 2084 .resources_init = geni_serial_pwr_init, 2085 .set_rate = geni_serial_set_level, 2086 }; 2087 2088 static const struct dev_pm_ops qcom_geni_serial_pm_ops = { 2089 SET_RUNTIME_PM_OPS(qcom_geni_serial_runtime_suspend, 2090 qcom_geni_serial_runtime_resume, NULL) 2091 SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_suspend, qcom_geni_serial_resume) 2092 }; 2093 2094 static const struct of_device_id qcom_geni_serial_match_table[] = { 2095 { 2096 .compatible = "qcom,geni-debug-uart", 2097 .data = &qcom_geni_console_data, 2098 }, 2099 { 2100 .compatible = "qcom,sa8255p-geni-debug-uart", 2101 .data = &sa8255p_qcom_geni_console_data, 2102 }, 2103 { 2104 .compatible = "qcom,geni-uart", 2105 .data = &qcom_geni_uart_data, 2106 }, 2107 { 2108 .compatible = "qcom,sa8255p-geni-uart", 2109 .data = &sa8255p_qcom_geni_uart_data, 2110 }, 2111 {} 2112 }; 2113 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); 2114 2115 static struct platform_driver qcom_geni_serial_platform_driver = { 2116 .remove = qcom_geni_serial_remove, 2117 .probe = qcom_geni_serial_probe, 2118 .driver = { 2119 .name = "qcom_geni_serial", 2120 .of_match_table = qcom_geni_serial_match_table, 2121 .pm = &qcom_geni_serial_pm_ops, 2122 }, 2123 }; 2124 2125 static int __init qcom_geni_serial_init(void) 2126 { 2127 int ret; 2128 2129 ret = console_register(&qcom_geni_console_driver); 2130 if (ret) 2131 return ret; 2132 2133 ret = uart_register_driver(&qcom_geni_uart_driver); 2134 if (ret) { 2135 console_unregister(&qcom_geni_console_driver); 2136 return ret; 2137 } 2138 2139 ret = platform_driver_register(&qcom_geni_serial_platform_driver); 2140 if (ret) { 2141 console_unregister(&qcom_geni_console_driver); 2142 uart_unregister_driver(&qcom_geni_uart_driver); 2143 } 2144 return ret; 2145 } 2146 module_init(qcom_geni_serial_init); 2147 2148 static void __exit qcom_geni_serial_exit(void) 2149 { 2150 platform_driver_unregister(&qcom_geni_serial_platform_driver); 2151 console_unregister(&qcom_geni_console_driver); 2152 uart_unregister_driver(&qcom_geni_uart_driver); 2153 } 2154 module_exit(qcom_geni_serial_exit); 2155 2156 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores"); 2157 MODULE_LICENSE("GPL v2"); 2158