1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */ 8 #define __DISABLE_TRACE_MMIO__ 9 10 #define CREATE_TRACE_POINTS 11 #include <trace/events/qcom_geni_serial.h> 12 13 #include <linux/clk.h> 14 #include <linux/console.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/io.h> 17 #include <linux/iopoll.h> 18 #include <linux/irq.h> 19 #include <linux/irq_work.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/panic_notifier.h> 23 #include <linux/pm_domain.h> 24 #include <linux/pm_opp.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/soc/qcom/geni-se.h> 29 #include <linux/serial.h> 30 #include <linux/serial_core.h> 31 #include <linux/slab.h> 32 #include <linux/tty.h> 33 #include <linux/tty_flip.h> 34 #include <dt-bindings/interconnect/qcom,icc.h> 35 36 /* UART specific GENI registers */ 37 #define SE_UART_LOOPBACK_CFG 0x22c 38 #define SE_UART_IO_MACRO_CTRL 0x240 39 #define SE_UART_TX_TRANS_CFG 0x25c 40 #define SE_UART_TX_WORD_LEN 0x268 41 #define SE_UART_TX_STOP_BIT_LEN 0x26c 42 #define SE_UART_TX_TRANS_LEN 0x270 43 #define SE_UART_RX_TRANS_CFG 0x280 44 #define SE_UART_RX_WORD_LEN 0x28c 45 #define SE_UART_RX_STALE_CNT 0x294 46 #define SE_UART_TX_PARITY_CFG 0x2a4 47 #define SE_UART_RX_PARITY_CFG 0x2a8 48 #define SE_UART_MANUAL_RFR 0x2ac 49 50 /* SE_UART_TRANS_CFG */ 51 #define UART_TX_PAR_EN BIT(0) 52 #define UART_CTS_MASK BIT(1) 53 54 /* SE_UART_TX_STOP_BIT_LEN */ 55 #define TX_STOP_BIT_LEN_1 0 56 #define TX_STOP_BIT_LEN_2 2 57 58 /* SE_UART_RX_TRANS_CFG */ 59 #define UART_RX_PAR_EN BIT(4) 60 61 /* SE_UART_RX_WORD_LEN */ 62 #define RX_WORD_LEN_MASK GENMASK(9, 0) 63 64 /* SE_UART_RX_STALE_CNT */ 65 #define RX_STALE_CNT GENMASK(23, 0) 66 67 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ 68 #define PAR_CALC_EN BIT(0) 69 #define PAR_EVEN 0x00 70 #define PAR_ODD 0x01 71 #define PAR_SPACE 0x10 72 73 /* SE_UART_MANUAL_RFR register fields */ 74 #define UART_MANUAL_RFR_EN BIT(31) 75 #define UART_RFR_NOT_READY BIT(1) 76 #define UART_RFR_READY BIT(0) 77 78 /* UART M_CMD OP codes */ 79 #define UART_START_TX 0x1 80 /* UART S_CMD OP codes */ 81 #define UART_START_READ 0x1 82 #define UART_PARAM 0x1 83 #define UART_PARAM_RFR_OPEN BIT(7) 84 85 #define UART_OVERSAMPLING 32 86 #define STALE_TIMEOUT 16 87 #define DEFAULT_BITS_PER_CHAR 10 88 #define GENI_UART_CONS_PORTS 1 89 #define DEF_FIFO_DEPTH_WORDS 16 90 #define DEF_TX_WM 2 91 #define DEF_FIFO_WIDTH_BITS 32 92 #define UART_RX_WM 2 93 #define CONSOLE_TX_CHUNK_SIZE 32 94 95 /* SE_UART_LOOPBACK_CFG */ 96 #define RX_TX_SORTED BIT(0) 97 #define CTS_RTS_SORTED BIT(1) 98 #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) 99 100 /* UART pin swap value */ 101 #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) 102 #define IO_MACRO_IO0_SEL 0x3 103 #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) 104 #define IO_MACRO_IO2_IO3_SWAP 0x4640 105 106 /* We always configure 4 bytes per FIFO word */ 107 #define BYTES_PER_FIFO_WORD 4U 108 109 #define DMA_RX_BUF_SIZE 2048 110 111 static DEFINE_IDA(port_ida); 112 113 struct qcom_geni_device_data { 114 bool console; 115 enum geni_se_xfer_mode mode; 116 int (*resources_init)(struct geni_se *se); 117 int (*set_rate)(struct geni_se *se, unsigned long baud); 118 int (*power_on)(struct geni_se *se); 119 int (*power_off)(struct geni_se *se); 120 }; 121 122 struct qcom_geni_private_data { 123 /* NOTE: earlycon port will have NULL here */ 124 struct uart_driver *drv; 125 126 u32 poll_cached_bytes; 127 unsigned int poll_cached_bytes_cnt; 128 129 u32 write_cached_bytes; 130 unsigned int write_cached_bytes_cnt; 131 }; 132 133 struct qcom_geni_serial_port { 134 struct uart_port uport; 135 struct geni_se se; 136 const char *name; 137 u32 tx_fifo_depth; 138 u32 tx_fifo_width; 139 u32 rx_fifo_depth; 140 dma_addr_t tx_dma_addr; 141 dma_addr_t rx_dma_addr; 142 bool setup; 143 unsigned long poll_timeout_us; 144 unsigned long clk_rate; 145 void *rx_buf; 146 u32 loopback; 147 bool brk; 148 149 unsigned int tx_remaining; 150 unsigned int tx_queued; 151 bool tx_dma_stale; 152 int wakeup_irq; 153 bool rx_tx_swap; 154 bool cts_rts_swap; 155 bool manual_flow; 156 bool tx_kick_enabled; 157 struct irq_work tx_kick; 158 struct qcom_geni_private_data private_data; 159 const struct qcom_geni_device_data *dev_data; 160 struct notifier_block panic_nb; 161 }; 162 163 static const struct uart_ops qcom_geni_console_pops; 164 static const struct uart_ops qcom_geni_uart_pops; 165 static struct uart_driver qcom_geni_console_driver; 166 static struct uart_driver qcom_geni_uart_driver; 167 168 static void qcom_geni_serial_stop_tx_dma(struct uart_port *uport); 169 static void __qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport); 170 static void qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport); 171 static int qcom_geni_serial_port_setup(struct uart_port *uport); 172 static void qcom_geni_serial_start_tx_fifo(struct uart_port *uport); 173 static void qcom_geni_serial_resume_tx(struct uart_port *uport); 174 175 static inline struct qcom_geni_serial_port *to_dev_port(struct uart_port *uport) 176 { 177 return container_of(uport, struct qcom_geni_serial_port, uport); 178 } 179 180 static struct qcom_geni_serial_port qcom_geni_console_port = { 181 .uport = { 182 .iotype = UPIO_MEM, 183 .ops = &qcom_geni_console_pops, 184 .flags = UPF_BOOT_AUTOCONF, 185 .line = 0, 186 }, 187 }; 188 189 static const struct serial_rs485 qcom_geni_rs485_supported = { 190 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND | SER_RS485_RTS_ON_SEND, 191 }; 192 193 /** 194 * qcom_geni_set_rs485_mode - Set RTS pin state for RS485 mode 195 * @uport: UART port 196 * @flag: RS485 flag to determine RTS polarity 197 * 198 * Enables manual RTS control for RS485. Sets RTS to READY or NOT_READY 199 * based on the specified flag if RS485 mode is enabled. 200 */ 201 static void qcom_geni_set_rs485_mode(struct uart_port *uport, u32 flag) 202 { 203 if (!(uport->rs485.flags & SER_RS485_ENABLED)) 204 return; 205 206 u32 rfr = UART_MANUAL_RFR_EN; 207 208 if (uport->rs485.flags & flag) 209 rfr |= UART_RFR_NOT_READY; 210 else 211 rfr |= UART_RFR_READY; 212 213 writel(rfr, uport->membase + SE_UART_MANUAL_RFR); 214 } 215 216 static int qcom_geni_serial_request_port(struct uart_port *uport) 217 { 218 struct platform_device *pdev = to_platform_device(uport->dev); 219 struct qcom_geni_serial_port *port = to_dev_port(uport); 220 221 uport->membase = devm_platform_ioremap_resource(pdev, 0); 222 if (IS_ERR(uport->membase)) 223 return PTR_ERR(uport->membase); 224 port->se.base = uport->membase; 225 return 0; 226 } 227 228 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags) 229 { 230 if (cfg_flags & UART_CONFIG_TYPE) { 231 uport->type = PORT_MSM; 232 qcom_geni_serial_request_port(uport); 233 } 234 } 235 236 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport) 237 { 238 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR; 239 u32 geni_ios = 0; 240 241 if (uart_console(uport)) { 242 mctrl |= TIOCM_CTS; 243 } else { 244 geni_ios = readl(uport->membase + SE_GENI_IOS); 245 if (!(geni_ios & IO2_DATA_IN)) 246 mctrl |= TIOCM_CTS; 247 } 248 249 trace_geni_serial_get_mctrl(uport->dev, mctrl, geni_ios); 250 251 return mctrl; 252 } 253 254 static void qcom_geni_serial_set_mctrl(struct uart_port *uport, 255 unsigned int mctrl) 256 { 257 u32 uart_manual_rfr = 0; 258 struct qcom_geni_serial_port *port = to_dev_port(uport); 259 260 if (uart_console(uport)) 261 return; 262 263 if (mctrl & TIOCM_LOOP) 264 port->loopback = RX_TX_CTS_RTS_SORTED; 265 266 if (port->manual_flow && !(mctrl & TIOCM_RTS) && !uport->suspended) 267 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; 268 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); 269 270 trace_geni_serial_set_mctrl(uport->dev, mctrl, uart_manual_rfr); 271 } 272 273 static const char *qcom_geni_serial_get_type(struct uart_port *uport) 274 { 275 return "MSM"; 276 } 277 278 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console, struct device *dev) 279 { 280 struct qcom_geni_serial_port *port; 281 int nr_ports = console ? GENI_UART_CONS_PORTS : CONFIG_SERIAL_QCOM_GENI_UART_PORTS; 282 283 if (console) { 284 if (line < 0 || line >= nr_ports) 285 return ERR_PTR(-ENXIO); 286 287 port = &qcom_geni_console_port; 288 } else { 289 int max_alias_num = of_alias_get_highest_id("serial"); 290 291 if (line < 0 || line >= nr_ports) 292 line = ida_alloc_range(&port_ida, max_alias_num + 1, 293 nr_ports - 1, GFP_KERNEL); 294 else 295 line = ida_alloc_range(&port_ida, line, 296 nr_ports - 1, GFP_KERNEL); 297 298 if (line < 0) 299 return ERR_PTR(-ENXIO); 300 301 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 302 if (!port) 303 return ERR_PTR(-ENOMEM); 304 305 port->uport.iotype = UPIO_MEM; 306 port->uport.ops = &qcom_geni_uart_pops; 307 port->uport.flags = UPF_BOOT_AUTOCONF; 308 port->uport.line = line; 309 } 310 return port; 311 } 312 313 static bool qcom_geni_serial_main_active(struct uart_port *uport) 314 { 315 return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE; 316 } 317 318 static bool qcom_geni_serial_secondary_active(struct uart_port *uport) 319 { 320 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE; 321 } 322 323 static bool qcom_geni_serial_poll_bitfield(struct uart_port *uport, 324 unsigned int offset, u32 field, u32 val) 325 { 326 u32 reg; 327 struct qcom_geni_serial_port *port; 328 unsigned long timeout_us = 20000; 329 struct qcom_geni_private_data *private_data = uport->private_data; 330 331 if (private_data->drv) { 332 port = to_dev_port(uport); 333 if (port->poll_timeout_us) 334 timeout_us = port->poll_timeout_us; 335 } 336 337 /* 338 * Use custom implementation instead of readl_poll_atomic since ktimer 339 * is not ready at the time of early console. 340 */ 341 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; 342 while (timeout_us) { 343 reg = readl(uport->membase + offset); 344 if ((reg & field) == val) 345 return true; 346 udelay(10); 347 timeout_us -= 10; 348 } 349 return false; 350 } 351 352 static bool qcom_geni_serial_poll_bit(struct uart_port *uport, 353 unsigned int offset, u32 field, bool set) 354 { 355 return qcom_geni_serial_poll_bitfield(uport, offset, field, set ? field : 0); 356 } 357 358 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size) 359 { 360 u32 m_cmd; 361 362 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); 363 m_cmd = UART_START_TX << M_OPCODE_SHFT; 364 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); 365 } 366 367 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport) 368 { 369 int done; 370 371 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 372 M_CMD_DONE_EN, true); 373 if (!done) { 374 writel(M_GENI_CMD_ABORT, uport->membase + 375 SE_GENI_M_CMD_CTRL_REG); 376 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 377 M_CMD_ABORT_EN, true); 378 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 379 } 380 } 381 382 static void qcom_geni_serial_abort_rx(struct uart_port *uport) 383 { 384 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN; 385 386 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); 387 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, 388 S_GENI_CMD_ABORT, false); 389 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); 390 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); 391 } 392 393 #ifdef CONFIG_CONSOLE_POLL 394 static int qcom_geni_serial_get_char(struct uart_port *uport) 395 { 396 struct qcom_geni_private_data *private_data = uport->private_data; 397 u32 status; 398 u32 word_cnt; 399 int ret; 400 401 if (!private_data->poll_cached_bytes_cnt) { 402 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 403 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR); 404 405 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 406 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR); 407 408 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 409 word_cnt = status & RX_FIFO_WC_MSK; 410 if (!word_cnt) 411 return NO_POLL_CHAR; 412 413 if (word_cnt == 1 && (status & RX_LAST)) 414 /* 415 * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be 416 * treated as if it was BYTES_PER_FIFO_WORD. 417 */ 418 private_data->poll_cached_bytes_cnt = 419 (status & RX_LAST_BYTE_VALID_MSK) >> 420 RX_LAST_BYTE_VALID_SHFT; 421 422 if (private_data->poll_cached_bytes_cnt == 0) 423 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD; 424 425 private_data->poll_cached_bytes = 426 readl(uport->membase + SE_GENI_RX_FIFOn); 427 } 428 429 private_data->poll_cached_bytes_cnt--; 430 ret = private_data->poll_cached_bytes & 0xff; 431 private_data->poll_cached_bytes >>= 8; 432 433 return ret; 434 } 435 436 static void qcom_geni_serial_poll_put_char(struct uart_port *uport, 437 unsigned char c) 438 { 439 if (qcom_geni_serial_main_active(uport)) { 440 qcom_geni_serial_poll_tx_done(uport); 441 __qcom_geni_serial_cancel_tx_cmd(uport); 442 } 443 444 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 445 qcom_geni_serial_setup_tx(uport, 1); 446 writel(c, uport->membase + SE_GENI_TX_FIFOn); 447 qcom_geni_serial_poll_tx_done(uport); 448 } 449 450 static int qcom_geni_serial_poll_init(struct uart_port *uport) 451 { 452 struct qcom_geni_serial_port *port = to_dev_port(uport); 453 int ret; 454 455 if (!port->setup) { 456 ret = qcom_geni_serial_port_setup(uport); 457 if (ret) 458 return ret; 459 } 460 461 if (!qcom_geni_serial_secondary_active(uport)) 462 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); 463 464 return 0; 465 } 466 #endif 467 468 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 469 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 470 { 471 u32 i; 472 unsigned char buf[sizeof(u32)]; 473 struct tty_port *tport; 474 struct qcom_geni_serial_port *port = to_dev_port(uport); 475 476 tport = &uport->state->port; 477 for (i = 0; i < bytes; ) { 478 int c; 479 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD); 480 481 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); 482 i += chunk; 483 if (drop) 484 continue; 485 486 for (c = 0; c < chunk; c++) { 487 int sysrq; 488 489 uport->icount.rx++; 490 if (port->brk && buf[c] == 0) { 491 port->brk = false; 492 if (uart_handle_break(uport)) 493 continue; 494 } 495 496 sysrq = uart_prepare_sysrq_char(uport, buf[c]); 497 498 if (!sysrq) 499 tty_insert_flip_char(tport, buf[c], TTY_NORMAL); 500 } 501 } 502 if (!drop) 503 tty_flip_buffer_push(tport); 504 } 505 #else 506 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 507 { 508 509 } 510 #endif 511 512 static void qcom_geni_serial_handle_rx_fifo(struct uart_port *uport, bool drop) 513 { 514 u32 status; 515 u32 word_cnt; 516 u32 last_word_byte_cnt; 517 u32 last_word_partial; 518 u32 total_bytes; 519 520 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 521 word_cnt = status & RX_FIFO_WC_MSK; 522 last_word_partial = status & RX_LAST; 523 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >> 524 RX_LAST_BYTE_VALID_SHFT; 525 526 if (!word_cnt) 527 return; 528 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1); 529 if (last_word_partial && last_word_byte_cnt) 530 total_bytes += last_word_byte_cnt; 531 else 532 total_bytes += BYTES_PER_FIFO_WORD; 533 handle_rx_console(uport, total_bytes, drop); 534 } 535 536 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 537 /* Caller holds the UART port lock. */ 538 static void qcom_geni_serial_poll_rx_fifo_locked(struct uart_port *uport) 539 { 540 struct qcom_geni_serial_port *port = to_dev_port(uport); 541 struct tty_port *tport = &uport->state->port; 542 u32 s_irq_status; 543 bool drop_rx = false; 544 545 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 546 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 547 548 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) { 549 uport->icount.overrun++; 550 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 551 } 552 553 if (s_irq_status & (S_GP_IRQ_0_EN | S_GP_IRQ_1_EN)) { 554 if (s_irq_status & S_GP_IRQ_0_EN) 555 uport->icount.parity++; 556 drop_rx = true; 557 } else if (s_irq_status & (S_GP_IRQ_2_EN | S_GP_IRQ_3_EN)) { 558 uport->icount.brk++; 559 port->brk = true; 560 } 561 562 qcom_geni_serial_handle_rx_fifo(uport, drop_rx); 563 } 564 565 static void qcom_geni_serial_drain_fifo(struct uart_port *uport) 566 { 567 struct qcom_geni_serial_port *port = to_dev_port(uport); 568 569 qcom_geni_serial_poll_bitfield(uport, SE_GENI_M_GP_LENGTH, GP_LENGTH, 570 port->tx_queued); 571 } 572 573 static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch) 574 { 575 struct qcom_geni_private_data *private_data = uport->private_data; 576 577 private_data->write_cached_bytes = 578 (private_data->write_cached_bytes >> 8) | (ch << 24); 579 private_data->write_cached_bytes_cnt++; 580 581 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) { 582 writel(private_data->write_cached_bytes, 583 uport->membase + SE_GENI_TX_FIFOn); 584 private_data->write_cached_bytes_cnt = 0; 585 } 586 } 587 588 static void 589 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s, 590 unsigned int count, bool poll_rx) 591 { 592 struct qcom_geni_private_data *private_data = uport->private_data; 593 594 int i; 595 u32 bytes_to_send = count; 596 597 for (i = 0; i < count; i++) { 598 /* 599 * uart_console_write() adds a carriage return for each newline. 600 * Account for additional bytes to be written. 601 */ 602 if (s[i] == '\n') 603 bytes_to_send++; 604 } 605 606 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 607 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 608 qcom_geni_serial_setup_tx(uport, bytes_to_send); 609 for (i = 0; i < count; ) { 610 size_t chars_to_write = 0; 611 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; 612 613 /* 614 * If the WM bit never set, then the Tx state machine is not 615 * in a valid state, so break, cancel/abort any existing 616 * command. Unfortunately the current data being written is 617 * lost. 618 */ 619 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 620 M_TX_FIFO_WATERMARK_EN, true)) 621 break; 622 if (poll_rx) 623 qcom_geni_serial_poll_rx_fifo_locked(uport); 624 chars_to_write = min_t(size_t, count - i, avail / 2); 625 uart_console_write(uport, s + i, chars_to_write, 626 qcom_geni_serial_wr_char); 627 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + 628 SE_GENI_M_IRQ_CLEAR); 629 i += chars_to_write; 630 } 631 632 if (private_data->write_cached_bytes_cnt) { 633 private_data->write_cached_bytes >>= BITS_PER_BYTE * 634 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt); 635 writel(private_data->write_cached_bytes, 636 uport->membase + SE_GENI_TX_FIFOn); 637 private_data->write_cached_bytes_cnt = 0; 638 } 639 640 qcom_geni_serial_poll_tx_done(uport); 641 } 642 643 static void qcom_geni_serial_console_takeover(struct uart_port *uport, 644 bool preserve_tx) 645 { 646 if (qcom_geni_serial_main_active(uport)) { 647 struct qcom_geni_serial_port *port = to_dev_port(uport); 648 649 if (preserve_tx) { 650 if (port->tx_remaining == 0) 651 qcom_geni_serial_poll_tx_done(uport); 652 else 653 qcom_geni_serial_drain_fifo(uport); 654 } 655 656 qcom_geni_serial_cancel_tx_cmd(uport); 657 } 658 } 659 660 static void qcom_geni_serial_console_write_thread(struct console *co, 661 struct nbcon_write_context *wctxt) 662 { 663 struct qcom_geni_serial_port *port; 664 struct uart_port *uport; 665 unsigned int offset = 0; 666 667 port = get_port_from_line(co->index, true, NULL); 668 if (IS_ERR(port)) 669 return; 670 671 uport = &port->uport; 672 if (!nbcon_enter_unsafe(wctxt)) 673 return; 674 675 qcom_geni_serial_console_takeover(uport, true); 676 if (!nbcon_exit_unsafe(wctxt)) 677 return; 678 679 while (offset < wctxt->len) { 680 /* 681 * Printk records can be much larger than the FIFO. Limit one 682 * M-side command to 32 source bytes so atomic console output can 683 * take over between commands instead of waiting for the record. 684 */ 685 unsigned int count = min_t(unsigned int, wctxt->len - offset, 686 CONSOLE_TX_CHUNK_SIZE); 687 688 if (!nbcon_enter_unsafe(wctxt)) 689 return; 690 691 __qcom_geni_serial_console_write(uport, wctxt->outbuf + offset, 692 count, true); 693 offset += count; 694 695 if (!nbcon_exit_unsafe(wctxt)) 696 return; 697 } 698 699 if (!nbcon_enter_unsafe(wctxt)) 700 return; 701 702 qcom_geni_serial_resume_tx(uport); 703 nbcon_exit_unsafe(wctxt); 704 } 705 706 static void qcom_geni_serial_console_write_atomic(struct console *co, 707 struct nbcon_write_context *wctxt) 708 { 709 struct qcom_geni_serial_port *port; 710 struct uart_port *uport; 711 u32 m_irq_en; 712 713 port = get_port_from_line(co->index, true, NULL); 714 if (IS_ERR(port)) 715 return; 716 717 uport = &port->uport; 718 if (!nbcon_enter_unsafe(wctxt)) 719 return; 720 721 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 722 writel(m_irq_en & ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN), 723 uport->membase + SE_GENI_M_IRQ_EN); 724 725 /* Atomic console output takes priority over an active normal TX command. */ 726 qcom_geni_serial_console_takeover(uport, false); 727 __qcom_geni_serial_console_write(uport, wctxt->outbuf, wctxt->len, false); 728 729 writel(m_irq_en, uport->membase + SE_GENI_M_IRQ_EN); 730 nbcon_exit_unsafe(wctxt); 731 732 /* Restart TTY data left queued when atomic output canceled M TX. */ 733 if (READ_ONCE(port->tx_kick_enabled)) 734 irq_work_queue(&port->tx_kick); 735 } 736 737 static void qcom_geni_serial_console_device_lock(struct console *co, 738 unsigned long *flags) 739 { 740 struct qcom_geni_serial_port *port; 741 742 port = get_port_from_line(co->index, true, NULL); 743 if (IS_ERR(port)) 744 return; 745 746 __uart_port_lock_irqsave(&port->uport, flags); 747 } 748 749 static void qcom_geni_serial_console_device_unlock(struct console *co, 750 unsigned long flags) 751 { 752 struct qcom_geni_serial_port *port; 753 #ifdef CONFIG_MAGIC_SYSRQ_SERIAL 754 u8 sysrq_ch; 755 #endif 756 757 port = get_port_from_line(co->index, true, NULL); 758 if (IS_ERR(port)) 759 return; 760 761 #ifdef CONFIG_MAGIC_SYSRQ_SERIAL 762 /* The threaded console writer can receive a SysRq character. */ 763 sysrq_ch = port->uport.sysrq_ch; 764 port->uport.sysrq_ch = 0; 765 #endif 766 __uart_port_unlock_irqrestore(&port->uport, flags); 767 768 #ifdef CONFIG_MAGIC_SYSRQ_SERIAL 769 if (sysrq_ch) 770 handle_sysrq(sysrq_ch); 771 #endif 772 } 773 774 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 775 776 static void handle_rx_uart(struct uart_port *uport, u32 bytes) 777 { 778 struct qcom_geni_serial_port *port = to_dev_port(uport); 779 struct tty_port *tport = &uport->state->port; 780 int ret; 781 782 ret = tty_insert_flip_string(tport, port->rx_buf, bytes); 783 if (ret != bytes) { 784 dev_err_ratelimited(uport->dev, "failed to push data (%d < %u)\n", 785 ret, bytes); 786 } 787 uport->icount.rx += ret; 788 tty_flip_buffer_push(tport); 789 } 790 791 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport) 792 { 793 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 794 } 795 796 static void qcom_geni_serial_flush_buffer_dma(struct uart_port *uport) 797 { 798 struct qcom_geni_serial_port *port = to_dev_port(uport); 799 800 qcom_geni_serial_stop_tx_dma(uport); 801 port->tx_remaining = 0; 802 port->tx_queued = 0; 803 } 804 805 static void qcom_geni_serial_stop_tx_dma(struct uart_port *uport) 806 { 807 struct qcom_geni_serial_port *port = to_dev_port(uport); 808 809 if (qcom_geni_serial_main_active(uport)) 810 __qcom_geni_serial_cancel_tx_cmd(uport); 811 812 if (port->tx_dma_addr) { 813 writel(1, uport->membase + SE_DMA_TX_FSM_RST); 814 if (!qcom_geni_serial_poll_bit(uport, SE_DMA_TX_IRQ_STAT, 815 TX_RESET_DONE, true)) 816 dev_err_ratelimited(uport->dev, "TX DMA reset failed"); 817 writel(TX_RESET_DONE | TX_DMA_DONE, 818 uport->membase + SE_DMA_TX_IRQ_CLR); 819 820 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, 821 port->tx_remaining); 822 port->tx_dma_addr = 0; 823 } 824 } 825 826 static void qcom_geni_serial_start_tx_dma(struct uart_port *uport) 827 { 828 struct qcom_geni_serial_port *port = to_dev_port(uport); 829 struct tty_port *tport = &uport->state->port; 830 unsigned int xmit_size; 831 u8 *tail; 832 int ret; 833 834 if (port->tx_dma_addr) 835 return; 836 837 if (kfifo_is_empty(&tport->xmit_fifo)) 838 return; 839 840 xmit_size = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, 841 UART_XMIT_SIZE); 842 843 trace_geni_serial_tx_data(uport->dev, tail, xmit_size); 844 845 qcom_geni_set_rs485_mode(uport, SER_RS485_RTS_ON_SEND); 846 847 qcom_geni_serial_setup_tx(uport, xmit_size); 848 849 ret = geni_se_tx_dma_prep(&port->se, tail, xmit_size, 850 &port->tx_dma_addr); 851 if (ret) { 852 dev_err(uport->dev, "unable to start TX SE DMA: %d\n", ret); 853 qcom_geni_serial_stop_tx_dma(uport); 854 return; 855 } 856 857 port->tx_remaining = xmit_size; 858 port->tx_dma_stale = false; 859 } 860 861 static void qcom_geni_serial_start_tx_fifo(struct uart_port *uport) 862 { 863 unsigned char c; 864 u32 irq_en; 865 866 /* 867 * Start a new transfer in case the previous command was cancelled and 868 * left data in the FIFO which may prevent the watermark interrupt 869 * from triggering. Note that the stale data is discarded. 870 */ 871 if (!qcom_geni_serial_main_active(uport) && 872 !qcom_geni_serial_tx_empty(uport)) { 873 if (uart_fifo_out(uport, &c, 1) == 1) { 874 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 875 qcom_geni_serial_setup_tx(uport, 1); 876 writel(c, uport->membase + SE_GENI_TX_FIFOn); 877 } 878 } 879 880 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 881 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; 882 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 883 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 884 } 885 886 /* Caller holds the UART port lock. */ 887 static void qcom_geni_serial_resume_tx(struct uart_port *uport) 888 { 889 if (!uart_tx_stopped(uport) && 890 !kfifo_is_empty(&uport->state->port.xmit_fifo)) 891 qcom_geni_serial_start_tx_fifo(uport); 892 } 893 894 static void qcom_geni_serial_restart_tx(struct irq_work *work) 895 { 896 struct qcom_geni_serial_port *port = container_of(work, 897 struct qcom_geni_serial_port, tx_kick); 898 struct uart_port *uport = &port->uport; 899 900 if (!READ_ONCE(port->tx_kick_enabled) || !uport->state || uport->suspended) 901 return; 902 903 uart_port_lock(uport); 904 if (READ_ONCE(port->tx_kick_enabled) && uport->state && !uport->suspended) 905 qcom_geni_serial_resume_tx(uport); 906 uart_port_unlock(uport); 907 } 908 909 static void qcom_geni_serial_stop_tx_fifo(struct uart_port *uport) 910 { 911 u32 irq_en; 912 913 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 914 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 915 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); 916 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 917 } 918 919 static void __qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport) 920 { 921 struct qcom_geni_serial_port *port = to_dev_port(uport); 922 923 geni_se_cancel_m_cmd(&port->se); 924 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 925 M_CMD_CANCEL_EN, true)) { 926 geni_se_abort_m_cmd(&port->se); 927 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 928 M_CMD_ABORT_EN, true); 929 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 930 } 931 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 932 } 933 934 static void qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport) 935 { 936 struct qcom_geni_serial_port *port = to_dev_port(uport); 937 938 if (!qcom_geni_serial_main_active(uport)) 939 return; 940 941 __qcom_geni_serial_cancel_tx_cmd(uport); 942 943 port->tx_remaining = 0; 944 port->tx_queued = 0; 945 } 946 947 static void qcom_geni_serial_stop_rx_fifo(struct uart_port *uport) 948 { 949 u32 irq_en; 950 struct qcom_geni_serial_port *port = to_dev_port(uport); 951 u32 s_irq_status; 952 953 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 954 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); 955 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 956 957 if (!qcom_geni_serial_secondary_active(uport)) 958 return; 959 960 geni_se_cancel_s_cmd(&port->se); 961 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 962 S_CMD_CANCEL_EN, true); 963 /* 964 * If timeout occurs secondary engine remains active 965 * and Abort sequence is executed. 966 */ 967 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 968 /* Flush the Rx buffer */ 969 if (s_irq_status & S_RX_FIFO_LAST_EN) 970 qcom_geni_serial_handle_rx_fifo(uport, true); 971 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 972 973 if (qcom_geni_serial_secondary_active(uport)) 974 qcom_geni_serial_abort_rx(uport); 975 } 976 977 static void qcom_geni_serial_start_rx_fifo(struct uart_port *uport) 978 { 979 u32 irq_en; 980 struct qcom_geni_serial_port *port = to_dev_port(uport); 981 982 if (qcom_geni_serial_secondary_active(uport)) 983 qcom_geni_serial_stop_rx_fifo(uport); 984 985 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); 986 987 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 988 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; 989 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 990 } 991 992 static void qcom_geni_serial_stop_rx_dma(struct uart_port *uport) 993 { 994 struct qcom_geni_serial_port *port = to_dev_port(uport); 995 bool done; 996 997 if (!qcom_geni_serial_secondary_active(uport)) 998 return; 999 1000 geni_se_cancel_s_cmd(&port->se); 1001 done = qcom_geni_serial_poll_bit(uport, SE_DMA_RX_IRQ_STAT, 1002 RX_EOT, true); 1003 if (done) { 1004 writel(RX_EOT | RX_DMA_DONE, 1005 uport->membase + SE_DMA_RX_IRQ_CLR); 1006 } else { 1007 qcom_geni_serial_abort_rx(uport); 1008 1009 writel(1, uport->membase + SE_DMA_RX_FSM_RST); 1010 qcom_geni_serial_poll_bit(uport, SE_DMA_RX_IRQ_STAT, 1011 RX_RESET_DONE, true); 1012 writel(RX_RESET_DONE | RX_DMA_DONE, 1013 uport->membase + SE_DMA_RX_IRQ_CLR); 1014 } 1015 1016 } 1017 1018 static void qcom_geni_serial_start_rx_dma(struct uart_port *uport) 1019 { 1020 struct qcom_geni_serial_port *port = to_dev_port(uport); 1021 1022 if (qcom_geni_serial_secondary_active(uport)) 1023 qcom_geni_serial_stop_rx_dma(uport); 1024 1025 geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN); 1026 1027 if (!port->rx_dma_addr) { 1028 dev_err(uport->dev, "RX DMA buffer not mapped\n"); 1029 return; 1030 } 1031 1032 dma_sync_single_for_device(uport->dev->parent, port->rx_dma_addr, 1033 DMA_RX_BUF_SIZE, DMA_FROM_DEVICE); 1034 geni_se_rx_init_dma(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE); 1035 } 1036 1037 static void qcom_geni_serial_handle_rx_dma(struct uart_port *uport, bool drop) 1038 { 1039 struct qcom_geni_serial_port *port = to_dev_port(uport); 1040 u32 rx_in; 1041 1042 if (!qcom_geni_serial_secondary_active(uport)) 1043 return; 1044 1045 if (!port->rx_dma_addr) 1046 return; 1047 1048 dma_sync_single_for_cpu(uport->dev->parent, port->rx_dma_addr, 1049 DMA_RX_BUF_SIZE, DMA_FROM_DEVICE); 1050 1051 rx_in = readl(uport->membase + SE_DMA_RX_LEN_IN); 1052 if (!rx_in) 1053 dev_warn_ratelimited(uport->dev, "serial engine reports 0 RX bytes in!\n"); 1054 else if (!drop) { 1055 trace_geni_serial_rx_data(uport->dev, port->rx_buf, rx_in); 1056 handle_rx_uart(uport, rx_in); 1057 } 1058 1059 dma_sync_single_for_device(uport->dev->parent, port->rx_dma_addr, 1060 DMA_RX_BUF_SIZE, DMA_FROM_DEVICE); 1061 geni_se_rx_init_dma(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE); 1062 } 1063 1064 static void qcom_geni_serial_start_rx(struct uart_port *uport) 1065 { 1066 uport->ops->start_rx(uport); 1067 } 1068 1069 static void qcom_geni_serial_stop_rx(struct uart_port *uport) 1070 { 1071 uport->ops->stop_rx(uport); 1072 } 1073 1074 static void qcom_geni_serial_stop_tx(struct uart_port *uport) 1075 { 1076 uport->ops->stop_tx(uport); 1077 } 1078 1079 static void qcom_geni_serial_send_chunk_fifo(struct uart_port *uport, 1080 unsigned int chunk) 1081 { 1082 struct qcom_geni_serial_port *port = to_dev_port(uport); 1083 unsigned int tx_bytes, remaining = chunk; 1084 u8 buf[BYTES_PER_FIFO_WORD]; 1085 1086 while (remaining) { 1087 memset(buf, 0, sizeof(buf)); 1088 tx_bytes = min(remaining, BYTES_PER_FIFO_WORD); 1089 1090 uart_fifo_out(uport, buf, tx_bytes); 1091 1092 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); 1093 1094 remaining -= tx_bytes; 1095 port->tx_remaining -= tx_bytes; 1096 } 1097 } 1098 1099 static void qcom_geni_serial_handle_tx_fifo(struct uart_port *uport, 1100 bool done, bool active) 1101 { 1102 struct qcom_geni_serial_port *port = to_dev_port(uport); 1103 struct tty_port *tport = &uport->state->port; 1104 size_t avail; 1105 size_t pending; 1106 u32 status; 1107 u32 irq_en; 1108 unsigned int chunk; 1109 1110 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 1111 1112 /* Complete the current tx command before taking newly added data */ 1113 if (active) 1114 pending = port->tx_remaining; 1115 else 1116 pending = kfifo_len(&tport->xmit_fifo); 1117 1118 /* All data has been transmitted or command has been cancelled */ 1119 if (!pending && done) { 1120 qcom_geni_serial_stop_tx_fifo(uport); 1121 goto out_write_wakeup; 1122 } 1123 1124 if (active) 1125 avail = port->tx_fifo_depth - (status & TX_FIFO_WC); 1126 else 1127 avail = port->tx_fifo_depth; 1128 1129 avail *= BYTES_PER_FIFO_WORD; 1130 1131 chunk = min(avail, pending); 1132 if (!chunk) 1133 goto out_write_wakeup; 1134 1135 if (!active) { 1136 qcom_geni_serial_setup_tx(uport, pending); 1137 port->tx_remaining = pending; 1138 port->tx_queued = 0; 1139 1140 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 1141 if (!(irq_en & M_TX_FIFO_WATERMARK_EN)) 1142 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 1143 uport->membase + SE_GENI_M_IRQ_EN); 1144 } 1145 1146 qcom_geni_serial_send_chunk_fifo(uport, chunk); 1147 port->tx_queued += chunk; 1148 1149 /* 1150 * The tx fifo watermark is level triggered and latched. Though we had 1151 * cleared it in qcom_geni_serial_isr it will have already reasserted 1152 * so we must clear it again here after our writes. 1153 */ 1154 writel(M_TX_FIFO_WATERMARK_EN, 1155 uport->membase + SE_GENI_M_IRQ_CLEAR); 1156 1157 out_write_wakeup: 1158 if (!port->tx_remaining) { 1159 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 1160 if (irq_en & M_TX_FIFO_WATERMARK_EN) 1161 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN, 1162 uport->membase + SE_GENI_M_IRQ_EN); 1163 } 1164 1165 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1166 uart_write_wakeup(uport); 1167 } 1168 1169 static void qcom_geni_serial_handle_tx_dma(struct uart_port *uport) 1170 { 1171 struct qcom_geni_serial_port *port = to_dev_port(uport); 1172 struct tty_port *tport = &uport->state->port; 1173 unsigned int fifo_len = kfifo_len(&tport->xmit_fifo); 1174 bool tx_dma_stale = port->tx_dma_stale; 1175 1176 /* 1177 * Only advance the kfifo if it still contains the bytes that were 1178 * transferred. uart_flush_buffer() may have run before this IRQ 1179 * fired: it calls kfifo_reset() under the port lock, making 1180 * fifo_len = 0 while tx_remaining remains non-zero. Calling 1181 * uart_xmit_advance() in that case would underflow kfifo->out past 1182 * kfifo->in, making kfifo_len() wrap to UART_XMIT_SIZE - tx_remaining 1183 * and triggering a spurious large DMA transfer of stale data. 1184 */ 1185 if (!tx_dma_stale && fifo_len >= port->tx_remaining) 1186 uart_xmit_advance(uport, port->tx_remaining); 1187 1188 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining); 1189 port->tx_dma_addr = 0; 1190 port->tx_remaining = 0; 1191 port->tx_dma_stale = false; 1192 1193 if (!kfifo_is_empty(&tport->xmit_fifo)) 1194 qcom_geni_serial_start_tx_dma(uport); 1195 1196 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1197 uart_write_wakeup(uport); 1198 } 1199 1200 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) 1201 { 1202 u32 m_irq_en; 1203 u32 m_irq_status; 1204 u32 s_irq_status; 1205 u32 geni_status; 1206 u32 dma; 1207 u32 dma_tx_status; 1208 u32 dma_rx_status; 1209 struct uart_port *uport = dev; 1210 bool drop_rx = false; 1211 struct tty_port *tport = &uport->state->port; 1212 struct qcom_geni_serial_port *port = to_dev_port(uport); 1213 1214 if (uport->suspended) 1215 return IRQ_NONE; 1216 1217 uart_port_lock(uport); 1218 1219 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 1220 dma_rx_status = readl(uport->membase + SE_DMA_RX_IRQ_STAT); 1221 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 1222 writel(dma_rx_status, uport->membase + SE_DMA_RX_IRQ_CLR); 1223 1224 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) { 1225 uport->icount.overrun++; 1226 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 1227 } 1228 1229 if (s_irq_status & (S_GP_IRQ_0_EN | S_GP_IRQ_1_EN)) { 1230 if (s_irq_status & S_GP_IRQ_0_EN) 1231 uport->icount.parity++; 1232 drop_rx = true; 1233 } else if (s_irq_status & (S_GP_IRQ_2_EN | S_GP_IRQ_3_EN)) { 1234 uport->icount.brk++; 1235 port->brk = true; 1236 } 1237 1238 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 1239 dma_tx_status = readl(uport->membase + SE_DMA_TX_IRQ_STAT); 1240 geni_status = readl(uport->membase + SE_GENI_STATUS); 1241 dma = readl(uport->membase + SE_GENI_DMA_MODE_EN); 1242 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 1243 1244 trace_geni_serial_irq(uport->dev, m_irq_status, s_irq_status, 1245 dma_tx_status, dma_rx_status); 1246 1247 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); 1248 writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR); 1249 1250 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN)) 1251 goto handle_rx; 1252 1253 if (dma) { 1254 if (dma_tx_status & TX_DMA_DONE) { 1255 qcom_geni_serial_handle_tx_dma(uport); 1256 qcom_geni_set_rs485_mode(uport, SER_RS485_RTS_AFTER_SEND); 1257 } 1258 } else if (m_irq_status & m_irq_en & 1259 (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) { 1260 qcom_geni_serial_handle_tx_fifo(uport, 1261 m_irq_status & M_CMD_DONE_EN, 1262 geni_status & M_GENI_CMD_ACTIVE); 1263 } 1264 1265 handle_rx: 1266 if (dma) { 1267 if (dma_rx_status) { 1268 if (dma_rx_status & RX_RESET_DONE) 1269 goto out_unlock; 1270 1271 if (dma_rx_status & RX_DMA_PARITY_ERR) { 1272 uport->icount.parity++; 1273 drop_rx = true; 1274 } 1275 1276 if (dma_rx_status & RX_DMA_BREAK) 1277 uport->icount.brk++; 1278 1279 if (dma_rx_status & (RX_DMA_DONE | RX_EOT)) 1280 qcom_geni_serial_handle_rx_dma(uport, drop_rx); 1281 } 1282 } else { 1283 if (s_irq_status & (S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN)) 1284 qcom_geni_serial_handle_rx_fifo(uport, drop_rx); 1285 } 1286 1287 out_unlock: 1288 uart_unlock_and_check_sysrq(uport); 1289 1290 return IRQ_HANDLED; 1291 } 1292 1293 static int setup_fifos(struct qcom_geni_serial_port *port) 1294 { 1295 struct uart_port *uport; 1296 u32 old_rx_fifo_depth = port->rx_fifo_depth; 1297 1298 uport = &port->uport; 1299 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); 1300 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); 1301 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); 1302 uport->fifosize = 1303 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; 1304 1305 if (port->rx_buf && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) { 1306 /* 1307 * Use krealloc rather than krealloc_array because rx_buf is 1308 * accessed as 1 byte entries as well as 4 byte entries so it's 1309 * not necessarily an array. 1310 */ 1311 port->rx_buf = devm_krealloc(uport->dev, port->rx_buf, 1312 port->rx_fifo_depth * sizeof(u32), 1313 GFP_KERNEL); 1314 if (!port->rx_buf) 1315 return -ENOMEM; 1316 } 1317 1318 return 0; 1319 } 1320 1321 1322 static void qcom_geni_serial_shutdown(struct uart_port *uport) 1323 { 1324 struct qcom_geni_serial_port *port = to_dev_port(uport); 1325 1326 /* Atomic console output queues tx_kick without taking the port lock. */ 1327 WRITE_ONCE(port->tx_kick_enabled, false); 1328 irq_work_sync(&port->tx_kick); 1329 disable_irq(uport->irq); 1330 1331 uart_port_lock_irq(uport); 1332 qcom_geni_serial_stop_tx(uport); 1333 qcom_geni_serial_stop_rx(uport); 1334 1335 qcom_geni_serial_cancel_tx_cmd(uport); 1336 uart_port_unlock_irq(uport); 1337 1338 pm_runtime_put_sync(uport->dev); 1339 } 1340 1341 static void qcom_geni_serial_flush_buffer_fifo(struct uart_port *uport) 1342 { 1343 struct qcom_geni_serial_port *port = to_dev_port(uport); 1344 1345 if (port->tx_dma_addr) 1346 port->tx_dma_stale = true; 1347 qcom_geni_serial_cancel_tx_cmd(uport); 1348 } 1349 1350 static int qcom_geni_serial_port_setup(struct uart_port *uport) 1351 { 1352 struct qcom_geni_serial_port *port = to_dev_port(uport); 1353 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT; 1354 u32 proto; 1355 u32 pin_swap; 1356 int ret; 1357 1358 proto = geni_se_read_proto(&port->se); 1359 if (proto == GENI_SE_INVALID_PROTO) { 1360 ret = geni_load_se_firmware(&port->se, GENI_SE_UART); 1361 if (ret) { 1362 dev_err(uport->dev, "UART firmware load failed ret: %d\n", ret); 1363 return ret; 1364 } 1365 } else if (proto != GENI_SE_UART) { 1366 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); 1367 return -ENXIO; 1368 } 1369 1370 qcom_geni_serial_stop_rx(uport); 1371 1372 ret = setup_fifos(port); 1373 if (ret) 1374 return ret; 1375 1376 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); 1377 1378 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL); 1379 if (port->rx_tx_swap) { 1380 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK; 1381 pin_swap |= IO_MACRO_IO2_IO3_SWAP; 1382 } 1383 if (port->cts_rts_swap) { 1384 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK; 1385 pin_swap |= IO_MACRO_IO0_SEL; 1386 } 1387 /* Configure this register if RX-TX, CTS-RTS pins are swapped */ 1388 if (port->rx_tx_swap || port->cts_rts_swap) 1389 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL); 1390 1391 /* 1392 * Make an unconditional cancel on the main sequencer to reset 1393 * it else we could end up in data loss scenarios. 1394 */ 1395 if (uart_console(uport)) 1396 qcom_geni_serial_poll_tx_done(uport); 1397 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1398 false, true, true); 1399 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); 1400 geni_se_select_mode(&port->se, port->dev_data->mode); 1401 port->setup = true; 1402 1403 return 0; 1404 } 1405 1406 static int qcom_geni_serial_startup(struct uart_port *uport) 1407 { 1408 int ret; 1409 struct qcom_geni_serial_port *port = to_dev_port(uport); 1410 struct tty_port *tport = &uport->state->port; 1411 1412 ret = pm_runtime_resume_and_get(uport->dev); 1413 if (ret < 0) { 1414 dev_err(uport->dev, "Failed to resume and get %d\n", ret); 1415 return ret; 1416 } 1417 1418 if (!port->setup) { 1419 ret = qcom_geni_serial_port_setup(uport); 1420 if (ret) { 1421 pm_runtime_put_sync(uport->dev); 1422 return ret; 1423 } 1424 } 1425 1426 /* 1427 * Skip the close-time transmit drain for console ports so that 1428 * shutdown can proceed without waiting for pending TX completion. 1429 */ 1430 if (uart_console(uport)) 1431 tport->closing_wait = ASYNC_CLOSING_WAIT_NONE; 1432 1433 uart_port_lock_irq(uport); 1434 qcom_geni_serial_start_rx(uport); 1435 uart_port_unlock_irq(uport); 1436 1437 enable_irq(uport->irq); 1438 WRITE_ONCE(port->tx_kick_enabled, true); 1439 1440 return 0; 1441 } 1442 1443 static int geni_serial_set_rate(struct geni_se *se, unsigned long baud) 1444 { 1445 struct qcom_geni_serial_port *port = dev_get_drvdata(se->dev); 1446 struct uart_port *uport = &port->uport; 1447 unsigned long clk_rate; 1448 unsigned int avg_bw_core, clk_idx; 1449 unsigned int clk_div; 1450 u32 ver, sampling_rate; 1451 u32 ser_clk_cfg; 1452 int ret; 1453 1454 sampling_rate = UART_OVERSAMPLING; 1455 /* Sampling rate is halved for IP versions >= 2.5 */ 1456 ver = geni_se_get_qup_hw_version(&port->se); 1457 if (ver >= QUP_SE_VERSION_2_5) 1458 sampling_rate /= 2; 1459 1460 ret = geni_se_clk_freq_match(&port->se, baud * sampling_rate, &clk_idx, &clk_rate, false); 1461 if (ret) { 1462 dev_err(port->se.dev, "Failed to find src clk for baud rate: %lu ret: %d\n", 1463 baud, ret); 1464 return ret; 1465 } 1466 1467 clk_div = DIV_ROUND_UP(clk_rate, baud * sampling_rate); 1468 /* Check if calculated divider exceeds maximum allowed value */ 1469 if (clk_div > (CLK_DIV_MSK >> CLK_DIV_SHFT)) { 1470 dev_err(port->se.dev, "Calculated clock divider %u exceeds maximum\n", clk_div); 1471 return -EINVAL; 1472 } 1473 1474 trace_geni_serial_clk_cfg(uport->dev, baud * sampling_rate, clk_rate, 1475 clk_div, clk_idx); 1476 1477 uport->uartclk = clk_rate; 1478 port->clk_rate = clk_rate; 1479 dev_pm_opp_set_rate(uport->dev, clk_rate); 1480 ser_clk_cfg = SER_CLK_EN; 1481 ser_clk_cfg |= clk_div << CLK_DIV_SHFT; 1482 1483 /* 1484 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode 1485 * only. 1486 */ 1487 avg_bw_core = baud > 115200 ? CORE_2X_50_MHZ : CORE_2X_19_2_MHZ; 1488 port->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(avg_bw_core); 1489 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); 1490 geni_icc_set_bw(&port->se); 1491 1492 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); 1493 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); 1494 /* Configure clock selection register with the selected clock index */ 1495 writel(clk_idx & CLK_SEL_MSK, uport->membase + SE_GENI_CLK_SEL); 1496 return 0; 1497 } 1498 1499 static void qcom_geni_serial_set_termios(struct uart_port *uport, 1500 struct ktermios *termios, 1501 const struct ktermios *old) 1502 { 1503 struct qcom_geni_serial_port *port = to_dev_port(uport); 1504 unsigned int baud; 1505 unsigned long timeout; 1506 u32 bits_per_char; 1507 u32 tx_trans_cfg; 1508 u32 tx_parity_cfg; 1509 u32 rx_trans_cfg; 1510 u32 rx_parity_cfg; 1511 u32 stop_bit_len; 1512 int ret = 0; 1513 1514 /* baud rate */ 1515 baud = uart_get_baud_rate(uport, termios, old, 300, 8000000); 1516 1517 ret = port->dev_data->set_rate(&port->se, baud); 1518 if (ret) 1519 return; 1520 1521 /* parity */ 1522 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); 1523 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); 1524 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG); 1525 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG); 1526 if (termios->c_cflag & PARENB) { 1527 tx_trans_cfg |= UART_TX_PAR_EN; 1528 rx_trans_cfg |= UART_RX_PAR_EN; 1529 tx_parity_cfg |= PAR_CALC_EN; 1530 rx_parity_cfg |= PAR_CALC_EN; 1531 if (termios->c_cflag & PARODD) { 1532 tx_parity_cfg |= PAR_ODD; 1533 rx_parity_cfg |= PAR_ODD; 1534 } else if (termios->c_cflag & CMSPAR) { 1535 tx_parity_cfg |= PAR_SPACE; 1536 rx_parity_cfg |= PAR_SPACE; 1537 } else { 1538 tx_parity_cfg |= PAR_EVEN; 1539 rx_parity_cfg |= PAR_EVEN; 1540 } 1541 } else { 1542 tx_trans_cfg &= ~UART_TX_PAR_EN; 1543 rx_trans_cfg &= ~UART_RX_PAR_EN; 1544 tx_parity_cfg &= ~PAR_CALC_EN; 1545 rx_parity_cfg &= ~PAR_CALC_EN; 1546 } 1547 1548 /* bits per char */ 1549 bits_per_char = tty_get_char_size(termios->c_cflag); 1550 1551 /* stop bits */ 1552 if (termios->c_cflag & CSTOPB) 1553 stop_bit_len = TX_STOP_BIT_LEN_2; 1554 else 1555 stop_bit_len = TX_STOP_BIT_LEN_1; 1556 1557 /* Configure flow control based on CRTSCTS flag. 1558 * When CRTSCTS is set, use HW/auto flow control mode, where HW 1559 * controls the RTS/CTS pin based FIFO state. 1560 * When CRTSCTS is clear, the CTS pin value is ignored for TX 1561 * path and RTS pin can be set/cleared using registers, for RX 1562 * path. 1563 */ 1564 1565 if (termios->c_cflag & CRTSCTS) { 1566 tx_trans_cfg &= ~UART_CTS_MASK; 1567 port->manual_flow = false; 1568 } else { 1569 tx_trans_cfg |= UART_CTS_MASK; 1570 port->manual_flow = true; 1571 } 1572 1573 if (baud) { 1574 uart_update_timeout(uport, termios->c_cflag, baud); 1575 1576 /* 1577 * Make sure that qcom_geni_serial_poll_bitfield() waits for 1578 * the FIFO, two-word intermediate transfer register and shift 1579 * register to clear. 1580 * 1581 * Note that uart_fifo_timeout() also adds a 20 ms margin. 1582 */ 1583 timeout = jiffies_to_usecs(uart_fifo_timeout(uport)); 1584 timeout += 3 * timeout / port->tx_fifo_depth; 1585 WRITE_ONCE(port->poll_timeout_us, timeout); 1586 } 1587 1588 if (!uart_console(uport)) 1589 writel(port->loopback, 1590 uport->membase + SE_UART_LOOPBACK_CFG); 1591 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1592 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1593 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1594 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1595 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1596 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1597 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1598 1599 trace_geni_serial_set_termios(uport->dev, baud, bits_per_char, 1600 tx_trans_cfg, tx_parity_cfg, rx_trans_cfg, 1601 rx_parity_cfg, stop_bit_len); 1602 } 1603 1604 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 1605 static int qcom_geni_console_setup(struct console *co, char *options) 1606 { 1607 struct uart_port *uport; 1608 struct qcom_geni_serial_port *port; 1609 int baud = 115200; 1610 int bits = 8; 1611 int parity = 'n'; 1612 int flow = 'n'; 1613 int ret; 1614 1615 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) 1616 return -ENXIO; 1617 1618 port = get_port_from_line(co->index, true, NULL); 1619 if (IS_ERR(port)) { 1620 pr_err("Invalid line %d\n", co->index); 1621 return PTR_ERR(port); 1622 } 1623 1624 uport = &port->uport; 1625 1626 if (unlikely(!uport->membase)) 1627 return -ENXIO; 1628 1629 ret = pm_runtime_resume_and_get(uport->dev); 1630 if (ret < 0) 1631 return ret; 1632 1633 if (!port->setup) { 1634 ret = qcom_geni_serial_port_setup(uport); 1635 if (ret) { 1636 pm_runtime_put_sync(uport->dev); 1637 return ret; 1638 } 1639 } 1640 1641 if (options) 1642 uart_parse_options(options, &baud, &parity, &bits, &flow); 1643 1644 ret = uart_set_options(uport, co, baud, parity, bits, flow); 1645 if (ret) 1646 pm_runtime_put_sync(uport->dev); 1647 1648 return ret; 1649 } 1650 1651 static int qcom_geni_console_exit(struct console *co) 1652 { 1653 struct qcom_geni_serial_port *port; 1654 1655 port = get_port_from_line(co->index, true, NULL); 1656 if (IS_ERR(port)) 1657 return PTR_ERR(port); 1658 1659 return pm_runtime_put_sync(port->uport.dev); 1660 } 1661 1662 static void qcom_geni_serial_earlycon_write(struct console *con, 1663 const char *s, unsigned int n) 1664 { 1665 struct earlycon_device *dev = con->data; 1666 1667 __qcom_geni_serial_console_write(&dev->port, s, n, false); 1668 } 1669 1670 #ifdef CONFIG_CONSOLE_POLL 1671 static int qcom_geni_serial_earlycon_read(struct console *con, 1672 char *s, unsigned int n) 1673 { 1674 struct earlycon_device *dev = con->data; 1675 struct uart_port *uport = &dev->port; 1676 int num_read = 0; 1677 int ch; 1678 1679 while (num_read < n) { 1680 ch = qcom_geni_serial_get_char(uport); 1681 if (ch == NO_POLL_CHAR) 1682 break; 1683 s[num_read++] = ch; 1684 } 1685 1686 return num_read; 1687 } 1688 1689 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se, 1690 struct console *con) 1691 { 1692 geni_se_setup_s_cmd(se, UART_START_READ, 0); 1693 con->read = qcom_geni_serial_earlycon_read; 1694 } 1695 #else 1696 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se, 1697 struct console *con) { } 1698 #endif 1699 1700 static struct qcom_geni_private_data earlycon_private_data; 1701 1702 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev, 1703 const char *opt) 1704 { 1705 struct uart_port *uport = &dev->port; 1706 u32 tx_trans_cfg; 1707 u32 tx_parity_cfg = 0; /* Disable Tx Parity */ 1708 u32 rx_trans_cfg = 0; 1709 u32 rx_parity_cfg = 0; /* Disable Rx Parity */ 1710 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ 1711 u32 bits_per_char; 1712 struct geni_se se; 1713 1714 if (!uport->membase) 1715 return -EINVAL; 1716 1717 uport->private_data = &earlycon_private_data; 1718 1719 memset(&se, 0, sizeof(se)); 1720 se.base = uport->membase; 1721 if (geni_se_read_proto(&se) != GENI_SE_UART) 1722 return -ENXIO; 1723 /* 1724 * Ignore Flow control. 1725 * n = 8. 1726 */ 1727 tx_trans_cfg = UART_CTS_MASK; 1728 bits_per_char = BITS_PER_BYTE; 1729 1730 /* 1731 * Make an unconditional cancel on the main sequencer to reset 1732 * it else we could end up in data loss scenarios. 1733 */ 1734 qcom_geni_serial_poll_tx_done(uport); 1735 qcom_geni_serial_abort_rx(uport); 1736 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1737 false, true, true); 1738 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); 1739 geni_se_select_mode(&se, GENI_SE_FIFO); 1740 1741 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1742 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1743 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1744 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1745 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1746 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1747 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1748 1749 dev->con->write = qcom_geni_serial_earlycon_write; 1750 dev->con->setup = NULL; 1751 qcom_geni_serial_enable_early_read(&se, dev->con); 1752 1753 return 0; 1754 } 1755 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart", 1756 qcom_geni_serial_earlycon_setup); 1757 1758 static int __init console_register(struct uart_driver *drv) 1759 { 1760 return uart_register_driver(drv); 1761 } 1762 1763 static void console_unregister(struct uart_driver *drv) 1764 { 1765 uart_unregister_driver(drv); 1766 } 1767 1768 static struct console cons_ops = { 1769 .name = "ttyMSM", 1770 .write_atomic = qcom_geni_serial_console_write_atomic, 1771 .write_thread = qcom_geni_serial_console_write_thread, 1772 .device_lock = qcom_geni_serial_console_device_lock, 1773 .device_unlock = qcom_geni_serial_console_device_unlock, 1774 .device = uart_console_device, 1775 .setup = qcom_geni_console_setup, 1776 .exit = qcom_geni_console_exit, 1777 .flags = CON_PRINTBUFFER | CON_NBCON, 1778 .index = -1, 1779 .data = &qcom_geni_console_driver, 1780 }; 1781 1782 static struct uart_driver qcom_geni_console_driver = { 1783 .owner = THIS_MODULE, 1784 .driver_name = "qcom_geni_console", 1785 .dev_name = "ttyMSM", 1786 .nr = GENI_UART_CONS_PORTS, 1787 .cons = &cons_ops, 1788 }; 1789 #else 1790 static int console_register(struct uart_driver *drv) 1791 { 1792 return 0; 1793 } 1794 1795 static void console_unregister(struct uart_driver *drv) 1796 { 1797 } 1798 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 1799 1800 static struct uart_driver qcom_geni_uart_driver = { 1801 .owner = THIS_MODULE, 1802 .driver_name = "qcom_geni_uart", 1803 .dev_name = "ttyHS", 1804 .nr = CONFIG_SERIAL_QCOM_GENI_UART_PORTS, 1805 }; 1806 1807 /** 1808 * qcom_geni_rs485_config - Configure RS485 settings for the UART port 1809 * @uport: Pointer to the UART port structure 1810 * @termios: Pointer to the termios structure 1811 * @rs485: Pointer to the RS485 configuration structure 1812 * This function configures the RTS (Request to Send) pin behavior for RS485 mode. 1813 * When RS485 mode is enabled, the RTS pin is kept in default ACTIVE HIGH state. 1814 * Return: Always returns 0. 1815 */ 1816 1817 static int qcom_geni_rs485_config(struct uart_port *uport, 1818 struct ktermios *termios, struct serial_rs485 *rs485) 1819 { 1820 qcom_geni_set_rs485_mode(uport, SER_RS485_ENABLED); 1821 1822 return 0; 1823 } 1824 1825 static const struct uart_ops qcom_geni_console_pops = { 1826 .tx_empty = qcom_geni_serial_tx_empty, 1827 .stop_tx = qcom_geni_serial_stop_tx_fifo, 1828 .start_tx = qcom_geni_serial_start_tx_fifo, 1829 .stop_rx = qcom_geni_serial_stop_rx_fifo, 1830 .start_rx = qcom_geni_serial_start_rx_fifo, 1831 .set_termios = qcom_geni_serial_set_termios, 1832 .startup = qcom_geni_serial_startup, 1833 .request_port = qcom_geni_serial_request_port, 1834 .config_port = qcom_geni_serial_config_port, 1835 .shutdown = qcom_geni_serial_shutdown, 1836 .flush_buffer = qcom_geni_serial_flush_buffer_fifo, 1837 .type = qcom_geni_serial_get_type, 1838 .set_mctrl = qcom_geni_serial_set_mctrl, 1839 .get_mctrl = qcom_geni_serial_get_mctrl, 1840 #ifdef CONFIG_CONSOLE_POLL 1841 .poll_get_char = qcom_geni_serial_get_char, 1842 .poll_put_char = qcom_geni_serial_poll_put_char, 1843 .poll_init = qcom_geni_serial_poll_init, 1844 #endif 1845 }; 1846 1847 static const struct uart_ops qcom_geni_uart_pops = { 1848 .tx_empty = qcom_geni_serial_tx_empty, 1849 .stop_tx = qcom_geni_serial_stop_tx_dma, 1850 .start_tx = qcom_geni_serial_start_tx_dma, 1851 .start_rx = qcom_geni_serial_start_rx_dma, 1852 .stop_rx = qcom_geni_serial_stop_rx_dma, 1853 .set_termios = qcom_geni_serial_set_termios, 1854 .startup = qcom_geni_serial_startup, 1855 .request_port = qcom_geni_serial_request_port, 1856 .config_port = qcom_geni_serial_config_port, 1857 .shutdown = qcom_geni_serial_shutdown, 1858 .flush_buffer = qcom_geni_serial_flush_buffer_dma, 1859 .type = qcom_geni_serial_get_type, 1860 .set_mctrl = qcom_geni_serial_set_mctrl, 1861 .get_mctrl = qcom_geni_serial_get_mctrl, 1862 }; 1863 1864 static int qcom_geni_serial_panic_notifier(struct notifier_block *nb, 1865 unsigned long action, void *data) 1866 { 1867 struct qcom_geni_serial_port *port = 1868 container_of(nb, struct qcom_geni_serial_port, panic_nb); 1869 struct uart_port *uport = &port->uport; 1870 1871 if (pm_runtime_status_suspended(uport->dev)) 1872 return NOTIFY_OK; 1873 1874 qcom_geni_serial_stop_tx(uport); 1875 qcom_geni_serial_stop_rx(uport); 1876 1877 return NOTIFY_OK; 1878 } 1879 1880 static int qcom_geni_serial_probe(struct platform_device *pdev) 1881 { 1882 int ret = 0; 1883 int line; 1884 struct qcom_geni_serial_port *port; 1885 struct uart_port *uport; 1886 struct resource *res; 1887 int irq; 1888 struct uart_driver *drv; 1889 const struct qcom_geni_device_data *data; 1890 1891 data = of_device_get_match_data(&pdev->dev); 1892 if (!data) 1893 return -EINVAL; 1894 1895 if (data->console) { 1896 drv = &qcom_geni_console_driver; 1897 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1898 } else { 1899 drv = &qcom_geni_uart_driver; 1900 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1901 if (line == -ENODEV) /* compat with non-standard aliases */ 1902 line = of_alias_get_id(pdev->dev.of_node, "hsuart"); 1903 } 1904 1905 port = get_port_from_line(line, data->console, &pdev->dev); 1906 if (IS_ERR(port)) { 1907 dev_err(&pdev->dev, "Invalid line %d\n", line); 1908 return PTR_ERR(port); 1909 } 1910 1911 uport = &port->uport; 1912 /* Don't allow 2 drivers to access the same port */ 1913 if (uport->private_data) 1914 return -ENODEV; 1915 1916 uport->dev = &pdev->dev; 1917 port->dev_data = data; 1918 port->se.dev = &pdev->dev; 1919 port->se.wrapper = dev_get_drvdata(pdev->dev.parent); 1920 1921 ret = port->dev_data->resources_init(&port->se); 1922 if (ret) 1923 return ret; 1924 1925 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1926 if (!res) { 1927 ret = -EINVAL; 1928 goto error; 1929 } 1930 1931 uport->mapbase = res->start; 1932 1933 uport->rs485_config = qcom_geni_rs485_config; 1934 uport->rs485_supported = qcom_geni_rs485_supported; 1935 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1936 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1937 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; 1938 1939 if (!data->console) { 1940 port->rx_buf = devm_kzalloc(uport->dev, 1941 DMA_RX_BUF_SIZE, GFP_KERNEL); 1942 if (!port->rx_buf) { 1943 ret = -ENOMEM; 1944 goto error; 1945 } 1946 1947 port->rx_dma_addr = dma_map_single(pdev->dev.parent, port->rx_buf, 1948 DMA_RX_BUF_SIZE, DMA_FROM_DEVICE); 1949 if (dma_mapping_error(pdev->dev.parent, port->rx_dma_addr)) { 1950 ret = -EIO; 1951 dev_err(&pdev->dev, "Failed to map RX DMA buffer: %d\n", ret); 1952 goto error; 1953 } 1954 } 1955 1956 port->name = devm_kasprintf(uport->dev, GFP_KERNEL, 1957 "qcom_geni_serial_%s%d", 1958 uart_console(uport) ? "console" : "uart", uport->line); 1959 if (!port->name) { 1960 ret = -ENOMEM; 1961 goto error; 1962 } 1963 1964 irq = platform_get_irq(pdev, 0); 1965 if (irq < 0) { 1966 ret = irq; 1967 goto error; 1968 } 1969 1970 uport->irq = irq; 1971 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); 1972 1973 if (!data->console) 1974 port->wakeup_irq = platform_get_irq_optional(pdev, 1); 1975 1976 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap")) 1977 port->rx_tx_swap = true; 1978 1979 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) 1980 port->cts_rts_swap = true; 1981 1982 port->private_data.drv = drv; 1983 uport->private_data = &port->private_data; 1984 init_irq_work(&port->tx_kick, qcom_geni_serial_restart_tx); 1985 platform_set_drvdata(pdev, port); 1986 1987 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); 1988 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, 1989 IRQF_TRIGGER_HIGH, port->name, uport); 1990 if (ret) { 1991 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); 1992 goto error; 1993 } 1994 1995 ret = uart_get_rs485_mode(uport); 1996 if (ret) 1997 goto error; 1998 1999 if (port->wakeup_irq > 0) { 2000 device_init_wakeup(&pdev->dev, true); 2001 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 2002 port->wakeup_irq); 2003 if (ret) { 2004 device_init_wakeup(&pdev->dev, false); 2005 ida_free(&port_ida, uport->line); 2006 goto error; 2007 } 2008 } 2009 2010 devm_pm_runtime_enable(port->se.dev); 2011 2012 ret = pm_runtime_resume_and_get(uport->dev); 2013 if (ret < 0) { 2014 dev_err(uport->dev, "Failed to resume and get %d\n", ret); 2015 goto error; 2016 } 2017 2018 ret = uart_add_one_port(drv, uport); 2019 pm_runtime_put(uport->dev); 2020 if (ret) 2021 goto error; 2022 2023 port->panic_nb.notifier_call = qcom_geni_serial_panic_notifier; 2024 atomic_notifier_chain_register(&panic_notifier_list, &port->panic_nb); 2025 2026 return 0; 2027 2028 error: 2029 if (port->rx_dma_addr) { 2030 dma_unmap_single(pdev->dev.parent, port->rx_dma_addr, 2031 DMA_RX_BUF_SIZE, DMA_FROM_DEVICE); 2032 port->rx_dma_addr = 0; 2033 } 2034 dev_pm_domain_detach_list(port->se.pd_list); 2035 return ret; 2036 } 2037 2038 static void qcom_geni_serial_remove(struct platform_device *pdev) 2039 { 2040 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); 2041 struct uart_port *uport = &port->uport; 2042 struct uart_driver *drv = port->private_data.drv; 2043 2044 atomic_notifier_chain_unregister(&panic_notifier_list, &port->panic_nb); 2045 2046 WRITE_ONCE(port->tx_kick_enabled, false); 2047 irq_work_sync(&port->tx_kick); 2048 dev_pm_clear_wake_irq(&pdev->dev); 2049 device_init_wakeup(&pdev->dev, false); 2050 ida_free(&port_ida, uport->line); 2051 uart_remove_one_port(drv, &port->uport); 2052 2053 if (port->rx_dma_addr) { 2054 dma_unmap_single(pdev->dev.parent, port->rx_dma_addr, 2055 DMA_RX_BUF_SIZE, DMA_FROM_DEVICE); 2056 port->rx_dma_addr = 0; 2057 } 2058 2059 dev_pm_domain_detach_list(port->se.pd_list); 2060 } 2061 2062 static int __maybe_unused qcom_geni_serial_runtime_suspend(struct device *dev) 2063 { 2064 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 2065 2066 return port->dev_data->power_off ? 2067 port->dev_data->power_off(&port->se) : 0; 2068 } 2069 2070 static int __maybe_unused qcom_geni_serial_runtime_resume(struct device *dev) 2071 { 2072 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 2073 struct uart_port *uport = &port->uport; 2074 int ret; 2075 2076 if (port->dev_data->power_on) { 2077 ret = port->dev_data->power_on(&port->se); 2078 if (ret) 2079 return ret; 2080 } 2081 2082 if (port->se.has_opp && port->clk_rate) 2083 return dev_pm_opp_set_rate(uport->dev, port->clk_rate); 2084 2085 return 0; 2086 } 2087 2088 static int qcom_geni_serial_suspend(struct device *dev) 2089 { 2090 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 2091 struct uart_port *uport = &port->uport; 2092 struct qcom_geni_private_data *private_data = uport->private_data; 2093 int ret; 2094 2095 /* 2096 * This is done so we can hit the lowest possible state in suspend 2097 * even with no_console_suspend 2098 */ 2099 if (uart_console(uport)) { 2100 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY); 2101 geni_icc_set_bw(&port->se); 2102 } 2103 2104 ret = uart_suspend_port(private_data->drv, uport); 2105 if (ret) 2106 return ret; 2107 2108 /* 2109 * When no_console_suspend is set the console must remain active 2110 * across system sleep, so skip the force suspend path. 2111 */ 2112 if (!console_suspend_enabled && uart_console(uport)) 2113 return 0; 2114 2115 return pm_runtime_force_suspend(dev); 2116 } 2117 2118 static int qcom_geni_serial_resume(struct device *dev) 2119 { 2120 int ret; 2121 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 2122 struct uart_port *uport = &port->uport; 2123 struct qcom_geni_private_data *private_data = uport->private_data; 2124 2125 if (console_suspend_enabled || !uart_console(uport)) { 2126 ret = pm_runtime_force_resume(dev); 2127 if (ret) 2128 return ret; 2129 } 2130 2131 ret = uart_resume_port(private_data->drv, uport); 2132 if (uart_console(uport)) { 2133 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); 2134 geni_icc_set_bw(&port->se); 2135 } 2136 return ret; 2137 } 2138 2139 #if IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE) 2140 static const struct qcom_geni_device_data qcom_geni_console_data = { 2141 .console = true, 2142 .mode = GENI_SE_FIFO, 2143 .resources_init = geni_se_resources_init, 2144 .set_rate = geni_serial_set_rate, 2145 .power_on = geni_se_resources_activate, 2146 .power_off = geni_se_resources_deactivate, 2147 }; 2148 2149 static const struct qcom_geni_device_data sa8255p_qcom_geni_console_data = { 2150 .console = true, 2151 .mode = GENI_SE_FIFO, 2152 .resources_init = geni_se_domain_attach, 2153 .set_rate = geni_se_set_perf_level, 2154 }; 2155 #endif 2156 2157 static const struct qcom_geni_device_data qcom_geni_uart_data = { 2158 .console = false, 2159 .mode = GENI_SE_DMA, 2160 .resources_init = geni_se_resources_init, 2161 .set_rate = geni_serial_set_rate, 2162 .power_on = geni_se_resources_activate, 2163 .power_off = geni_se_resources_deactivate, 2164 }; 2165 2166 static const struct qcom_geni_device_data sa8255p_qcom_geni_uart_data = { 2167 .console = false, 2168 .mode = GENI_SE_DMA, 2169 .resources_init = geni_se_domain_attach, 2170 .set_rate = geni_se_set_perf_level, 2171 }; 2172 2173 static const struct dev_pm_ops qcom_geni_serial_pm_ops = { 2174 SET_RUNTIME_PM_OPS(qcom_geni_serial_runtime_suspend, 2175 qcom_geni_serial_runtime_resume, NULL) 2176 SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_suspend, qcom_geni_serial_resume) 2177 }; 2178 2179 static void qcom_geni_serial_sys_shutdown(struct platform_device *pdev) 2180 { 2181 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); 2182 struct uart_port *uport = &port->uport; 2183 2184 if (pm_runtime_status_suspended(uport->dev)) 2185 return; 2186 2187 qcom_geni_serial_stop_tx(uport); 2188 qcom_geni_serial_stop_rx(uport); 2189 } 2190 2191 static const struct of_device_id qcom_geni_serial_match_table[] = { 2192 #if IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE) 2193 { 2194 .compatible = "qcom,geni-debug-uart", 2195 .data = &qcom_geni_console_data, 2196 }, 2197 { 2198 .compatible = "qcom,sa8255p-geni-debug-uart", 2199 .data = &sa8255p_qcom_geni_console_data, 2200 }, 2201 #endif 2202 { 2203 .compatible = "qcom,geni-uart", 2204 .data = &qcom_geni_uart_data, 2205 }, 2206 { 2207 .compatible = "qcom,sa8255p-geni-uart", 2208 .data = &sa8255p_qcom_geni_uart_data, 2209 }, 2210 {} 2211 }; 2212 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); 2213 2214 static struct platform_driver qcom_geni_serial_platform_driver = { 2215 .remove = qcom_geni_serial_remove, 2216 .probe = qcom_geni_serial_probe, 2217 .shutdown = qcom_geni_serial_sys_shutdown, 2218 .driver = { 2219 .name = "qcom_geni_serial", 2220 .of_match_table = qcom_geni_serial_match_table, 2221 .pm = &qcom_geni_serial_pm_ops, 2222 }, 2223 }; 2224 2225 static int __init qcom_geni_serial_init(void) 2226 { 2227 int ret; 2228 2229 ret = console_register(&qcom_geni_console_driver); 2230 if (ret) 2231 return ret; 2232 2233 ret = uart_register_driver(&qcom_geni_uart_driver); 2234 if (ret) { 2235 console_unregister(&qcom_geni_console_driver); 2236 return ret; 2237 } 2238 2239 ret = platform_driver_register(&qcom_geni_serial_platform_driver); 2240 if (ret) { 2241 console_unregister(&qcom_geni_console_driver); 2242 uart_unregister_driver(&qcom_geni_uart_driver); 2243 } 2244 return ret; 2245 } 2246 module_init(qcom_geni_serial_init); 2247 2248 static void __exit qcom_geni_serial_exit(void) 2249 { 2250 platform_driver_unregister(&qcom_geni_serial_platform_driver); 2251 console_unregister(&qcom_geni_console_driver); 2252 uart_unregister_driver(&qcom_geni_uart_driver); 2253 } 2254 module_exit(qcom_geni_serial_exit); 2255 2256 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores"); 2257 MODULE_LICENSE("GPL v2"); 2258