1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */ 5 #define __DISABLE_TRACE_MMIO__ 6 7 #include <linux/clk.h> 8 #include <linux/console.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/irq.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/pm_opp.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/pm_wakeirq.h> 18 #include <linux/soc/qcom/geni-se.h> 19 #include <linux/serial.h> 20 #include <linux/serial_core.h> 21 #include <linux/slab.h> 22 #include <linux/tty.h> 23 #include <linux/tty_flip.h> 24 #include <dt-bindings/interconnect/qcom,icc.h> 25 26 /* UART specific GENI registers */ 27 #define SE_UART_LOOPBACK_CFG 0x22c 28 #define SE_UART_IO_MACRO_CTRL 0x240 29 #define SE_UART_TX_TRANS_CFG 0x25c 30 #define SE_UART_TX_WORD_LEN 0x268 31 #define SE_UART_TX_STOP_BIT_LEN 0x26c 32 #define SE_UART_TX_TRANS_LEN 0x270 33 #define SE_UART_RX_TRANS_CFG 0x280 34 #define SE_UART_RX_WORD_LEN 0x28c 35 #define SE_UART_RX_STALE_CNT 0x294 36 #define SE_UART_TX_PARITY_CFG 0x2a4 37 #define SE_UART_RX_PARITY_CFG 0x2a8 38 #define SE_UART_MANUAL_RFR 0x2ac 39 40 /* SE_UART_TRANS_CFG */ 41 #define UART_TX_PAR_EN BIT(0) 42 #define UART_CTS_MASK BIT(1) 43 44 /* SE_UART_TX_STOP_BIT_LEN */ 45 #define TX_STOP_BIT_LEN_1 0 46 #define TX_STOP_BIT_LEN_2 2 47 48 /* SE_UART_RX_TRANS_CFG */ 49 #define UART_RX_PAR_EN BIT(3) 50 51 /* SE_UART_RX_WORD_LEN */ 52 #define RX_WORD_LEN_MASK GENMASK(9, 0) 53 54 /* SE_UART_RX_STALE_CNT */ 55 #define RX_STALE_CNT GENMASK(23, 0) 56 57 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ 58 #define PAR_CALC_EN BIT(0) 59 #define PAR_EVEN 0x00 60 #define PAR_ODD 0x01 61 #define PAR_SPACE 0x10 62 63 /* SE_UART_MANUAL_RFR register fields */ 64 #define UART_MANUAL_RFR_EN BIT(31) 65 #define UART_RFR_NOT_READY BIT(1) 66 #define UART_RFR_READY BIT(0) 67 68 /* UART M_CMD OP codes */ 69 #define UART_START_TX 0x1 70 /* UART S_CMD OP codes */ 71 #define UART_START_READ 0x1 72 #define UART_PARAM 0x1 73 #define UART_PARAM_RFR_OPEN BIT(7) 74 75 #define UART_OVERSAMPLING 32 76 #define STALE_TIMEOUT 16 77 #define DEFAULT_BITS_PER_CHAR 10 78 #define GENI_UART_CONS_PORTS 1 79 #define GENI_UART_PORTS 3 80 #define DEF_FIFO_DEPTH_WORDS 16 81 #define DEF_TX_WM 2 82 #define DEF_FIFO_WIDTH_BITS 32 83 #define UART_RX_WM 2 84 85 /* SE_UART_LOOPBACK_CFG */ 86 #define RX_TX_SORTED BIT(0) 87 #define CTS_RTS_SORTED BIT(1) 88 #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) 89 90 /* UART pin swap value */ 91 #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) 92 #define IO_MACRO_IO0_SEL 0x3 93 #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) 94 #define IO_MACRO_IO2_IO3_SWAP 0x4640 95 96 /* We always configure 4 bytes per FIFO word */ 97 #define BYTES_PER_FIFO_WORD 4U 98 99 #define DMA_RX_BUF_SIZE 2048 100 101 struct qcom_geni_device_data { 102 bool console; 103 enum geni_se_xfer_mode mode; 104 }; 105 106 struct qcom_geni_private_data { 107 /* NOTE: earlycon port will have NULL here */ 108 struct uart_driver *drv; 109 110 u32 poll_cached_bytes; 111 unsigned int poll_cached_bytes_cnt; 112 113 u32 write_cached_bytes; 114 unsigned int write_cached_bytes_cnt; 115 }; 116 117 struct qcom_geni_serial_port { 118 struct uart_port uport; 119 struct geni_se se; 120 const char *name; 121 u32 tx_fifo_depth; 122 u32 tx_fifo_width; 123 u32 rx_fifo_depth; 124 dma_addr_t tx_dma_addr; 125 dma_addr_t rx_dma_addr; 126 bool setup; 127 unsigned int baud; 128 unsigned long clk_rate; 129 void *rx_buf; 130 u32 loopback; 131 bool brk; 132 133 unsigned int tx_remaining; 134 int wakeup_irq; 135 bool rx_tx_swap; 136 bool cts_rts_swap; 137 138 struct qcom_geni_private_data private_data; 139 const struct qcom_geni_device_data *dev_data; 140 }; 141 142 static const struct uart_ops qcom_geni_console_pops; 143 static const struct uart_ops qcom_geni_uart_pops; 144 static struct uart_driver qcom_geni_console_driver; 145 static struct uart_driver qcom_geni_uart_driver; 146 147 static inline struct qcom_geni_serial_port *to_dev_port(struct uart_port *uport) 148 { 149 return container_of(uport, struct qcom_geni_serial_port, uport); 150 } 151 152 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = { 153 [0] = { 154 .uport = { 155 .iotype = UPIO_MEM, 156 .ops = &qcom_geni_uart_pops, 157 .flags = UPF_BOOT_AUTOCONF, 158 .line = 0, 159 }, 160 }, 161 [1] = { 162 .uport = { 163 .iotype = UPIO_MEM, 164 .ops = &qcom_geni_uart_pops, 165 .flags = UPF_BOOT_AUTOCONF, 166 .line = 1, 167 }, 168 }, 169 [2] = { 170 .uport = { 171 .iotype = UPIO_MEM, 172 .ops = &qcom_geni_uart_pops, 173 .flags = UPF_BOOT_AUTOCONF, 174 .line = 2, 175 }, 176 }, 177 }; 178 179 static struct qcom_geni_serial_port qcom_geni_console_port = { 180 .uport = { 181 .iotype = UPIO_MEM, 182 .ops = &qcom_geni_console_pops, 183 .flags = UPF_BOOT_AUTOCONF, 184 .line = 0, 185 }, 186 }; 187 188 static int qcom_geni_serial_request_port(struct uart_port *uport) 189 { 190 struct platform_device *pdev = to_platform_device(uport->dev); 191 struct qcom_geni_serial_port *port = to_dev_port(uport); 192 193 uport->membase = devm_platform_ioremap_resource(pdev, 0); 194 if (IS_ERR(uport->membase)) 195 return PTR_ERR(uport->membase); 196 port->se.base = uport->membase; 197 return 0; 198 } 199 200 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags) 201 { 202 if (cfg_flags & UART_CONFIG_TYPE) { 203 uport->type = PORT_MSM; 204 qcom_geni_serial_request_port(uport); 205 } 206 } 207 208 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport) 209 { 210 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR; 211 u32 geni_ios; 212 213 if (uart_console(uport)) { 214 mctrl |= TIOCM_CTS; 215 } else { 216 geni_ios = readl(uport->membase + SE_GENI_IOS); 217 if (!(geni_ios & IO2_DATA_IN)) 218 mctrl |= TIOCM_CTS; 219 } 220 221 return mctrl; 222 } 223 224 static void qcom_geni_serial_set_mctrl(struct uart_port *uport, 225 unsigned int mctrl) 226 { 227 u32 uart_manual_rfr = 0; 228 struct qcom_geni_serial_port *port = to_dev_port(uport); 229 230 if (uart_console(uport)) 231 return; 232 233 if (mctrl & TIOCM_LOOP) 234 port->loopback = RX_TX_CTS_RTS_SORTED; 235 236 if (!(mctrl & TIOCM_RTS) && !uport->suspended) 237 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; 238 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); 239 } 240 241 static const char *qcom_geni_serial_get_type(struct uart_port *uport) 242 { 243 return "MSM"; 244 } 245 246 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console) 247 { 248 struct qcom_geni_serial_port *port; 249 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS; 250 251 if (line < 0 || line >= nr_ports) 252 return ERR_PTR(-ENXIO); 253 254 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line]; 255 return port; 256 } 257 258 static bool qcom_geni_serial_main_active(struct uart_port *uport) 259 { 260 return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE; 261 } 262 263 static bool qcom_geni_serial_secondary_active(struct uart_port *uport) 264 { 265 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE; 266 } 267 268 static bool qcom_geni_serial_poll_bit(struct uart_port *uport, 269 int offset, int field, bool set) 270 { 271 u32 reg; 272 struct qcom_geni_serial_port *port; 273 unsigned int baud; 274 unsigned int fifo_bits; 275 unsigned long timeout_us = 20000; 276 struct qcom_geni_private_data *private_data = uport->private_data; 277 278 if (private_data->drv) { 279 port = to_dev_port(uport); 280 baud = port->baud; 281 if (!baud) 282 baud = 115200; 283 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width; 284 /* 285 * Total polling iterations based on FIFO worth of bytes to be 286 * sent at current baud. Add a little fluff to the wait. 287 */ 288 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; 289 } 290 291 /* 292 * Use custom implementation instead of readl_poll_atomic since ktimer 293 * is not ready at the time of early console. 294 */ 295 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; 296 while (timeout_us) { 297 reg = readl(uport->membase + offset); 298 if ((bool)(reg & field) == set) 299 return true; 300 udelay(10); 301 timeout_us -= 10; 302 } 303 return false; 304 } 305 306 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size) 307 { 308 u32 m_cmd; 309 310 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); 311 m_cmd = UART_START_TX << M_OPCODE_SHFT; 312 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); 313 } 314 315 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport) 316 { 317 int done; 318 u32 irq_clear = M_CMD_DONE_EN; 319 320 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 321 M_CMD_DONE_EN, true); 322 if (!done) { 323 writel(M_GENI_CMD_ABORT, uport->membase + 324 SE_GENI_M_CMD_CTRL_REG); 325 irq_clear |= M_CMD_ABORT_EN; 326 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 327 M_CMD_ABORT_EN, true); 328 } 329 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR); 330 } 331 332 static void qcom_geni_serial_abort_rx(struct uart_port *uport) 333 { 334 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN; 335 336 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); 337 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, 338 S_GENI_CMD_ABORT, false); 339 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); 340 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); 341 } 342 343 #ifdef CONFIG_CONSOLE_POLL 344 static int qcom_geni_serial_get_char(struct uart_port *uport) 345 { 346 struct qcom_geni_private_data *private_data = uport->private_data; 347 u32 status; 348 u32 word_cnt; 349 int ret; 350 351 if (!private_data->poll_cached_bytes_cnt) { 352 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 353 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR); 354 355 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 356 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR); 357 358 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 359 word_cnt = status & RX_FIFO_WC_MSK; 360 if (!word_cnt) 361 return NO_POLL_CHAR; 362 363 if (word_cnt == 1 && (status & RX_LAST)) 364 /* 365 * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be 366 * treated as if it was BYTES_PER_FIFO_WORD. 367 */ 368 private_data->poll_cached_bytes_cnt = 369 (status & RX_LAST_BYTE_VALID_MSK) >> 370 RX_LAST_BYTE_VALID_SHFT; 371 372 if (private_data->poll_cached_bytes_cnt == 0) 373 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD; 374 375 private_data->poll_cached_bytes = 376 readl(uport->membase + SE_GENI_RX_FIFOn); 377 } 378 379 private_data->poll_cached_bytes_cnt--; 380 ret = private_data->poll_cached_bytes & 0xff; 381 private_data->poll_cached_bytes >>= 8; 382 383 return ret; 384 } 385 386 static void qcom_geni_serial_poll_put_char(struct uart_port *uport, 387 unsigned char c) 388 { 389 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 390 qcom_geni_serial_setup_tx(uport, 1); 391 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 392 M_TX_FIFO_WATERMARK_EN, true)); 393 writel(c, uport->membase + SE_GENI_TX_FIFOn); 394 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 395 qcom_geni_serial_poll_tx_done(uport); 396 } 397 #endif 398 399 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 400 static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch) 401 { 402 struct qcom_geni_private_data *private_data = uport->private_data; 403 404 private_data->write_cached_bytes = 405 (private_data->write_cached_bytes >> 8) | (ch << 24); 406 private_data->write_cached_bytes_cnt++; 407 408 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) { 409 writel(private_data->write_cached_bytes, 410 uport->membase + SE_GENI_TX_FIFOn); 411 private_data->write_cached_bytes_cnt = 0; 412 } 413 } 414 415 static void 416 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s, 417 unsigned int count) 418 { 419 struct qcom_geni_private_data *private_data = uport->private_data; 420 421 int i; 422 u32 bytes_to_send = count; 423 424 for (i = 0; i < count; i++) { 425 /* 426 * uart_console_write() adds a carriage return for each newline. 427 * Account for additional bytes to be written. 428 */ 429 if (s[i] == '\n') 430 bytes_to_send++; 431 } 432 433 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 434 qcom_geni_serial_setup_tx(uport, bytes_to_send); 435 for (i = 0; i < count; ) { 436 size_t chars_to_write = 0; 437 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; 438 439 /* 440 * If the WM bit never set, then the Tx state machine is not 441 * in a valid state, so break, cancel/abort any existing 442 * command. Unfortunately the current data being written is 443 * lost. 444 */ 445 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 446 M_TX_FIFO_WATERMARK_EN, true)) 447 break; 448 chars_to_write = min_t(size_t, count - i, avail / 2); 449 uart_console_write(uport, s + i, chars_to_write, 450 qcom_geni_serial_wr_char); 451 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + 452 SE_GENI_M_IRQ_CLEAR); 453 i += chars_to_write; 454 } 455 456 if (private_data->write_cached_bytes_cnt) { 457 private_data->write_cached_bytes >>= BITS_PER_BYTE * 458 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt); 459 writel(private_data->write_cached_bytes, 460 uport->membase + SE_GENI_TX_FIFOn); 461 private_data->write_cached_bytes_cnt = 0; 462 } 463 464 qcom_geni_serial_poll_tx_done(uport); 465 } 466 467 static void qcom_geni_serial_console_write(struct console *co, const char *s, 468 unsigned int count) 469 { 470 struct uart_port *uport; 471 struct qcom_geni_serial_port *port; 472 bool locked = true; 473 unsigned long flags; 474 u32 geni_status; 475 u32 irq_en; 476 477 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); 478 479 port = get_port_from_line(co->index, true); 480 if (IS_ERR(port)) 481 return; 482 483 uport = &port->uport; 484 if (oops_in_progress) 485 locked = uart_port_trylock_irqsave(uport, &flags); 486 else 487 uart_port_lock_irqsave(uport, &flags); 488 489 geni_status = readl(uport->membase + SE_GENI_STATUS); 490 491 if (!locked) { 492 /* 493 * We can only get here if an oops is in progress then we were 494 * unable to get the lock. This means we can't safely access 495 * our state variables like tx_remaining. About the best we 496 * can do is wait for the FIFO to be empty before we start our 497 * transfer, so we'll do that. 498 */ 499 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 500 M_TX_FIFO_NOT_EMPTY_EN, false); 501 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) { 502 /* 503 * It seems we can't interrupt existing transfers if all data 504 * has been sent, in which case we need to look for done first. 505 */ 506 qcom_geni_serial_poll_tx_done(uport); 507 508 if (!uart_circ_empty(&uport->state->xmit)) { 509 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 510 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 511 uport->membase + SE_GENI_M_IRQ_EN); 512 } 513 } 514 515 __qcom_geni_serial_console_write(uport, s, count); 516 517 518 if (locked) { 519 if (port->tx_remaining) 520 qcom_geni_serial_setup_tx(uport, port->tx_remaining); 521 uart_port_unlock_irqrestore(uport, flags); 522 } 523 } 524 525 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 526 { 527 u32 i; 528 unsigned char buf[sizeof(u32)]; 529 struct tty_port *tport; 530 struct qcom_geni_serial_port *port = to_dev_port(uport); 531 532 tport = &uport->state->port; 533 for (i = 0; i < bytes; ) { 534 int c; 535 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD); 536 537 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); 538 i += chunk; 539 if (drop) 540 continue; 541 542 for (c = 0; c < chunk; c++) { 543 int sysrq; 544 545 uport->icount.rx++; 546 if (port->brk && buf[c] == 0) { 547 port->brk = false; 548 if (uart_handle_break(uport)) 549 continue; 550 } 551 552 sysrq = uart_prepare_sysrq_char(uport, buf[c]); 553 554 if (!sysrq) 555 tty_insert_flip_char(tport, buf[c], TTY_NORMAL); 556 } 557 } 558 if (!drop) 559 tty_flip_buffer_push(tport); 560 } 561 #else 562 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 563 { 564 565 } 566 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 567 568 static void handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop) 569 { 570 struct qcom_geni_serial_port *port = to_dev_port(uport); 571 struct tty_port *tport = &uport->state->port; 572 int ret; 573 574 ret = tty_insert_flip_string(tport, port->rx_buf, bytes); 575 if (ret != bytes) { 576 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n", 577 __func__, ret, bytes); 578 WARN_ON_ONCE(1); 579 } 580 uport->icount.rx += ret; 581 tty_flip_buffer_push(tport); 582 } 583 584 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport) 585 { 586 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 587 } 588 589 static void qcom_geni_serial_stop_tx_dma(struct uart_port *uport) 590 { 591 struct qcom_geni_serial_port *port = to_dev_port(uport); 592 bool done; 593 594 if (!qcom_geni_serial_main_active(uport)) 595 return; 596 597 if (port->tx_dma_addr) { 598 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, 599 port->tx_remaining); 600 port->tx_dma_addr = 0; 601 port->tx_remaining = 0; 602 } 603 604 geni_se_cancel_m_cmd(&port->se); 605 606 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 607 M_CMD_CANCEL_EN, true); 608 if (!done) { 609 geni_se_abort_m_cmd(&port->se); 610 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 611 M_CMD_ABORT_EN, true); 612 if (!done) 613 dev_err_ratelimited(uport->dev, "M_CMD_ABORT_EN not set"); 614 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 615 } 616 617 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 618 } 619 620 static void qcom_geni_serial_start_tx_dma(struct uart_port *uport) 621 { 622 struct qcom_geni_serial_port *port = to_dev_port(uport); 623 struct circ_buf *xmit = &uport->state->xmit; 624 unsigned int xmit_size; 625 int ret; 626 627 if (port->tx_dma_addr) 628 return; 629 630 if (uart_circ_empty(xmit)) 631 return; 632 633 xmit_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 634 635 qcom_geni_serial_setup_tx(uport, xmit_size); 636 637 ret = geni_se_tx_dma_prep(&port->se, &xmit->buf[xmit->tail], 638 xmit_size, &port->tx_dma_addr); 639 if (ret) { 640 dev_err(uport->dev, "unable to start TX SE DMA: %d\n", ret); 641 qcom_geni_serial_stop_tx_dma(uport); 642 return; 643 } 644 645 port->tx_remaining = xmit_size; 646 } 647 648 static void qcom_geni_serial_start_tx_fifo(struct uart_port *uport) 649 { 650 u32 irq_en; 651 652 if (qcom_geni_serial_main_active(uport) || 653 !qcom_geni_serial_tx_empty(uport)) 654 return; 655 656 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 657 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; 658 659 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 660 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 661 } 662 663 static void qcom_geni_serial_stop_tx_fifo(struct uart_port *uport) 664 { 665 u32 irq_en; 666 struct qcom_geni_serial_port *port = to_dev_port(uport); 667 668 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 669 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 670 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); 671 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 672 /* Possible stop tx is called multiple times. */ 673 if (!qcom_geni_serial_main_active(uport)) 674 return; 675 676 geni_se_cancel_m_cmd(&port->se); 677 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 678 M_CMD_CANCEL_EN, true)) { 679 geni_se_abort_m_cmd(&port->se); 680 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 681 M_CMD_ABORT_EN, true); 682 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 683 } 684 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 685 } 686 687 static void qcom_geni_serial_handle_rx_fifo(struct uart_port *uport, bool drop) 688 { 689 u32 status; 690 u32 word_cnt; 691 u32 last_word_byte_cnt; 692 u32 last_word_partial; 693 u32 total_bytes; 694 695 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 696 word_cnt = status & RX_FIFO_WC_MSK; 697 last_word_partial = status & RX_LAST; 698 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >> 699 RX_LAST_BYTE_VALID_SHFT; 700 701 if (!word_cnt) 702 return; 703 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1); 704 if (last_word_partial && last_word_byte_cnt) 705 total_bytes += last_word_byte_cnt; 706 else 707 total_bytes += BYTES_PER_FIFO_WORD; 708 handle_rx_console(uport, total_bytes, drop); 709 } 710 711 static void qcom_geni_serial_stop_rx_fifo(struct uart_port *uport) 712 { 713 u32 irq_en; 714 struct qcom_geni_serial_port *port = to_dev_port(uport); 715 u32 s_irq_status; 716 717 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 718 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); 719 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 720 721 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 722 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 723 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 724 725 if (!qcom_geni_serial_secondary_active(uport)) 726 return; 727 728 geni_se_cancel_s_cmd(&port->se); 729 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 730 S_CMD_CANCEL_EN, true); 731 /* 732 * If timeout occurs secondary engine remains active 733 * and Abort sequence is executed. 734 */ 735 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 736 /* Flush the Rx buffer */ 737 if (s_irq_status & S_RX_FIFO_LAST_EN) 738 qcom_geni_serial_handle_rx_fifo(uport, true); 739 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 740 741 if (qcom_geni_serial_secondary_active(uport)) 742 qcom_geni_serial_abort_rx(uport); 743 } 744 745 static void qcom_geni_serial_start_rx_fifo(struct uart_port *uport) 746 { 747 u32 irq_en; 748 struct qcom_geni_serial_port *port = to_dev_port(uport); 749 750 if (qcom_geni_serial_secondary_active(uport)) 751 qcom_geni_serial_stop_rx_fifo(uport); 752 753 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); 754 755 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 756 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; 757 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 758 759 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 760 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 761 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 762 } 763 764 static void qcom_geni_serial_stop_rx_dma(struct uart_port *uport) 765 { 766 struct qcom_geni_serial_port *port = to_dev_port(uport); 767 768 if (!qcom_geni_serial_secondary_active(uport)) 769 return; 770 771 geni_se_cancel_s_cmd(&port->se); 772 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 773 S_CMD_CANCEL_EN, true); 774 775 if (qcom_geni_serial_secondary_active(uport)) 776 qcom_geni_serial_abort_rx(uport); 777 778 if (port->rx_dma_addr) { 779 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, 780 DMA_RX_BUF_SIZE); 781 port->rx_dma_addr = 0; 782 } 783 } 784 785 static void qcom_geni_serial_start_rx_dma(struct uart_port *uport) 786 { 787 struct qcom_geni_serial_port *port = to_dev_port(uport); 788 int ret; 789 790 if (qcom_geni_serial_secondary_active(uport)) 791 qcom_geni_serial_stop_rx_dma(uport); 792 793 geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN); 794 795 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, 796 DMA_RX_BUF_SIZE, 797 &port->rx_dma_addr); 798 if (ret) { 799 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); 800 qcom_geni_serial_stop_rx_dma(uport); 801 } 802 } 803 804 static void qcom_geni_serial_handle_rx_dma(struct uart_port *uport, bool drop) 805 { 806 struct qcom_geni_serial_port *port = to_dev_port(uport); 807 u32 rx_in; 808 int ret; 809 810 if (!qcom_geni_serial_secondary_active(uport)) 811 return; 812 813 if (!port->rx_dma_addr) 814 return; 815 816 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE); 817 port->rx_dma_addr = 0; 818 819 rx_in = readl(uport->membase + SE_DMA_RX_LEN_IN); 820 if (!rx_in) { 821 dev_warn(uport->dev, "serial engine reports 0 RX bytes in!\n"); 822 return; 823 } 824 825 if (!drop) 826 handle_rx_uart(uport, rx_in, drop); 827 828 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, 829 DMA_RX_BUF_SIZE, 830 &port->rx_dma_addr); 831 if (ret) { 832 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); 833 qcom_geni_serial_stop_rx_dma(uport); 834 } 835 } 836 837 static void qcom_geni_serial_start_rx(struct uart_port *uport) 838 { 839 uport->ops->start_rx(uport); 840 } 841 842 static void qcom_geni_serial_stop_rx(struct uart_port *uport) 843 { 844 uport->ops->stop_rx(uport); 845 } 846 847 static void qcom_geni_serial_stop_tx(struct uart_port *uport) 848 { 849 uport->ops->stop_tx(uport); 850 } 851 852 static void qcom_geni_serial_send_chunk_fifo(struct uart_port *uport, 853 unsigned int chunk) 854 { 855 struct qcom_geni_serial_port *port = to_dev_port(uport); 856 struct circ_buf *xmit = &uport->state->xmit; 857 unsigned int tx_bytes, c, remaining = chunk; 858 u8 buf[BYTES_PER_FIFO_WORD]; 859 860 while (remaining) { 861 memset(buf, 0, sizeof(buf)); 862 tx_bytes = min(remaining, BYTES_PER_FIFO_WORD); 863 864 for (c = 0; c < tx_bytes ; c++) { 865 buf[c] = xmit->buf[xmit->tail]; 866 uart_xmit_advance(uport, 1); 867 } 868 869 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); 870 871 remaining -= tx_bytes; 872 port->tx_remaining -= tx_bytes; 873 } 874 } 875 876 static void qcom_geni_serial_handle_tx_fifo(struct uart_port *uport, 877 bool done, bool active) 878 { 879 struct qcom_geni_serial_port *port = to_dev_port(uport); 880 struct circ_buf *xmit = &uport->state->xmit; 881 size_t avail; 882 size_t pending; 883 u32 status; 884 u32 irq_en; 885 unsigned int chunk; 886 887 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 888 889 /* Complete the current tx command before taking newly added data */ 890 if (active) 891 pending = port->tx_remaining; 892 else 893 pending = uart_circ_chars_pending(xmit); 894 895 /* All data has been transmitted and acknowledged as received */ 896 if (!pending && !status && done) { 897 qcom_geni_serial_stop_tx_fifo(uport); 898 goto out_write_wakeup; 899 } 900 901 avail = port->tx_fifo_depth - (status & TX_FIFO_WC); 902 avail *= BYTES_PER_FIFO_WORD; 903 904 chunk = min(avail, pending); 905 if (!chunk) 906 goto out_write_wakeup; 907 908 if (!port->tx_remaining) { 909 qcom_geni_serial_setup_tx(uport, pending); 910 port->tx_remaining = pending; 911 912 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 913 if (!(irq_en & M_TX_FIFO_WATERMARK_EN)) 914 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 915 uport->membase + SE_GENI_M_IRQ_EN); 916 } 917 918 qcom_geni_serial_send_chunk_fifo(uport, chunk); 919 920 /* 921 * The tx fifo watermark is level triggered and latched. Though we had 922 * cleared it in qcom_geni_serial_isr it will have already reasserted 923 * so we must clear it again here after our writes. 924 */ 925 writel(M_TX_FIFO_WATERMARK_EN, 926 uport->membase + SE_GENI_M_IRQ_CLEAR); 927 928 out_write_wakeup: 929 if (!port->tx_remaining) { 930 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 931 if (irq_en & M_TX_FIFO_WATERMARK_EN) 932 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN, 933 uport->membase + SE_GENI_M_IRQ_EN); 934 } 935 936 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 937 uart_write_wakeup(uport); 938 } 939 940 static void qcom_geni_serial_handle_tx_dma(struct uart_port *uport) 941 { 942 struct qcom_geni_serial_port *port = to_dev_port(uport); 943 struct circ_buf *xmit = &uport->state->xmit; 944 945 uart_xmit_advance(uport, port->tx_remaining); 946 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining); 947 port->tx_dma_addr = 0; 948 port->tx_remaining = 0; 949 950 if (!uart_circ_empty(xmit)) 951 qcom_geni_serial_start_tx_dma(uport); 952 953 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 954 uart_write_wakeup(uport); 955 } 956 957 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) 958 { 959 u32 m_irq_en; 960 u32 m_irq_status; 961 u32 s_irq_status; 962 u32 geni_status; 963 u32 dma; 964 u32 dma_tx_status; 965 u32 dma_rx_status; 966 struct uart_port *uport = dev; 967 bool drop_rx = false; 968 struct tty_port *tport = &uport->state->port; 969 struct qcom_geni_serial_port *port = to_dev_port(uport); 970 971 if (uport->suspended) 972 return IRQ_NONE; 973 974 uart_port_lock(uport); 975 976 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 977 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 978 dma_tx_status = readl(uport->membase + SE_DMA_TX_IRQ_STAT); 979 dma_rx_status = readl(uport->membase + SE_DMA_RX_IRQ_STAT); 980 geni_status = readl(uport->membase + SE_GENI_STATUS); 981 dma = readl(uport->membase + SE_GENI_DMA_MODE_EN); 982 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 983 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); 984 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 985 writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR); 986 writel(dma_rx_status, uport->membase + SE_DMA_RX_IRQ_CLR); 987 988 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN)) 989 goto out_unlock; 990 991 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) { 992 uport->icount.overrun++; 993 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 994 } 995 996 if (s_irq_status & (S_GP_IRQ_0_EN | S_GP_IRQ_1_EN)) { 997 if (s_irq_status & S_GP_IRQ_0_EN) 998 uport->icount.parity++; 999 drop_rx = true; 1000 } else if (s_irq_status & (S_GP_IRQ_2_EN | S_GP_IRQ_3_EN)) { 1001 uport->icount.brk++; 1002 port->brk = true; 1003 } 1004 1005 if (dma) { 1006 if (dma_tx_status & TX_DMA_DONE) 1007 qcom_geni_serial_handle_tx_dma(uport); 1008 1009 if (dma_rx_status) { 1010 if (dma_rx_status & RX_RESET_DONE) 1011 goto out_unlock; 1012 1013 if (dma_rx_status & RX_DMA_PARITY_ERR) { 1014 uport->icount.parity++; 1015 drop_rx = true; 1016 } 1017 1018 if (dma_rx_status & RX_DMA_BREAK) 1019 uport->icount.brk++; 1020 1021 if (dma_rx_status & (RX_DMA_DONE | RX_EOT)) 1022 qcom_geni_serial_handle_rx_dma(uport, drop_rx); 1023 } 1024 } else { 1025 if (m_irq_status & m_irq_en & 1026 (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) 1027 qcom_geni_serial_handle_tx_fifo(uport, 1028 m_irq_status & M_CMD_DONE_EN, 1029 geni_status & M_GENI_CMD_ACTIVE); 1030 1031 if (s_irq_status & (S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN)) 1032 qcom_geni_serial_handle_rx_fifo(uport, drop_rx); 1033 } 1034 1035 out_unlock: 1036 uart_unlock_and_check_sysrq(uport); 1037 1038 return IRQ_HANDLED; 1039 } 1040 1041 static int setup_fifos(struct qcom_geni_serial_port *port) 1042 { 1043 struct uart_port *uport; 1044 u32 old_rx_fifo_depth = port->rx_fifo_depth; 1045 1046 uport = &port->uport; 1047 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); 1048 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); 1049 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); 1050 uport->fifosize = 1051 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; 1052 1053 if (port->rx_buf && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) { 1054 /* 1055 * Use krealloc rather than krealloc_array because rx_buf is 1056 * accessed as 1 byte entries as well as 4 byte entries so it's 1057 * not necessarily an array. 1058 */ 1059 port->rx_buf = devm_krealloc(uport->dev, port->rx_buf, 1060 port->rx_fifo_depth * sizeof(u32), 1061 GFP_KERNEL); 1062 if (!port->rx_buf) 1063 return -ENOMEM; 1064 } 1065 1066 return 0; 1067 } 1068 1069 1070 static void qcom_geni_serial_shutdown(struct uart_port *uport) 1071 { 1072 disable_irq(uport->irq); 1073 1074 if (uart_console(uport)) 1075 return; 1076 1077 qcom_geni_serial_stop_tx(uport); 1078 qcom_geni_serial_stop_rx(uport); 1079 } 1080 1081 static int qcom_geni_serial_port_setup(struct uart_port *uport) 1082 { 1083 struct qcom_geni_serial_port *port = to_dev_port(uport); 1084 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT; 1085 u32 proto; 1086 u32 pin_swap; 1087 int ret; 1088 1089 proto = geni_se_read_proto(&port->se); 1090 if (proto != GENI_SE_UART) { 1091 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); 1092 return -ENXIO; 1093 } 1094 1095 qcom_geni_serial_stop_rx(uport); 1096 1097 ret = setup_fifos(port); 1098 if (ret) 1099 return ret; 1100 1101 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); 1102 1103 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL); 1104 if (port->rx_tx_swap) { 1105 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK; 1106 pin_swap |= IO_MACRO_IO2_IO3_SWAP; 1107 } 1108 if (port->cts_rts_swap) { 1109 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK; 1110 pin_swap |= IO_MACRO_IO0_SEL; 1111 } 1112 /* Configure this register if RX-TX, CTS-RTS pins are swapped */ 1113 if (port->rx_tx_swap || port->cts_rts_swap) 1114 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL); 1115 1116 /* 1117 * Make an unconditional cancel on the main sequencer to reset 1118 * it else we could end up in data loss scenarios. 1119 */ 1120 if (uart_console(uport)) 1121 qcom_geni_serial_poll_tx_done(uport); 1122 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1123 false, true, true); 1124 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); 1125 geni_se_select_mode(&port->se, port->dev_data->mode); 1126 qcom_geni_serial_start_rx(uport); 1127 port->setup = true; 1128 1129 return 0; 1130 } 1131 1132 static int qcom_geni_serial_startup(struct uart_port *uport) 1133 { 1134 int ret; 1135 struct qcom_geni_serial_port *port = to_dev_port(uport); 1136 1137 if (!port->setup) { 1138 ret = qcom_geni_serial_port_setup(uport); 1139 if (ret) 1140 return ret; 1141 } 1142 enable_irq(uport->irq); 1143 1144 return 0; 1145 } 1146 1147 static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int desired_clk, 1148 unsigned int *clk_div, unsigned int percent_tol) 1149 { 1150 unsigned long freq; 1151 unsigned long div, maxdiv; 1152 u64 mult; 1153 unsigned long offset, abs_tol, achieved; 1154 1155 abs_tol = div_u64((u64)desired_clk * percent_tol, 100); 1156 maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT; 1157 div = 1; 1158 while (div <= maxdiv) { 1159 mult = (u64)div * desired_clk; 1160 if (mult != (unsigned long)mult) 1161 break; 1162 1163 offset = div * abs_tol; 1164 freq = clk_round_rate(clk, mult - offset); 1165 1166 /* Can only get lower if we're done */ 1167 if (freq < mult - offset) 1168 break; 1169 1170 /* 1171 * Re-calculate div in case rounding skipped rates but we 1172 * ended up at a good one, then check for a match. 1173 */ 1174 div = DIV_ROUND_CLOSEST(freq, desired_clk); 1175 achieved = DIV_ROUND_CLOSEST(freq, div); 1176 if (achieved <= desired_clk + abs_tol && 1177 achieved >= desired_clk - abs_tol) { 1178 *clk_div = div; 1179 return freq; 1180 } 1181 1182 div = DIV_ROUND_UP(freq, desired_clk); 1183 } 1184 1185 return 0; 1186 } 1187 1188 static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud, 1189 unsigned int sampling_rate, unsigned int *clk_div) 1190 { 1191 unsigned long ser_clk; 1192 unsigned long desired_clk; 1193 1194 desired_clk = baud * sampling_rate; 1195 if (!desired_clk) 1196 return 0; 1197 1198 /* 1199 * try to find a clock rate within 2% tolerance, then within 5% 1200 */ 1201 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2); 1202 if (!ser_clk) 1203 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5); 1204 1205 return ser_clk; 1206 } 1207 1208 static void qcom_geni_serial_set_termios(struct uart_port *uport, 1209 struct ktermios *termios, 1210 const struct ktermios *old) 1211 { 1212 unsigned int baud; 1213 u32 bits_per_char; 1214 u32 tx_trans_cfg; 1215 u32 tx_parity_cfg; 1216 u32 rx_trans_cfg; 1217 u32 rx_parity_cfg; 1218 u32 stop_bit_len; 1219 unsigned int clk_div; 1220 u32 ser_clk_cfg; 1221 struct qcom_geni_serial_port *port = to_dev_port(uport); 1222 unsigned long clk_rate; 1223 u32 ver, sampling_rate; 1224 unsigned int avg_bw_core; 1225 1226 qcom_geni_serial_stop_rx(uport); 1227 /* baud rate */ 1228 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); 1229 port->baud = baud; 1230 1231 sampling_rate = UART_OVERSAMPLING; 1232 /* Sampling rate is halved for IP versions >= 2.5 */ 1233 ver = geni_se_get_qup_hw_version(&port->se); 1234 if (ver >= QUP_SE_VERSION_2_5) 1235 sampling_rate /= 2; 1236 1237 clk_rate = get_clk_div_rate(port->se.clk, baud, 1238 sampling_rate, &clk_div); 1239 if (!clk_rate) { 1240 dev_err(port->se.dev, 1241 "Couldn't find suitable clock rate for %u\n", 1242 baud * sampling_rate); 1243 goto out_restart_rx; 1244 } 1245 1246 dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n", 1247 baud * sampling_rate, clk_rate, clk_div); 1248 1249 uport->uartclk = clk_rate; 1250 port->clk_rate = clk_rate; 1251 dev_pm_opp_set_rate(uport->dev, clk_rate); 1252 ser_clk_cfg = SER_CLK_EN; 1253 ser_clk_cfg |= clk_div << CLK_DIV_SHFT; 1254 1255 /* 1256 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode 1257 * only. 1258 */ 1259 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ) 1260 : GENI_DEFAULT_BW; 1261 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core; 1262 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); 1263 geni_icc_set_bw(&port->se); 1264 1265 /* parity */ 1266 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); 1267 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); 1268 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG); 1269 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG); 1270 if (termios->c_cflag & PARENB) { 1271 tx_trans_cfg |= UART_TX_PAR_EN; 1272 rx_trans_cfg |= UART_RX_PAR_EN; 1273 tx_parity_cfg |= PAR_CALC_EN; 1274 rx_parity_cfg |= PAR_CALC_EN; 1275 if (termios->c_cflag & PARODD) { 1276 tx_parity_cfg |= PAR_ODD; 1277 rx_parity_cfg |= PAR_ODD; 1278 } else if (termios->c_cflag & CMSPAR) { 1279 tx_parity_cfg |= PAR_SPACE; 1280 rx_parity_cfg |= PAR_SPACE; 1281 } else { 1282 tx_parity_cfg |= PAR_EVEN; 1283 rx_parity_cfg |= PAR_EVEN; 1284 } 1285 } else { 1286 tx_trans_cfg &= ~UART_TX_PAR_EN; 1287 rx_trans_cfg &= ~UART_RX_PAR_EN; 1288 tx_parity_cfg &= ~PAR_CALC_EN; 1289 rx_parity_cfg &= ~PAR_CALC_EN; 1290 } 1291 1292 /* bits per char */ 1293 bits_per_char = tty_get_char_size(termios->c_cflag); 1294 1295 /* stop bits */ 1296 if (termios->c_cflag & CSTOPB) 1297 stop_bit_len = TX_STOP_BIT_LEN_2; 1298 else 1299 stop_bit_len = TX_STOP_BIT_LEN_1; 1300 1301 /* flow control, clear the CTS_MASK bit if using flow control. */ 1302 if (termios->c_cflag & CRTSCTS) 1303 tx_trans_cfg &= ~UART_CTS_MASK; 1304 else 1305 tx_trans_cfg |= UART_CTS_MASK; 1306 1307 if (baud) 1308 uart_update_timeout(uport, termios->c_cflag, baud); 1309 1310 if (!uart_console(uport)) 1311 writel(port->loopback, 1312 uport->membase + SE_UART_LOOPBACK_CFG); 1313 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1314 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1315 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1316 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1317 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1318 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1319 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1320 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); 1321 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); 1322 out_restart_rx: 1323 qcom_geni_serial_start_rx(uport); 1324 } 1325 1326 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 1327 static int qcom_geni_console_setup(struct console *co, char *options) 1328 { 1329 struct uart_port *uport; 1330 struct qcom_geni_serial_port *port; 1331 int baud = 115200; 1332 int bits = 8; 1333 int parity = 'n'; 1334 int flow = 'n'; 1335 int ret; 1336 1337 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) 1338 return -ENXIO; 1339 1340 port = get_port_from_line(co->index, true); 1341 if (IS_ERR(port)) { 1342 pr_err("Invalid line %d\n", co->index); 1343 return PTR_ERR(port); 1344 } 1345 1346 uport = &port->uport; 1347 1348 if (unlikely(!uport->membase)) 1349 return -ENXIO; 1350 1351 if (!port->setup) { 1352 ret = qcom_geni_serial_port_setup(uport); 1353 if (ret) 1354 return ret; 1355 } 1356 1357 if (options) 1358 uart_parse_options(options, &baud, &parity, &bits, &flow); 1359 1360 return uart_set_options(uport, co, baud, parity, bits, flow); 1361 } 1362 1363 static void qcom_geni_serial_earlycon_write(struct console *con, 1364 const char *s, unsigned int n) 1365 { 1366 struct earlycon_device *dev = con->data; 1367 1368 __qcom_geni_serial_console_write(&dev->port, s, n); 1369 } 1370 1371 #ifdef CONFIG_CONSOLE_POLL 1372 static int qcom_geni_serial_earlycon_read(struct console *con, 1373 char *s, unsigned int n) 1374 { 1375 struct earlycon_device *dev = con->data; 1376 struct uart_port *uport = &dev->port; 1377 int num_read = 0; 1378 int ch; 1379 1380 while (num_read < n) { 1381 ch = qcom_geni_serial_get_char(uport); 1382 if (ch == NO_POLL_CHAR) 1383 break; 1384 s[num_read++] = ch; 1385 } 1386 1387 return num_read; 1388 } 1389 1390 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se, 1391 struct console *con) 1392 { 1393 geni_se_setup_s_cmd(se, UART_START_READ, 0); 1394 con->read = qcom_geni_serial_earlycon_read; 1395 } 1396 #else 1397 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se, 1398 struct console *con) { } 1399 #endif 1400 1401 static struct qcom_geni_private_data earlycon_private_data; 1402 1403 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev, 1404 const char *opt) 1405 { 1406 struct uart_port *uport = &dev->port; 1407 u32 tx_trans_cfg; 1408 u32 tx_parity_cfg = 0; /* Disable Tx Parity */ 1409 u32 rx_trans_cfg = 0; 1410 u32 rx_parity_cfg = 0; /* Disable Rx Parity */ 1411 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ 1412 u32 bits_per_char; 1413 struct geni_se se; 1414 1415 if (!uport->membase) 1416 return -EINVAL; 1417 1418 uport->private_data = &earlycon_private_data; 1419 1420 memset(&se, 0, sizeof(se)); 1421 se.base = uport->membase; 1422 if (geni_se_read_proto(&se) != GENI_SE_UART) 1423 return -ENXIO; 1424 /* 1425 * Ignore Flow control. 1426 * n = 8. 1427 */ 1428 tx_trans_cfg = UART_CTS_MASK; 1429 bits_per_char = BITS_PER_BYTE; 1430 1431 /* 1432 * Make an unconditional cancel on the main sequencer to reset 1433 * it else we could end up in data loss scenarios. 1434 */ 1435 qcom_geni_serial_poll_tx_done(uport); 1436 qcom_geni_serial_abort_rx(uport); 1437 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1438 false, true, true); 1439 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); 1440 geni_se_select_mode(&se, GENI_SE_FIFO); 1441 1442 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1443 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1444 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1445 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1446 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1447 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1448 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1449 1450 dev->con->write = qcom_geni_serial_earlycon_write; 1451 dev->con->setup = NULL; 1452 qcom_geni_serial_enable_early_read(&se, dev->con); 1453 1454 return 0; 1455 } 1456 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart", 1457 qcom_geni_serial_earlycon_setup); 1458 1459 static int __init console_register(struct uart_driver *drv) 1460 { 1461 return uart_register_driver(drv); 1462 } 1463 1464 static void console_unregister(struct uart_driver *drv) 1465 { 1466 uart_unregister_driver(drv); 1467 } 1468 1469 static struct console cons_ops = { 1470 .name = "ttyMSM", 1471 .write = qcom_geni_serial_console_write, 1472 .device = uart_console_device, 1473 .setup = qcom_geni_console_setup, 1474 .flags = CON_PRINTBUFFER, 1475 .index = -1, 1476 .data = &qcom_geni_console_driver, 1477 }; 1478 1479 static struct uart_driver qcom_geni_console_driver = { 1480 .owner = THIS_MODULE, 1481 .driver_name = "qcom_geni_console", 1482 .dev_name = "ttyMSM", 1483 .nr = GENI_UART_CONS_PORTS, 1484 .cons = &cons_ops, 1485 }; 1486 #else 1487 static int console_register(struct uart_driver *drv) 1488 { 1489 return 0; 1490 } 1491 1492 static void console_unregister(struct uart_driver *drv) 1493 { 1494 } 1495 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 1496 1497 static struct uart_driver qcom_geni_uart_driver = { 1498 .owner = THIS_MODULE, 1499 .driver_name = "qcom_geni_uart", 1500 .dev_name = "ttyHS", 1501 .nr = GENI_UART_PORTS, 1502 }; 1503 1504 static void qcom_geni_serial_pm(struct uart_port *uport, 1505 unsigned int new_state, unsigned int old_state) 1506 { 1507 struct qcom_geni_serial_port *port = to_dev_port(uport); 1508 1509 /* If we've never been called, treat it as off */ 1510 if (old_state == UART_PM_STATE_UNDEFINED) 1511 old_state = UART_PM_STATE_OFF; 1512 1513 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) { 1514 geni_icc_enable(&port->se); 1515 if (port->clk_rate) 1516 dev_pm_opp_set_rate(uport->dev, port->clk_rate); 1517 geni_se_resources_on(&port->se); 1518 } else if (new_state == UART_PM_STATE_OFF && 1519 old_state == UART_PM_STATE_ON) { 1520 geni_se_resources_off(&port->se); 1521 dev_pm_opp_set_rate(uport->dev, 0); 1522 geni_icc_disable(&port->se); 1523 } 1524 } 1525 1526 static const struct uart_ops qcom_geni_console_pops = { 1527 .tx_empty = qcom_geni_serial_tx_empty, 1528 .stop_tx = qcom_geni_serial_stop_tx_fifo, 1529 .start_tx = qcom_geni_serial_start_tx_fifo, 1530 .stop_rx = qcom_geni_serial_stop_rx_fifo, 1531 .start_rx = qcom_geni_serial_start_rx_fifo, 1532 .set_termios = qcom_geni_serial_set_termios, 1533 .startup = qcom_geni_serial_startup, 1534 .request_port = qcom_geni_serial_request_port, 1535 .config_port = qcom_geni_serial_config_port, 1536 .shutdown = qcom_geni_serial_shutdown, 1537 .type = qcom_geni_serial_get_type, 1538 .set_mctrl = qcom_geni_serial_set_mctrl, 1539 .get_mctrl = qcom_geni_serial_get_mctrl, 1540 #ifdef CONFIG_CONSOLE_POLL 1541 .poll_get_char = qcom_geni_serial_get_char, 1542 .poll_put_char = qcom_geni_serial_poll_put_char, 1543 .poll_init = qcom_geni_serial_port_setup, 1544 #endif 1545 .pm = qcom_geni_serial_pm, 1546 }; 1547 1548 static const struct uart_ops qcom_geni_uart_pops = { 1549 .tx_empty = qcom_geni_serial_tx_empty, 1550 .stop_tx = qcom_geni_serial_stop_tx_dma, 1551 .start_tx = qcom_geni_serial_start_tx_dma, 1552 .start_rx = qcom_geni_serial_start_rx_dma, 1553 .stop_rx = qcom_geni_serial_stop_rx_dma, 1554 .set_termios = qcom_geni_serial_set_termios, 1555 .startup = qcom_geni_serial_startup, 1556 .request_port = qcom_geni_serial_request_port, 1557 .config_port = qcom_geni_serial_config_port, 1558 .shutdown = qcom_geni_serial_shutdown, 1559 .type = qcom_geni_serial_get_type, 1560 .set_mctrl = qcom_geni_serial_set_mctrl, 1561 .get_mctrl = qcom_geni_serial_get_mctrl, 1562 .pm = qcom_geni_serial_pm, 1563 }; 1564 1565 static int qcom_geni_serial_probe(struct platform_device *pdev) 1566 { 1567 int ret = 0; 1568 int line; 1569 struct qcom_geni_serial_port *port; 1570 struct uart_port *uport; 1571 struct resource *res; 1572 int irq; 1573 struct uart_driver *drv; 1574 const struct qcom_geni_device_data *data; 1575 1576 data = of_device_get_match_data(&pdev->dev); 1577 if (!data) 1578 return -EINVAL; 1579 1580 if (data->console) { 1581 drv = &qcom_geni_console_driver; 1582 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1583 } else { 1584 drv = &qcom_geni_uart_driver; 1585 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1586 if (line == -ENODEV) /* compat with non-standard aliases */ 1587 line = of_alias_get_id(pdev->dev.of_node, "hsuart"); 1588 } 1589 1590 port = get_port_from_line(line, data->console); 1591 if (IS_ERR(port)) { 1592 dev_err(&pdev->dev, "Invalid line %d\n", line); 1593 return PTR_ERR(port); 1594 } 1595 1596 uport = &port->uport; 1597 /* Don't allow 2 drivers to access the same port */ 1598 if (uport->private_data) 1599 return -ENODEV; 1600 1601 uport->dev = &pdev->dev; 1602 port->dev_data = data; 1603 port->se.dev = &pdev->dev; 1604 port->se.wrapper = dev_get_drvdata(pdev->dev.parent); 1605 port->se.clk = devm_clk_get(&pdev->dev, "se"); 1606 if (IS_ERR(port->se.clk)) { 1607 ret = PTR_ERR(port->se.clk); 1608 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); 1609 return ret; 1610 } 1611 1612 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1613 if (!res) 1614 return -EINVAL; 1615 uport->mapbase = res->start; 1616 1617 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1618 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1619 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; 1620 1621 if (!data->console) { 1622 port->rx_buf = devm_kzalloc(uport->dev, 1623 DMA_RX_BUF_SIZE, GFP_KERNEL); 1624 if (!port->rx_buf) 1625 return -ENOMEM; 1626 } 1627 1628 ret = geni_icc_get(&port->se, NULL); 1629 if (ret) 1630 return ret; 1631 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; 1632 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 1633 1634 /* Set BW for register access */ 1635 ret = geni_icc_set_bw(&port->se); 1636 if (ret) 1637 return ret; 1638 1639 port->name = devm_kasprintf(uport->dev, GFP_KERNEL, 1640 "qcom_geni_serial_%s%d", 1641 uart_console(uport) ? "console" : "uart", uport->line); 1642 if (!port->name) 1643 return -ENOMEM; 1644 1645 irq = platform_get_irq(pdev, 0); 1646 if (irq < 0) 1647 return irq; 1648 uport->irq = irq; 1649 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); 1650 1651 if (!data->console) 1652 port->wakeup_irq = platform_get_irq_optional(pdev, 1); 1653 1654 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap")) 1655 port->rx_tx_swap = true; 1656 1657 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) 1658 port->cts_rts_swap = true; 1659 1660 ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); 1661 if (ret) 1662 return ret; 1663 /* OPP table is optional */ 1664 ret = devm_pm_opp_of_add_table(&pdev->dev); 1665 if (ret && ret != -ENODEV) { 1666 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1667 return ret; 1668 } 1669 1670 port->private_data.drv = drv; 1671 uport->private_data = &port->private_data; 1672 platform_set_drvdata(pdev, port); 1673 1674 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); 1675 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, 1676 IRQF_TRIGGER_HIGH, port->name, uport); 1677 if (ret) { 1678 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); 1679 return ret; 1680 } 1681 1682 ret = uart_add_one_port(drv, uport); 1683 if (ret) 1684 return ret; 1685 1686 if (port->wakeup_irq > 0) { 1687 device_init_wakeup(&pdev->dev, true); 1688 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1689 port->wakeup_irq); 1690 if (ret) { 1691 device_init_wakeup(&pdev->dev, false); 1692 uart_remove_one_port(drv, uport); 1693 return ret; 1694 } 1695 } 1696 1697 return 0; 1698 } 1699 1700 static void qcom_geni_serial_remove(struct platform_device *pdev) 1701 { 1702 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); 1703 struct uart_driver *drv = port->private_data.drv; 1704 1705 dev_pm_clear_wake_irq(&pdev->dev); 1706 device_init_wakeup(&pdev->dev, false); 1707 uart_remove_one_port(drv, &port->uport); 1708 } 1709 1710 static int qcom_geni_serial_sys_suspend(struct device *dev) 1711 { 1712 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1713 struct uart_port *uport = &port->uport; 1714 struct qcom_geni_private_data *private_data = uport->private_data; 1715 1716 /* 1717 * This is done so we can hit the lowest possible state in suspend 1718 * even with no_console_suspend 1719 */ 1720 if (uart_console(uport)) { 1721 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY); 1722 geni_icc_set_bw(&port->se); 1723 } 1724 return uart_suspend_port(private_data->drv, uport); 1725 } 1726 1727 static int qcom_geni_serial_sys_resume(struct device *dev) 1728 { 1729 int ret; 1730 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1731 struct uart_port *uport = &port->uport; 1732 struct qcom_geni_private_data *private_data = uport->private_data; 1733 1734 ret = uart_resume_port(private_data->drv, uport); 1735 if (uart_console(uport)) { 1736 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); 1737 geni_icc_set_bw(&port->se); 1738 } 1739 return ret; 1740 } 1741 1742 static int qcom_geni_serial_sys_hib_resume(struct device *dev) 1743 { 1744 int ret = 0; 1745 struct uart_port *uport; 1746 struct qcom_geni_private_data *private_data; 1747 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1748 1749 uport = &port->uport; 1750 private_data = uport->private_data; 1751 1752 if (uart_console(uport)) { 1753 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); 1754 geni_icc_set_bw(&port->se); 1755 ret = uart_resume_port(private_data->drv, uport); 1756 /* 1757 * For hibernation usecase clients for 1758 * console UART won't call port setup during restore, 1759 * hence call port setup for console uart. 1760 */ 1761 qcom_geni_serial_port_setup(uport); 1762 } else { 1763 /* 1764 * Peripheral register settings are lost during hibernation. 1765 * Update setup flag such that port setup happens again 1766 * during next session. Clients of HS-UART will close and 1767 * open the port during hibernation. 1768 */ 1769 port->setup = false; 1770 } 1771 return ret; 1772 } 1773 1774 static const struct qcom_geni_device_data qcom_geni_console_data = { 1775 .console = true, 1776 .mode = GENI_SE_FIFO, 1777 }; 1778 1779 static const struct qcom_geni_device_data qcom_geni_uart_data = { 1780 .console = false, 1781 .mode = GENI_SE_DMA, 1782 }; 1783 1784 static const struct dev_pm_ops qcom_geni_serial_pm_ops = { 1785 .suspend = pm_sleep_ptr(qcom_geni_serial_sys_suspend), 1786 .resume = pm_sleep_ptr(qcom_geni_serial_sys_resume), 1787 .freeze = pm_sleep_ptr(qcom_geni_serial_sys_suspend), 1788 .poweroff = pm_sleep_ptr(qcom_geni_serial_sys_suspend), 1789 .restore = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume), 1790 .thaw = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume), 1791 }; 1792 1793 static const struct of_device_id qcom_geni_serial_match_table[] = { 1794 { 1795 .compatible = "qcom,geni-debug-uart", 1796 .data = &qcom_geni_console_data, 1797 }, 1798 { 1799 .compatible = "qcom,geni-uart", 1800 .data = &qcom_geni_uart_data, 1801 }, 1802 {} 1803 }; 1804 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); 1805 1806 static struct platform_driver qcom_geni_serial_platform_driver = { 1807 .remove_new = qcom_geni_serial_remove, 1808 .probe = qcom_geni_serial_probe, 1809 .driver = { 1810 .name = "qcom_geni_serial", 1811 .of_match_table = qcom_geni_serial_match_table, 1812 .pm = &qcom_geni_serial_pm_ops, 1813 }, 1814 }; 1815 1816 static int __init qcom_geni_serial_init(void) 1817 { 1818 int ret; 1819 1820 ret = console_register(&qcom_geni_console_driver); 1821 if (ret) 1822 return ret; 1823 1824 ret = uart_register_driver(&qcom_geni_uart_driver); 1825 if (ret) { 1826 console_unregister(&qcom_geni_console_driver); 1827 return ret; 1828 } 1829 1830 ret = platform_driver_register(&qcom_geni_serial_platform_driver); 1831 if (ret) { 1832 console_unregister(&qcom_geni_console_driver); 1833 uart_unregister_driver(&qcom_geni_uart_driver); 1834 } 1835 return ret; 1836 } 1837 module_init(qcom_geni_serial_init); 1838 1839 static void __exit qcom_geni_serial_exit(void) 1840 { 1841 platform_driver_unregister(&qcom_geni_serial_platform_driver); 1842 console_unregister(&qcom_geni_console_driver); 1843 uart_unregister_driver(&qcom_geni_uart_driver); 1844 } 1845 module_exit(qcom_geni_serial_exit); 1846 1847 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores"); 1848 MODULE_LICENSE("GPL v2"); 1849