1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */ 5 #define __DISABLE_TRACE_MMIO__ 6 7 #include <linux/clk.h> 8 #include <linux/console.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/irq.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/pm_opp.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/pm_wakeirq.h> 19 #include <linux/qcom-geni-se.h> 20 #include <linux/serial.h> 21 #include <linux/serial_core.h> 22 #include <linux/slab.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <dt-bindings/interconnect/qcom,icc.h> 26 27 /* UART specific GENI registers */ 28 #define SE_UART_LOOPBACK_CFG 0x22c 29 #define SE_UART_IO_MACRO_CTRL 0x240 30 #define SE_UART_TX_TRANS_CFG 0x25c 31 #define SE_UART_TX_WORD_LEN 0x268 32 #define SE_UART_TX_STOP_BIT_LEN 0x26c 33 #define SE_UART_TX_TRANS_LEN 0x270 34 #define SE_UART_RX_TRANS_CFG 0x280 35 #define SE_UART_RX_WORD_LEN 0x28c 36 #define SE_UART_RX_STALE_CNT 0x294 37 #define SE_UART_TX_PARITY_CFG 0x2a4 38 #define SE_UART_RX_PARITY_CFG 0x2a8 39 #define SE_UART_MANUAL_RFR 0x2ac 40 41 /* SE_UART_TRANS_CFG */ 42 #define UART_TX_PAR_EN BIT(0) 43 #define UART_CTS_MASK BIT(1) 44 45 /* SE_UART_TX_WORD_LEN */ 46 #define TX_WORD_LEN_MSK GENMASK(9, 0) 47 48 /* SE_UART_TX_STOP_BIT_LEN */ 49 #define TX_STOP_BIT_LEN_MSK GENMASK(23, 0) 50 #define TX_STOP_BIT_LEN_1 0 51 #define TX_STOP_BIT_LEN_1_5 1 52 #define TX_STOP_BIT_LEN_2 2 53 54 /* SE_UART_TX_TRANS_LEN */ 55 #define TX_TRANS_LEN_MSK GENMASK(23, 0) 56 57 /* SE_UART_RX_TRANS_CFG */ 58 #define UART_RX_INS_STATUS_BIT BIT(2) 59 #define UART_RX_PAR_EN BIT(3) 60 61 /* SE_UART_RX_WORD_LEN */ 62 #define RX_WORD_LEN_MASK GENMASK(9, 0) 63 64 /* SE_UART_RX_STALE_CNT */ 65 #define RX_STALE_CNT GENMASK(23, 0) 66 67 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ 68 #define PAR_CALC_EN BIT(0) 69 #define PAR_MODE_MSK GENMASK(2, 1) 70 #define PAR_MODE_SHFT 1 71 #define PAR_EVEN 0x00 72 #define PAR_ODD 0x01 73 #define PAR_SPACE 0x10 74 #define PAR_MARK 0x11 75 76 /* SE_UART_MANUAL_RFR register fields */ 77 #define UART_MANUAL_RFR_EN BIT(31) 78 #define UART_RFR_NOT_READY BIT(1) 79 #define UART_RFR_READY BIT(0) 80 81 /* UART M_CMD OP codes */ 82 #define UART_START_TX 0x1 83 #define UART_START_BREAK 0x4 84 #define UART_STOP_BREAK 0x5 85 /* UART S_CMD OP codes */ 86 #define UART_START_READ 0x1 87 #define UART_PARAM 0x1 88 89 #define UART_OVERSAMPLING 32 90 #define STALE_TIMEOUT 16 91 #define DEFAULT_BITS_PER_CHAR 10 92 #define GENI_UART_CONS_PORTS 1 93 #define GENI_UART_PORTS 3 94 #define DEF_FIFO_DEPTH_WORDS 16 95 #define DEF_TX_WM 2 96 #define DEF_FIFO_WIDTH_BITS 32 97 #define UART_RX_WM 2 98 99 /* SE_UART_LOOPBACK_CFG */ 100 #define RX_TX_SORTED BIT(0) 101 #define CTS_RTS_SORTED BIT(1) 102 #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) 103 104 /* UART pin swap value */ 105 #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) 106 #define IO_MACRO_IO0_SEL 0x3 107 #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) 108 #define IO_MACRO_IO2_IO3_SWAP 0x4640 109 110 /* We always configure 4 bytes per FIFO word */ 111 #define BYTES_PER_FIFO_WORD 4 112 113 struct qcom_geni_private_data { 114 /* NOTE: earlycon port will have NULL here */ 115 struct uart_driver *drv; 116 117 u32 poll_cached_bytes; 118 unsigned int poll_cached_bytes_cnt; 119 120 u32 write_cached_bytes; 121 unsigned int write_cached_bytes_cnt; 122 }; 123 124 struct qcom_geni_serial_port { 125 struct uart_port uport; 126 struct geni_se se; 127 const char *name; 128 u32 tx_fifo_depth; 129 u32 tx_fifo_width; 130 u32 rx_fifo_depth; 131 bool setup; 132 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop); 133 unsigned int baud; 134 void *rx_fifo; 135 u32 loopback; 136 bool brk; 137 138 unsigned int tx_remaining; 139 int wakeup_irq; 140 bool rx_tx_swap; 141 bool cts_rts_swap; 142 143 struct qcom_geni_private_data private_data; 144 }; 145 146 static const struct uart_ops qcom_geni_console_pops; 147 static const struct uart_ops qcom_geni_uart_pops; 148 static struct uart_driver qcom_geni_console_driver; 149 static struct uart_driver qcom_geni_uart_driver; 150 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop); 151 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop); 152 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port); 153 static void qcom_geni_serial_stop_rx(struct uart_port *uport); 154 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop); 155 156 #define to_dev_port(ptr, member) \ 157 container_of(ptr, struct qcom_geni_serial_port, member) 158 159 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = { 160 [0] = { 161 .uport = { 162 .iotype = UPIO_MEM, 163 .ops = &qcom_geni_uart_pops, 164 .flags = UPF_BOOT_AUTOCONF, 165 .line = 0, 166 }, 167 }, 168 [1] = { 169 .uport = { 170 .iotype = UPIO_MEM, 171 .ops = &qcom_geni_uart_pops, 172 .flags = UPF_BOOT_AUTOCONF, 173 .line = 1, 174 }, 175 }, 176 [2] = { 177 .uport = { 178 .iotype = UPIO_MEM, 179 .ops = &qcom_geni_uart_pops, 180 .flags = UPF_BOOT_AUTOCONF, 181 .line = 2, 182 }, 183 }, 184 }; 185 186 static struct qcom_geni_serial_port qcom_geni_console_port = { 187 .uport = { 188 .iotype = UPIO_MEM, 189 .ops = &qcom_geni_console_pops, 190 .flags = UPF_BOOT_AUTOCONF, 191 .line = 0, 192 }, 193 }; 194 195 static int qcom_geni_serial_request_port(struct uart_port *uport) 196 { 197 struct platform_device *pdev = to_platform_device(uport->dev); 198 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 199 200 uport->membase = devm_platform_ioremap_resource(pdev, 0); 201 if (IS_ERR(uport->membase)) 202 return PTR_ERR(uport->membase); 203 port->se.base = uport->membase; 204 return 0; 205 } 206 207 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags) 208 { 209 if (cfg_flags & UART_CONFIG_TYPE) { 210 uport->type = PORT_MSM; 211 qcom_geni_serial_request_port(uport); 212 } 213 } 214 215 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport) 216 { 217 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR; 218 u32 geni_ios; 219 220 if (uart_console(uport)) { 221 mctrl |= TIOCM_CTS; 222 } else { 223 geni_ios = readl(uport->membase + SE_GENI_IOS); 224 if (!(geni_ios & IO2_DATA_IN)) 225 mctrl |= TIOCM_CTS; 226 } 227 228 return mctrl; 229 } 230 231 static void qcom_geni_serial_set_mctrl(struct uart_port *uport, 232 unsigned int mctrl) 233 { 234 u32 uart_manual_rfr = 0; 235 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 236 237 if (uart_console(uport)) 238 return; 239 240 if (mctrl & TIOCM_LOOP) 241 port->loopback = RX_TX_CTS_RTS_SORTED; 242 243 if (!(mctrl & TIOCM_RTS) && !uport->suspended) 244 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; 245 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); 246 } 247 248 static const char *qcom_geni_serial_get_type(struct uart_port *uport) 249 { 250 return "MSM"; 251 } 252 253 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console) 254 { 255 struct qcom_geni_serial_port *port; 256 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS; 257 258 if (line < 0 || line >= nr_ports) 259 return ERR_PTR(-ENXIO); 260 261 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line]; 262 return port; 263 } 264 265 static bool qcom_geni_serial_poll_bit(struct uart_port *uport, 266 int offset, int field, bool set) 267 { 268 u32 reg; 269 struct qcom_geni_serial_port *port; 270 unsigned int baud; 271 unsigned int fifo_bits; 272 unsigned long timeout_us = 20000; 273 struct qcom_geni_private_data *private_data = uport->private_data; 274 275 if (private_data->drv) { 276 port = to_dev_port(uport, uport); 277 baud = port->baud; 278 if (!baud) 279 baud = 115200; 280 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width; 281 /* 282 * Total polling iterations based on FIFO worth of bytes to be 283 * sent at current baud. Add a little fluff to the wait. 284 */ 285 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; 286 } 287 288 /* 289 * Use custom implementation instead of readl_poll_atomic since ktimer 290 * is not ready at the time of early console. 291 */ 292 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; 293 while (timeout_us) { 294 reg = readl(uport->membase + offset); 295 if ((bool)(reg & field) == set) 296 return true; 297 udelay(10); 298 timeout_us -= 10; 299 } 300 return false; 301 } 302 303 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size) 304 { 305 u32 m_cmd; 306 307 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); 308 m_cmd = UART_START_TX << M_OPCODE_SHFT; 309 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); 310 } 311 312 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport) 313 { 314 int done; 315 u32 irq_clear = M_CMD_DONE_EN; 316 317 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 318 M_CMD_DONE_EN, true); 319 if (!done) { 320 writel(M_GENI_CMD_ABORT, uport->membase + 321 SE_GENI_M_CMD_CTRL_REG); 322 irq_clear |= M_CMD_ABORT_EN; 323 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 324 M_CMD_ABORT_EN, true); 325 } 326 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR); 327 } 328 329 static void qcom_geni_serial_abort_rx(struct uart_port *uport) 330 { 331 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN; 332 333 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); 334 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, 335 S_GENI_CMD_ABORT, false); 336 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); 337 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); 338 } 339 340 #ifdef CONFIG_CONSOLE_POLL 341 342 static int qcom_geni_serial_get_char(struct uart_port *uport) 343 { 344 struct qcom_geni_private_data *private_data = uport->private_data; 345 u32 status; 346 u32 word_cnt; 347 int ret; 348 349 if (!private_data->poll_cached_bytes_cnt) { 350 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 351 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR); 352 353 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 354 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR); 355 356 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 357 word_cnt = status & RX_FIFO_WC_MSK; 358 if (!word_cnt) 359 return NO_POLL_CHAR; 360 361 if (word_cnt == 1 && (status & RX_LAST)) 362 /* 363 * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be 364 * treated as if it was BYTES_PER_FIFO_WORD. 365 */ 366 private_data->poll_cached_bytes_cnt = 367 (status & RX_LAST_BYTE_VALID_MSK) >> 368 RX_LAST_BYTE_VALID_SHFT; 369 370 if (private_data->poll_cached_bytes_cnt == 0) 371 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD; 372 373 private_data->poll_cached_bytes = 374 readl(uport->membase + SE_GENI_RX_FIFOn); 375 } 376 377 private_data->poll_cached_bytes_cnt--; 378 ret = private_data->poll_cached_bytes & 0xff; 379 private_data->poll_cached_bytes >>= 8; 380 381 return ret; 382 } 383 384 static void qcom_geni_serial_poll_put_char(struct uart_port *uport, 385 unsigned char c) 386 { 387 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 388 qcom_geni_serial_setup_tx(uport, 1); 389 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 390 M_TX_FIFO_WATERMARK_EN, true)); 391 writel(c, uport->membase + SE_GENI_TX_FIFOn); 392 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 393 qcom_geni_serial_poll_tx_done(uport); 394 } 395 #endif 396 397 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 398 static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch) 399 { 400 struct qcom_geni_private_data *private_data = uport->private_data; 401 402 private_data->write_cached_bytes = 403 (private_data->write_cached_bytes >> 8) | (ch << 24); 404 private_data->write_cached_bytes_cnt++; 405 406 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) { 407 writel(private_data->write_cached_bytes, 408 uport->membase + SE_GENI_TX_FIFOn); 409 private_data->write_cached_bytes_cnt = 0; 410 } 411 } 412 413 static void 414 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s, 415 unsigned int count) 416 { 417 struct qcom_geni_private_data *private_data = uport->private_data; 418 419 int i; 420 u32 bytes_to_send = count; 421 422 for (i = 0; i < count; i++) { 423 /* 424 * uart_console_write() adds a carriage return for each newline. 425 * Account for additional bytes to be written. 426 */ 427 if (s[i] == '\n') 428 bytes_to_send++; 429 } 430 431 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 432 qcom_geni_serial_setup_tx(uport, bytes_to_send); 433 for (i = 0; i < count; ) { 434 size_t chars_to_write = 0; 435 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; 436 437 /* 438 * If the WM bit never set, then the Tx state machine is not 439 * in a valid state, so break, cancel/abort any existing 440 * command. Unfortunately the current data being written is 441 * lost. 442 */ 443 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 444 M_TX_FIFO_WATERMARK_EN, true)) 445 break; 446 chars_to_write = min_t(size_t, count - i, avail / 2); 447 uart_console_write(uport, s + i, chars_to_write, 448 qcom_geni_serial_wr_char); 449 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + 450 SE_GENI_M_IRQ_CLEAR); 451 i += chars_to_write; 452 } 453 454 if (private_data->write_cached_bytes_cnt) { 455 private_data->write_cached_bytes >>= BITS_PER_BYTE * 456 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt); 457 writel(private_data->write_cached_bytes, 458 uport->membase + SE_GENI_TX_FIFOn); 459 private_data->write_cached_bytes_cnt = 0; 460 } 461 462 qcom_geni_serial_poll_tx_done(uport); 463 } 464 465 static void qcom_geni_serial_console_write(struct console *co, const char *s, 466 unsigned int count) 467 { 468 struct uart_port *uport; 469 struct qcom_geni_serial_port *port; 470 bool locked = true; 471 unsigned long flags; 472 u32 geni_status; 473 u32 irq_en; 474 475 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); 476 477 port = get_port_from_line(co->index, true); 478 if (IS_ERR(port)) 479 return; 480 481 uport = &port->uport; 482 if (oops_in_progress) 483 locked = spin_trylock_irqsave(&uport->lock, flags); 484 else 485 spin_lock_irqsave(&uport->lock, flags); 486 487 geni_status = readl(uport->membase + SE_GENI_STATUS); 488 489 /* Cancel the current write to log the fault */ 490 if (!locked) { 491 geni_se_cancel_m_cmd(&port->se); 492 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 493 M_CMD_CANCEL_EN, true)) { 494 geni_se_abort_m_cmd(&port->se); 495 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 496 M_CMD_ABORT_EN, true); 497 writel(M_CMD_ABORT_EN, uport->membase + 498 SE_GENI_M_IRQ_CLEAR); 499 } 500 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 501 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) { 502 /* 503 * It seems we can't interrupt existing transfers if all data 504 * has been sent, in which case we need to look for done first. 505 */ 506 qcom_geni_serial_poll_tx_done(uport); 507 508 if (!uart_circ_empty(&uport->state->xmit)) { 509 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 510 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 511 uport->membase + SE_GENI_M_IRQ_EN); 512 } 513 } 514 515 __qcom_geni_serial_console_write(uport, s, count); 516 517 if (port->tx_remaining) 518 qcom_geni_serial_setup_tx(uport, port->tx_remaining); 519 520 if (locked) 521 spin_unlock_irqrestore(&uport->lock, flags); 522 } 523 524 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 525 { 526 u32 i; 527 unsigned char buf[sizeof(u32)]; 528 struct tty_port *tport; 529 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 530 531 tport = &uport->state->port; 532 for (i = 0; i < bytes; ) { 533 int c; 534 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD); 535 536 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); 537 i += chunk; 538 if (drop) 539 continue; 540 541 for (c = 0; c < chunk; c++) { 542 int sysrq; 543 544 uport->icount.rx++; 545 if (port->brk && buf[c] == 0) { 546 port->brk = false; 547 if (uart_handle_break(uport)) 548 continue; 549 } 550 551 sysrq = uart_prepare_sysrq_char(uport, buf[c]); 552 553 if (!sysrq) 554 tty_insert_flip_char(tport, buf[c], TTY_NORMAL); 555 } 556 } 557 if (!drop) 558 tty_flip_buffer_push(tport); 559 return 0; 560 } 561 #else 562 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 563 { 564 return -EPERM; 565 } 566 567 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 568 569 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop) 570 { 571 struct tty_port *tport; 572 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 573 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE; 574 u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw; 575 int ret; 576 577 tport = &uport->state->port; 578 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words); 579 if (drop) 580 return 0; 581 582 ret = tty_insert_flip_string(tport, port->rx_fifo, bytes); 583 if (ret != bytes) { 584 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n", 585 __func__, ret, bytes); 586 WARN_ON_ONCE(1); 587 } 588 uport->icount.rx += ret; 589 tty_flip_buffer_push(tport); 590 return ret; 591 } 592 593 static void qcom_geni_serial_start_tx(struct uart_port *uport) 594 { 595 u32 irq_en; 596 u32 status; 597 598 status = readl(uport->membase + SE_GENI_STATUS); 599 if (status & M_GENI_CMD_ACTIVE) 600 return; 601 602 if (!qcom_geni_serial_tx_empty(uport)) 603 return; 604 605 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 606 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; 607 608 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 609 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 610 } 611 612 static void qcom_geni_serial_stop_tx(struct uart_port *uport) 613 { 614 u32 irq_en; 615 u32 status; 616 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 617 618 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 619 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 620 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); 621 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 622 status = readl(uport->membase + SE_GENI_STATUS); 623 /* Possible stop tx is called multiple times. */ 624 if (!(status & M_GENI_CMD_ACTIVE)) 625 return; 626 627 geni_se_cancel_m_cmd(&port->se); 628 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 629 M_CMD_CANCEL_EN, true)) { 630 geni_se_abort_m_cmd(&port->se); 631 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 632 M_CMD_ABORT_EN, true); 633 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 634 } 635 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 636 } 637 638 static void qcom_geni_serial_start_rx(struct uart_port *uport) 639 { 640 u32 irq_en; 641 u32 status; 642 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 643 644 status = readl(uport->membase + SE_GENI_STATUS); 645 if (status & S_GENI_CMD_ACTIVE) 646 qcom_geni_serial_stop_rx(uport); 647 648 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); 649 650 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 651 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; 652 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 653 654 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 655 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 656 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 657 } 658 659 static void qcom_geni_serial_stop_rx(struct uart_port *uport) 660 { 661 u32 irq_en; 662 u32 status; 663 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 664 u32 s_irq_status; 665 666 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 667 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); 668 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 669 670 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 671 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 672 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 673 674 status = readl(uport->membase + SE_GENI_STATUS); 675 /* Possible stop rx is called multiple times. */ 676 if (!(status & S_GENI_CMD_ACTIVE)) 677 return; 678 679 geni_se_cancel_s_cmd(&port->se); 680 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 681 S_CMD_CANCEL_EN, true); 682 /* 683 * If timeout occurs secondary engine remains active 684 * and Abort sequence is executed. 685 */ 686 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 687 /* Flush the Rx buffer */ 688 if (s_irq_status & S_RX_FIFO_LAST_EN) 689 qcom_geni_serial_handle_rx(uport, true); 690 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 691 692 status = readl(uport->membase + SE_GENI_STATUS); 693 if (status & S_GENI_CMD_ACTIVE) 694 qcom_geni_serial_abort_rx(uport); 695 } 696 697 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop) 698 { 699 u32 status; 700 u32 word_cnt; 701 u32 last_word_byte_cnt; 702 u32 last_word_partial; 703 u32 total_bytes; 704 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 705 706 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 707 word_cnt = status & RX_FIFO_WC_MSK; 708 last_word_partial = status & RX_LAST; 709 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >> 710 RX_LAST_BYTE_VALID_SHFT; 711 712 if (!word_cnt) 713 return; 714 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1); 715 if (last_word_partial && last_word_byte_cnt) 716 total_bytes += last_word_byte_cnt; 717 else 718 total_bytes += BYTES_PER_FIFO_WORD; 719 port->handle_rx(uport, total_bytes, drop); 720 } 721 722 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done, 723 bool active) 724 { 725 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 726 struct circ_buf *xmit = &uport->state->xmit; 727 size_t avail; 728 size_t remaining; 729 size_t pending; 730 int i; 731 u32 status; 732 u32 irq_en; 733 unsigned int chunk; 734 int tail; 735 736 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 737 738 /* Complete the current tx command before taking newly added data */ 739 if (active) 740 pending = port->tx_remaining; 741 else 742 pending = uart_circ_chars_pending(xmit); 743 744 /* All data has been transmitted and acknowledged as received */ 745 if (!pending && !status && done) { 746 qcom_geni_serial_stop_tx(uport); 747 goto out_write_wakeup; 748 } 749 750 avail = port->tx_fifo_depth - (status & TX_FIFO_WC); 751 avail *= BYTES_PER_FIFO_WORD; 752 753 tail = xmit->tail; 754 chunk = min(avail, pending); 755 if (!chunk) 756 goto out_write_wakeup; 757 758 if (!port->tx_remaining) { 759 qcom_geni_serial_setup_tx(uport, pending); 760 port->tx_remaining = pending; 761 762 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 763 if (!(irq_en & M_TX_FIFO_WATERMARK_EN)) 764 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 765 uport->membase + SE_GENI_M_IRQ_EN); 766 } 767 768 remaining = chunk; 769 for (i = 0; i < chunk; ) { 770 unsigned int tx_bytes; 771 u8 buf[sizeof(u32)]; 772 int c; 773 774 memset(buf, 0, sizeof(buf)); 775 tx_bytes = min_t(size_t, remaining, BYTES_PER_FIFO_WORD); 776 777 for (c = 0; c < tx_bytes ; c++) { 778 buf[c] = xmit->buf[tail++]; 779 tail &= UART_XMIT_SIZE - 1; 780 } 781 782 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); 783 784 i += tx_bytes; 785 uport->icount.tx += tx_bytes; 786 remaining -= tx_bytes; 787 port->tx_remaining -= tx_bytes; 788 } 789 790 xmit->tail = tail; 791 792 /* 793 * The tx fifo watermark is level triggered and latched. Though we had 794 * cleared it in qcom_geni_serial_isr it will have already reasserted 795 * so we must clear it again here after our writes. 796 */ 797 writel(M_TX_FIFO_WATERMARK_EN, 798 uport->membase + SE_GENI_M_IRQ_CLEAR); 799 800 out_write_wakeup: 801 if (!port->tx_remaining) { 802 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 803 if (irq_en & M_TX_FIFO_WATERMARK_EN) 804 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN, 805 uport->membase + SE_GENI_M_IRQ_EN); 806 } 807 808 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 809 uart_write_wakeup(uport); 810 } 811 812 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) 813 { 814 u32 m_irq_en; 815 u32 m_irq_status; 816 u32 s_irq_status; 817 u32 geni_status; 818 struct uart_port *uport = dev; 819 bool drop_rx = false; 820 struct tty_port *tport = &uport->state->port; 821 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 822 823 if (uport->suspended) 824 return IRQ_NONE; 825 826 spin_lock(&uport->lock); 827 828 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 829 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 830 geni_status = readl(uport->membase + SE_GENI_STATUS); 831 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 832 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); 833 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 834 835 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN)) 836 goto out_unlock; 837 838 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) { 839 uport->icount.overrun++; 840 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 841 } 842 843 if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) 844 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN, 845 geni_status & M_GENI_CMD_ACTIVE); 846 847 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) { 848 if (s_irq_status & S_GP_IRQ_0_EN) 849 uport->icount.parity++; 850 drop_rx = true; 851 } else if (s_irq_status & S_GP_IRQ_2_EN || 852 s_irq_status & S_GP_IRQ_3_EN) { 853 uport->icount.brk++; 854 port->brk = true; 855 } 856 857 if (s_irq_status & S_RX_FIFO_WATERMARK_EN || 858 s_irq_status & S_RX_FIFO_LAST_EN) 859 qcom_geni_serial_handle_rx(uport, drop_rx); 860 861 out_unlock: 862 uart_unlock_and_check_sysrq(uport); 863 864 return IRQ_HANDLED; 865 } 866 867 static void get_tx_fifo_size(struct qcom_geni_serial_port *port) 868 { 869 struct uart_port *uport; 870 871 uport = &port->uport; 872 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); 873 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); 874 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); 875 uport->fifosize = 876 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; 877 } 878 879 880 static void qcom_geni_serial_shutdown(struct uart_port *uport) 881 { 882 disable_irq(uport->irq); 883 } 884 885 static int qcom_geni_serial_port_setup(struct uart_port *uport) 886 { 887 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 888 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT; 889 u32 proto; 890 u32 pin_swap; 891 892 proto = geni_se_read_proto(&port->se); 893 if (proto != GENI_SE_UART) { 894 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); 895 return -ENXIO; 896 } 897 898 qcom_geni_serial_stop_rx(uport); 899 900 get_tx_fifo_size(port); 901 902 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); 903 904 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL); 905 if (port->rx_tx_swap) { 906 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK; 907 pin_swap |= IO_MACRO_IO2_IO3_SWAP; 908 } 909 if (port->cts_rts_swap) { 910 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK; 911 pin_swap |= IO_MACRO_IO0_SEL; 912 } 913 /* Configure this register if RX-TX, CTS-RTS pins are swapped */ 914 if (port->rx_tx_swap || port->cts_rts_swap) 915 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL); 916 917 /* 918 * Make an unconditional cancel on the main sequencer to reset 919 * it else we could end up in data loss scenarios. 920 */ 921 if (uart_console(uport)) 922 qcom_geni_serial_poll_tx_done(uport); 923 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 924 false, true, true); 925 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); 926 geni_se_select_mode(&port->se, GENI_SE_FIFO); 927 qcom_geni_serial_start_rx(uport); 928 port->setup = true; 929 930 return 0; 931 } 932 933 static int qcom_geni_serial_startup(struct uart_port *uport) 934 { 935 int ret; 936 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 937 938 if (!port->setup) { 939 ret = qcom_geni_serial_port_setup(uport); 940 if (ret) 941 return ret; 942 } 943 enable_irq(uport->irq); 944 945 return 0; 946 } 947 948 static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int desired_clk, 949 unsigned int *clk_div, unsigned int percent_tol) 950 { 951 unsigned long freq; 952 unsigned long div, maxdiv; 953 u64 mult; 954 unsigned long offset, abs_tol, achieved; 955 956 abs_tol = div_u64((u64)desired_clk * percent_tol, 100); 957 maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT; 958 div = 1; 959 while (div <= maxdiv) { 960 mult = (u64)div * desired_clk; 961 if (mult != (unsigned long)mult) 962 break; 963 964 offset = div * abs_tol; 965 freq = clk_round_rate(clk, mult - offset); 966 967 /* Can only get lower if we're done */ 968 if (freq < mult - offset) 969 break; 970 971 /* 972 * Re-calculate div in case rounding skipped rates but we 973 * ended up at a good one, then check for a match. 974 */ 975 div = DIV_ROUND_CLOSEST(freq, desired_clk); 976 achieved = DIV_ROUND_CLOSEST(freq, div); 977 if (achieved <= desired_clk + abs_tol && 978 achieved >= desired_clk - abs_tol) { 979 *clk_div = div; 980 return freq; 981 } 982 983 div = DIV_ROUND_UP(freq, desired_clk); 984 } 985 986 return 0; 987 } 988 989 static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud, 990 unsigned int sampling_rate, unsigned int *clk_div) 991 { 992 unsigned long ser_clk; 993 unsigned long desired_clk; 994 995 desired_clk = baud * sampling_rate; 996 if (!desired_clk) 997 return 0; 998 999 /* 1000 * try to find a clock rate within 2% tolerance, then within 5% 1001 */ 1002 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2); 1003 if (!ser_clk) 1004 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5); 1005 1006 return ser_clk; 1007 } 1008 1009 static void qcom_geni_serial_set_termios(struct uart_port *uport, 1010 struct ktermios *termios, 1011 const struct ktermios *old) 1012 { 1013 unsigned int baud; 1014 u32 bits_per_char; 1015 u32 tx_trans_cfg; 1016 u32 tx_parity_cfg; 1017 u32 rx_trans_cfg; 1018 u32 rx_parity_cfg; 1019 u32 stop_bit_len; 1020 unsigned int clk_div; 1021 u32 ser_clk_cfg; 1022 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 1023 unsigned long clk_rate; 1024 u32 ver, sampling_rate; 1025 unsigned int avg_bw_core; 1026 1027 qcom_geni_serial_stop_rx(uport); 1028 /* baud rate */ 1029 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); 1030 port->baud = baud; 1031 1032 sampling_rate = UART_OVERSAMPLING; 1033 /* Sampling rate is halved for IP versions >= 2.5 */ 1034 ver = geni_se_get_qup_hw_version(&port->se); 1035 if (ver >= QUP_SE_VERSION_2_5) 1036 sampling_rate /= 2; 1037 1038 clk_rate = get_clk_div_rate(port->se.clk, baud, 1039 sampling_rate, &clk_div); 1040 if (!clk_rate) { 1041 dev_err(port->se.dev, 1042 "Couldn't find suitable clock rate for %u\n", 1043 baud * sampling_rate); 1044 goto out_restart_rx; 1045 } 1046 1047 dev_dbg(port->se.dev, "desired_rate-%u, clk_rate-%lu, clk_div-%u\n", 1048 baud * sampling_rate, clk_rate, clk_div); 1049 1050 uport->uartclk = clk_rate; 1051 dev_pm_opp_set_rate(uport->dev, clk_rate); 1052 ser_clk_cfg = SER_CLK_EN; 1053 ser_clk_cfg |= clk_div << CLK_DIV_SHFT; 1054 1055 /* 1056 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode 1057 * only. 1058 */ 1059 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ) 1060 : GENI_DEFAULT_BW; 1061 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core; 1062 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); 1063 geni_icc_set_bw(&port->se); 1064 1065 /* parity */ 1066 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); 1067 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); 1068 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG); 1069 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG); 1070 if (termios->c_cflag & PARENB) { 1071 tx_trans_cfg |= UART_TX_PAR_EN; 1072 rx_trans_cfg |= UART_RX_PAR_EN; 1073 tx_parity_cfg |= PAR_CALC_EN; 1074 rx_parity_cfg |= PAR_CALC_EN; 1075 if (termios->c_cflag & PARODD) { 1076 tx_parity_cfg |= PAR_ODD; 1077 rx_parity_cfg |= PAR_ODD; 1078 } else if (termios->c_cflag & CMSPAR) { 1079 tx_parity_cfg |= PAR_SPACE; 1080 rx_parity_cfg |= PAR_SPACE; 1081 } else { 1082 tx_parity_cfg |= PAR_EVEN; 1083 rx_parity_cfg |= PAR_EVEN; 1084 } 1085 } else { 1086 tx_trans_cfg &= ~UART_TX_PAR_EN; 1087 rx_trans_cfg &= ~UART_RX_PAR_EN; 1088 tx_parity_cfg &= ~PAR_CALC_EN; 1089 rx_parity_cfg &= ~PAR_CALC_EN; 1090 } 1091 1092 /* bits per char */ 1093 bits_per_char = tty_get_char_size(termios->c_cflag); 1094 1095 /* stop bits */ 1096 if (termios->c_cflag & CSTOPB) 1097 stop_bit_len = TX_STOP_BIT_LEN_2; 1098 else 1099 stop_bit_len = TX_STOP_BIT_LEN_1; 1100 1101 /* flow control, clear the CTS_MASK bit if using flow control. */ 1102 if (termios->c_cflag & CRTSCTS) 1103 tx_trans_cfg &= ~UART_CTS_MASK; 1104 else 1105 tx_trans_cfg |= UART_CTS_MASK; 1106 1107 if (baud) 1108 uart_update_timeout(uport, termios->c_cflag, baud); 1109 1110 if (!uart_console(uport)) 1111 writel(port->loopback, 1112 uport->membase + SE_UART_LOOPBACK_CFG); 1113 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1114 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1115 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1116 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1117 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1118 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1119 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1120 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); 1121 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); 1122 out_restart_rx: 1123 qcom_geni_serial_start_rx(uport); 1124 } 1125 1126 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport) 1127 { 1128 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 1129 } 1130 1131 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 1132 static int qcom_geni_console_setup(struct console *co, char *options) 1133 { 1134 struct uart_port *uport; 1135 struct qcom_geni_serial_port *port; 1136 int baud = 115200; 1137 int bits = 8; 1138 int parity = 'n'; 1139 int flow = 'n'; 1140 int ret; 1141 1142 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) 1143 return -ENXIO; 1144 1145 port = get_port_from_line(co->index, true); 1146 if (IS_ERR(port)) { 1147 pr_err("Invalid line %d\n", co->index); 1148 return PTR_ERR(port); 1149 } 1150 1151 uport = &port->uport; 1152 1153 if (unlikely(!uport->membase)) 1154 return -ENXIO; 1155 1156 if (!port->setup) { 1157 ret = qcom_geni_serial_port_setup(uport); 1158 if (ret) 1159 return ret; 1160 } 1161 1162 if (options) 1163 uart_parse_options(options, &baud, &parity, &bits, &flow); 1164 1165 return uart_set_options(uport, co, baud, parity, bits, flow); 1166 } 1167 1168 static void qcom_geni_serial_earlycon_write(struct console *con, 1169 const char *s, unsigned int n) 1170 { 1171 struct earlycon_device *dev = con->data; 1172 1173 __qcom_geni_serial_console_write(&dev->port, s, n); 1174 } 1175 1176 #ifdef CONFIG_CONSOLE_POLL 1177 static int qcom_geni_serial_earlycon_read(struct console *con, 1178 char *s, unsigned int n) 1179 { 1180 struct earlycon_device *dev = con->data; 1181 struct uart_port *uport = &dev->port; 1182 int num_read = 0; 1183 int ch; 1184 1185 while (num_read < n) { 1186 ch = qcom_geni_serial_get_char(uport); 1187 if (ch == NO_POLL_CHAR) 1188 break; 1189 s[num_read++] = ch; 1190 } 1191 1192 return num_read; 1193 } 1194 1195 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se, 1196 struct console *con) 1197 { 1198 geni_se_setup_s_cmd(se, UART_START_READ, 0); 1199 con->read = qcom_geni_serial_earlycon_read; 1200 } 1201 #else 1202 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se, 1203 struct console *con) { } 1204 #endif 1205 1206 static struct qcom_geni_private_data earlycon_private_data; 1207 1208 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev, 1209 const char *opt) 1210 { 1211 struct uart_port *uport = &dev->port; 1212 u32 tx_trans_cfg; 1213 u32 tx_parity_cfg = 0; /* Disable Tx Parity */ 1214 u32 rx_trans_cfg = 0; 1215 u32 rx_parity_cfg = 0; /* Disable Rx Parity */ 1216 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ 1217 u32 bits_per_char; 1218 struct geni_se se; 1219 1220 if (!uport->membase) 1221 return -EINVAL; 1222 1223 uport->private_data = &earlycon_private_data; 1224 1225 memset(&se, 0, sizeof(se)); 1226 se.base = uport->membase; 1227 if (geni_se_read_proto(&se) != GENI_SE_UART) 1228 return -ENXIO; 1229 /* 1230 * Ignore Flow control. 1231 * n = 8. 1232 */ 1233 tx_trans_cfg = UART_CTS_MASK; 1234 bits_per_char = BITS_PER_BYTE; 1235 1236 /* 1237 * Make an unconditional cancel on the main sequencer to reset 1238 * it else we could end up in data loss scenarios. 1239 */ 1240 qcom_geni_serial_poll_tx_done(uport); 1241 qcom_geni_serial_abort_rx(uport); 1242 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1243 false, true, true); 1244 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); 1245 geni_se_select_mode(&se, GENI_SE_FIFO); 1246 1247 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1248 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1249 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1250 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1251 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1252 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1253 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1254 1255 dev->con->write = qcom_geni_serial_earlycon_write; 1256 dev->con->setup = NULL; 1257 qcom_geni_serial_enable_early_read(&se, dev->con); 1258 1259 return 0; 1260 } 1261 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart", 1262 qcom_geni_serial_earlycon_setup); 1263 1264 static int __init console_register(struct uart_driver *drv) 1265 { 1266 return uart_register_driver(drv); 1267 } 1268 1269 static void console_unregister(struct uart_driver *drv) 1270 { 1271 uart_unregister_driver(drv); 1272 } 1273 1274 static struct console cons_ops = { 1275 .name = "ttyMSM", 1276 .write = qcom_geni_serial_console_write, 1277 .device = uart_console_device, 1278 .setup = qcom_geni_console_setup, 1279 .flags = CON_PRINTBUFFER, 1280 .index = -1, 1281 .data = &qcom_geni_console_driver, 1282 }; 1283 1284 static struct uart_driver qcom_geni_console_driver = { 1285 .owner = THIS_MODULE, 1286 .driver_name = "qcom_geni_console", 1287 .dev_name = "ttyMSM", 1288 .nr = GENI_UART_CONS_PORTS, 1289 .cons = &cons_ops, 1290 }; 1291 #else 1292 static int console_register(struct uart_driver *drv) 1293 { 1294 return 0; 1295 } 1296 1297 static void console_unregister(struct uart_driver *drv) 1298 { 1299 } 1300 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 1301 1302 static struct uart_driver qcom_geni_uart_driver = { 1303 .owner = THIS_MODULE, 1304 .driver_name = "qcom_geni_uart", 1305 .dev_name = "ttyHS", 1306 .nr = GENI_UART_PORTS, 1307 }; 1308 1309 static void qcom_geni_serial_pm(struct uart_port *uport, 1310 unsigned int new_state, unsigned int old_state) 1311 { 1312 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 1313 1314 /* If we've never been called, treat it as off */ 1315 if (old_state == UART_PM_STATE_UNDEFINED) 1316 old_state = UART_PM_STATE_OFF; 1317 1318 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) { 1319 geni_icc_enable(&port->se); 1320 geni_se_resources_on(&port->se); 1321 } else if (new_state == UART_PM_STATE_OFF && 1322 old_state == UART_PM_STATE_ON) { 1323 geni_se_resources_off(&port->se); 1324 geni_icc_disable(&port->se); 1325 } 1326 } 1327 1328 static const struct uart_ops qcom_geni_console_pops = { 1329 .tx_empty = qcom_geni_serial_tx_empty, 1330 .stop_tx = qcom_geni_serial_stop_tx, 1331 .start_tx = qcom_geni_serial_start_tx, 1332 .stop_rx = qcom_geni_serial_stop_rx, 1333 .start_rx = qcom_geni_serial_start_rx, 1334 .set_termios = qcom_geni_serial_set_termios, 1335 .startup = qcom_geni_serial_startup, 1336 .request_port = qcom_geni_serial_request_port, 1337 .config_port = qcom_geni_serial_config_port, 1338 .shutdown = qcom_geni_serial_shutdown, 1339 .type = qcom_geni_serial_get_type, 1340 .set_mctrl = qcom_geni_serial_set_mctrl, 1341 .get_mctrl = qcom_geni_serial_get_mctrl, 1342 #ifdef CONFIG_CONSOLE_POLL 1343 .poll_get_char = qcom_geni_serial_get_char, 1344 .poll_put_char = qcom_geni_serial_poll_put_char, 1345 #endif 1346 .pm = qcom_geni_serial_pm, 1347 }; 1348 1349 static const struct uart_ops qcom_geni_uart_pops = { 1350 .tx_empty = qcom_geni_serial_tx_empty, 1351 .stop_tx = qcom_geni_serial_stop_tx, 1352 .start_tx = qcom_geni_serial_start_tx, 1353 .stop_rx = qcom_geni_serial_stop_rx, 1354 .set_termios = qcom_geni_serial_set_termios, 1355 .startup = qcom_geni_serial_startup, 1356 .request_port = qcom_geni_serial_request_port, 1357 .config_port = qcom_geni_serial_config_port, 1358 .shutdown = qcom_geni_serial_shutdown, 1359 .type = qcom_geni_serial_get_type, 1360 .set_mctrl = qcom_geni_serial_set_mctrl, 1361 .get_mctrl = qcom_geni_serial_get_mctrl, 1362 .pm = qcom_geni_serial_pm, 1363 }; 1364 1365 static int qcom_geni_serial_probe(struct platform_device *pdev) 1366 { 1367 int ret = 0; 1368 int line; 1369 struct qcom_geni_serial_port *port; 1370 struct uart_port *uport; 1371 struct resource *res; 1372 int irq; 1373 bool console = false; 1374 struct uart_driver *drv; 1375 1376 if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart")) 1377 console = true; 1378 1379 if (console) { 1380 drv = &qcom_geni_console_driver; 1381 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1382 } else { 1383 drv = &qcom_geni_uart_driver; 1384 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1385 if (line == -ENODEV) /* compat with non-standard aliases */ 1386 line = of_alias_get_id(pdev->dev.of_node, "hsuart"); 1387 } 1388 1389 port = get_port_from_line(line, console); 1390 if (IS_ERR(port)) { 1391 dev_err(&pdev->dev, "Invalid line %d\n", line); 1392 return PTR_ERR(port); 1393 } 1394 1395 uport = &port->uport; 1396 /* Don't allow 2 drivers to access the same port */ 1397 if (uport->private_data) 1398 return -ENODEV; 1399 1400 uport->dev = &pdev->dev; 1401 port->se.dev = &pdev->dev; 1402 port->se.wrapper = dev_get_drvdata(pdev->dev.parent); 1403 port->se.clk = devm_clk_get(&pdev->dev, "se"); 1404 if (IS_ERR(port->se.clk)) { 1405 ret = PTR_ERR(port->se.clk); 1406 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); 1407 return ret; 1408 } 1409 1410 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1411 if (!res) 1412 return -EINVAL; 1413 uport->mapbase = res->start; 1414 1415 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1416 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1417 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; 1418 1419 if (!console) { 1420 port->rx_fifo = devm_kcalloc(uport->dev, 1421 port->rx_fifo_depth, sizeof(u32), GFP_KERNEL); 1422 if (!port->rx_fifo) 1423 return -ENOMEM; 1424 } 1425 1426 ret = geni_icc_get(&port->se, NULL); 1427 if (ret) 1428 return ret; 1429 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; 1430 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 1431 1432 /* Set BW for register access */ 1433 ret = geni_icc_set_bw(&port->se); 1434 if (ret) 1435 return ret; 1436 1437 port->name = devm_kasprintf(uport->dev, GFP_KERNEL, 1438 "qcom_geni_serial_%s%d", 1439 uart_console(uport) ? "console" : "uart", uport->line); 1440 if (!port->name) 1441 return -ENOMEM; 1442 1443 irq = platform_get_irq(pdev, 0); 1444 if (irq < 0) 1445 return irq; 1446 uport->irq = irq; 1447 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); 1448 1449 if (!console) 1450 port->wakeup_irq = platform_get_irq_optional(pdev, 1); 1451 1452 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap")) 1453 port->rx_tx_swap = true; 1454 1455 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) 1456 port->cts_rts_swap = true; 1457 1458 ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); 1459 if (ret) 1460 return ret; 1461 /* OPP table is optional */ 1462 ret = devm_pm_opp_of_add_table(&pdev->dev); 1463 if (ret && ret != -ENODEV) { 1464 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1465 return ret; 1466 } 1467 1468 port->private_data.drv = drv; 1469 uport->private_data = &port->private_data; 1470 platform_set_drvdata(pdev, port); 1471 port->handle_rx = console ? handle_rx_console : handle_rx_uart; 1472 1473 ret = uart_add_one_port(drv, uport); 1474 if (ret) 1475 return ret; 1476 1477 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); 1478 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, 1479 IRQF_TRIGGER_HIGH, port->name, uport); 1480 if (ret) { 1481 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); 1482 uart_remove_one_port(drv, uport); 1483 return ret; 1484 } 1485 1486 /* 1487 * Set pm_runtime status as ACTIVE so that wakeup_irq gets 1488 * enabled/disabled from dev_pm_arm_wake_irq during system 1489 * suspend/resume respectively. 1490 */ 1491 pm_runtime_set_active(&pdev->dev); 1492 1493 if (port->wakeup_irq > 0) { 1494 device_init_wakeup(&pdev->dev, true); 1495 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1496 port->wakeup_irq); 1497 if (ret) { 1498 device_init_wakeup(&pdev->dev, false); 1499 uart_remove_one_port(drv, uport); 1500 return ret; 1501 } 1502 } 1503 1504 return 0; 1505 } 1506 1507 static int qcom_geni_serial_remove(struct platform_device *pdev) 1508 { 1509 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); 1510 struct uart_driver *drv = port->private_data.drv; 1511 1512 dev_pm_clear_wake_irq(&pdev->dev); 1513 device_init_wakeup(&pdev->dev, false); 1514 uart_remove_one_port(drv, &port->uport); 1515 1516 return 0; 1517 } 1518 1519 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev) 1520 { 1521 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1522 struct uart_port *uport = &port->uport; 1523 struct qcom_geni_private_data *private_data = uport->private_data; 1524 1525 /* 1526 * This is done so we can hit the lowest possible state in suspend 1527 * even with no_console_suspend 1528 */ 1529 if (uart_console(uport)) { 1530 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY); 1531 geni_icc_set_bw(&port->se); 1532 } 1533 return uart_suspend_port(private_data->drv, uport); 1534 } 1535 1536 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev) 1537 { 1538 int ret; 1539 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1540 struct uart_port *uport = &port->uport; 1541 struct qcom_geni_private_data *private_data = uport->private_data; 1542 1543 ret = uart_resume_port(private_data->drv, uport); 1544 if (uart_console(uport)) { 1545 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); 1546 geni_icc_set_bw(&port->se); 1547 } 1548 return ret; 1549 } 1550 1551 static int qcom_geni_serial_sys_hib_resume(struct device *dev) 1552 { 1553 int ret = 0; 1554 struct uart_port *uport; 1555 struct qcom_geni_private_data *private_data; 1556 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1557 1558 uport = &port->uport; 1559 private_data = uport->private_data; 1560 1561 if (uart_console(uport)) { 1562 geni_icc_set_tag(&port->se, 0x7); 1563 geni_icc_set_bw(&port->se); 1564 ret = uart_resume_port(private_data->drv, uport); 1565 /* 1566 * For hibernation usecase clients for 1567 * console UART won't call port setup during restore, 1568 * hence call port setup for console uart. 1569 */ 1570 qcom_geni_serial_port_setup(uport); 1571 } else { 1572 /* 1573 * Peripheral register settings are lost during hibernation. 1574 * Update setup flag such that port setup happens again 1575 * during next session. Clients of HS-UART will close and 1576 * open the port during hibernation. 1577 */ 1578 port->setup = false; 1579 } 1580 return ret; 1581 } 1582 1583 static const struct dev_pm_ops qcom_geni_serial_pm_ops = { 1584 SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend, 1585 qcom_geni_serial_sys_resume) 1586 .restore = qcom_geni_serial_sys_hib_resume, 1587 .thaw = qcom_geni_serial_sys_hib_resume, 1588 }; 1589 1590 static const struct of_device_id qcom_geni_serial_match_table[] = { 1591 { .compatible = "qcom,geni-debug-uart", }, 1592 { .compatible = "qcom,geni-uart", }, 1593 {} 1594 }; 1595 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); 1596 1597 static struct platform_driver qcom_geni_serial_platform_driver = { 1598 .remove = qcom_geni_serial_remove, 1599 .probe = qcom_geni_serial_probe, 1600 .driver = { 1601 .name = "qcom_geni_serial", 1602 .of_match_table = qcom_geni_serial_match_table, 1603 .pm = &qcom_geni_serial_pm_ops, 1604 }, 1605 }; 1606 1607 static int __init qcom_geni_serial_init(void) 1608 { 1609 int ret; 1610 1611 ret = console_register(&qcom_geni_console_driver); 1612 if (ret) 1613 return ret; 1614 1615 ret = uart_register_driver(&qcom_geni_uart_driver); 1616 if (ret) { 1617 console_unregister(&qcom_geni_console_driver); 1618 return ret; 1619 } 1620 1621 ret = platform_driver_register(&qcom_geni_serial_platform_driver); 1622 if (ret) { 1623 console_unregister(&qcom_geni_console_driver); 1624 uart_unregister_driver(&qcom_geni_uart_driver); 1625 } 1626 return ret; 1627 } 1628 module_init(qcom_geni_serial_init); 1629 1630 static void __exit qcom_geni_serial_exit(void) 1631 { 1632 platform_driver_unregister(&qcom_geni_serial_platform_driver); 1633 console_unregister(&qcom_geni_console_driver); 1634 uart_unregister_driver(&qcom_geni_uart_driver); 1635 } 1636 module_exit(qcom_geni_serial_exit); 1637 1638 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores"); 1639 MODULE_LICENSE("GPL v2"); 1640