1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */ 5 #define __DISABLE_TRACE_MMIO__ 6 7 #include <linux/clk.h> 8 #include <linux/console.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/irq.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/pm_opp.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/pm_wakeirq.h> 18 #include <linux/soc/qcom/geni-se.h> 19 #include <linux/serial.h> 20 #include <linux/serial_core.h> 21 #include <linux/slab.h> 22 #include <linux/tty.h> 23 #include <linux/tty_flip.h> 24 #include <dt-bindings/interconnect/qcom,icc.h> 25 26 /* UART specific GENI registers */ 27 #define SE_UART_LOOPBACK_CFG 0x22c 28 #define SE_UART_IO_MACRO_CTRL 0x240 29 #define SE_UART_TX_TRANS_CFG 0x25c 30 #define SE_UART_TX_WORD_LEN 0x268 31 #define SE_UART_TX_STOP_BIT_LEN 0x26c 32 #define SE_UART_TX_TRANS_LEN 0x270 33 #define SE_UART_RX_TRANS_CFG 0x280 34 #define SE_UART_RX_WORD_LEN 0x28c 35 #define SE_UART_RX_STALE_CNT 0x294 36 #define SE_UART_TX_PARITY_CFG 0x2a4 37 #define SE_UART_RX_PARITY_CFG 0x2a8 38 #define SE_UART_MANUAL_RFR 0x2ac 39 40 /* SE_UART_TRANS_CFG */ 41 #define UART_TX_PAR_EN BIT(0) 42 #define UART_CTS_MASK BIT(1) 43 44 /* SE_UART_TX_STOP_BIT_LEN */ 45 #define TX_STOP_BIT_LEN_1 0 46 #define TX_STOP_BIT_LEN_2 2 47 48 /* SE_UART_RX_TRANS_CFG */ 49 #define UART_RX_PAR_EN BIT(3) 50 51 /* SE_UART_RX_WORD_LEN */ 52 #define RX_WORD_LEN_MASK GENMASK(9, 0) 53 54 /* SE_UART_RX_STALE_CNT */ 55 #define RX_STALE_CNT GENMASK(23, 0) 56 57 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ 58 #define PAR_CALC_EN BIT(0) 59 #define PAR_EVEN 0x00 60 #define PAR_ODD 0x01 61 #define PAR_SPACE 0x10 62 63 /* SE_UART_MANUAL_RFR register fields */ 64 #define UART_MANUAL_RFR_EN BIT(31) 65 #define UART_RFR_NOT_READY BIT(1) 66 #define UART_RFR_READY BIT(0) 67 68 /* UART M_CMD OP codes */ 69 #define UART_START_TX 0x1 70 /* UART S_CMD OP codes */ 71 #define UART_START_READ 0x1 72 #define UART_PARAM 0x1 73 #define UART_PARAM_RFR_OPEN BIT(7) 74 75 #define UART_OVERSAMPLING 32 76 #define STALE_TIMEOUT 16 77 #define DEFAULT_BITS_PER_CHAR 10 78 #define GENI_UART_CONS_PORTS 1 79 #define GENI_UART_PORTS 3 80 #define DEF_FIFO_DEPTH_WORDS 16 81 #define DEF_TX_WM 2 82 #define DEF_FIFO_WIDTH_BITS 32 83 #define UART_RX_WM 2 84 85 /* SE_UART_LOOPBACK_CFG */ 86 #define RX_TX_SORTED BIT(0) 87 #define CTS_RTS_SORTED BIT(1) 88 #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) 89 90 /* UART pin swap value */ 91 #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) 92 #define IO_MACRO_IO0_SEL 0x3 93 #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) 94 #define IO_MACRO_IO2_IO3_SWAP 0x4640 95 96 /* We always configure 4 bytes per FIFO word */ 97 #define BYTES_PER_FIFO_WORD 4U 98 99 #define DMA_RX_BUF_SIZE 2048 100 101 struct qcom_geni_device_data { 102 bool console; 103 enum geni_se_xfer_mode mode; 104 }; 105 106 struct qcom_geni_private_data { 107 /* NOTE: earlycon port will have NULL here */ 108 struct uart_driver *drv; 109 110 u32 poll_cached_bytes; 111 unsigned int poll_cached_bytes_cnt; 112 113 u32 write_cached_bytes; 114 unsigned int write_cached_bytes_cnt; 115 }; 116 117 struct qcom_geni_serial_port { 118 struct uart_port uport; 119 struct geni_se se; 120 const char *name; 121 u32 tx_fifo_depth; 122 u32 tx_fifo_width; 123 u32 rx_fifo_depth; 124 dma_addr_t tx_dma_addr; 125 dma_addr_t rx_dma_addr; 126 bool setup; 127 unsigned int baud; 128 unsigned long clk_rate; 129 void *rx_buf; 130 u32 loopback; 131 bool brk; 132 133 unsigned int tx_remaining; 134 int wakeup_irq; 135 bool rx_tx_swap; 136 bool cts_rts_swap; 137 138 struct qcom_geni_private_data private_data; 139 const struct qcom_geni_device_data *dev_data; 140 }; 141 142 static const struct uart_ops qcom_geni_console_pops; 143 static const struct uart_ops qcom_geni_uart_pops; 144 static struct uart_driver qcom_geni_console_driver; 145 static struct uart_driver qcom_geni_uart_driver; 146 147 static inline struct qcom_geni_serial_port *to_dev_port(struct uart_port *uport) 148 { 149 return container_of(uport, struct qcom_geni_serial_port, uport); 150 } 151 152 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = { 153 [0] = { 154 .uport = { 155 .iotype = UPIO_MEM, 156 .ops = &qcom_geni_uart_pops, 157 .flags = UPF_BOOT_AUTOCONF, 158 .line = 0, 159 }, 160 }, 161 [1] = { 162 .uport = { 163 .iotype = UPIO_MEM, 164 .ops = &qcom_geni_uart_pops, 165 .flags = UPF_BOOT_AUTOCONF, 166 .line = 1, 167 }, 168 }, 169 [2] = { 170 .uport = { 171 .iotype = UPIO_MEM, 172 .ops = &qcom_geni_uart_pops, 173 .flags = UPF_BOOT_AUTOCONF, 174 .line = 2, 175 }, 176 }, 177 }; 178 179 static struct qcom_geni_serial_port qcom_geni_console_port = { 180 .uport = { 181 .iotype = UPIO_MEM, 182 .ops = &qcom_geni_console_pops, 183 .flags = UPF_BOOT_AUTOCONF, 184 .line = 0, 185 }, 186 }; 187 188 static int qcom_geni_serial_request_port(struct uart_port *uport) 189 { 190 struct platform_device *pdev = to_platform_device(uport->dev); 191 struct qcom_geni_serial_port *port = to_dev_port(uport); 192 193 uport->membase = devm_platform_ioremap_resource(pdev, 0); 194 if (IS_ERR(uport->membase)) 195 return PTR_ERR(uport->membase); 196 port->se.base = uport->membase; 197 return 0; 198 } 199 200 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags) 201 { 202 if (cfg_flags & UART_CONFIG_TYPE) { 203 uport->type = PORT_MSM; 204 qcom_geni_serial_request_port(uport); 205 } 206 } 207 208 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport) 209 { 210 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR; 211 u32 geni_ios; 212 213 if (uart_console(uport)) { 214 mctrl |= TIOCM_CTS; 215 } else { 216 geni_ios = readl(uport->membase + SE_GENI_IOS); 217 if (!(geni_ios & IO2_DATA_IN)) 218 mctrl |= TIOCM_CTS; 219 } 220 221 return mctrl; 222 } 223 224 static void qcom_geni_serial_set_mctrl(struct uart_port *uport, 225 unsigned int mctrl) 226 { 227 u32 uart_manual_rfr = 0; 228 struct qcom_geni_serial_port *port = to_dev_port(uport); 229 230 if (uart_console(uport)) 231 return; 232 233 if (mctrl & TIOCM_LOOP) 234 port->loopback = RX_TX_CTS_RTS_SORTED; 235 236 if (!(mctrl & TIOCM_RTS) && !uport->suspended) 237 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; 238 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); 239 } 240 241 static const char *qcom_geni_serial_get_type(struct uart_port *uport) 242 { 243 return "MSM"; 244 } 245 246 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console) 247 { 248 struct qcom_geni_serial_port *port; 249 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS; 250 251 if (line < 0 || line >= nr_ports) 252 return ERR_PTR(-ENXIO); 253 254 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line]; 255 return port; 256 } 257 258 static bool qcom_geni_serial_main_active(struct uart_port *uport) 259 { 260 return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE; 261 } 262 263 static bool qcom_geni_serial_secondary_active(struct uart_port *uport) 264 { 265 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE; 266 } 267 268 static bool qcom_geni_serial_poll_bit(struct uart_port *uport, 269 int offset, int field, bool set) 270 { 271 u32 reg; 272 struct qcom_geni_serial_port *port; 273 unsigned int baud; 274 unsigned int fifo_bits; 275 unsigned long timeout_us = 20000; 276 struct qcom_geni_private_data *private_data = uport->private_data; 277 278 if (private_data->drv) { 279 port = to_dev_port(uport); 280 baud = port->baud; 281 if (!baud) 282 baud = 115200; 283 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width; 284 /* 285 * Total polling iterations based on FIFO worth of bytes to be 286 * sent at current baud. Add a little fluff to the wait. 287 */ 288 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; 289 } 290 291 /* 292 * Use custom implementation instead of readl_poll_atomic since ktimer 293 * is not ready at the time of early console. 294 */ 295 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; 296 while (timeout_us) { 297 reg = readl(uport->membase + offset); 298 if ((bool)(reg & field) == set) 299 return true; 300 udelay(10); 301 timeout_us -= 10; 302 } 303 return false; 304 } 305 306 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size) 307 { 308 u32 m_cmd; 309 310 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); 311 m_cmd = UART_START_TX << M_OPCODE_SHFT; 312 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); 313 } 314 315 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport) 316 { 317 int done; 318 u32 irq_clear = M_CMD_DONE_EN; 319 320 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 321 M_CMD_DONE_EN, true); 322 if (!done) { 323 writel(M_GENI_CMD_ABORT, uport->membase + 324 SE_GENI_M_CMD_CTRL_REG); 325 irq_clear |= M_CMD_ABORT_EN; 326 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 327 M_CMD_ABORT_EN, true); 328 } 329 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR); 330 } 331 332 static void qcom_geni_serial_abort_rx(struct uart_port *uport) 333 { 334 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN; 335 336 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); 337 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, 338 S_GENI_CMD_ABORT, false); 339 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); 340 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); 341 } 342 343 #ifdef CONFIG_CONSOLE_POLL 344 static int qcom_geni_serial_get_char(struct uart_port *uport) 345 { 346 struct qcom_geni_private_data *private_data = uport->private_data; 347 u32 status; 348 u32 word_cnt; 349 int ret; 350 351 if (!private_data->poll_cached_bytes_cnt) { 352 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 353 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR); 354 355 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 356 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR); 357 358 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 359 word_cnt = status & RX_FIFO_WC_MSK; 360 if (!word_cnt) 361 return NO_POLL_CHAR; 362 363 if (word_cnt == 1 && (status & RX_LAST)) 364 /* 365 * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be 366 * treated as if it was BYTES_PER_FIFO_WORD. 367 */ 368 private_data->poll_cached_bytes_cnt = 369 (status & RX_LAST_BYTE_VALID_MSK) >> 370 RX_LAST_BYTE_VALID_SHFT; 371 372 if (private_data->poll_cached_bytes_cnt == 0) 373 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD; 374 375 private_data->poll_cached_bytes = 376 readl(uport->membase + SE_GENI_RX_FIFOn); 377 } 378 379 private_data->poll_cached_bytes_cnt--; 380 ret = private_data->poll_cached_bytes & 0xff; 381 private_data->poll_cached_bytes >>= 8; 382 383 return ret; 384 } 385 386 static void qcom_geni_serial_poll_put_char(struct uart_port *uport, 387 unsigned char c) 388 { 389 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 390 qcom_geni_serial_setup_tx(uport, 1); 391 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 392 M_TX_FIFO_WATERMARK_EN, true)); 393 writel(c, uport->membase + SE_GENI_TX_FIFOn); 394 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 395 qcom_geni_serial_poll_tx_done(uport); 396 } 397 #endif 398 399 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 400 static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch) 401 { 402 struct qcom_geni_private_data *private_data = uport->private_data; 403 404 private_data->write_cached_bytes = 405 (private_data->write_cached_bytes >> 8) | (ch << 24); 406 private_data->write_cached_bytes_cnt++; 407 408 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) { 409 writel(private_data->write_cached_bytes, 410 uport->membase + SE_GENI_TX_FIFOn); 411 private_data->write_cached_bytes_cnt = 0; 412 } 413 } 414 415 static void 416 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s, 417 unsigned int count) 418 { 419 struct qcom_geni_private_data *private_data = uport->private_data; 420 421 int i; 422 u32 bytes_to_send = count; 423 424 for (i = 0; i < count; i++) { 425 /* 426 * uart_console_write() adds a carriage return for each newline. 427 * Account for additional bytes to be written. 428 */ 429 if (s[i] == '\n') 430 bytes_to_send++; 431 } 432 433 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 434 qcom_geni_serial_setup_tx(uport, bytes_to_send); 435 for (i = 0; i < count; ) { 436 size_t chars_to_write = 0; 437 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; 438 439 /* 440 * If the WM bit never set, then the Tx state machine is not 441 * in a valid state, so break, cancel/abort any existing 442 * command. Unfortunately the current data being written is 443 * lost. 444 */ 445 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 446 M_TX_FIFO_WATERMARK_EN, true)) 447 break; 448 chars_to_write = min_t(size_t, count - i, avail / 2); 449 uart_console_write(uport, s + i, chars_to_write, 450 qcom_geni_serial_wr_char); 451 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + 452 SE_GENI_M_IRQ_CLEAR); 453 i += chars_to_write; 454 } 455 456 if (private_data->write_cached_bytes_cnt) { 457 private_data->write_cached_bytes >>= BITS_PER_BYTE * 458 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt); 459 writel(private_data->write_cached_bytes, 460 uport->membase + SE_GENI_TX_FIFOn); 461 private_data->write_cached_bytes_cnt = 0; 462 } 463 464 qcom_geni_serial_poll_tx_done(uport); 465 } 466 467 static void qcom_geni_serial_console_write(struct console *co, const char *s, 468 unsigned int count) 469 { 470 struct uart_port *uport; 471 struct qcom_geni_serial_port *port; 472 bool locked = true; 473 unsigned long flags; 474 u32 geni_status; 475 u32 irq_en; 476 477 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); 478 479 port = get_port_from_line(co->index, true); 480 if (IS_ERR(port)) 481 return; 482 483 uport = &port->uport; 484 if (oops_in_progress) 485 locked = uart_port_trylock_irqsave(uport, &flags); 486 else 487 uart_port_lock_irqsave(uport, &flags); 488 489 geni_status = readl(uport->membase + SE_GENI_STATUS); 490 491 if (!locked) { 492 /* 493 * We can only get here if an oops is in progress then we were 494 * unable to get the lock. This means we can't safely access 495 * our state variables like tx_remaining. About the best we 496 * can do is wait for the FIFO to be empty before we start our 497 * transfer, so we'll do that. 498 */ 499 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 500 M_TX_FIFO_NOT_EMPTY_EN, false); 501 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) { 502 /* 503 * It seems we can't interrupt existing transfers if all data 504 * has been sent, in which case we need to look for done first. 505 */ 506 qcom_geni_serial_poll_tx_done(uport); 507 508 if (!kfifo_is_empty(&uport->state->port.xmit_fifo)) { 509 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 510 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 511 uport->membase + SE_GENI_M_IRQ_EN); 512 } 513 } 514 515 __qcom_geni_serial_console_write(uport, s, count); 516 517 518 if (locked) { 519 if (port->tx_remaining) 520 qcom_geni_serial_setup_tx(uport, port->tx_remaining); 521 uart_port_unlock_irqrestore(uport, flags); 522 } 523 } 524 525 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 526 { 527 u32 i; 528 unsigned char buf[sizeof(u32)]; 529 struct tty_port *tport; 530 struct qcom_geni_serial_port *port = to_dev_port(uport); 531 532 tport = &uport->state->port; 533 for (i = 0; i < bytes; ) { 534 int c; 535 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD); 536 537 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); 538 i += chunk; 539 if (drop) 540 continue; 541 542 for (c = 0; c < chunk; c++) { 543 int sysrq; 544 545 uport->icount.rx++; 546 if (port->brk && buf[c] == 0) { 547 port->brk = false; 548 if (uart_handle_break(uport)) 549 continue; 550 } 551 552 sysrq = uart_prepare_sysrq_char(uport, buf[c]); 553 554 if (!sysrq) 555 tty_insert_flip_char(tport, buf[c], TTY_NORMAL); 556 } 557 } 558 if (!drop) 559 tty_flip_buffer_push(tport); 560 } 561 #else 562 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 563 { 564 565 } 566 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 567 568 static void handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop) 569 { 570 struct qcom_geni_serial_port *port = to_dev_port(uport); 571 struct tty_port *tport = &uport->state->port; 572 int ret; 573 574 ret = tty_insert_flip_string(tport, port->rx_buf, bytes); 575 if (ret != bytes) { 576 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n", 577 __func__, ret, bytes); 578 WARN_ON_ONCE(1); 579 } 580 uport->icount.rx += ret; 581 tty_flip_buffer_push(tport); 582 } 583 584 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport) 585 { 586 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 587 } 588 589 static void qcom_geni_serial_stop_tx_dma(struct uart_port *uport) 590 { 591 struct qcom_geni_serial_port *port = to_dev_port(uport); 592 bool done; 593 594 if (!qcom_geni_serial_main_active(uport)) 595 return; 596 597 if (port->tx_dma_addr) { 598 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, 599 port->tx_remaining); 600 port->tx_dma_addr = 0; 601 port->tx_remaining = 0; 602 } 603 604 geni_se_cancel_m_cmd(&port->se); 605 606 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 607 M_CMD_CANCEL_EN, true); 608 if (!done) { 609 geni_se_abort_m_cmd(&port->se); 610 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 611 M_CMD_ABORT_EN, true); 612 if (!done) 613 dev_err_ratelimited(uport->dev, "M_CMD_ABORT_EN not set"); 614 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 615 } 616 617 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 618 } 619 620 static void qcom_geni_serial_start_tx_dma(struct uart_port *uport) 621 { 622 struct qcom_geni_serial_port *port = to_dev_port(uport); 623 struct tty_port *tport = &uport->state->port; 624 unsigned int xmit_size; 625 u8 *tail; 626 int ret; 627 628 if (port->tx_dma_addr) 629 return; 630 631 if (kfifo_is_empty(&tport->xmit_fifo)) 632 return; 633 634 xmit_size = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, 635 UART_XMIT_SIZE); 636 637 qcom_geni_serial_setup_tx(uport, xmit_size); 638 639 ret = geni_se_tx_dma_prep(&port->se, tail, xmit_size, 640 &port->tx_dma_addr); 641 if (ret) { 642 dev_err(uport->dev, "unable to start TX SE DMA: %d\n", ret); 643 qcom_geni_serial_stop_tx_dma(uport); 644 return; 645 } 646 647 port->tx_remaining = xmit_size; 648 } 649 650 static void qcom_geni_serial_start_tx_fifo(struct uart_port *uport) 651 { 652 u32 irq_en; 653 654 if (qcom_geni_serial_main_active(uport) || 655 !qcom_geni_serial_tx_empty(uport)) 656 return; 657 658 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 659 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; 660 661 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 662 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 663 } 664 665 static void qcom_geni_serial_stop_tx_fifo(struct uart_port *uport) 666 { 667 u32 irq_en; 668 struct qcom_geni_serial_port *port = to_dev_port(uport); 669 670 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 671 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 672 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); 673 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 674 /* Possible stop tx is called multiple times. */ 675 if (!qcom_geni_serial_main_active(uport)) 676 return; 677 678 geni_se_cancel_m_cmd(&port->se); 679 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 680 M_CMD_CANCEL_EN, true)) { 681 geni_se_abort_m_cmd(&port->se); 682 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 683 M_CMD_ABORT_EN, true); 684 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 685 } 686 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 687 } 688 689 static void qcom_geni_serial_handle_rx_fifo(struct uart_port *uport, bool drop) 690 { 691 u32 status; 692 u32 word_cnt; 693 u32 last_word_byte_cnt; 694 u32 last_word_partial; 695 u32 total_bytes; 696 697 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 698 word_cnt = status & RX_FIFO_WC_MSK; 699 last_word_partial = status & RX_LAST; 700 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >> 701 RX_LAST_BYTE_VALID_SHFT; 702 703 if (!word_cnt) 704 return; 705 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1); 706 if (last_word_partial && last_word_byte_cnt) 707 total_bytes += last_word_byte_cnt; 708 else 709 total_bytes += BYTES_PER_FIFO_WORD; 710 handle_rx_console(uport, total_bytes, drop); 711 } 712 713 static void qcom_geni_serial_stop_rx_fifo(struct uart_port *uport) 714 { 715 u32 irq_en; 716 struct qcom_geni_serial_port *port = to_dev_port(uport); 717 u32 s_irq_status; 718 719 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 720 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); 721 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 722 723 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 724 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 725 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 726 727 if (!qcom_geni_serial_secondary_active(uport)) 728 return; 729 730 geni_se_cancel_s_cmd(&port->se); 731 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 732 S_CMD_CANCEL_EN, true); 733 /* 734 * If timeout occurs secondary engine remains active 735 * and Abort sequence is executed. 736 */ 737 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 738 /* Flush the Rx buffer */ 739 if (s_irq_status & S_RX_FIFO_LAST_EN) 740 qcom_geni_serial_handle_rx_fifo(uport, true); 741 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 742 743 if (qcom_geni_serial_secondary_active(uport)) 744 qcom_geni_serial_abort_rx(uport); 745 } 746 747 static void qcom_geni_serial_start_rx_fifo(struct uart_port *uport) 748 { 749 u32 irq_en; 750 struct qcom_geni_serial_port *port = to_dev_port(uport); 751 752 if (qcom_geni_serial_secondary_active(uport)) 753 qcom_geni_serial_stop_rx_fifo(uport); 754 755 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); 756 757 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 758 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; 759 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 760 761 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 762 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 763 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 764 } 765 766 static void qcom_geni_serial_stop_rx_dma(struct uart_port *uport) 767 { 768 struct qcom_geni_serial_port *port = to_dev_port(uport); 769 770 if (!qcom_geni_serial_secondary_active(uport)) 771 return; 772 773 geni_se_cancel_s_cmd(&port->se); 774 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 775 S_CMD_CANCEL_EN, true); 776 777 if (qcom_geni_serial_secondary_active(uport)) 778 qcom_geni_serial_abort_rx(uport); 779 780 if (port->rx_dma_addr) { 781 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, 782 DMA_RX_BUF_SIZE); 783 port->rx_dma_addr = 0; 784 } 785 } 786 787 static void qcom_geni_serial_start_rx_dma(struct uart_port *uport) 788 { 789 struct qcom_geni_serial_port *port = to_dev_port(uport); 790 int ret; 791 792 if (qcom_geni_serial_secondary_active(uport)) 793 qcom_geni_serial_stop_rx_dma(uport); 794 795 geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN); 796 797 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, 798 DMA_RX_BUF_SIZE, 799 &port->rx_dma_addr); 800 if (ret) { 801 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); 802 qcom_geni_serial_stop_rx_dma(uport); 803 } 804 } 805 806 static void qcom_geni_serial_handle_rx_dma(struct uart_port *uport, bool drop) 807 { 808 struct qcom_geni_serial_port *port = to_dev_port(uport); 809 u32 rx_in; 810 int ret; 811 812 if (!qcom_geni_serial_secondary_active(uport)) 813 return; 814 815 if (!port->rx_dma_addr) 816 return; 817 818 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE); 819 port->rx_dma_addr = 0; 820 821 rx_in = readl(uport->membase + SE_DMA_RX_LEN_IN); 822 if (!rx_in) { 823 dev_warn(uport->dev, "serial engine reports 0 RX bytes in!\n"); 824 return; 825 } 826 827 if (!drop) 828 handle_rx_uart(uport, rx_in, drop); 829 830 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, 831 DMA_RX_BUF_SIZE, 832 &port->rx_dma_addr); 833 if (ret) { 834 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); 835 qcom_geni_serial_stop_rx_dma(uport); 836 } 837 } 838 839 static void qcom_geni_serial_start_rx(struct uart_port *uport) 840 { 841 uport->ops->start_rx(uport); 842 } 843 844 static void qcom_geni_serial_stop_rx(struct uart_port *uport) 845 { 846 uport->ops->stop_rx(uport); 847 } 848 849 static void qcom_geni_serial_stop_tx(struct uart_port *uport) 850 { 851 uport->ops->stop_tx(uport); 852 } 853 854 static void qcom_geni_serial_send_chunk_fifo(struct uart_port *uport, 855 unsigned int chunk) 856 { 857 struct qcom_geni_serial_port *port = to_dev_port(uport); 858 unsigned int tx_bytes, remaining = chunk; 859 u8 buf[BYTES_PER_FIFO_WORD]; 860 861 while (remaining) { 862 memset(buf, 0, sizeof(buf)); 863 tx_bytes = min(remaining, BYTES_PER_FIFO_WORD); 864 865 tx_bytes = uart_fifo_out(uport, buf, tx_bytes); 866 867 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); 868 869 remaining -= tx_bytes; 870 port->tx_remaining -= tx_bytes; 871 } 872 } 873 874 static void qcom_geni_serial_handle_tx_fifo(struct uart_port *uport, 875 bool done, bool active) 876 { 877 struct qcom_geni_serial_port *port = to_dev_port(uport); 878 struct tty_port *tport = &uport->state->port; 879 size_t avail; 880 size_t pending; 881 u32 status; 882 u32 irq_en; 883 unsigned int chunk; 884 885 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 886 887 /* Complete the current tx command before taking newly added data */ 888 if (active) 889 pending = port->tx_remaining; 890 else 891 pending = kfifo_len(&tport->xmit_fifo); 892 893 /* All data has been transmitted and acknowledged as received */ 894 if (!pending && !status && done) { 895 qcom_geni_serial_stop_tx_fifo(uport); 896 goto out_write_wakeup; 897 } 898 899 avail = port->tx_fifo_depth - (status & TX_FIFO_WC); 900 avail *= BYTES_PER_FIFO_WORD; 901 902 chunk = min(avail, pending); 903 if (!chunk) 904 goto out_write_wakeup; 905 906 if (!port->tx_remaining) { 907 qcom_geni_serial_setup_tx(uport, pending); 908 port->tx_remaining = pending; 909 910 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 911 if (!(irq_en & M_TX_FIFO_WATERMARK_EN)) 912 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 913 uport->membase + SE_GENI_M_IRQ_EN); 914 } 915 916 qcom_geni_serial_send_chunk_fifo(uport, chunk); 917 918 /* 919 * The tx fifo watermark is level triggered and latched. Though we had 920 * cleared it in qcom_geni_serial_isr it will have already reasserted 921 * so we must clear it again here after our writes. 922 */ 923 writel(M_TX_FIFO_WATERMARK_EN, 924 uport->membase + SE_GENI_M_IRQ_CLEAR); 925 926 out_write_wakeup: 927 if (!port->tx_remaining) { 928 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 929 if (irq_en & M_TX_FIFO_WATERMARK_EN) 930 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN, 931 uport->membase + SE_GENI_M_IRQ_EN); 932 } 933 934 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 935 uart_write_wakeup(uport); 936 } 937 938 static void qcom_geni_serial_handle_tx_dma(struct uart_port *uport) 939 { 940 struct qcom_geni_serial_port *port = to_dev_port(uport); 941 struct tty_port *tport = &uport->state->port; 942 943 uart_xmit_advance(uport, port->tx_remaining); 944 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining); 945 port->tx_dma_addr = 0; 946 port->tx_remaining = 0; 947 948 if (!kfifo_is_empty(&tport->xmit_fifo)) 949 qcom_geni_serial_start_tx_dma(uport); 950 951 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 952 uart_write_wakeup(uport); 953 } 954 955 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) 956 { 957 u32 m_irq_en; 958 u32 m_irq_status; 959 u32 s_irq_status; 960 u32 geni_status; 961 u32 dma; 962 u32 dma_tx_status; 963 u32 dma_rx_status; 964 struct uart_port *uport = dev; 965 bool drop_rx = false; 966 struct tty_port *tport = &uport->state->port; 967 struct qcom_geni_serial_port *port = to_dev_port(uport); 968 969 if (uport->suspended) 970 return IRQ_NONE; 971 972 uart_port_lock(uport); 973 974 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 975 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 976 dma_tx_status = readl(uport->membase + SE_DMA_TX_IRQ_STAT); 977 dma_rx_status = readl(uport->membase + SE_DMA_RX_IRQ_STAT); 978 geni_status = readl(uport->membase + SE_GENI_STATUS); 979 dma = readl(uport->membase + SE_GENI_DMA_MODE_EN); 980 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 981 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); 982 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 983 writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR); 984 writel(dma_rx_status, uport->membase + SE_DMA_RX_IRQ_CLR); 985 986 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN)) 987 goto out_unlock; 988 989 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) { 990 uport->icount.overrun++; 991 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 992 } 993 994 if (s_irq_status & (S_GP_IRQ_0_EN | S_GP_IRQ_1_EN)) { 995 if (s_irq_status & S_GP_IRQ_0_EN) 996 uport->icount.parity++; 997 drop_rx = true; 998 } else if (s_irq_status & (S_GP_IRQ_2_EN | S_GP_IRQ_3_EN)) { 999 uport->icount.brk++; 1000 port->brk = true; 1001 } 1002 1003 if (dma) { 1004 if (dma_tx_status & TX_DMA_DONE) 1005 qcom_geni_serial_handle_tx_dma(uport); 1006 1007 if (dma_rx_status) { 1008 if (dma_rx_status & RX_RESET_DONE) 1009 goto out_unlock; 1010 1011 if (dma_rx_status & RX_DMA_PARITY_ERR) { 1012 uport->icount.parity++; 1013 drop_rx = true; 1014 } 1015 1016 if (dma_rx_status & RX_DMA_BREAK) 1017 uport->icount.brk++; 1018 1019 if (dma_rx_status & (RX_DMA_DONE | RX_EOT)) 1020 qcom_geni_serial_handle_rx_dma(uport, drop_rx); 1021 } 1022 } else { 1023 if (m_irq_status & m_irq_en & 1024 (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) 1025 qcom_geni_serial_handle_tx_fifo(uport, 1026 m_irq_status & M_CMD_DONE_EN, 1027 geni_status & M_GENI_CMD_ACTIVE); 1028 1029 if (s_irq_status & (S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN)) 1030 qcom_geni_serial_handle_rx_fifo(uport, drop_rx); 1031 } 1032 1033 out_unlock: 1034 uart_unlock_and_check_sysrq(uport); 1035 1036 return IRQ_HANDLED; 1037 } 1038 1039 static int setup_fifos(struct qcom_geni_serial_port *port) 1040 { 1041 struct uart_port *uport; 1042 u32 old_rx_fifo_depth = port->rx_fifo_depth; 1043 1044 uport = &port->uport; 1045 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); 1046 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); 1047 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); 1048 uport->fifosize = 1049 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; 1050 1051 if (port->rx_buf && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) { 1052 /* 1053 * Use krealloc rather than krealloc_array because rx_buf is 1054 * accessed as 1 byte entries as well as 4 byte entries so it's 1055 * not necessarily an array. 1056 */ 1057 port->rx_buf = devm_krealloc(uport->dev, port->rx_buf, 1058 port->rx_fifo_depth * sizeof(u32), 1059 GFP_KERNEL); 1060 if (!port->rx_buf) 1061 return -ENOMEM; 1062 } 1063 1064 return 0; 1065 } 1066 1067 1068 static void qcom_geni_serial_shutdown(struct uart_port *uport) 1069 { 1070 disable_irq(uport->irq); 1071 1072 if (uart_console(uport)) 1073 return; 1074 1075 qcom_geni_serial_stop_tx(uport); 1076 qcom_geni_serial_stop_rx(uport); 1077 } 1078 1079 static int qcom_geni_serial_port_setup(struct uart_port *uport) 1080 { 1081 struct qcom_geni_serial_port *port = to_dev_port(uport); 1082 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT; 1083 u32 proto; 1084 u32 pin_swap; 1085 int ret; 1086 1087 proto = geni_se_read_proto(&port->se); 1088 if (proto != GENI_SE_UART) { 1089 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); 1090 return -ENXIO; 1091 } 1092 1093 qcom_geni_serial_stop_rx(uport); 1094 1095 ret = setup_fifos(port); 1096 if (ret) 1097 return ret; 1098 1099 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); 1100 1101 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL); 1102 if (port->rx_tx_swap) { 1103 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK; 1104 pin_swap |= IO_MACRO_IO2_IO3_SWAP; 1105 } 1106 if (port->cts_rts_swap) { 1107 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK; 1108 pin_swap |= IO_MACRO_IO0_SEL; 1109 } 1110 /* Configure this register if RX-TX, CTS-RTS pins are swapped */ 1111 if (port->rx_tx_swap || port->cts_rts_swap) 1112 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL); 1113 1114 /* 1115 * Make an unconditional cancel on the main sequencer to reset 1116 * it else we could end up in data loss scenarios. 1117 */ 1118 if (uart_console(uport)) 1119 qcom_geni_serial_poll_tx_done(uport); 1120 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1121 false, true, true); 1122 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); 1123 geni_se_select_mode(&port->se, port->dev_data->mode); 1124 qcom_geni_serial_start_rx(uport); 1125 port->setup = true; 1126 1127 return 0; 1128 } 1129 1130 static int qcom_geni_serial_startup(struct uart_port *uport) 1131 { 1132 int ret; 1133 struct qcom_geni_serial_port *port = to_dev_port(uport); 1134 1135 if (!port->setup) { 1136 ret = qcom_geni_serial_port_setup(uport); 1137 if (ret) 1138 return ret; 1139 } 1140 enable_irq(uport->irq); 1141 1142 return 0; 1143 } 1144 1145 static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int desired_clk, 1146 unsigned int *clk_div, unsigned int percent_tol) 1147 { 1148 unsigned long freq; 1149 unsigned long div, maxdiv; 1150 u64 mult; 1151 unsigned long offset, abs_tol, achieved; 1152 1153 abs_tol = div_u64((u64)desired_clk * percent_tol, 100); 1154 maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT; 1155 div = 1; 1156 while (div <= maxdiv) { 1157 mult = (u64)div * desired_clk; 1158 if (mult != (unsigned long)mult) 1159 break; 1160 1161 offset = div * abs_tol; 1162 freq = clk_round_rate(clk, mult - offset); 1163 1164 /* Can only get lower if we're done */ 1165 if (freq < mult - offset) 1166 break; 1167 1168 /* 1169 * Re-calculate div in case rounding skipped rates but we 1170 * ended up at a good one, then check for a match. 1171 */ 1172 div = DIV_ROUND_CLOSEST(freq, desired_clk); 1173 achieved = DIV_ROUND_CLOSEST(freq, div); 1174 if (achieved <= desired_clk + abs_tol && 1175 achieved >= desired_clk - abs_tol) { 1176 *clk_div = div; 1177 return freq; 1178 } 1179 1180 div = DIV_ROUND_UP(freq, desired_clk); 1181 } 1182 1183 return 0; 1184 } 1185 1186 static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud, 1187 unsigned int sampling_rate, unsigned int *clk_div) 1188 { 1189 unsigned long ser_clk; 1190 unsigned long desired_clk; 1191 1192 desired_clk = baud * sampling_rate; 1193 if (!desired_clk) 1194 return 0; 1195 1196 /* 1197 * try to find a clock rate within 2% tolerance, then within 5% 1198 */ 1199 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2); 1200 if (!ser_clk) 1201 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5); 1202 1203 return ser_clk; 1204 } 1205 1206 static void qcom_geni_serial_set_termios(struct uart_port *uport, 1207 struct ktermios *termios, 1208 const struct ktermios *old) 1209 { 1210 unsigned int baud; 1211 u32 bits_per_char; 1212 u32 tx_trans_cfg; 1213 u32 tx_parity_cfg; 1214 u32 rx_trans_cfg; 1215 u32 rx_parity_cfg; 1216 u32 stop_bit_len; 1217 unsigned int clk_div; 1218 u32 ser_clk_cfg; 1219 struct qcom_geni_serial_port *port = to_dev_port(uport); 1220 unsigned long clk_rate; 1221 u32 ver, sampling_rate; 1222 unsigned int avg_bw_core; 1223 1224 qcom_geni_serial_stop_rx(uport); 1225 /* baud rate */ 1226 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); 1227 port->baud = baud; 1228 1229 sampling_rate = UART_OVERSAMPLING; 1230 /* Sampling rate is halved for IP versions >= 2.5 */ 1231 ver = geni_se_get_qup_hw_version(&port->se); 1232 if (ver >= QUP_SE_VERSION_2_5) 1233 sampling_rate /= 2; 1234 1235 clk_rate = get_clk_div_rate(port->se.clk, baud, 1236 sampling_rate, &clk_div); 1237 if (!clk_rate) { 1238 dev_err(port->se.dev, 1239 "Couldn't find suitable clock rate for %u\n", 1240 baud * sampling_rate); 1241 goto out_restart_rx; 1242 } 1243 1244 dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n", 1245 baud * sampling_rate, clk_rate, clk_div); 1246 1247 uport->uartclk = clk_rate; 1248 port->clk_rate = clk_rate; 1249 dev_pm_opp_set_rate(uport->dev, clk_rate); 1250 ser_clk_cfg = SER_CLK_EN; 1251 ser_clk_cfg |= clk_div << CLK_DIV_SHFT; 1252 1253 /* 1254 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode 1255 * only. 1256 */ 1257 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ) 1258 : GENI_DEFAULT_BW; 1259 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core; 1260 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); 1261 geni_icc_set_bw(&port->se); 1262 1263 /* parity */ 1264 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); 1265 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); 1266 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG); 1267 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG); 1268 if (termios->c_cflag & PARENB) { 1269 tx_trans_cfg |= UART_TX_PAR_EN; 1270 rx_trans_cfg |= UART_RX_PAR_EN; 1271 tx_parity_cfg |= PAR_CALC_EN; 1272 rx_parity_cfg |= PAR_CALC_EN; 1273 if (termios->c_cflag & PARODD) { 1274 tx_parity_cfg |= PAR_ODD; 1275 rx_parity_cfg |= PAR_ODD; 1276 } else if (termios->c_cflag & CMSPAR) { 1277 tx_parity_cfg |= PAR_SPACE; 1278 rx_parity_cfg |= PAR_SPACE; 1279 } else { 1280 tx_parity_cfg |= PAR_EVEN; 1281 rx_parity_cfg |= PAR_EVEN; 1282 } 1283 } else { 1284 tx_trans_cfg &= ~UART_TX_PAR_EN; 1285 rx_trans_cfg &= ~UART_RX_PAR_EN; 1286 tx_parity_cfg &= ~PAR_CALC_EN; 1287 rx_parity_cfg &= ~PAR_CALC_EN; 1288 } 1289 1290 /* bits per char */ 1291 bits_per_char = tty_get_char_size(termios->c_cflag); 1292 1293 /* stop bits */ 1294 if (termios->c_cflag & CSTOPB) 1295 stop_bit_len = TX_STOP_BIT_LEN_2; 1296 else 1297 stop_bit_len = TX_STOP_BIT_LEN_1; 1298 1299 /* flow control, clear the CTS_MASK bit if using flow control. */ 1300 if (termios->c_cflag & CRTSCTS) 1301 tx_trans_cfg &= ~UART_CTS_MASK; 1302 else 1303 tx_trans_cfg |= UART_CTS_MASK; 1304 1305 if (baud) 1306 uart_update_timeout(uport, termios->c_cflag, baud); 1307 1308 if (!uart_console(uport)) 1309 writel(port->loopback, 1310 uport->membase + SE_UART_LOOPBACK_CFG); 1311 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1312 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1313 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1314 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1315 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1316 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1317 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1318 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); 1319 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); 1320 out_restart_rx: 1321 qcom_geni_serial_start_rx(uport); 1322 } 1323 1324 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 1325 static int qcom_geni_console_setup(struct console *co, char *options) 1326 { 1327 struct uart_port *uport; 1328 struct qcom_geni_serial_port *port; 1329 int baud = 115200; 1330 int bits = 8; 1331 int parity = 'n'; 1332 int flow = 'n'; 1333 int ret; 1334 1335 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) 1336 return -ENXIO; 1337 1338 port = get_port_from_line(co->index, true); 1339 if (IS_ERR(port)) { 1340 pr_err("Invalid line %d\n", co->index); 1341 return PTR_ERR(port); 1342 } 1343 1344 uport = &port->uport; 1345 1346 if (unlikely(!uport->membase)) 1347 return -ENXIO; 1348 1349 if (!port->setup) { 1350 ret = qcom_geni_serial_port_setup(uport); 1351 if (ret) 1352 return ret; 1353 } 1354 1355 if (options) 1356 uart_parse_options(options, &baud, &parity, &bits, &flow); 1357 1358 return uart_set_options(uport, co, baud, parity, bits, flow); 1359 } 1360 1361 static void qcom_geni_serial_earlycon_write(struct console *con, 1362 const char *s, unsigned int n) 1363 { 1364 struct earlycon_device *dev = con->data; 1365 1366 __qcom_geni_serial_console_write(&dev->port, s, n); 1367 } 1368 1369 #ifdef CONFIG_CONSOLE_POLL 1370 static int qcom_geni_serial_earlycon_read(struct console *con, 1371 char *s, unsigned int n) 1372 { 1373 struct earlycon_device *dev = con->data; 1374 struct uart_port *uport = &dev->port; 1375 int num_read = 0; 1376 int ch; 1377 1378 while (num_read < n) { 1379 ch = qcom_geni_serial_get_char(uport); 1380 if (ch == NO_POLL_CHAR) 1381 break; 1382 s[num_read++] = ch; 1383 } 1384 1385 return num_read; 1386 } 1387 1388 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se, 1389 struct console *con) 1390 { 1391 geni_se_setup_s_cmd(se, UART_START_READ, 0); 1392 con->read = qcom_geni_serial_earlycon_read; 1393 } 1394 #else 1395 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se, 1396 struct console *con) { } 1397 #endif 1398 1399 static struct qcom_geni_private_data earlycon_private_data; 1400 1401 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev, 1402 const char *opt) 1403 { 1404 struct uart_port *uport = &dev->port; 1405 u32 tx_trans_cfg; 1406 u32 tx_parity_cfg = 0; /* Disable Tx Parity */ 1407 u32 rx_trans_cfg = 0; 1408 u32 rx_parity_cfg = 0; /* Disable Rx Parity */ 1409 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ 1410 u32 bits_per_char; 1411 struct geni_se se; 1412 1413 if (!uport->membase) 1414 return -EINVAL; 1415 1416 uport->private_data = &earlycon_private_data; 1417 1418 memset(&se, 0, sizeof(se)); 1419 se.base = uport->membase; 1420 if (geni_se_read_proto(&se) != GENI_SE_UART) 1421 return -ENXIO; 1422 /* 1423 * Ignore Flow control. 1424 * n = 8. 1425 */ 1426 tx_trans_cfg = UART_CTS_MASK; 1427 bits_per_char = BITS_PER_BYTE; 1428 1429 /* 1430 * Make an unconditional cancel on the main sequencer to reset 1431 * it else we could end up in data loss scenarios. 1432 */ 1433 qcom_geni_serial_poll_tx_done(uport); 1434 qcom_geni_serial_abort_rx(uport); 1435 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1436 false, true, true); 1437 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); 1438 geni_se_select_mode(&se, GENI_SE_FIFO); 1439 1440 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1441 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1442 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1443 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1444 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1445 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1446 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1447 1448 dev->con->write = qcom_geni_serial_earlycon_write; 1449 dev->con->setup = NULL; 1450 qcom_geni_serial_enable_early_read(&se, dev->con); 1451 1452 return 0; 1453 } 1454 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart", 1455 qcom_geni_serial_earlycon_setup); 1456 1457 static int __init console_register(struct uart_driver *drv) 1458 { 1459 return uart_register_driver(drv); 1460 } 1461 1462 static void console_unregister(struct uart_driver *drv) 1463 { 1464 uart_unregister_driver(drv); 1465 } 1466 1467 static struct console cons_ops = { 1468 .name = "ttyMSM", 1469 .write = qcom_geni_serial_console_write, 1470 .device = uart_console_device, 1471 .setup = qcom_geni_console_setup, 1472 .flags = CON_PRINTBUFFER, 1473 .index = -1, 1474 .data = &qcom_geni_console_driver, 1475 }; 1476 1477 static struct uart_driver qcom_geni_console_driver = { 1478 .owner = THIS_MODULE, 1479 .driver_name = "qcom_geni_console", 1480 .dev_name = "ttyMSM", 1481 .nr = GENI_UART_CONS_PORTS, 1482 .cons = &cons_ops, 1483 }; 1484 #else 1485 static int console_register(struct uart_driver *drv) 1486 { 1487 return 0; 1488 } 1489 1490 static void console_unregister(struct uart_driver *drv) 1491 { 1492 } 1493 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 1494 1495 static struct uart_driver qcom_geni_uart_driver = { 1496 .owner = THIS_MODULE, 1497 .driver_name = "qcom_geni_uart", 1498 .dev_name = "ttyHS", 1499 .nr = GENI_UART_PORTS, 1500 }; 1501 1502 static void qcom_geni_serial_pm(struct uart_port *uport, 1503 unsigned int new_state, unsigned int old_state) 1504 { 1505 struct qcom_geni_serial_port *port = to_dev_port(uport); 1506 1507 /* If we've never been called, treat it as off */ 1508 if (old_state == UART_PM_STATE_UNDEFINED) 1509 old_state = UART_PM_STATE_OFF; 1510 1511 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) { 1512 geni_icc_enable(&port->se); 1513 if (port->clk_rate) 1514 dev_pm_opp_set_rate(uport->dev, port->clk_rate); 1515 geni_se_resources_on(&port->se); 1516 } else if (new_state == UART_PM_STATE_OFF && 1517 old_state == UART_PM_STATE_ON) { 1518 geni_se_resources_off(&port->se); 1519 dev_pm_opp_set_rate(uport->dev, 0); 1520 geni_icc_disable(&port->se); 1521 } 1522 } 1523 1524 static const struct uart_ops qcom_geni_console_pops = { 1525 .tx_empty = qcom_geni_serial_tx_empty, 1526 .stop_tx = qcom_geni_serial_stop_tx_fifo, 1527 .start_tx = qcom_geni_serial_start_tx_fifo, 1528 .stop_rx = qcom_geni_serial_stop_rx_fifo, 1529 .start_rx = qcom_geni_serial_start_rx_fifo, 1530 .set_termios = qcom_geni_serial_set_termios, 1531 .startup = qcom_geni_serial_startup, 1532 .request_port = qcom_geni_serial_request_port, 1533 .config_port = qcom_geni_serial_config_port, 1534 .shutdown = qcom_geni_serial_shutdown, 1535 .type = qcom_geni_serial_get_type, 1536 .set_mctrl = qcom_geni_serial_set_mctrl, 1537 .get_mctrl = qcom_geni_serial_get_mctrl, 1538 #ifdef CONFIG_CONSOLE_POLL 1539 .poll_get_char = qcom_geni_serial_get_char, 1540 .poll_put_char = qcom_geni_serial_poll_put_char, 1541 .poll_init = qcom_geni_serial_port_setup, 1542 #endif 1543 .pm = qcom_geni_serial_pm, 1544 }; 1545 1546 static const struct uart_ops qcom_geni_uart_pops = { 1547 .tx_empty = qcom_geni_serial_tx_empty, 1548 .stop_tx = qcom_geni_serial_stop_tx_dma, 1549 .start_tx = qcom_geni_serial_start_tx_dma, 1550 .start_rx = qcom_geni_serial_start_rx_dma, 1551 .stop_rx = qcom_geni_serial_stop_rx_dma, 1552 .set_termios = qcom_geni_serial_set_termios, 1553 .startup = qcom_geni_serial_startup, 1554 .request_port = qcom_geni_serial_request_port, 1555 .config_port = qcom_geni_serial_config_port, 1556 .shutdown = qcom_geni_serial_shutdown, 1557 .type = qcom_geni_serial_get_type, 1558 .set_mctrl = qcom_geni_serial_set_mctrl, 1559 .get_mctrl = qcom_geni_serial_get_mctrl, 1560 .pm = qcom_geni_serial_pm, 1561 }; 1562 1563 static int qcom_geni_serial_probe(struct platform_device *pdev) 1564 { 1565 int ret = 0; 1566 int line; 1567 struct qcom_geni_serial_port *port; 1568 struct uart_port *uport; 1569 struct resource *res; 1570 int irq; 1571 struct uart_driver *drv; 1572 const struct qcom_geni_device_data *data; 1573 1574 data = of_device_get_match_data(&pdev->dev); 1575 if (!data) 1576 return -EINVAL; 1577 1578 if (data->console) { 1579 drv = &qcom_geni_console_driver; 1580 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1581 } else { 1582 drv = &qcom_geni_uart_driver; 1583 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1584 if (line == -ENODEV) /* compat with non-standard aliases */ 1585 line = of_alias_get_id(pdev->dev.of_node, "hsuart"); 1586 } 1587 1588 port = get_port_from_line(line, data->console); 1589 if (IS_ERR(port)) { 1590 dev_err(&pdev->dev, "Invalid line %d\n", line); 1591 return PTR_ERR(port); 1592 } 1593 1594 uport = &port->uport; 1595 /* Don't allow 2 drivers to access the same port */ 1596 if (uport->private_data) 1597 return -ENODEV; 1598 1599 uport->dev = &pdev->dev; 1600 port->dev_data = data; 1601 port->se.dev = &pdev->dev; 1602 port->se.wrapper = dev_get_drvdata(pdev->dev.parent); 1603 port->se.clk = devm_clk_get(&pdev->dev, "se"); 1604 if (IS_ERR(port->se.clk)) { 1605 ret = PTR_ERR(port->se.clk); 1606 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); 1607 return ret; 1608 } 1609 1610 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1611 if (!res) 1612 return -EINVAL; 1613 uport->mapbase = res->start; 1614 1615 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1616 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1617 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; 1618 1619 if (!data->console) { 1620 port->rx_buf = devm_kzalloc(uport->dev, 1621 DMA_RX_BUF_SIZE, GFP_KERNEL); 1622 if (!port->rx_buf) 1623 return -ENOMEM; 1624 } 1625 1626 ret = geni_icc_get(&port->se, NULL); 1627 if (ret) 1628 return ret; 1629 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; 1630 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 1631 1632 /* Set BW for register access */ 1633 ret = geni_icc_set_bw(&port->se); 1634 if (ret) 1635 return ret; 1636 1637 port->name = devm_kasprintf(uport->dev, GFP_KERNEL, 1638 "qcom_geni_serial_%s%d", 1639 uart_console(uport) ? "console" : "uart", uport->line); 1640 if (!port->name) 1641 return -ENOMEM; 1642 1643 irq = platform_get_irq(pdev, 0); 1644 if (irq < 0) 1645 return irq; 1646 uport->irq = irq; 1647 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); 1648 1649 if (!data->console) 1650 port->wakeup_irq = platform_get_irq_optional(pdev, 1); 1651 1652 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap")) 1653 port->rx_tx_swap = true; 1654 1655 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) 1656 port->cts_rts_swap = true; 1657 1658 ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); 1659 if (ret) 1660 return ret; 1661 /* OPP table is optional */ 1662 ret = devm_pm_opp_of_add_table(&pdev->dev); 1663 if (ret && ret != -ENODEV) { 1664 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1665 return ret; 1666 } 1667 1668 port->private_data.drv = drv; 1669 uport->private_data = &port->private_data; 1670 platform_set_drvdata(pdev, port); 1671 1672 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); 1673 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, 1674 IRQF_TRIGGER_HIGH, port->name, uport); 1675 if (ret) { 1676 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); 1677 return ret; 1678 } 1679 1680 ret = uart_add_one_port(drv, uport); 1681 if (ret) 1682 return ret; 1683 1684 if (port->wakeup_irq > 0) { 1685 device_init_wakeup(&pdev->dev, true); 1686 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1687 port->wakeup_irq); 1688 if (ret) { 1689 device_init_wakeup(&pdev->dev, false); 1690 uart_remove_one_port(drv, uport); 1691 return ret; 1692 } 1693 } 1694 1695 return 0; 1696 } 1697 1698 static void qcom_geni_serial_remove(struct platform_device *pdev) 1699 { 1700 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); 1701 struct uart_driver *drv = port->private_data.drv; 1702 1703 dev_pm_clear_wake_irq(&pdev->dev); 1704 device_init_wakeup(&pdev->dev, false); 1705 uart_remove_one_port(drv, &port->uport); 1706 } 1707 1708 static int qcom_geni_serial_sys_suspend(struct device *dev) 1709 { 1710 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1711 struct uart_port *uport = &port->uport; 1712 struct qcom_geni_private_data *private_data = uport->private_data; 1713 1714 /* 1715 * This is done so we can hit the lowest possible state in suspend 1716 * even with no_console_suspend 1717 */ 1718 if (uart_console(uport)) { 1719 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY); 1720 geni_icc_set_bw(&port->se); 1721 } 1722 return uart_suspend_port(private_data->drv, uport); 1723 } 1724 1725 static int qcom_geni_serial_sys_resume(struct device *dev) 1726 { 1727 int ret; 1728 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1729 struct uart_port *uport = &port->uport; 1730 struct qcom_geni_private_data *private_data = uport->private_data; 1731 1732 ret = uart_resume_port(private_data->drv, uport); 1733 if (uart_console(uport)) { 1734 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); 1735 geni_icc_set_bw(&port->se); 1736 } 1737 return ret; 1738 } 1739 1740 static int qcom_geni_serial_sys_hib_resume(struct device *dev) 1741 { 1742 int ret = 0; 1743 struct uart_port *uport; 1744 struct qcom_geni_private_data *private_data; 1745 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1746 1747 uport = &port->uport; 1748 private_data = uport->private_data; 1749 1750 if (uart_console(uport)) { 1751 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); 1752 geni_icc_set_bw(&port->se); 1753 ret = uart_resume_port(private_data->drv, uport); 1754 /* 1755 * For hibernation usecase clients for 1756 * console UART won't call port setup during restore, 1757 * hence call port setup for console uart. 1758 */ 1759 qcom_geni_serial_port_setup(uport); 1760 } else { 1761 /* 1762 * Peripheral register settings are lost during hibernation. 1763 * Update setup flag such that port setup happens again 1764 * during next session. Clients of HS-UART will close and 1765 * open the port during hibernation. 1766 */ 1767 port->setup = false; 1768 } 1769 return ret; 1770 } 1771 1772 static const struct qcom_geni_device_data qcom_geni_console_data = { 1773 .console = true, 1774 .mode = GENI_SE_FIFO, 1775 }; 1776 1777 static const struct qcom_geni_device_data qcom_geni_uart_data = { 1778 .console = false, 1779 .mode = GENI_SE_DMA, 1780 }; 1781 1782 static const struct dev_pm_ops qcom_geni_serial_pm_ops = { 1783 .suspend = pm_sleep_ptr(qcom_geni_serial_sys_suspend), 1784 .resume = pm_sleep_ptr(qcom_geni_serial_sys_resume), 1785 .freeze = pm_sleep_ptr(qcom_geni_serial_sys_suspend), 1786 .poweroff = pm_sleep_ptr(qcom_geni_serial_sys_suspend), 1787 .restore = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume), 1788 .thaw = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume), 1789 }; 1790 1791 static const struct of_device_id qcom_geni_serial_match_table[] = { 1792 { 1793 .compatible = "qcom,geni-debug-uart", 1794 .data = &qcom_geni_console_data, 1795 }, 1796 { 1797 .compatible = "qcom,geni-uart", 1798 .data = &qcom_geni_uart_data, 1799 }, 1800 {} 1801 }; 1802 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); 1803 1804 static struct platform_driver qcom_geni_serial_platform_driver = { 1805 .remove_new = qcom_geni_serial_remove, 1806 .probe = qcom_geni_serial_probe, 1807 .driver = { 1808 .name = "qcom_geni_serial", 1809 .of_match_table = qcom_geni_serial_match_table, 1810 .pm = &qcom_geni_serial_pm_ops, 1811 }, 1812 }; 1813 1814 static int __init qcom_geni_serial_init(void) 1815 { 1816 int ret; 1817 1818 ret = console_register(&qcom_geni_console_driver); 1819 if (ret) 1820 return ret; 1821 1822 ret = uart_register_driver(&qcom_geni_uart_driver); 1823 if (ret) { 1824 console_unregister(&qcom_geni_console_driver); 1825 return ret; 1826 } 1827 1828 ret = platform_driver_register(&qcom_geni_serial_platform_driver); 1829 if (ret) { 1830 console_unregister(&qcom_geni_console_driver); 1831 uart_unregister_driver(&qcom_geni_uart_driver); 1832 } 1833 return ret; 1834 } 1835 module_init(qcom_geni_serial_init); 1836 1837 static void __exit qcom_geni_serial_exit(void) 1838 { 1839 platform_driver_unregister(&qcom_geni_serial_platform_driver); 1840 console_unregister(&qcom_geni_console_driver); 1841 uart_unregister_driver(&qcom_geni_uart_driver); 1842 } 1843 module_exit(qcom_geni_serial_exit); 1844 1845 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores"); 1846 MODULE_LICENSE("GPL v2"); 1847