1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PIC32 Integrated Serial Driver. 4 * 5 * Copyright (C) 2015 Microchip Technology, Inc. 6 * 7 * Authors: 8 * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/platform_device.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_gpio.h> 17 #include <linux/init.h> 18 #include <linux/module.h> 19 #include <linux/slab.h> 20 #include <linux/console.h> 21 #include <linux/clk.h> 22 #include <linux/tty.h> 23 #include <linux/tty_flip.h> 24 #include <linux/serial_core.h> 25 #include <linux/delay.h> 26 27 #include <asm/mach-pic32/pic32.h> 28 29 /* UART name and device definitions */ 30 #define PIC32_DEV_NAME "pic32-uart" 31 #define PIC32_MAX_UARTS 6 32 #define PIC32_SDEV_NAME "ttyPIC" 33 34 #define PIC32_UART_DFLT_BRATE 9600 35 #define PIC32_UART_TX_FIFO_DEPTH 8 36 #define PIC32_UART_RX_FIFO_DEPTH 8 37 38 #define PIC32_UART_MODE 0x00 39 #define PIC32_UART_STA 0x10 40 #define PIC32_UART_TX 0x20 41 #define PIC32_UART_RX 0x30 42 #define PIC32_UART_BRG 0x40 43 44 /* struct pic32_sport - pic32 serial port descriptor 45 * @port: uart port descriptor 46 * @idx: port index 47 * @irq_fault: virtual fault interrupt number 48 * @irq_fault_name: irq fault name 49 * @irq_rx: virtual rx interrupt number 50 * @irq_rx_name: irq rx name 51 * @irq_tx: virtual tx interrupt number 52 * @irq_tx_name: irq tx name 53 * @cts_gpio: clear to send gpio 54 * @dev: device descriptor 55 **/ 56 struct pic32_sport { 57 struct uart_port port; 58 int idx; 59 60 int irq_fault; 61 const char *irq_fault_name; 62 int irq_rx; 63 const char *irq_rx_name; 64 int irq_tx; 65 const char *irq_tx_name; 66 bool enable_tx_irq; 67 68 bool hw_flow_ctrl; 69 int cts_gpio; 70 71 struct clk *clk; 72 73 struct device *dev; 74 }; 75 76 static inline struct pic32_sport *to_pic32_sport(struct uart_port *port) 77 { 78 return container_of(port, struct pic32_sport, port); 79 } 80 81 static inline void pic32_uart_writel(struct pic32_sport *sport, 82 u32 reg, u32 val) 83 { 84 __raw_writel(val, sport->port.membase + reg); 85 } 86 87 static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg) 88 { 89 return __raw_readl(sport->port.membase + reg); 90 } 91 92 /* pic32 uart mode register bits */ 93 #define PIC32_UART_MODE_ON BIT(15) 94 #define PIC32_UART_MODE_FRZ BIT(14) 95 #define PIC32_UART_MODE_SIDL BIT(13) 96 #define PIC32_UART_MODE_IREN BIT(12) 97 #define PIC32_UART_MODE_RTSMD BIT(11) 98 #define PIC32_UART_MODE_RESV1 BIT(10) 99 #define PIC32_UART_MODE_UEN1 BIT(9) 100 #define PIC32_UART_MODE_UEN0 BIT(8) 101 #define PIC32_UART_MODE_WAKE BIT(7) 102 #define PIC32_UART_MODE_LPBK BIT(6) 103 #define PIC32_UART_MODE_ABAUD BIT(5) 104 #define PIC32_UART_MODE_RXINV BIT(4) 105 #define PIC32_UART_MODE_BRGH BIT(3) 106 #define PIC32_UART_MODE_PDSEL1 BIT(2) 107 #define PIC32_UART_MODE_PDSEL0 BIT(1) 108 #define PIC32_UART_MODE_STSEL BIT(0) 109 110 /* pic32 uart status register bits */ 111 #define PIC32_UART_STA_UTXISEL1 BIT(15) 112 #define PIC32_UART_STA_UTXISEL0 BIT(14) 113 #define PIC32_UART_STA_UTXINV BIT(13) 114 #define PIC32_UART_STA_URXEN BIT(12) 115 #define PIC32_UART_STA_UTXBRK BIT(11) 116 #define PIC32_UART_STA_UTXEN BIT(10) 117 #define PIC32_UART_STA_UTXBF BIT(9) 118 #define PIC32_UART_STA_TRMT BIT(8) 119 #define PIC32_UART_STA_URXISEL1 BIT(7) 120 #define PIC32_UART_STA_URXISEL0 BIT(6) 121 #define PIC32_UART_STA_ADDEN BIT(5) 122 #define PIC32_UART_STA_RIDLE BIT(4) 123 #define PIC32_UART_STA_PERR BIT(3) 124 #define PIC32_UART_STA_FERR BIT(2) 125 #define PIC32_UART_STA_OERR BIT(1) 126 #define PIC32_UART_STA_URXDA BIT(0) 127 128 /* pic32_sport pointer for console use */ 129 static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS]; 130 131 static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport) 132 { 133 /* wait for tx empty, otherwise chars will be lost or corrupted */ 134 while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT)) 135 udelay(1); 136 } 137 138 /* serial core request to check if uart tx buffer is empty */ 139 static unsigned int pic32_uart_tx_empty(struct uart_port *port) 140 { 141 struct pic32_sport *sport = to_pic32_sport(port); 142 u32 val = pic32_uart_readl(sport, PIC32_UART_STA); 143 144 return (val & PIC32_UART_STA_TRMT) ? 1 : 0; 145 } 146 147 /* serial core request to set UART outputs */ 148 static void pic32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 149 { 150 struct pic32_sport *sport = to_pic32_sport(port); 151 152 /* set loopback mode */ 153 if (mctrl & TIOCM_LOOP) 154 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 155 PIC32_UART_MODE_LPBK); 156 else 157 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 158 PIC32_UART_MODE_LPBK); 159 } 160 161 /* get the state of CTS input pin for this port */ 162 static unsigned int get_cts_state(struct pic32_sport *sport) 163 { 164 /* read and invert UxCTS */ 165 if (gpio_is_valid(sport->cts_gpio)) 166 return !gpio_get_value(sport->cts_gpio); 167 168 return 1; 169 } 170 171 /* serial core request to return the state of misc UART input pins */ 172 static unsigned int pic32_uart_get_mctrl(struct uart_port *port) 173 { 174 struct pic32_sport *sport = to_pic32_sport(port); 175 unsigned int mctrl = 0; 176 177 if (!sport->hw_flow_ctrl) 178 mctrl |= TIOCM_CTS; 179 else if (get_cts_state(sport)) 180 mctrl |= TIOCM_CTS; 181 182 /* DSR and CD are not supported in PIC32, so return 1 183 * RI is not supported in PIC32, so return 0 184 */ 185 mctrl |= TIOCM_CD; 186 mctrl |= TIOCM_DSR; 187 188 return mctrl; 189 } 190 191 /* stop tx and start tx are not called in pairs, therefore a flag indicates 192 * the status of irq to control the irq-depth. 193 */ 194 static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en) 195 { 196 if (en && !sport->enable_tx_irq) { 197 enable_irq(sport->irq_tx); 198 sport->enable_tx_irq = true; 199 } else if (!en && sport->enable_tx_irq) { 200 /* use disable_irq_nosync() and not disable_irq() to avoid self 201 * imposed deadlock by not waiting for irq handler to end, 202 * since this callback is called from interrupt context. 203 */ 204 disable_irq_nosync(sport->irq_tx); 205 sport->enable_tx_irq = false; 206 } 207 } 208 209 /* serial core request to disable tx ASAP (used for flow control) */ 210 static void pic32_uart_stop_tx(struct uart_port *port) 211 { 212 struct pic32_sport *sport = to_pic32_sport(port); 213 214 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON)) 215 return; 216 217 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN)) 218 return; 219 220 /* wait for tx empty */ 221 pic32_wait_deplete_txbuf(sport); 222 223 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 224 PIC32_UART_STA_UTXEN); 225 pic32_uart_irqtxen(sport, 0); 226 } 227 228 /* serial core request to (re)enable tx */ 229 static void pic32_uart_start_tx(struct uart_port *port) 230 { 231 struct pic32_sport *sport = to_pic32_sport(port); 232 233 pic32_uart_irqtxen(sport, 1); 234 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA), 235 PIC32_UART_STA_UTXEN); 236 } 237 238 /* serial core request to stop rx, called before port shutdown */ 239 static void pic32_uart_stop_rx(struct uart_port *port) 240 { 241 struct pic32_sport *sport = to_pic32_sport(port); 242 243 /* disable rx interrupts */ 244 disable_irq(sport->irq_rx); 245 246 /* receiver Enable bit OFF */ 247 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 248 PIC32_UART_STA_URXEN); 249 } 250 251 /* serial core request to start/stop emitting break char */ 252 static void pic32_uart_break_ctl(struct uart_port *port, int ctl) 253 { 254 struct pic32_sport *sport = to_pic32_sport(port); 255 unsigned long flags; 256 257 spin_lock_irqsave(&port->lock, flags); 258 259 if (ctl) 260 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA), 261 PIC32_UART_STA_UTXBRK); 262 else 263 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 264 PIC32_UART_STA_UTXBRK); 265 266 spin_unlock_irqrestore(&port->lock, flags); 267 } 268 269 /* get port type in string format */ 270 static const char *pic32_uart_type(struct uart_port *port) 271 { 272 return (port->type == PORT_PIC32) ? PIC32_DEV_NAME : NULL; 273 } 274 275 /* read all chars in rx fifo and send them to core */ 276 static void pic32_uart_do_rx(struct uart_port *port) 277 { 278 struct pic32_sport *sport = to_pic32_sport(port); 279 struct tty_port *tty; 280 unsigned int max_count; 281 282 /* limit number of char read in interrupt, should not be 283 * higher than fifo size anyway since we're much faster than 284 * serial port 285 */ 286 max_count = PIC32_UART_RX_FIFO_DEPTH; 287 288 spin_lock(&port->lock); 289 290 tty = &port->state->port; 291 292 do { 293 u32 sta_reg, c; 294 char flag; 295 296 /* get overrun/fifo empty information from status register */ 297 sta_reg = pic32_uart_readl(sport, PIC32_UART_STA); 298 if (unlikely(sta_reg & PIC32_UART_STA_OERR)) { 299 300 /* fifo reset is required to clear interrupt */ 301 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 302 PIC32_UART_STA_OERR); 303 304 port->icount.overrun++; 305 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 306 } 307 308 /* Can at least one more character can be read? */ 309 if (!(sta_reg & PIC32_UART_STA_URXDA)) 310 break; 311 312 /* read the character and increment the rx counter */ 313 c = pic32_uart_readl(sport, PIC32_UART_RX); 314 315 port->icount.rx++; 316 flag = TTY_NORMAL; 317 c &= 0xff; 318 319 if (unlikely((sta_reg & PIC32_UART_STA_PERR) || 320 (sta_reg & PIC32_UART_STA_FERR))) { 321 322 /* do stats first */ 323 if (sta_reg & PIC32_UART_STA_PERR) 324 port->icount.parity++; 325 if (sta_reg & PIC32_UART_STA_FERR) 326 port->icount.frame++; 327 328 /* update flag wrt read_status_mask */ 329 sta_reg &= port->read_status_mask; 330 331 if (sta_reg & PIC32_UART_STA_FERR) 332 flag = TTY_FRAME; 333 if (sta_reg & PIC32_UART_STA_PERR) 334 flag = TTY_PARITY; 335 } 336 337 if (uart_handle_sysrq_char(port, c)) 338 continue; 339 340 if ((sta_reg & port->ignore_status_mask) == 0) 341 tty_insert_flip_char(tty, c, flag); 342 343 } while (--max_count); 344 345 spin_unlock(&port->lock); 346 347 tty_flip_buffer_push(tty); 348 } 349 350 /* fill tx fifo with chars to send, stop when fifo is about to be full 351 * or when all chars have been sent. 352 */ 353 static void pic32_uart_do_tx(struct uart_port *port) 354 { 355 struct pic32_sport *sport = to_pic32_sport(port); 356 struct circ_buf *xmit = &port->state->xmit; 357 unsigned int max_count = PIC32_UART_TX_FIFO_DEPTH; 358 359 if (port->x_char) { 360 pic32_uart_writel(sport, PIC32_UART_TX, port->x_char); 361 port->icount.tx++; 362 port->x_char = 0; 363 return; 364 } 365 366 if (uart_tx_stopped(port)) { 367 pic32_uart_stop_tx(port); 368 return; 369 } 370 371 if (uart_circ_empty(xmit)) 372 goto txq_empty; 373 374 /* keep stuffing chars into uart tx buffer 375 * 1) until uart fifo is full 376 * or 377 * 2) until the circ buffer is empty 378 * (all chars have been sent) 379 * or 380 * 3) until the max count is reached 381 * (prevents lingering here for too long in certain cases) 382 */ 383 while (!(PIC32_UART_STA_UTXBF & 384 pic32_uart_readl(sport, PIC32_UART_STA))) { 385 unsigned int c = xmit->buf[xmit->tail]; 386 387 pic32_uart_writel(sport, PIC32_UART_TX, c); 388 389 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 390 port->icount.tx++; 391 if (uart_circ_empty(xmit)) 392 break; 393 if (--max_count == 0) 394 break; 395 } 396 397 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 398 uart_write_wakeup(port); 399 400 if (uart_circ_empty(xmit)) 401 goto txq_empty; 402 403 return; 404 405 txq_empty: 406 pic32_uart_irqtxen(sport, 0); 407 } 408 409 /* RX interrupt handler */ 410 static irqreturn_t pic32_uart_rx_interrupt(int irq, void *dev_id) 411 { 412 struct uart_port *port = dev_id; 413 414 pic32_uart_do_rx(port); 415 416 return IRQ_HANDLED; 417 } 418 419 /* TX interrupt handler */ 420 static irqreturn_t pic32_uart_tx_interrupt(int irq, void *dev_id) 421 { 422 struct uart_port *port = dev_id; 423 unsigned long flags; 424 425 spin_lock_irqsave(&port->lock, flags); 426 pic32_uart_do_tx(port); 427 spin_unlock_irqrestore(&port->lock, flags); 428 429 return IRQ_HANDLED; 430 } 431 432 /* FAULT interrupt handler */ 433 static irqreturn_t pic32_uart_fault_interrupt(int irq, void *dev_id) 434 { 435 /* do nothing: pic32_uart_do_rx() handles faults. */ 436 return IRQ_HANDLED; 437 } 438 439 /* enable rx & tx operation on uart */ 440 static void pic32_uart_en_and_unmask(struct uart_port *port) 441 { 442 struct pic32_sport *sport = to_pic32_sport(port); 443 444 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA), 445 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN); 446 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 447 PIC32_UART_MODE_ON); 448 } 449 450 /* disable rx & tx operation on uart */ 451 static void pic32_uart_dsbl_and_mask(struct uart_port *port) 452 { 453 struct pic32_sport *sport = to_pic32_sport(port); 454 455 /* wait for tx empty, otherwise chars will be lost or corrupted */ 456 pic32_wait_deplete_txbuf(sport); 457 458 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 459 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN); 460 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 461 PIC32_UART_MODE_ON); 462 } 463 464 /* serial core request to initialize uart and start rx operation */ 465 static int pic32_uart_startup(struct uart_port *port) 466 { 467 struct pic32_sport *sport = to_pic32_sport(port); 468 u32 dflt_baud = (port->uartclk / PIC32_UART_DFLT_BRATE / 16) - 1; 469 unsigned long flags; 470 int ret; 471 472 local_irq_save(flags); 473 474 ret = clk_prepare_enable(sport->clk); 475 if (ret) { 476 local_irq_restore(flags); 477 goto out_done; 478 } 479 480 /* clear status and mode registers */ 481 pic32_uart_writel(sport, PIC32_UART_MODE, 0); 482 pic32_uart_writel(sport, PIC32_UART_STA, 0); 483 484 /* disable uart and mask all interrupts */ 485 pic32_uart_dsbl_and_mask(port); 486 487 /* set default baud */ 488 pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud); 489 490 local_irq_restore(flags); 491 492 /* Each UART of a PIC32 has three interrupts therefore, 493 * we setup driver to register the 3 irqs for the device. 494 * 495 * For each irq request_irq() is called with interrupt disabled. 496 * And the irq is enabled as soon as we are ready to handle them. 497 */ 498 sport->enable_tx_irq = false; 499 500 sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault", 501 pic32_uart_type(port), 502 sport->idx); 503 if (!sport->irq_fault_name) { 504 dev_err(port->dev, "%s: kasprintf err!", __func__); 505 ret = -ENOMEM; 506 goto out_disable_clk; 507 } 508 irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN); 509 ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt, 510 IRQF_NO_THREAD, sport->irq_fault_name, port); 511 if (ret) { 512 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n", 513 __func__, sport->irq_fault, ret, 514 pic32_uart_type(port)); 515 goto out_f; 516 } 517 518 sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx", 519 pic32_uart_type(port), 520 sport->idx); 521 if (!sport->irq_rx_name) { 522 dev_err(port->dev, "%s: kasprintf err!", __func__); 523 ret = -ENOMEM; 524 goto out_f; 525 } 526 irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN); 527 ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt, 528 IRQF_NO_THREAD, sport->irq_rx_name, port); 529 if (ret) { 530 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n", 531 __func__, sport->irq_rx, ret, 532 pic32_uart_type(port)); 533 goto out_r; 534 } 535 536 sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx", 537 pic32_uart_type(port), 538 sport->idx); 539 if (!sport->irq_tx_name) { 540 dev_err(port->dev, "%s: kasprintf err!", __func__); 541 ret = -ENOMEM; 542 goto out_r; 543 } 544 irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN); 545 ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt, 546 IRQF_NO_THREAD, sport->irq_tx_name, port); 547 if (ret) { 548 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n", 549 __func__, sport->irq_tx, ret, 550 pic32_uart_type(port)); 551 goto out_t; 552 } 553 554 local_irq_save(flags); 555 556 /* set rx interrupt on first receive */ 557 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 558 PIC32_UART_STA_URXISEL1 | PIC32_UART_STA_URXISEL0); 559 560 /* set interrupt on empty */ 561 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 562 PIC32_UART_STA_UTXISEL1); 563 564 /* enable all interrupts and eanable uart */ 565 pic32_uart_en_and_unmask(port); 566 567 local_irq_restore(flags); 568 569 enable_irq(sport->irq_rx); 570 571 return 0; 572 573 out_t: 574 free_irq(sport->irq_tx, port); 575 kfree(sport->irq_tx_name); 576 out_r: 577 free_irq(sport->irq_rx, port); 578 kfree(sport->irq_rx_name); 579 out_f: 580 free_irq(sport->irq_fault, port); 581 kfree(sport->irq_fault_name); 582 out_disable_clk: 583 clk_disable_unprepare(sport->clk); 584 out_done: 585 return ret; 586 } 587 588 /* serial core request to flush & disable uart */ 589 static void pic32_uart_shutdown(struct uart_port *port) 590 { 591 struct pic32_sport *sport = to_pic32_sport(port); 592 unsigned long flags; 593 594 /* disable uart */ 595 spin_lock_irqsave(&port->lock, flags); 596 pic32_uart_dsbl_and_mask(port); 597 spin_unlock_irqrestore(&port->lock, flags); 598 clk_disable_unprepare(sport->clk); 599 600 /* free all 3 interrupts for this UART */ 601 free_irq(sport->irq_fault, port); 602 kfree(sport->irq_fault_name); 603 free_irq(sport->irq_tx, port); 604 kfree(sport->irq_tx_name); 605 free_irq(sport->irq_rx, port); 606 kfree(sport->irq_rx_name); 607 } 608 609 /* serial core request to change current uart setting */ 610 static void pic32_uart_set_termios(struct uart_port *port, 611 struct ktermios *new, 612 struct ktermios *old) 613 { 614 struct pic32_sport *sport = to_pic32_sport(port); 615 unsigned int baud; 616 unsigned int quot; 617 unsigned long flags; 618 619 spin_lock_irqsave(&port->lock, flags); 620 621 /* disable uart and mask all interrupts while changing speed */ 622 pic32_uart_dsbl_and_mask(port); 623 624 /* stop bit options */ 625 if (new->c_cflag & CSTOPB) 626 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 627 PIC32_UART_MODE_STSEL); 628 else 629 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 630 PIC32_UART_MODE_STSEL); 631 632 /* parity options */ 633 if (new->c_cflag & PARENB) { 634 if (new->c_cflag & PARODD) { 635 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 636 PIC32_UART_MODE_PDSEL1); 637 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 638 PIC32_UART_MODE_PDSEL0); 639 } else { 640 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 641 PIC32_UART_MODE_PDSEL0); 642 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 643 PIC32_UART_MODE_PDSEL1); 644 } 645 } else { 646 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 647 PIC32_UART_MODE_PDSEL1 | 648 PIC32_UART_MODE_PDSEL0); 649 } 650 /* if hw flow ctrl, then the pins must be specified in device tree */ 651 if ((new->c_cflag & CRTSCTS) && sport->hw_flow_ctrl) { 652 /* enable hardware flow control */ 653 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 654 PIC32_UART_MODE_UEN1); 655 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 656 PIC32_UART_MODE_UEN0); 657 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 658 PIC32_UART_MODE_RTSMD); 659 } else { 660 /* disable hardware flow control */ 661 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 662 PIC32_UART_MODE_UEN1); 663 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 664 PIC32_UART_MODE_UEN0); 665 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 666 PIC32_UART_MODE_RTSMD); 667 } 668 669 /* Always 8-bit */ 670 new->c_cflag |= CS8; 671 672 /* Mark/Space parity is not supported */ 673 new->c_cflag &= ~CMSPAR; 674 675 /* update baud */ 676 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); 677 quot = uart_get_divisor(port, baud) - 1; 678 pic32_uart_writel(sport, PIC32_UART_BRG, quot); 679 uart_update_timeout(port, new->c_cflag, baud); 680 681 if (tty_termios_baud_rate(new)) 682 tty_termios_encode_baud_rate(new, baud, baud); 683 684 /* enable uart */ 685 pic32_uart_en_and_unmask(port); 686 687 spin_unlock_irqrestore(&port->lock, flags); 688 } 689 690 /* serial core request to claim uart iomem */ 691 static int pic32_uart_request_port(struct uart_port *port) 692 { 693 struct platform_device *pdev = to_platform_device(port->dev); 694 struct resource *res_mem; 695 696 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 697 if (unlikely(!res_mem)) 698 return -EINVAL; 699 700 if (!request_mem_region(port->mapbase, resource_size(res_mem), 701 "pic32_uart_mem")) 702 return -EBUSY; 703 704 port->membase = devm_ioremap(port->dev, port->mapbase, 705 resource_size(res_mem)); 706 if (!port->membase) { 707 dev_err(port->dev, "Unable to map registers\n"); 708 release_mem_region(port->mapbase, resource_size(res_mem)); 709 return -ENOMEM; 710 } 711 712 return 0; 713 } 714 715 /* serial core request to release uart iomem */ 716 static void pic32_uart_release_port(struct uart_port *port) 717 { 718 struct platform_device *pdev = to_platform_device(port->dev); 719 struct resource *res_mem; 720 unsigned int res_size; 721 722 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 723 if (unlikely(!res_mem)) 724 return; 725 res_size = resource_size(res_mem); 726 727 release_mem_region(port->mapbase, res_size); 728 } 729 730 /* serial core request to do any port required auto-configuration */ 731 static void pic32_uart_config_port(struct uart_port *port, int flags) 732 { 733 if (flags & UART_CONFIG_TYPE) { 734 if (pic32_uart_request_port(port)) 735 return; 736 port->type = PORT_PIC32; 737 } 738 } 739 740 /* serial core request to check that port information in serinfo are suitable */ 741 static int pic32_uart_verify_port(struct uart_port *port, 742 struct serial_struct *serinfo) 743 { 744 if (port->type != PORT_PIC32) 745 return -EINVAL; 746 if (port->irq != serinfo->irq) 747 return -EINVAL; 748 if (port->iotype != serinfo->io_type) 749 return -EINVAL; 750 if (port->mapbase != (unsigned long)serinfo->iomem_base) 751 return -EINVAL; 752 753 return 0; 754 } 755 756 /* serial core callbacks */ 757 static const struct uart_ops pic32_uart_ops = { 758 .tx_empty = pic32_uart_tx_empty, 759 .get_mctrl = pic32_uart_get_mctrl, 760 .set_mctrl = pic32_uart_set_mctrl, 761 .start_tx = pic32_uart_start_tx, 762 .stop_tx = pic32_uart_stop_tx, 763 .stop_rx = pic32_uart_stop_rx, 764 .break_ctl = pic32_uart_break_ctl, 765 .startup = pic32_uart_startup, 766 .shutdown = pic32_uart_shutdown, 767 .set_termios = pic32_uart_set_termios, 768 .type = pic32_uart_type, 769 .release_port = pic32_uart_release_port, 770 .request_port = pic32_uart_request_port, 771 .config_port = pic32_uart_config_port, 772 .verify_port = pic32_uart_verify_port, 773 }; 774 775 #ifdef CONFIG_SERIAL_PIC32_CONSOLE 776 /* output given char */ 777 static void pic32_console_putchar(struct uart_port *port, unsigned char ch) 778 { 779 struct pic32_sport *sport = to_pic32_sport(port); 780 781 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON)) 782 return; 783 784 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN)) 785 return; 786 787 /* wait for tx empty */ 788 pic32_wait_deplete_txbuf(sport); 789 790 pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff); 791 } 792 793 /* console core request to output given string */ 794 static void pic32_console_write(struct console *co, const char *s, 795 unsigned int count) 796 { 797 struct pic32_sport *sport = pic32_sports[co->index]; 798 799 /* call uart helper to deal with \r\n */ 800 uart_console_write(&sport->port, s, count, pic32_console_putchar); 801 } 802 803 /* console core request to setup given console, find matching uart 804 * port and setup it. 805 */ 806 static int pic32_console_setup(struct console *co, char *options) 807 { 808 struct pic32_sport *sport; 809 int baud = 115200; 810 int bits = 8; 811 int parity = 'n'; 812 int flow = 'n'; 813 int ret = 0; 814 815 if (unlikely(co->index < 0 || co->index >= PIC32_MAX_UARTS)) 816 return -ENODEV; 817 818 sport = pic32_sports[co->index]; 819 if (!sport) 820 return -ENODEV; 821 822 ret = clk_prepare_enable(sport->clk); 823 if (ret) 824 return ret; 825 826 if (options) 827 uart_parse_options(options, &baud, &parity, &bits, &flow); 828 829 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 830 } 831 832 static struct uart_driver pic32_uart_driver; 833 static struct console pic32_console = { 834 .name = PIC32_SDEV_NAME, 835 .write = pic32_console_write, 836 .device = uart_console_device, 837 .setup = pic32_console_setup, 838 .flags = CON_PRINTBUFFER, 839 .index = -1, 840 .data = &pic32_uart_driver, 841 }; 842 #define PIC32_SCONSOLE (&pic32_console) 843 844 static int __init pic32_console_init(void) 845 { 846 register_console(&pic32_console); 847 return 0; 848 } 849 console_initcall(pic32_console_init); 850 851 /* 852 * Late console initialization. 853 */ 854 static int __init pic32_late_console_init(void) 855 { 856 if (!(pic32_console.flags & CON_ENABLED)) 857 register_console(&pic32_console); 858 859 return 0; 860 } 861 862 core_initcall(pic32_late_console_init); 863 864 #else 865 #define PIC32_SCONSOLE NULL 866 #endif 867 868 static struct uart_driver pic32_uart_driver = { 869 .owner = THIS_MODULE, 870 .driver_name = PIC32_DEV_NAME, 871 .dev_name = PIC32_SDEV_NAME, 872 .nr = PIC32_MAX_UARTS, 873 .cons = PIC32_SCONSOLE, 874 }; 875 876 static int pic32_uart_probe(struct platform_device *pdev) 877 { 878 struct device_node *np = pdev->dev.of_node; 879 struct pic32_sport *sport; 880 int uart_idx = 0; 881 struct resource *res_mem; 882 struct uart_port *port; 883 int ret; 884 885 uart_idx = of_alias_get_id(np, "serial"); 886 if (uart_idx < 0 || uart_idx >= PIC32_MAX_UARTS) 887 return -EINVAL; 888 889 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 890 if (!res_mem) 891 return -EINVAL; 892 893 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 894 if (!sport) 895 return -ENOMEM; 896 897 sport->idx = uart_idx; 898 sport->irq_fault = irq_of_parse_and_map(np, 0); 899 sport->irq_rx = irq_of_parse_and_map(np, 1); 900 sport->irq_tx = irq_of_parse_and_map(np, 2); 901 sport->clk = devm_clk_get(&pdev->dev, NULL); 902 sport->dev = &pdev->dev; 903 904 /* Hardware flow control: gpios 905 * !Note: Basically, CTS is needed for reading the status. 906 */ 907 sport->hw_flow_ctrl = false; 908 sport->cts_gpio = of_get_named_gpio(np, "cts-gpios", 0); 909 if (gpio_is_valid(sport->cts_gpio)) { 910 sport->hw_flow_ctrl = true; 911 912 ret = devm_gpio_request(sport->dev, 913 sport->cts_gpio, "CTS"); 914 if (ret) { 915 dev_err(&pdev->dev, 916 "error requesting CTS GPIO\n"); 917 goto err; 918 } 919 920 ret = gpio_direction_input(sport->cts_gpio); 921 if (ret) { 922 dev_err(&pdev->dev, "error setting CTS GPIO\n"); 923 goto err; 924 } 925 } 926 927 pic32_sports[uart_idx] = sport; 928 port = &sport->port; 929 port->iotype = UPIO_MEM; 930 port->mapbase = res_mem->start; 931 port->ops = &pic32_uart_ops; 932 port->flags = UPF_BOOT_AUTOCONF; 933 port->dev = &pdev->dev; 934 port->fifosize = PIC32_UART_TX_FIFO_DEPTH; 935 port->uartclk = clk_get_rate(sport->clk); 936 port->line = uart_idx; 937 938 ret = uart_add_one_port(&pic32_uart_driver, port); 939 if (ret) { 940 port->membase = NULL; 941 dev_err(port->dev, "%s: uart add port error!\n", __func__); 942 goto err; 943 } 944 945 #ifdef CONFIG_SERIAL_PIC32_CONSOLE 946 if (uart_console(port) && (pic32_console.flags & CON_ENABLED)) { 947 /* The peripheral clock has been enabled by console_setup, 948 * so disable it till the port is used. 949 */ 950 clk_disable_unprepare(sport->clk); 951 } 952 #endif 953 954 platform_set_drvdata(pdev, port); 955 956 dev_info(&pdev->dev, "%s: uart(%d) driver initialized.\n", 957 __func__, uart_idx); 958 959 return 0; 960 err: 961 /* automatic unroll of sport and gpios */ 962 return ret; 963 } 964 965 static int pic32_uart_remove(struct platform_device *pdev) 966 { 967 struct uart_port *port = platform_get_drvdata(pdev); 968 struct pic32_sport *sport = to_pic32_sport(port); 969 970 uart_remove_one_port(&pic32_uart_driver, port); 971 clk_disable_unprepare(sport->clk); 972 platform_set_drvdata(pdev, NULL); 973 pic32_sports[sport->idx] = NULL; 974 975 /* automatic unroll of sport and gpios */ 976 return 0; 977 } 978 979 static const struct of_device_id pic32_serial_dt_ids[] = { 980 { .compatible = "microchip,pic32mzda-uart" }, 981 { /* sentinel */ } 982 }; 983 MODULE_DEVICE_TABLE(of, pic32_serial_dt_ids); 984 985 static struct platform_driver pic32_uart_platform_driver = { 986 .probe = pic32_uart_probe, 987 .remove = pic32_uart_remove, 988 .driver = { 989 .name = PIC32_DEV_NAME, 990 .of_match_table = of_match_ptr(pic32_serial_dt_ids), 991 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_PIC32), 992 }, 993 }; 994 995 static int __init pic32_uart_init(void) 996 { 997 int ret; 998 999 ret = uart_register_driver(&pic32_uart_driver); 1000 if (ret) { 1001 pr_err("failed to register %s:%d\n", 1002 pic32_uart_driver.driver_name, ret); 1003 return ret; 1004 } 1005 1006 ret = platform_driver_register(&pic32_uart_platform_driver); 1007 if (ret) { 1008 pr_err("fail to register pic32 uart\n"); 1009 uart_unregister_driver(&pic32_uart_driver); 1010 } 1011 1012 return ret; 1013 } 1014 arch_initcall(pic32_uart_init); 1015 1016 static void __exit pic32_uart_exit(void) 1017 { 1018 #ifdef CONFIG_SERIAL_PIC32_CONSOLE 1019 unregister_console(&pic32_console); 1020 #endif 1021 platform_driver_unregister(&pic32_uart_platform_driver); 1022 uart_unregister_driver(&pic32_uart_driver); 1023 } 1024 module_exit(pic32_uart_exit); 1025 1026 MODULE_AUTHOR("Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>"); 1027 MODULE_DESCRIPTION("Microchip PIC32 integrated serial port driver"); 1028 MODULE_LICENSE("GPL v2"); 1029