1 /* 2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 3 * 4 *This program is free software; you can redistribute it and/or modify 5 *it under the terms of the GNU General Public License as published by 6 *the Free Software Foundation; version 2 of the License. 7 * 8 *This program is distributed in the hope that it will be useful, 9 *but WITHOUT ANY WARRANTY; without even the implied warranty of 10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 *GNU General Public License for more details. 12 * 13 *You should have received a copy of the GNU General Public License 14 *along with this program; if not, write to the Free Software 15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 16 */ 17 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 18 #define SUPPORT_SYSRQ 19 #endif 20 #include <linux/kernel.h> 21 #include <linux/serial_reg.h> 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/pci.h> 25 #include <linux/console.h> 26 #include <linux/serial_core.h> 27 #include <linux/tty.h> 28 #include <linux/tty_flip.h> 29 #include <linux/interrupt.h> 30 #include <linux/io.h> 31 #include <linux/dmi.h> 32 #include <linux/nmi.h> 33 #include <linux/delay.h> 34 35 #include <linux/debugfs.h> 36 #include <linux/dmaengine.h> 37 #include <linux/pch_dma.h> 38 39 enum { 40 PCH_UART_HANDLED_RX_INT_SHIFT, 41 PCH_UART_HANDLED_TX_INT_SHIFT, 42 PCH_UART_HANDLED_RX_ERR_INT_SHIFT, 43 PCH_UART_HANDLED_RX_TRG_INT_SHIFT, 44 PCH_UART_HANDLED_MS_INT_SHIFT, 45 PCH_UART_HANDLED_LS_INT_SHIFT, 46 }; 47 48 enum { 49 PCH_UART_8LINE, 50 PCH_UART_2LINE, 51 }; 52 53 #define PCH_UART_DRIVER_DEVICE "ttyPCH" 54 55 /* Set the max number of UART port 56 * Intel EG20T PCH: 4 port 57 * LAPIS Semiconductor ML7213 IOH: 3 port 58 * LAPIS Semiconductor ML7223 IOH: 2 port 59 */ 60 #define PCH_UART_NR 4 61 62 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) 63 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) 64 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ 65 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) 66 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ 67 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) 68 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) 69 70 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1)) 71 72 #define PCH_UART_RBR 0x00 73 #define PCH_UART_THR 0x00 74 75 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ 76 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) 77 #define PCH_UART_IER_ERBFI 0x00000001 78 #define PCH_UART_IER_ETBEI 0x00000002 79 #define PCH_UART_IER_ELSI 0x00000004 80 #define PCH_UART_IER_EDSSI 0x00000008 81 82 #define PCH_UART_IIR_IP 0x00000001 83 #define PCH_UART_IIR_IID 0x00000006 84 #define PCH_UART_IIR_MSI 0x00000000 85 #define PCH_UART_IIR_TRI 0x00000002 86 #define PCH_UART_IIR_RRI 0x00000004 87 #define PCH_UART_IIR_REI 0x00000006 88 #define PCH_UART_IIR_TOI 0x00000008 89 #define PCH_UART_IIR_FIFO256 0x00000020 90 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 91 #define PCH_UART_IIR_FE 0x000000C0 92 93 #define PCH_UART_FCR_FIFOE 0x00000001 94 #define PCH_UART_FCR_RFR 0x00000002 95 #define PCH_UART_FCR_TFR 0x00000004 96 #define PCH_UART_FCR_DMS 0x00000008 97 #define PCH_UART_FCR_FIFO256 0x00000020 98 #define PCH_UART_FCR_RFTL 0x000000C0 99 100 #define PCH_UART_FCR_RFTL1 0x00000000 101 #define PCH_UART_FCR_RFTL64 0x00000040 102 #define PCH_UART_FCR_RFTL128 0x00000080 103 #define PCH_UART_FCR_RFTL224 0x000000C0 104 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 105 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 106 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 107 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 108 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 109 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 110 #define PCH_UART_FCR_RFTL_SHIFT 6 111 112 #define PCH_UART_LCR_WLS 0x00000003 113 #define PCH_UART_LCR_STB 0x00000004 114 #define PCH_UART_LCR_PEN 0x00000008 115 #define PCH_UART_LCR_EPS 0x00000010 116 #define PCH_UART_LCR_SP 0x00000020 117 #define PCH_UART_LCR_SB 0x00000040 118 #define PCH_UART_LCR_DLAB 0x00000080 119 #define PCH_UART_LCR_NP 0x00000000 120 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN 121 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) 122 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) 123 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ 124 PCH_UART_LCR_SP) 125 126 #define PCH_UART_LCR_5BIT 0x00000000 127 #define PCH_UART_LCR_6BIT 0x00000001 128 #define PCH_UART_LCR_7BIT 0x00000002 129 #define PCH_UART_LCR_8BIT 0x00000003 130 131 #define PCH_UART_MCR_DTR 0x00000001 132 #define PCH_UART_MCR_RTS 0x00000002 133 #define PCH_UART_MCR_OUT 0x0000000C 134 #define PCH_UART_MCR_LOOP 0x00000010 135 #define PCH_UART_MCR_AFE 0x00000020 136 137 #define PCH_UART_LSR_DR 0x00000001 138 #define PCH_UART_LSR_ERR (1<<7) 139 140 #define PCH_UART_MSR_DCTS 0x00000001 141 #define PCH_UART_MSR_DDSR 0x00000002 142 #define PCH_UART_MSR_TERI 0x00000004 143 #define PCH_UART_MSR_DDCD 0x00000008 144 #define PCH_UART_MSR_CTS 0x00000010 145 #define PCH_UART_MSR_DSR 0x00000020 146 #define PCH_UART_MSR_RI 0x00000040 147 #define PCH_UART_MSR_DCD 0x00000080 148 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ 149 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) 150 151 #define PCH_UART_DLL 0x00 152 #define PCH_UART_DLM 0x01 153 154 #define PCH_UART_BRCSR 0x0E 155 156 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) 157 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) 158 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) 159 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) 160 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) 161 162 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) 163 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) 164 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) 165 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) 166 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) 167 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) 168 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) 169 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) 170 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) 171 #define PCH_UART_HAL_STB1 0 172 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) 173 174 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) 175 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) 176 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ 177 PCH_UART_HAL_CLR_RX_FIFO) 178 179 #define PCH_UART_HAL_DMA_MODE0 0 180 #define PCH_UART_HAL_FIFO_DIS 0 181 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) 182 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ 183 PCH_UART_FCR_FIFO256) 184 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) 185 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) 186 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) 187 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) 188 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) 189 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) 190 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) 191 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) 192 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) 193 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) 194 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) 195 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) 196 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) 197 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) 198 199 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) 200 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) 201 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) 202 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) 203 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) 204 205 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) 206 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) 207 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) 208 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) 209 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) 210 211 #define PCI_VENDOR_ID_ROHM 0x10DB 212 213 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 214 215 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */ 216 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */ 217 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */ 218 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */ 219 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */ 220 #define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */ 221 222 struct pch_uart_buffer { 223 unsigned char *buf; 224 int size; 225 }; 226 227 struct eg20t_port { 228 struct uart_port port; 229 int port_type; 230 void __iomem *membase; 231 resource_size_t mapbase; 232 unsigned int iobase; 233 struct pci_dev *pdev; 234 int fifo_size; 235 int uartclk; 236 int start_tx; 237 int start_rx; 238 int tx_empty; 239 int trigger; 240 int trigger_level; 241 struct pch_uart_buffer rxbuf; 242 unsigned int dmsr; 243 unsigned int fcr; 244 unsigned int mcr; 245 unsigned int use_dma; 246 struct dma_async_tx_descriptor *desc_tx; 247 struct dma_async_tx_descriptor *desc_rx; 248 struct pch_dma_slave param_tx; 249 struct pch_dma_slave param_rx; 250 struct dma_chan *chan_tx; 251 struct dma_chan *chan_rx; 252 struct scatterlist *sg_tx_p; 253 int nent; 254 struct scatterlist sg_rx; 255 int tx_dma_use; 256 void *rx_buf_virt; 257 dma_addr_t rx_buf_dma; 258 259 struct dentry *debugfs; 260 261 /* protect the eg20t_port private structure and io access to membase */ 262 spinlock_t lock; 263 }; 264 265 /** 266 * struct pch_uart_driver_data - private data structure for UART-DMA 267 * @port_type: The number of DMA channel 268 * @line_no: UART port line number (0, 1, 2...) 269 */ 270 struct pch_uart_driver_data { 271 int port_type; 272 int line_no; 273 }; 274 275 enum pch_uart_num_t { 276 pch_et20t_uart0 = 0, 277 pch_et20t_uart1, 278 pch_et20t_uart2, 279 pch_et20t_uart3, 280 pch_ml7213_uart0, 281 pch_ml7213_uart1, 282 pch_ml7213_uart2, 283 pch_ml7223_uart0, 284 pch_ml7223_uart1, 285 pch_ml7831_uart0, 286 pch_ml7831_uart1, 287 }; 288 289 static struct pch_uart_driver_data drv_dat[] = { 290 [pch_et20t_uart0] = {PCH_UART_8LINE, 0}, 291 [pch_et20t_uart1] = {PCH_UART_2LINE, 1}, 292 [pch_et20t_uart2] = {PCH_UART_2LINE, 2}, 293 [pch_et20t_uart3] = {PCH_UART_2LINE, 3}, 294 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0}, 295 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1}, 296 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2}, 297 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0}, 298 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1}, 299 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0}, 300 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1}, 301 }; 302 303 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 304 static struct eg20t_port *pch_uart_ports[PCH_UART_NR]; 305 #endif 306 static unsigned int default_baud = 9600; 307 static unsigned int user_uartclk = 0; 308 static const int trigger_level_256[4] = { 1, 64, 128, 224 }; 309 static const int trigger_level_64[4] = { 1, 16, 32, 56 }; 310 static const int trigger_level_16[4] = { 1, 4, 8, 14 }; 311 static const int trigger_level_1[4] = { 1, 1, 1, 1 }; 312 313 #ifdef CONFIG_DEBUG_FS 314 315 #define PCH_REGS_BUFSIZE 1024 316 317 318 static ssize_t port_show_regs(struct file *file, char __user *user_buf, 319 size_t count, loff_t *ppos) 320 { 321 struct eg20t_port *priv = file->private_data; 322 char *buf; 323 u32 len = 0; 324 ssize_t ret; 325 unsigned char lcr; 326 327 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL); 328 if (!buf) 329 return 0; 330 331 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 332 "PCH EG20T port[%d] regs:\n", priv->port.line); 333 334 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 335 "=================================\n"); 336 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 337 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); 338 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 339 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); 340 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 341 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); 342 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 343 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); 344 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 345 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); 346 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 347 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); 348 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 349 "BRCSR: \t0x%02x\n", 350 ioread8(priv->membase + PCH_UART_BRCSR)); 351 352 lcr = ioread8(priv->membase + UART_LCR); 353 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 354 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 355 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); 356 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 357 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); 358 iowrite8(lcr, priv->membase + UART_LCR); 359 360 if (len > PCH_REGS_BUFSIZE) 361 len = PCH_REGS_BUFSIZE; 362 363 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 364 kfree(buf); 365 return ret; 366 } 367 368 static const struct file_operations port_regs_ops = { 369 .owner = THIS_MODULE, 370 .open = simple_open, 371 .read = port_show_regs, 372 .llseek = default_llseek, 373 }; 374 #endif /* CONFIG_DEBUG_FS */ 375 376 /* Return UART clock, checking for board specific clocks. */ 377 static int pch_uart_get_uartclk(void) 378 { 379 const char *cmp; 380 381 if (user_uartclk) 382 return user_uartclk; 383 384 cmp = dmi_get_system_info(DMI_BOARD_NAME); 385 if (cmp && strstr(cmp, "CM-iTC")) 386 return CMITC_UARTCLK; 387 388 cmp = dmi_get_system_info(DMI_BIOS_VERSION); 389 if (cmp && strnstr(cmp, "FRI2", 4)) 390 return FRI2_64_UARTCLK; 391 392 cmp = dmi_get_system_info(DMI_PRODUCT_NAME); 393 if (cmp && strstr(cmp, "Fish River Island II")) 394 return FRI2_48_UARTCLK; 395 396 /* Kontron COMe-mTT10 (nanoETXexpress-TT) */ 397 cmp = dmi_get_system_info(DMI_BOARD_NAME); 398 if (cmp && (strstr(cmp, "COMe-mTT") || 399 strstr(cmp, "nanoETXexpress-TT"))) 400 return NTC1_UARTCLK; 401 402 cmp = dmi_get_system_info(DMI_BOARD_NAME); 403 if (cmp && strstr(cmp, "MinnowBoard")) 404 return MINNOW_UARTCLK; 405 406 return DEFAULT_UARTCLK; 407 } 408 409 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, 410 unsigned int flag) 411 { 412 u8 ier = ioread8(priv->membase + UART_IER); 413 ier |= flag & PCH_UART_IER_MASK; 414 iowrite8(ier, priv->membase + UART_IER); 415 } 416 417 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, 418 unsigned int flag) 419 { 420 u8 ier = ioread8(priv->membase + UART_IER); 421 ier &= ~(flag & PCH_UART_IER_MASK); 422 iowrite8(ier, priv->membase + UART_IER); 423 } 424 425 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud, 426 unsigned int parity, unsigned int bits, 427 unsigned int stb) 428 { 429 unsigned int dll, dlm, lcr; 430 int div; 431 432 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); 433 if (div < 0 || USHRT_MAX <= div) { 434 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); 435 return -EINVAL; 436 } 437 438 dll = (unsigned int)div & 0x00FFU; 439 dlm = ((unsigned int)div >> 8) & 0x00FFU; 440 441 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { 442 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); 443 return -EINVAL; 444 } 445 446 if (bits & ~PCH_UART_LCR_WLS) { 447 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); 448 return -EINVAL; 449 } 450 451 if (stb & ~PCH_UART_LCR_STB) { 452 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); 453 return -EINVAL; 454 } 455 456 lcr = parity; 457 lcr |= bits; 458 lcr |= stb; 459 460 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n", 461 __func__, baud, div, lcr, jiffies); 462 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 463 iowrite8(dll, priv->membase + PCH_UART_DLL); 464 iowrite8(dlm, priv->membase + PCH_UART_DLM); 465 iowrite8(lcr, priv->membase + UART_LCR); 466 467 return 0; 468 } 469 470 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, 471 unsigned int flag) 472 { 473 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { 474 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", 475 __func__, flag); 476 return -EINVAL; 477 } 478 479 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); 480 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, 481 priv->membase + UART_FCR); 482 iowrite8(priv->fcr, priv->membase + UART_FCR); 483 484 return 0; 485 } 486 487 static int pch_uart_hal_set_fifo(struct eg20t_port *priv, 488 unsigned int dmamode, 489 unsigned int fifo_size, unsigned int trigger) 490 { 491 u8 fcr; 492 493 if (dmamode & ~PCH_UART_FCR_DMS) { 494 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", 495 __func__, dmamode); 496 return -EINVAL; 497 } 498 499 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { 500 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", 501 __func__, fifo_size); 502 return -EINVAL; 503 } 504 505 if (trigger & ~PCH_UART_FCR_RFTL) { 506 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", 507 __func__, trigger); 508 return -EINVAL; 509 } 510 511 switch (priv->fifo_size) { 512 case 256: 513 priv->trigger_level = 514 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 515 break; 516 case 64: 517 priv->trigger_level = 518 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 519 break; 520 case 16: 521 priv->trigger_level = 522 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 523 break; 524 default: 525 priv->trigger_level = 526 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 527 break; 528 } 529 fcr = 530 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; 531 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); 532 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, 533 priv->membase + UART_FCR); 534 iowrite8(fcr, priv->membase + UART_FCR); 535 priv->fcr = fcr; 536 537 return 0; 538 } 539 540 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) 541 { 542 unsigned int msr = ioread8(priv->membase + UART_MSR); 543 priv->dmsr = msr & PCH_UART_MSR_DELTA; 544 return (u8)msr; 545 } 546 547 static void pch_uart_hal_write(struct eg20t_port *priv, 548 const unsigned char *buf, int tx_size) 549 { 550 int i; 551 unsigned int thr; 552 553 for (i = 0; i < tx_size;) { 554 thr = buf[i++]; 555 iowrite8(thr, priv->membase + PCH_UART_THR); 556 } 557 } 558 559 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, 560 int rx_size) 561 { 562 int i; 563 u8 rbr, lsr; 564 struct uart_port *port = &priv->port; 565 566 lsr = ioread8(priv->membase + UART_LSR); 567 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); 568 i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI); 569 lsr = ioread8(priv->membase + UART_LSR)) { 570 rbr = ioread8(priv->membase + PCH_UART_RBR); 571 572 if (lsr & UART_LSR_BI) { 573 port->icount.brk++; 574 if (uart_handle_break(port)) 575 continue; 576 } 577 #ifdef SUPPORT_SYSRQ 578 if (port->sysrq) { 579 if (uart_handle_sysrq_char(port, rbr)) 580 continue; 581 } 582 #endif 583 584 buf[i++] = rbr; 585 } 586 return i; 587 } 588 589 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv) 590 { 591 return ioread8(priv->membase + UART_IIR) &\ 592 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP); 593 } 594 595 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) 596 { 597 return ioread8(priv->membase + UART_LSR); 598 } 599 600 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) 601 { 602 unsigned int lcr; 603 604 lcr = ioread8(priv->membase + UART_LCR); 605 if (on) 606 lcr |= PCH_UART_LCR_SB; 607 else 608 lcr &= ~PCH_UART_LCR_SB; 609 610 iowrite8(lcr, priv->membase + UART_LCR); 611 } 612 613 static int push_rx(struct eg20t_port *priv, const unsigned char *buf, 614 int size) 615 { 616 struct uart_port *port = &priv->port; 617 struct tty_port *tport = &port->state->port; 618 619 tty_insert_flip_string(tport, buf, size); 620 tty_flip_buffer_push(tport); 621 622 return 0; 623 } 624 625 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) 626 { 627 int ret = 0; 628 struct uart_port *port = &priv->port; 629 630 if (port->x_char) { 631 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n", 632 __func__, port->x_char, jiffies); 633 buf[0] = port->x_char; 634 port->x_char = 0; 635 ret = 1; 636 } 637 638 return ret; 639 } 640 641 static int dma_push_rx(struct eg20t_port *priv, int size) 642 { 643 struct tty_struct *tty; 644 int room; 645 struct uart_port *port = &priv->port; 646 struct tty_port *tport = &port->state->port; 647 648 port = &priv->port; 649 tty = tty_port_tty_get(tport); 650 if (!tty) { 651 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 652 return 0; 653 } 654 655 room = tty_buffer_request_room(tport, size); 656 657 if (room < size) 658 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 659 size - room); 660 if (!room) 661 return room; 662 663 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size); 664 665 port->icount.rx += room; 666 tty_kref_put(tty); 667 668 return room; 669 } 670 671 static void pch_free_dma(struct uart_port *port) 672 { 673 struct eg20t_port *priv; 674 priv = container_of(port, struct eg20t_port, port); 675 676 if (priv->chan_tx) { 677 dma_release_channel(priv->chan_tx); 678 priv->chan_tx = NULL; 679 } 680 if (priv->chan_rx) { 681 dma_release_channel(priv->chan_rx); 682 priv->chan_rx = NULL; 683 } 684 685 if (priv->rx_buf_dma) { 686 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt, 687 priv->rx_buf_dma); 688 priv->rx_buf_virt = NULL; 689 priv->rx_buf_dma = 0; 690 } 691 692 return; 693 } 694 695 static bool filter(struct dma_chan *chan, void *slave) 696 { 697 struct pch_dma_slave *param = slave; 698 699 if ((chan->chan_id == param->chan_id) && (param->dma_dev == 700 chan->device->dev)) { 701 chan->private = param; 702 return true; 703 } else { 704 return false; 705 } 706 } 707 708 static void pch_request_dma(struct uart_port *port) 709 { 710 dma_cap_mask_t mask; 711 struct dma_chan *chan; 712 struct pci_dev *dma_dev; 713 struct pch_dma_slave *param; 714 struct eg20t_port *priv = 715 container_of(port, struct eg20t_port, port); 716 dma_cap_zero(mask); 717 dma_cap_set(DMA_SLAVE, mask); 718 719 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number, 720 PCI_DEVFN(0xa, 0)); /* Get DMA's dev 721 information */ 722 /* Set Tx DMA */ 723 param = &priv->param_tx; 724 param->dma_dev = &dma_dev->dev; 725 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ 726 727 param->tx_reg = port->mapbase + UART_TX; 728 chan = dma_request_channel(mask, filter, param); 729 if (!chan) { 730 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", 731 __func__); 732 return; 733 } 734 priv->chan_tx = chan; 735 736 /* Set Rx DMA */ 737 param = &priv->param_rx; 738 param->dma_dev = &dma_dev->dev; 739 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ 740 741 param->rx_reg = port->mapbase + UART_RX; 742 chan = dma_request_channel(mask, filter, param); 743 if (!chan) { 744 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", 745 __func__); 746 dma_release_channel(priv->chan_tx); 747 priv->chan_tx = NULL; 748 return; 749 } 750 751 /* Get Consistent memory for DMA */ 752 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, 753 &priv->rx_buf_dma, GFP_KERNEL); 754 priv->chan_rx = chan; 755 } 756 757 static void pch_dma_rx_complete(void *arg) 758 { 759 struct eg20t_port *priv = arg; 760 struct uart_port *port = &priv->port; 761 int count; 762 763 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); 764 count = dma_push_rx(priv, priv->trigger_level); 765 if (count) 766 tty_flip_buffer_push(&port->state->port); 767 async_tx_ack(priv->desc_rx); 768 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | 769 PCH_UART_HAL_RX_ERR_INT); 770 } 771 772 static void pch_dma_tx_complete(void *arg) 773 { 774 struct eg20t_port *priv = arg; 775 struct uart_port *port = &priv->port; 776 struct circ_buf *xmit = &port->state->xmit; 777 struct scatterlist *sg = priv->sg_tx_p; 778 int i; 779 780 for (i = 0; i < priv->nent; i++, sg++) { 781 xmit->tail += sg_dma_len(sg); 782 port->icount.tx += sg_dma_len(sg); 783 } 784 xmit->tail &= UART_XMIT_SIZE - 1; 785 async_tx_ack(priv->desc_tx); 786 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE); 787 priv->tx_dma_use = 0; 788 priv->nent = 0; 789 kfree(priv->sg_tx_p); 790 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 791 } 792 793 static int pop_tx(struct eg20t_port *priv, int size) 794 { 795 int count = 0; 796 struct uart_port *port = &priv->port; 797 struct circ_buf *xmit = &port->state->xmit; 798 799 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size) 800 goto pop_tx_end; 801 802 do { 803 int cnt_to_end = 804 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 805 int sz = min(size - count, cnt_to_end); 806 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz); 807 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1); 808 count += sz; 809 } while (!uart_circ_empty(xmit) && count < size); 810 811 pop_tx_end: 812 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n", 813 count, size - count, jiffies); 814 815 return count; 816 } 817 818 static int handle_rx_to(struct eg20t_port *priv) 819 { 820 struct pch_uart_buffer *buf; 821 int rx_size; 822 int ret; 823 if (!priv->start_rx) { 824 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | 825 PCH_UART_HAL_RX_ERR_INT); 826 return 0; 827 } 828 buf = &priv->rxbuf; 829 do { 830 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); 831 ret = push_rx(priv, buf->buf, rx_size); 832 if (ret) 833 return 0; 834 } while (rx_size == buf->size); 835 836 return PCH_UART_HANDLED_RX_INT; 837 } 838 839 static int handle_rx(struct eg20t_port *priv) 840 { 841 return handle_rx_to(priv); 842 } 843 844 static int dma_handle_rx(struct eg20t_port *priv) 845 { 846 struct uart_port *port = &priv->port; 847 struct dma_async_tx_descriptor *desc; 848 struct scatterlist *sg; 849 850 priv = container_of(port, struct eg20t_port, port); 851 sg = &priv->sg_rx; 852 853 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ 854 855 sg_dma_len(sg) = priv->trigger_level; 856 857 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), 858 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt & 859 ~PAGE_MASK); 860 861 sg_dma_address(sg) = priv->rx_buf_dma; 862 863 desc = dmaengine_prep_slave_sg(priv->chan_rx, 864 sg, 1, DMA_DEV_TO_MEM, 865 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 866 867 if (!desc) 868 return 0; 869 870 priv->desc_rx = desc; 871 desc->callback = pch_dma_rx_complete; 872 desc->callback_param = priv; 873 desc->tx_submit(desc); 874 dma_async_issue_pending(priv->chan_rx); 875 876 return PCH_UART_HANDLED_RX_INT; 877 } 878 879 static unsigned int handle_tx(struct eg20t_port *priv) 880 { 881 struct uart_port *port = &priv->port; 882 struct circ_buf *xmit = &port->state->xmit; 883 int fifo_size; 884 int tx_size; 885 int size; 886 int tx_empty; 887 888 if (!priv->start_tx) { 889 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 890 __func__, jiffies); 891 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 892 priv->tx_empty = 1; 893 return 0; 894 } 895 896 fifo_size = max(priv->fifo_size, 1); 897 tx_empty = 1; 898 if (pop_tx_x(priv, xmit->buf)) { 899 pch_uart_hal_write(priv, xmit->buf, 1); 900 port->icount.tx++; 901 tx_empty = 0; 902 fifo_size--; 903 } 904 size = min(xmit->head - xmit->tail, fifo_size); 905 if (size < 0) 906 size = fifo_size; 907 908 tx_size = pop_tx(priv, size); 909 if (tx_size > 0) { 910 port->icount.tx += tx_size; 911 tx_empty = 0; 912 } 913 914 priv->tx_empty = tx_empty; 915 916 if (tx_empty) { 917 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 918 uart_write_wakeup(port); 919 } 920 921 return PCH_UART_HANDLED_TX_INT; 922 } 923 924 static unsigned int dma_handle_tx(struct eg20t_port *priv) 925 { 926 struct uart_port *port = &priv->port; 927 struct circ_buf *xmit = &port->state->xmit; 928 struct scatterlist *sg; 929 int nent; 930 int fifo_size; 931 int tx_empty; 932 struct dma_async_tx_descriptor *desc; 933 int num; 934 int i; 935 int bytes; 936 int size; 937 int rem; 938 939 if (!priv->start_tx) { 940 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 941 __func__, jiffies); 942 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 943 priv->tx_empty = 1; 944 return 0; 945 } 946 947 if (priv->tx_dma_use) { 948 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", 949 __func__, jiffies); 950 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 951 priv->tx_empty = 1; 952 return 0; 953 } 954 955 fifo_size = max(priv->fifo_size, 1); 956 tx_empty = 1; 957 if (pop_tx_x(priv, xmit->buf)) { 958 pch_uart_hal_write(priv, xmit->buf, 1); 959 port->icount.tx++; 960 tx_empty = 0; 961 fifo_size--; 962 } 963 964 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail, 965 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head, 966 xmit->tail, UART_XMIT_SIZE)); 967 if (!bytes) { 968 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); 969 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 970 uart_write_wakeup(port); 971 return 0; 972 } 973 974 if (bytes > fifo_size) { 975 num = bytes / fifo_size + 1; 976 size = fifo_size; 977 rem = bytes % fifo_size; 978 } else { 979 num = 1; 980 size = bytes; 981 rem = bytes; 982 } 983 984 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", 985 __func__, num, size, rem); 986 987 priv->tx_dma_use = 1; 988 989 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); 990 if (!priv->sg_tx_p) { 991 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__); 992 return 0; 993 } 994 995 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ 996 sg = priv->sg_tx_p; 997 998 for (i = 0; i < num; i++, sg++) { 999 if (i == (num - 1)) 1000 sg_set_page(sg, virt_to_page(xmit->buf), 1001 rem, fifo_size * i); 1002 else 1003 sg_set_page(sg, virt_to_page(xmit->buf), 1004 size, fifo_size * i); 1005 } 1006 1007 sg = priv->sg_tx_p; 1008 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); 1009 if (!nent) { 1010 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); 1011 return 0; 1012 } 1013 priv->nent = nent; 1014 1015 for (i = 0; i < nent; i++, sg++) { 1016 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + 1017 fifo_size * i; 1018 sg_dma_address(sg) = (sg_dma_address(sg) & 1019 ~(UART_XMIT_SIZE - 1)) + sg->offset; 1020 if (i == (nent - 1)) 1021 sg_dma_len(sg) = rem; 1022 else 1023 sg_dma_len(sg) = size; 1024 } 1025 1026 desc = dmaengine_prep_slave_sg(priv->chan_tx, 1027 priv->sg_tx_p, nent, DMA_MEM_TO_DEV, 1028 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1029 if (!desc) { 1030 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n", 1031 __func__); 1032 return 0; 1033 } 1034 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); 1035 priv->desc_tx = desc; 1036 desc->callback = pch_dma_tx_complete; 1037 desc->callback_param = priv; 1038 1039 desc->tx_submit(desc); 1040 1041 dma_async_issue_pending(priv->chan_tx); 1042 1043 return PCH_UART_HANDLED_TX_INT; 1044 } 1045 1046 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) 1047 { 1048 struct uart_port *port = &priv->port; 1049 struct tty_struct *tty = tty_port_tty_get(&port->state->port); 1050 char *error_msg[5] = {}; 1051 int i = 0; 1052 1053 if (lsr & PCH_UART_LSR_ERR) 1054 error_msg[i++] = "Error data in FIFO\n"; 1055 1056 if (lsr & UART_LSR_FE) { 1057 port->icount.frame++; 1058 error_msg[i++] = " Framing Error\n"; 1059 } 1060 1061 if (lsr & UART_LSR_PE) { 1062 port->icount.parity++; 1063 error_msg[i++] = " Parity Error\n"; 1064 } 1065 1066 if (lsr & UART_LSR_OE) { 1067 port->icount.overrun++; 1068 error_msg[i++] = " Overrun Error\n"; 1069 } 1070 1071 if (tty == NULL) { 1072 for (i = 0; error_msg[i] != NULL; i++) 1073 dev_err(&priv->pdev->dev, error_msg[i]); 1074 } 1075 } 1076 1077 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) 1078 { 1079 struct eg20t_port *priv = dev_id; 1080 unsigned int handled; 1081 u8 lsr; 1082 int ret = 0; 1083 unsigned char iid; 1084 unsigned long flags; 1085 int next = 1; 1086 u8 msr; 1087 1088 spin_lock_irqsave(&priv->lock, flags); 1089 handled = 0; 1090 while (next) { 1091 iid = pch_uart_hal_get_iid(priv); 1092 if (iid & PCH_UART_IIR_IP) /* No Interrupt */ 1093 break; 1094 switch (iid) { 1095 case PCH_UART_IID_RLS: /* Receiver Line Status */ 1096 lsr = pch_uart_hal_get_line_status(priv); 1097 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | 1098 UART_LSR_PE | UART_LSR_OE)) { 1099 pch_uart_err_ir(priv, lsr); 1100 ret = PCH_UART_HANDLED_RX_ERR_INT; 1101 } else { 1102 ret = PCH_UART_HANDLED_LS_INT; 1103 } 1104 break; 1105 case PCH_UART_IID_RDR: /* Received Data Ready */ 1106 if (priv->use_dma) { 1107 pch_uart_hal_disable_interrupt(priv, 1108 PCH_UART_HAL_RX_INT | 1109 PCH_UART_HAL_RX_ERR_INT); 1110 ret = dma_handle_rx(priv); 1111 if (!ret) 1112 pch_uart_hal_enable_interrupt(priv, 1113 PCH_UART_HAL_RX_INT | 1114 PCH_UART_HAL_RX_ERR_INT); 1115 } else { 1116 ret = handle_rx(priv); 1117 } 1118 break; 1119 case PCH_UART_IID_RDR_TO: /* Received Data Ready 1120 (FIFO Timeout) */ 1121 ret = handle_rx_to(priv); 1122 break; 1123 case PCH_UART_IID_THRE: /* Transmitter Holding Register 1124 Empty */ 1125 if (priv->use_dma) 1126 ret = dma_handle_tx(priv); 1127 else 1128 ret = handle_tx(priv); 1129 break; 1130 case PCH_UART_IID_MS: /* Modem Status */ 1131 msr = pch_uart_hal_get_modem(priv); 1132 next = 0; /* MS ir prioirty is the lowest. So, MS ir 1133 means final interrupt */ 1134 if ((msr & UART_MSR_ANY_DELTA) == 0) 1135 break; 1136 ret |= PCH_UART_HANDLED_MS_INT; 1137 break; 1138 default: /* Never junp to this label */ 1139 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__, 1140 iid, jiffies); 1141 ret = -1; 1142 next = 0; 1143 break; 1144 } 1145 handled |= (unsigned int)ret; 1146 } 1147 1148 spin_unlock_irqrestore(&priv->lock, flags); 1149 return IRQ_RETVAL(handled); 1150 } 1151 1152 /* This function tests whether the transmitter fifo and shifter for the port 1153 described by 'port' is empty. */ 1154 static unsigned int pch_uart_tx_empty(struct uart_port *port) 1155 { 1156 struct eg20t_port *priv; 1157 1158 priv = container_of(port, struct eg20t_port, port); 1159 if (priv->tx_empty) 1160 return TIOCSER_TEMT; 1161 else 1162 return 0; 1163 } 1164 1165 /* Returns the current state of modem control inputs. */ 1166 static unsigned int pch_uart_get_mctrl(struct uart_port *port) 1167 { 1168 struct eg20t_port *priv; 1169 u8 modem; 1170 unsigned int ret = 0; 1171 1172 priv = container_of(port, struct eg20t_port, port); 1173 modem = pch_uart_hal_get_modem(priv); 1174 1175 if (modem & UART_MSR_DCD) 1176 ret |= TIOCM_CAR; 1177 1178 if (modem & UART_MSR_RI) 1179 ret |= TIOCM_RNG; 1180 1181 if (modem & UART_MSR_DSR) 1182 ret |= TIOCM_DSR; 1183 1184 if (modem & UART_MSR_CTS) 1185 ret |= TIOCM_CTS; 1186 1187 return ret; 1188 } 1189 1190 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1191 { 1192 u32 mcr = 0; 1193 struct eg20t_port *priv = container_of(port, struct eg20t_port, port); 1194 1195 if (mctrl & TIOCM_DTR) 1196 mcr |= UART_MCR_DTR; 1197 if (mctrl & TIOCM_RTS) 1198 mcr |= UART_MCR_RTS; 1199 if (mctrl & TIOCM_LOOP) 1200 mcr |= UART_MCR_LOOP; 1201 1202 if (priv->mcr & UART_MCR_AFE) 1203 mcr |= UART_MCR_AFE; 1204 1205 if (mctrl) 1206 iowrite8(mcr, priv->membase + UART_MCR); 1207 } 1208 1209 static void pch_uart_stop_tx(struct uart_port *port) 1210 { 1211 struct eg20t_port *priv; 1212 priv = container_of(port, struct eg20t_port, port); 1213 priv->start_tx = 0; 1214 priv->tx_dma_use = 0; 1215 } 1216 1217 static void pch_uart_start_tx(struct uart_port *port) 1218 { 1219 struct eg20t_port *priv; 1220 1221 priv = container_of(port, struct eg20t_port, port); 1222 1223 if (priv->use_dma) { 1224 if (priv->tx_dma_use) { 1225 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", 1226 __func__); 1227 return; 1228 } 1229 } 1230 1231 priv->start_tx = 1; 1232 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 1233 } 1234 1235 static void pch_uart_stop_rx(struct uart_port *port) 1236 { 1237 struct eg20t_port *priv; 1238 priv = container_of(port, struct eg20t_port, port); 1239 priv->start_rx = 0; 1240 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | 1241 PCH_UART_HAL_RX_ERR_INT); 1242 } 1243 1244 /* Enable the modem status interrupts. */ 1245 static void pch_uart_enable_ms(struct uart_port *port) 1246 { 1247 struct eg20t_port *priv; 1248 priv = container_of(port, struct eg20t_port, port); 1249 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); 1250 } 1251 1252 /* Control the transmission of a break signal. */ 1253 static void pch_uart_break_ctl(struct uart_port *port, int ctl) 1254 { 1255 struct eg20t_port *priv; 1256 unsigned long flags; 1257 1258 priv = container_of(port, struct eg20t_port, port); 1259 spin_lock_irqsave(&priv->lock, flags); 1260 pch_uart_hal_set_break(priv, ctl); 1261 spin_unlock_irqrestore(&priv->lock, flags); 1262 } 1263 1264 /* Grab any interrupt resources and initialise any low level driver state. */ 1265 static int pch_uart_startup(struct uart_port *port) 1266 { 1267 struct eg20t_port *priv; 1268 int ret; 1269 int fifo_size; 1270 int trigger_level; 1271 1272 priv = container_of(port, struct eg20t_port, port); 1273 priv->tx_empty = 1; 1274 1275 if (port->uartclk) 1276 priv->uartclk = port->uartclk; 1277 else 1278 port->uartclk = priv->uartclk; 1279 1280 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1281 ret = pch_uart_hal_set_line(priv, default_baud, 1282 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, 1283 PCH_UART_HAL_STB1); 1284 if (ret) 1285 return ret; 1286 1287 switch (priv->fifo_size) { 1288 case 256: 1289 fifo_size = PCH_UART_HAL_FIFO256; 1290 break; 1291 case 64: 1292 fifo_size = PCH_UART_HAL_FIFO64; 1293 break; 1294 case 16: 1295 fifo_size = PCH_UART_HAL_FIFO16; 1296 break; 1297 case 1: 1298 default: 1299 fifo_size = PCH_UART_HAL_FIFO_DIS; 1300 break; 1301 } 1302 1303 switch (priv->trigger) { 1304 case PCH_UART_HAL_TRIGGER1: 1305 trigger_level = 1; 1306 break; 1307 case PCH_UART_HAL_TRIGGER_L: 1308 trigger_level = priv->fifo_size / 4; 1309 break; 1310 case PCH_UART_HAL_TRIGGER_M: 1311 trigger_level = priv->fifo_size / 2; 1312 break; 1313 case PCH_UART_HAL_TRIGGER_H: 1314 default: 1315 trigger_level = priv->fifo_size - (priv->fifo_size / 8); 1316 break; 1317 } 1318 1319 priv->trigger_level = trigger_level; 1320 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1321 fifo_size, priv->trigger); 1322 if (ret < 0) 1323 return ret; 1324 1325 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, 1326 KBUILD_MODNAME, priv); 1327 if (ret < 0) 1328 return ret; 1329 1330 if (priv->use_dma) 1331 pch_request_dma(port); 1332 1333 priv->start_rx = 1; 1334 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | 1335 PCH_UART_HAL_RX_ERR_INT); 1336 uart_update_timeout(port, CS8, default_baud); 1337 1338 return 0; 1339 } 1340 1341 static void pch_uart_shutdown(struct uart_port *port) 1342 { 1343 struct eg20t_port *priv; 1344 int ret; 1345 1346 priv = container_of(port, struct eg20t_port, port); 1347 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1348 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); 1349 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1350 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); 1351 if (ret) 1352 dev_err(priv->port.dev, 1353 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); 1354 1355 pch_free_dma(port); 1356 1357 free_irq(priv->port.irq, priv); 1358 } 1359 1360 /* Change the port parameters, including word length, parity, stop 1361 *bits. Update read_status_mask and ignore_status_mask to indicate 1362 *the types of events we are interested in receiving. */ 1363 static void pch_uart_set_termios(struct uart_port *port, 1364 struct ktermios *termios, struct ktermios *old) 1365 { 1366 int baud; 1367 int rtn; 1368 unsigned int parity, bits, stb; 1369 struct eg20t_port *priv; 1370 unsigned long flags; 1371 1372 priv = container_of(port, struct eg20t_port, port); 1373 switch (termios->c_cflag & CSIZE) { 1374 case CS5: 1375 bits = PCH_UART_HAL_5BIT; 1376 break; 1377 case CS6: 1378 bits = PCH_UART_HAL_6BIT; 1379 break; 1380 case CS7: 1381 bits = PCH_UART_HAL_7BIT; 1382 break; 1383 default: /* CS8 */ 1384 bits = PCH_UART_HAL_8BIT; 1385 break; 1386 } 1387 if (termios->c_cflag & CSTOPB) 1388 stb = PCH_UART_HAL_STB2; 1389 else 1390 stb = PCH_UART_HAL_STB1; 1391 1392 if (termios->c_cflag & PARENB) { 1393 if (termios->c_cflag & PARODD) 1394 parity = PCH_UART_HAL_PARITY_ODD; 1395 else 1396 parity = PCH_UART_HAL_PARITY_EVEN; 1397 1398 } else 1399 parity = PCH_UART_HAL_PARITY_NONE; 1400 1401 /* Only UART0 has auto hardware flow function */ 1402 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) 1403 priv->mcr |= UART_MCR_AFE; 1404 else 1405 priv->mcr &= ~UART_MCR_AFE; 1406 1407 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 1408 1409 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1410 1411 spin_lock_irqsave(&priv->lock, flags); 1412 spin_lock(&port->lock); 1413 1414 uart_update_timeout(port, termios->c_cflag, baud); 1415 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); 1416 if (rtn) 1417 goto out; 1418 1419 pch_uart_set_mctrl(&priv->port, priv->port.mctrl); 1420 /* Don't rewrite B0 */ 1421 if (tty_termios_baud_rate(termios)) 1422 tty_termios_encode_baud_rate(termios, baud, baud); 1423 1424 out: 1425 spin_unlock(&port->lock); 1426 spin_unlock_irqrestore(&priv->lock, flags); 1427 } 1428 1429 static const char *pch_uart_type(struct uart_port *port) 1430 { 1431 return KBUILD_MODNAME; 1432 } 1433 1434 static void pch_uart_release_port(struct uart_port *port) 1435 { 1436 struct eg20t_port *priv; 1437 1438 priv = container_of(port, struct eg20t_port, port); 1439 pci_iounmap(priv->pdev, priv->membase); 1440 pci_release_regions(priv->pdev); 1441 } 1442 1443 static int pch_uart_request_port(struct uart_port *port) 1444 { 1445 struct eg20t_port *priv; 1446 int ret; 1447 void __iomem *membase; 1448 1449 priv = container_of(port, struct eg20t_port, port); 1450 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); 1451 if (ret < 0) 1452 return -EBUSY; 1453 1454 membase = pci_iomap(priv->pdev, 1, 0); 1455 if (!membase) { 1456 pci_release_regions(priv->pdev); 1457 return -EBUSY; 1458 } 1459 priv->membase = port->membase = membase; 1460 1461 return 0; 1462 } 1463 1464 static void pch_uart_config_port(struct uart_port *port, int type) 1465 { 1466 struct eg20t_port *priv; 1467 1468 priv = container_of(port, struct eg20t_port, port); 1469 if (type & UART_CONFIG_TYPE) { 1470 port->type = priv->port_type; 1471 pch_uart_request_port(port); 1472 } 1473 } 1474 1475 static int pch_uart_verify_port(struct uart_port *port, 1476 struct serial_struct *serinfo) 1477 { 1478 struct eg20t_port *priv; 1479 1480 priv = container_of(port, struct eg20t_port, port); 1481 if (serinfo->flags & UPF_LOW_LATENCY) { 1482 dev_info(priv->port.dev, 1483 "PCH UART : Use PIO Mode (without DMA)\n"); 1484 priv->use_dma = 0; 1485 serinfo->flags &= ~UPF_LOW_LATENCY; 1486 } else { 1487 #ifndef CONFIG_PCH_DMA 1488 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", 1489 __func__); 1490 return -EOPNOTSUPP; 1491 #endif 1492 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n"); 1493 if (!priv->use_dma) 1494 pch_request_dma(port); 1495 priv->use_dma = 1; 1496 } 1497 1498 return 0; 1499 } 1500 1501 /* 1502 * Wait for transmitter & holding register to empty 1503 */ 1504 static void wait_for_xmitr(struct eg20t_port *up, int bits) 1505 { 1506 unsigned int status, tmout = 10000; 1507 1508 /* Wait up to 10ms for the character(s) to be sent. */ 1509 for (;;) { 1510 status = ioread8(up->membase + UART_LSR); 1511 1512 if ((status & bits) == bits) 1513 break; 1514 if (--tmout == 0) 1515 break; 1516 udelay(1); 1517 } 1518 1519 /* Wait up to 1s for flow control if necessary */ 1520 if (up->port.flags & UPF_CONS_FLOW) { 1521 unsigned int tmout; 1522 for (tmout = 1000000; tmout; tmout--) { 1523 unsigned int msr = ioread8(up->membase + UART_MSR); 1524 if (msr & UART_MSR_CTS) 1525 break; 1526 udelay(1); 1527 touch_nmi_watchdog(); 1528 } 1529 } 1530 } 1531 1532 #ifdef CONFIG_CONSOLE_POLL 1533 /* 1534 * Console polling routines for communicate via uart while 1535 * in an interrupt or debug context. 1536 */ 1537 static int pch_uart_get_poll_char(struct uart_port *port) 1538 { 1539 struct eg20t_port *priv = 1540 container_of(port, struct eg20t_port, port); 1541 u8 lsr = ioread8(priv->membase + UART_LSR); 1542 1543 if (!(lsr & UART_LSR_DR)) 1544 return NO_POLL_CHAR; 1545 1546 return ioread8(priv->membase + PCH_UART_RBR); 1547 } 1548 1549 1550 static void pch_uart_put_poll_char(struct uart_port *port, 1551 unsigned char c) 1552 { 1553 unsigned int ier; 1554 struct eg20t_port *priv = 1555 container_of(port, struct eg20t_port, port); 1556 1557 /* 1558 * First save the IER then disable the interrupts 1559 */ 1560 ier = ioread8(priv->membase + UART_IER); 1561 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1562 1563 wait_for_xmitr(priv, UART_LSR_THRE); 1564 /* 1565 * Send the character out. 1566 * If a LF, also do CR... 1567 */ 1568 iowrite8(c, priv->membase + PCH_UART_THR); 1569 if (c == 10) { 1570 wait_for_xmitr(priv, UART_LSR_THRE); 1571 iowrite8(13, priv->membase + PCH_UART_THR); 1572 } 1573 1574 /* 1575 * Finally, wait for transmitter to become empty 1576 * and restore the IER 1577 */ 1578 wait_for_xmitr(priv, BOTH_EMPTY); 1579 iowrite8(ier, priv->membase + UART_IER); 1580 } 1581 #endif /* CONFIG_CONSOLE_POLL */ 1582 1583 static struct uart_ops pch_uart_ops = { 1584 .tx_empty = pch_uart_tx_empty, 1585 .set_mctrl = pch_uart_set_mctrl, 1586 .get_mctrl = pch_uart_get_mctrl, 1587 .stop_tx = pch_uart_stop_tx, 1588 .start_tx = pch_uart_start_tx, 1589 .stop_rx = pch_uart_stop_rx, 1590 .enable_ms = pch_uart_enable_ms, 1591 .break_ctl = pch_uart_break_ctl, 1592 .startup = pch_uart_startup, 1593 .shutdown = pch_uart_shutdown, 1594 .set_termios = pch_uart_set_termios, 1595 /* .pm = pch_uart_pm, Not supported yet */ 1596 /* .set_wake = pch_uart_set_wake, Not supported yet */ 1597 .type = pch_uart_type, 1598 .release_port = pch_uart_release_port, 1599 .request_port = pch_uart_request_port, 1600 .config_port = pch_uart_config_port, 1601 .verify_port = pch_uart_verify_port, 1602 #ifdef CONFIG_CONSOLE_POLL 1603 .poll_get_char = pch_uart_get_poll_char, 1604 .poll_put_char = pch_uart_put_poll_char, 1605 #endif 1606 }; 1607 1608 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1609 1610 static void pch_console_putchar(struct uart_port *port, int ch) 1611 { 1612 struct eg20t_port *priv = 1613 container_of(port, struct eg20t_port, port); 1614 1615 wait_for_xmitr(priv, UART_LSR_THRE); 1616 iowrite8(ch, priv->membase + PCH_UART_THR); 1617 } 1618 1619 /* 1620 * Print a string to the serial port trying not to disturb 1621 * any possible real use of the port... 1622 * 1623 * The console_lock must be held when we get here. 1624 */ 1625 static void 1626 pch_console_write(struct console *co, const char *s, unsigned int count) 1627 { 1628 struct eg20t_port *priv; 1629 unsigned long flags; 1630 int priv_locked = 1; 1631 int port_locked = 1; 1632 u8 ier; 1633 1634 priv = pch_uart_ports[co->index]; 1635 1636 touch_nmi_watchdog(); 1637 1638 local_irq_save(flags); 1639 if (priv->port.sysrq) { 1640 /* call to uart_handle_sysrq_char already took the priv lock */ 1641 priv_locked = 0; 1642 /* serial8250_handle_port() already took the port lock */ 1643 port_locked = 0; 1644 } else if (oops_in_progress) { 1645 priv_locked = spin_trylock(&priv->lock); 1646 port_locked = spin_trylock(&priv->port.lock); 1647 } else { 1648 spin_lock(&priv->lock); 1649 spin_lock(&priv->port.lock); 1650 } 1651 1652 /* 1653 * First save the IER then disable the interrupts 1654 */ 1655 ier = ioread8(priv->membase + UART_IER); 1656 1657 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1658 1659 uart_console_write(&priv->port, s, count, pch_console_putchar); 1660 1661 /* 1662 * Finally, wait for transmitter to become empty 1663 * and restore the IER 1664 */ 1665 wait_for_xmitr(priv, BOTH_EMPTY); 1666 iowrite8(ier, priv->membase + UART_IER); 1667 1668 if (port_locked) 1669 spin_unlock(&priv->port.lock); 1670 if (priv_locked) 1671 spin_unlock(&priv->lock); 1672 local_irq_restore(flags); 1673 } 1674 1675 static int __init pch_console_setup(struct console *co, char *options) 1676 { 1677 struct uart_port *port; 1678 int baud = default_baud; 1679 int bits = 8; 1680 int parity = 'n'; 1681 int flow = 'n'; 1682 1683 /* 1684 * Check whether an invalid uart number has been specified, and 1685 * if so, search for the first available port that does have 1686 * console support. 1687 */ 1688 if (co->index >= PCH_UART_NR) 1689 co->index = 0; 1690 port = &pch_uart_ports[co->index]->port; 1691 1692 if (!port || (!port->iobase && !port->membase)) 1693 return -ENODEV; 1694 1695 port->uartclk = pch_uart_get_uartclk(); 1696 1697 if (options) 1698 uart_parse_options(options, &baud, &parity, &bits, &flow); 1699 1700 return uart_set_options(port, co, baud, parity, bits, flow); 1701 } 1702 1703 static struct uart_driver pch_uart_driver; 1704 1705 static struct console pch_console = { 1706 .name = PCH_UART_DRIVER_DEVICE, 1707 .write = pch_console_write, 1708 .device = uart_console_device, 1709 .setup = pch_console_setup, 1710 .flags = CON_PRINTBUFFER | CON_ANYTIME, 1711 .index = -1, 1712 .data = &pch_uart_driver, 1713 }; 1714 1715 #define PCH_CONSOLE (&pch_console) 1716 #else 1717 #define PCH_CONSOLE NULL 1718 #endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */ 1719 1720 static struct uart_driver pch_uart_driver = { 1721 .owner = THIS_MODULE, 1722 .driver_name = KBUILD_MODNAME, 1723 .dev_name = PCH_UART_DRIVER_DEVICE, 1724 .major = 0, 1725 .minor = 0, 1726 .nr = PCH_UART_NR, 1727 .cons = PCH_CONSOLE, 1728 }; 1729 1730 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, 1731 const struct pci_device_id *id) 1732 { 1733 struct eg20t_port *priv; 1734 int ret; 1735 unsigned int iobase; 1736 unsigned int mapbase; 1737 unsigned char *rxbuf; 1738 int fifosize; 1739 int port_type; 1740 struct pch_uart_driver_data *board; 1741 char name[32]; /* for debugfs file name */ 1742 1743 board = &drv_dat[id->driver_data]; 1744 port_type = board->port_type; 1745 1746 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); 1747 if (priv == NULL) 1748 goto init_port_alloc_err; 1749 1750 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); 1751 if (!rxbuf) 1752 goto init_port_free_txbuf; 1753 1754 switch (port_type) { 1755 case PORT_UNKNOWN: 1756 fifosize = 256; /* EG20T/ML7213: UART0 */ 1757 break; 1758 case PORT_8250: 1759 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ 1760 break; 1761 default: 1762 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); 1763 goto init_port_hal_free; 1764 } 1765 1766 pci_enable_msi(pdev); 1767 pci_set_master(pdev); 1768 1769 spin_lock_init(&priv->lock); 1770 1771 iobase = pci_resource_start(pdev, 0); 1772 mapbase = pci_resource_start(pdev, 1); 1773 priv->mapbase = mapbase; 1774 priv->iobase = iobase; 1775 priv->pdev = pdev; 1776 priv->tx_empty = 1; 1777 priv->rxbuf.buf = rxbuf; 1778 priv->rxbuf.size = PAGE_SIZE; 1779 1780 priv->fifo_size = fifosize; 1781 priv->uartclk = pch_uart_get_uartclk(); 1782 priv->port_type = PORT_MAX_8250 + port_type + 1; 1783 priv->port.dev = &pdev->dev; 1784 priv->port.iobase = iobase; 1785 priv->port.membase = NULL; 1786 priv->port.mapbase = mapbase; 1787 priv->port.irq = pdev->irq; 1788 priv->port.iotype = UPIO_PORT; 1789 priv->port.ops = &pch_uart_ops; 1790 priv->port.flags = UPF_BOOT_AUTOCONF; 1791 priv->port.fifosize = fifosize; 1792 priv->port.line = board->line_no; 1793 priv->trigger = PCH_UART_HAL_TRIGGER_M; 1794 1795 spin_lock_init(&priv->port.lock); 1796 1797 pci_set_drvdata(pdev, priv); 1798 priv->trigger_level = 1; 1799 priv->fcr = 0; 1800 1801 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1802 pch_uart_ports[board->line_no] = priv; 1803 #endif 1804 ret = uart_add_one_port(&pch_uart_driver, &priv->port); 1805 if (ret < 0) 1806 goto init_port_hal_free; 1807 1808 #ifdef CONFIG_DEBUG_FS 1809 snprintf(name, sizeof(name), "uart%d_regs", board->line_no); 1810 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO, 1811 NULL, priv, &port_regs_ops); 1812 #endif 1813 1814 return priv; 1815 1816 init_port_hal_free: 1817 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1818 pch_uart_ports[board->line_no] = NULL; 1819 #endif 1820 free_page((unsigned long)rxbuf); 1821 init_port_free_txbuf: 1822 kfree(priv); 1823 init_port_alloc_err: 1824 1825 return NULL; 1826 } 1827 1828 static void pch_uart_exit_port(struct eg20t_port *priv) 1829 { 1830 1831 #ifdef CONFIG_DEBUG_FS 1832 if (priv->debugfs) 1833 debugfs_remove(priv->debugfs); 1834 #endif 1835 uart_remove_one_port(&pch_uart_driver, &priv->port); 1836 pci_set_drvdata(priv->pdev, NULL); 1837 free_page((unsigned long)priv->rxbuf.buf); 1838 } 1839 1840 static void pch_uart_pci_remove(struct pci_dev *pdev) 1841 { 1842 struct eg20t_port *priv = pci_get_drvdata(pdev); 1843 1844 pci_disable_msi(pdev); 1845 1846 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1847 pch_uart_ports[priv->port.line] = NULL; 1848 #endif 1849 pch_uart_exit_port(priv); 1850 pci_disable_device(pdev); 1851 kfree(priv); 1852 return; 1853 } 1854 #ifdef CONFIG_PM 1855 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1856 { 1857 struct eg20t_port *priv = pci_get_drvdata(pdev); 1858 1859 uart_suspend_port(&pch_uart_driver, &priv->port); 1860 1861 pci_save_state(pdev); 1862 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1863 return 0; 1864 } 1865 1866 static int pch_uart_pci_resume(struct pci_dev *pdev) 1867 { 1868 struct eg20t_port *priv = pci_get_drvdata(pdev); 1869 int ret; 1870 1871 pci_set_power_state(pdev, PCI_D0); 1872 pci_restore_state(pdev); 1873 1874 ret = pci_enable_device(pdev); 1875 if (ret) { 1876 dev_err(&pdev->dev, 1877 "%s-pci_enable_device failed(ret=%d) ", __func__, ret); 1878 return ret; 1879 } 1880 1881 uart_resume_port(&pch_uart_driver, &priv->port); 1882 1883 return 0; 1884 } 1885 #else 1886 #define pch_uart_pci_suspend NULL 1887 #define pch_uart_pci_resume NULL 1888 #endif 1889 1890 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = { 1891 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), 1892 .driver_data = pch_et20t_uart0}, 1893 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), 1894 .driver_data = pch_et20t_uart1}, 1895 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), 1896 .driver_data = pch_et20t_uart2}, 1897 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), 1898 .driver_data = pch_et20t_uart3}, 1899 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), 1900 .driver_data = pch_ml7213_uart0}, 1901 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), 1902 .driver_data = pch_ml7213_uart1}, 1903 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), 1904 .driver_data = pch_ml7213_uart2}, 1905 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C), 1906 .driver_data = pch_ml7223_uart0}, 1907 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D), 1908 .driver_data = pch_ml7223_uart1}, 1909 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811), 1910 .driver_data = pch_ml7831_uart0}, 1911 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812), 1912 .driver_data = pch_ml7831_uart1}, 1913 {0,}, 1914 }; 1915 1916 static int pch_uart_pci_probe(struct pci_dev *pdev, 1917 const struct pci_device_id *id) 1918 { 1919 int ret; 1920 struct eg20t_port *priv; 1921 1922 ret = pci_enable_device(pdev); 1923 if (ret < 0) 1924 goto probe_error; 1925 1926 priv = pch_uart_init_port(pdev, id); 1927 if (!priv) { 1928 ret = -EBUSY; 1929 goto probe_disable_device; 1930 } 1931 pci_set_drvdata(pdev, priv); 1932 1933 return ret; 1934 1935 probe_disable_device: 1936 pci_disable_msi(pdev); 1937 pci_disable_device(pdev); 1938 probe_error: 1939 return ret; 1940 } 1941 1942 static struct pci_driver pch_uart_pci_driver = { 1943 .name = "pch_uart", 1944 .id_table = pch_uart_pci_id, 1945 .probe = pch_uart_pci_probe, 1946 .remove = pch_uart_pci_remove, 1947 .suspend = pch_uart_pci_suspend, 1948 .resume = pch_uart_pci_resume, 1949 }; 1950 1951 static int __init pch_uart_module_init(void) 1952 { 1953 int ret; 1954 1955 /* register as UART driver */ 1956 ret = uart_register_driver(&pch_uart_driver); 1957 if (ret < 0) 1958 return ret; 1959 1960 /* register as PCI driver */ 1961 ret = pci_register_driver(&pch_uart_pci_driver); 1962 if (ret < 0) 1963 uart_unregister_driver(&pch_uart_driver); 1964 1965 return ret; 1966 } 1967 module_init(pch_uart_module_init); 1968 1969 static void __exit pch_uart_module_exit(void) 1970 { 1971 pci_unregister_driver(&pch_uart_pci_driver); 1972 uart_unregister_driver(&pch_uart_driver); 1973 } 1974 module_exit(pch_uart_module_exit); 1975 1976 MODULE_LICENSE("GPL v2"); 1977 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); 1978 module_param(default_baud, uint, S_IRUGO); 1979 MODULE_PARM_DESC(default_baud, 1980 "Default BAUD for initial driver state and console (default 9600)"); 1981 module_param(user_uartclk, uint, S_IRUGO); 1982 MODULE_PARM_DESC(user_uartclk, 1983 "Override UART default or board specific UART clock"); 1984