1 /* 2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 3 * 4 *This program is free software; you can redistribute it and/or modify 5 *it under the terms of the GNU General Public License as published by 6 *the Free Software Foundation; version 2 of the License. 7 * 8 *This program is distributed in the hope that it will be useful, 9 *but WITHOUT ANY WARRANTY; without even the implied warranty of 10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 *GNU General Public License for more details. 12 * 13 *You should have received a copy of the GNU General Public License 14 *along with this program; if not, write to the Free Software 15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 16 */ 17 #include <linux/kernel.h> 18 #include <linux/serial_reg.h> 19 #include <linux/slab.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/serial_core.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/dmi.h> 28 #include <linux/console.h> 29 #include <linux/nmi.h> 30 #include <linux/delay.h> 31 32 #include <linux/debugfs.h> 33 #include <linux/dmaengine.h> 34 #include <linux/pch_dma.h> 35 36 enum { 37 PCH_UART_HANDLED_RX_INT_SHIFT, 38 PCH_UART_HANDLED_TX_INT_SHIFT, 39 PCH_UART_HANDLED_RX_ERR_INT_SHIFT, 40 PCH_UART_HANDLED_RX_TRG_INT_SHIFT, 41 PCH_UART_HANDLED_MS_INT_SHIFT, 42 PCH_UART_HANDLED_LS_INT_SHIFT, 43 }; 44 45 enum { 46 PCH_UART_8LINE, 47 PCH_UART_2LINE, 48 }; 49 50 #define PCH_UART_DRIVER_DEVICE "ttyPCH" 51 52 /* Set the max number of UART port 53 * Intel EG20T PCH: 4 port 54 * LAPIS Semiconductor ML7213 IOH: 3 port 55 * LAPIS Semiconductor ML7223 IOH: 2 port 56 */ 57 #define PCH_UART_NR 4 58 59 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) 60 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) 61 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ 62 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) 63 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ 64 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) 65 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) 66 67 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1)) 68 69 #define PCH_UART_RBR 0x00 70 #define PCH_UART_THR 0x00 71 72 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ 73 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) 74 #define PCH_UART_IER_ERBFI 0x00000001 75 #define PCH_UART_IER_ETBEI 0x00000002 76 #define PCH_UART_IER_ELSI 0x00000004 77 #define PCH_UART_IER_EDSSI 0x00000008 78 79 #define PCH_UART_IIR_IP 0x00000001 80 #define PCH_UART_IIR_IID 0x00000006 81 #define PCH_UART_IIR_MSI 0x00000000 82 #define PCH_UART_IIR_TRI 0x00000002 83 #define PCH_UART_IIR_RRI 0x00000004 84 #define PCH_UART_IIR_REI 0x00000006 85 #define PCH_UART_IIR_TOI 0x00000008 86 #define PCH_UART_IIR_FIFO256 0x00000020 87 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 88 #define PCH_UART_IIR_FE 0x000000C0 89 90 #define PCH_UART_FCR_FIFOE 0x00000001 91 #define PCH_UART_FCR_RFR 0x00000002 92 #define PCH_UART_FCR_TFR 0x00000004 93 #define PCH_UART_FCR_DMS 0x00000008 94 #define PCH_UART_FCR_FIFO256 0x00000020 95 #define PCH_UART_FCR_RFTL 0x000000C0 96 97 #define PCH_UART_FCR_RFTL1 0x00000000 98 #define PCH_UART_FCR_RFTL64 0x00000040 99 #define PCH_UART_FCR_RFTL128 0x00000080 100 #define PCH_UART_FCR_RFTL224 0x000000C0 101 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 102 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 103 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 104 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 105 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 106 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 107 #define PCH_UART_FCR_RFTL_SHIFT 6 108 109 #define PCH_UART_LCR_WLS 0x00000003 110 #define PCH_UART_LCR_STB 0x00000004 111 #define PCH_UART_LCR_PEN 0x00000008 112 #define PCH_UART_LCR_EPS 0x00000010 113 #define PCH_UART_LCR_SP 0x00000020 114 #define PCH_UART_LCR_SB 0x00000040 115 #define PCH_UART_LCR_DLAB 0x00000080 116 #define PCH_UART_LCR_NP 0x00000000 117 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN 118 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) 119 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) 120 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ 121 PCH_UART_LCR_SP) 122 123 #define PCH_UART_LCR_5BIT 0x00000000 124 #define PCH_UART_LCR_6BIT 0x00000001 125 #define PCH_UART_LCR_7BIT 0x00000002 126 #define PCH_UART_LCR_8BIT 0x00000003 127 128 #define PCH_UART_MCR_DTR 0x00000001 129 #define PCH_UART_MCR_RTS 0x00000002 130 #define PCH_UART_MCR_OUT 0x0000000C 131 #define PCH_UART_MCR_LOOP 0x00000010 132 #define PCH_UART_MCR_AFE 0x00000020 133 134 #define PCH_UART_LSR_DR 0x00000001 135 #define PCH_UART_LSR_ERR (1<<7) 136 137 #define PCH_UART_MSR_DCTS 0x00000001 138 #define PCH_UART_MSR_DDSR 0x00000002 139 #define PCH_UART_MSR_TERI 0x00000004 140 #define PCH_UART_MSR_DDCD 0x00000008 141 #define PCH_UART_MSR_CTS 0x00000010 142 #define PCH_UART_MSR_DSR 0x00000020 143 #define PCH_UART_MSR_RI 0x00000040 144 #define PCH_UART_MSR_DCD 0x00000080 145 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ 146 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) 147 148 #define PCH_UART_DLL 0x00 149 #define PCH_UART_DLM 0x01 150 151 #define PCH_UART_BRCSR 0x0E 152 153 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) 154 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) 155 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) 156 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) 157 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) 158 159 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) 160 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) 161 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) 162 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) 163 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) 164 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) 165 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) 166 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) 167 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) 168 #define PCH_UART_HAL_STB1 0 169 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) 170 171 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) 172 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) 173 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ 174 PCH_UART_HAL_CLR_RX_FIFO) 175 176 #define PCH_UART_HAL_DMA_MODE0 0 177 #define PCH_UART_HAL_FIFO_DIS 0 178 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) 179 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ 180 PCH_UART_FCR_FIFO256) 181 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) 182 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) 183 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) 184 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) 185 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) 186 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) 187 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) 188 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) 189 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) 190 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) 191 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) 192 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) 193 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) 194 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) 195 196 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) 197 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) 198 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) 199 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) 200 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) 201 202 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) 203 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) 204 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) 205 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) 206 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) 207 208 #define PCI_VENDOR_ID_ROHM 0x10DB 209 210 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 211 212 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */ 213 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */ 214 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */ 215 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */ 216 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */ 217 218 struct pch_uart_buffer { 219 unsigned char *buf; 220 int size; 221 }; 222 223 struct eg20t_port { 224 struct uart_port port; 225 int port_type; 226 void __iomem *membase; 227 resource_size_t mapbase; 228 unsigned int iobase; 229 struct pci_dev *pdev; 230 int fifo_size; 231 int uartclk; 232 int start_tx; 233 int start_rx; 234 int tx_empty; 235 int trigger; 236 int trigger_level; 237 struct pch_uart_buffer rxbuf; 238 unsigned int dmsr; 239 unsigned int fcr; 240 unsigned int mcr; 241 unsigned int use_dma; 242 struct dma_async_tx_descriptor *desc_tx; 243 struct dma_async_tx_descriptor *desc_rx; 244 struct pch_dma_slave param_tx; 245 struct pch_dma_slave param_rx; 246 struct dma_chan *chan_tx; 247 struct dma_chan *chan_rx; 248 struct scatterlist *sg_tx_p; 249 int nent; 250 struct scatterlist sg_rx; 251 int tx_dma_use; 252 void *rx_buf_virt; 253 dma_addr_t rx_buf_dma; 254 255 struct dentry *debugfs; 256 257 /* protect the eg20t_port private structure and io access to membase */ 258 spinlock_t lock; 259 }; 260 261 /** 262 * struct pch_uart_driver_data - private data structure for UART-DMA 263 * @port_type: The number of DMA channel 264 * @line_no: UART port line number (0, 1, 2...) 265 */ 266 struct pch_uart_driver_data { 267 int port_type; 268 int line_no; 269 }; 270 271 enum pch_uart_num_t { 272 pch_et20t_uart0 = 0, 273 pch_et20t_uart1, 274 pch_et20t_uart2, 275 pch_et20t_uart3, 276 pch_ml7213_uart0, 277 pch_ml7213_uart1, 278 pch_ml7213_uart2, 279 pch_ml7223_uart0, 280 pch_ml7223_uart1, 281 pch_ml7831_uart0, 282 pch_ml7831_uart1, 283 }; 284 285 static struct pch_uart_driver_data drv_dat[] = { 286 [pch_et20t_uart0] = {PCH_UART_8LINE, 0}, 287 [pch_et20t_uart1] = {PCH_UART_2LINE, 1}, 288 [pch_et20t_uart2] = {PCH_UART_2LINE, 2}, 289 [pch_et20t_uart3] = {PCH_UART_2LINE, 3}, 290 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0}, 291 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1}, 292 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2}, 293 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0}, 294 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1}, 295 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0}, 296 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1}, 297 }; 298 299 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 300 static struct eg20t_port *pch_uart_ports[PCH_UART_NR]; 301 #endif 302 static unsigned int default_baud = 9600; 303 static unsigned int user_uartclk = 0; 304 static const int trigger_level_256[4] = { 1, 64, 128, 224 }; 305 static const int trigger_level_64[4] = { 1, 16, 32, 56 }; 306 static const int trigger_level_16[4] = { 1, 4, 8, 14 }; 307 static const int trigger_level_1[4] = { 1, 1, 1, 1 }; 308 309 #ifdef CONFIG_DEBUG_FS 310 311 #define PCH_REGS_BUFSIZE 1024 312 313 314 static ssize_t port_show_regs(struct file *file, char __user *user_buf, 315 size_t count, loff_t *ppos) 316 { 317 struct eg20t_port *priv = file->private_data; 318 char *buf; 319 u32 len = 0; 320 ssize_t ret; 321 unsigned char lcr; 322 323 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL); 324 if (!buf) 325 return 0; 326 327 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 328 "PCH EG20T port[%d] regs:\n", priv->port.line); 329 330 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 331 "=================================\n"); 332 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 333 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); 334 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 335 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); 336 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 337 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); 338 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 339 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); 340 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 341 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); 342 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 343 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); 344 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 345 "BRCSR: \t0x%02x\n", 346 ioread8(priv->membase + PCH_UART_BRCSR)); 347 348 lcr = ioread8(priv->membase + UART_LCR); 349 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 350 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 351 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); 352 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 353 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); 354 iowrite8(lcr, priv->membase + UART_LCR); 355 356 if (len > PCH_REGS_BUFSIZE) 357 len = PCH_REGS_BUFSIZE; 358 359 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 360 kfree(buf); 361 return ret; 362 } 363 364 static const struct file_operations port_regs_ops = { 365 .owner = THIS_MODULE, 366 .open = simple_open, 367 .read = port_show_regs, 368 .llseek = default_llseek, 369 }; 370 #endif /* CONFIG_DEBUG_FS */ 371 372 /* Return UART clock, checking for board specific clocks. */ 373 static int pch_uart_get_uartclk(void) 374 { 375 const char *cmp; 376 377 if (user_uartclk) 378 return user_uartclk; 379 380 cmp = dmi_get_system_info(DMI_BOARD_NAME); 381 if (cmp && strstr(cmp, "CM-iTC")) 382 return CMITC_UARTCLK; 383 384 cmp = dmi_get_system_info(DMI_BIOS_VERSION); 385 if (cmp && strnstr(cmp, "FRI2", 4)) 386 return FRI2_64_UARTCLK; 387 388 cmp = dmi_get_system_info(DMI_PRODUCT_NAME); 389 if (cmp && strstr(cmp, "Fish River Island II")) 390 return FRI2_48_UARTCLK; 391 392 /* Kontron COMe-mTT10 (nanoETXexpress-TT) */ 393 cmp = dmi_get_system_info(DMI_BOARD_NAME); 394 if (cmp && (strstr(cmp, "COMe-mTT") || 395 strstr(cmp, "nanoETXexpress-TT"))) 396 return NTC1_UARTCLK; 397 398 return DEFAULT_UARTCLK; 399 } 400 401 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, 402 unsigned int flag) 403 { 404 u8 ier = ioread8(priv->membase + UART_IER); 405 ier |= flag & PCH_UART_IER_MASK; 406 iowrite8(ier, priv->membase + UART_IER); 407 } 408 409 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, 410 unsigned int flag) 411 { 412 u8 ier = ioread8(priv->membase + UART_IER); 413 ier &= ~(flag & PCH_UART_IER_MASK); 414 iowrite8(ier, priv->membase + UART_IER); 415 } 416 417 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud, 418 unsigned int parity, unsigned int bits, 419 unsigned int stb) 420 { 421 unsigned int dll, dlm, lcr; 422 int div; 423 424 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); 425 if (div < 0 || USHRT_MAX <= div) { 426 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); 427 return -EINVAL; 428 } 429 430 dll = (unsigned int)div & 0x00FFU; 431 dlm = ((unsigned int)div >> 8) & 0x00FFU; 432 433 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { 434 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); 435 return -EINVAL; 436 } 437 438 if (bits & ~PCH_UART_LCR_WLS) { 439 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); 440 return -EINVAL; 441 } 442 443 if (stb & ~PCH_UART_LCR_STB) { 444 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); 445 return -EINVAL; 446 } 447 448 lcr = parity; 449 lcr |= bits; 450 lcr |= stb; 451 452 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n", 453 __func__, baud, div, lcr, jiffies); 454 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 455 iowrite8(dll, priv->membase + PCH_UART_DLL); 456 iowrite8(dlm, priv->membase + PCH_UART_DLM); 457 iowrite8(lcr, priv->membase + UART_LCR); 458 459 return 0; 460 } 461 462 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, 463 unsigned int flag) 464 { 465 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { 466 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", 467 __func__, flag); 468 return -EINVAL; 469 } 470 471 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); 472 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, 473 priv->membase + UART_FCR); 474 iowrite8(priv->fcr, priv->membase + UART_FCR); 475 476 return 0; 477 } 478 479 static int pch_uart_hal_set_fifo(struct eg20t_port *priv, 480 unsigned int dmamode, 481 unsigned int fifo_size, unsigned int trigger) 482 { 483 u8 fcr; 484 485 if (dmamode & ~PCH_UART_FCR_DMS) { 486 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", 487 __func__, dmamode); 488 return -EINVAL; 489 } 490 491 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { 492 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", 493 __func__, fifo_size); 494 return -EINVAL; 495 } 496 497 if (trigger & ~PCH_UART_FCR_RFTL) { 498 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", 499 __func__, trigger); 500 return -EINVAL; 501 } 502 503 switch (priv->fifo_size) { 504 case 256: 505 priv->trigger_level = 506 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 507 break; 508 case 64: 509 priv->trigger_level = 510 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 511 break; 512 case 16: 513 priv->trigger_level = 514 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 515 break; 516 default: 517 priv->trigger_level = 518 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 519 break; 520 } 521 fcr = 522 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; 523 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); 524 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, 525 priv->membase + UART_FCR); 526 iowrite8(fcr, priv->membase + UART_FCR); 527 priv->fcr = fcr; 528 529 return 0; 530 } 531 532 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) 533 { 534 unsigned int msr = ioread8(priv->membase + UART_MSR); 535 priv->dmsr = msr & PCH_UART_MSR_DELTA; 536 return (u8)msr; 537 } 538 539 static void pch_uart_hal_write(struct eg20t_port *priv, 540 const unsigned char *buf, int tx_size) 541 { 542 int i; 543 unsigned int thr; 544 545 for (i = 0; i < tx_size;) { 546 thr = buf[i++]; 547 iowrite8(thr, priv->membase + PCH_UART_THR); 548 } 549 } 550 551 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, 552 int rx_size) 553 { 554 int i; 555 u8 rbr, lsr; 556 557 lsr = ioread8(priv->membase + UART_LSR); 558 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); 559 i < rx_size && lsr & UART_LSR_DR; 560 lsr = ioread8(priv->membase + UART_LSR)) { 561 rbr = ioread8(priv->membase + PCH_UART_RBR); 562 buf[i++] = rbr; 563 } 564 return i; 565 } 566 567 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv) 568 { 569 return ioread8(priv->membase + UART_IIR) &\ 570 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP); 571 } 572 573 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) 574 { 575 return ioread8(priv->membase + UART_LSR); 576 } 577 578 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) 579 { 580 unsigned int lcr; 581 582 lcr = ioread8(priv->membase + UART_LCR); 583 if (on) 584 lcr |= PCH_UART_LCR_SB; 585 else 586 lcr &= ~PCH_UART_LCR_SB; 587 588 iowrite8(lcr, priv->membase + UART_LCR); 589 } 590 591 static int push_rx(struct eg20t_port *priv, const unsigned char *buf, 592 int size) 593 { 594 struct uart_port *port; 595 struct tty_struct *tty; 596 597 port = &priv->port; 598 tty = tty_port_tty_get(&port->state->port); 599 if (!tty) { 600 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 601 return -EBUSY; 602 } 603 604 tty_insert_flip_string(tty, buf, size); 605 tty_flip_buffer_push(tty); 606 tty_kref_put(tty); 607 608 return 0; 609 } 610 611 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) 612 { 613 int ret = 0; 614 struct uart_port *port = &priv->port; 615 616 if (port->x_char) { 617 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n", 618 __func__, port->x_char, jiffies); 619 buf[0] = port->x_char; 620 port->x_char = 0; 621 ret = 1; 622 } 623 624 return ret; 625 } 626 627 static int dma_push_rx(struct eg20t_port *priv, int size) 628 { 629 struct tty_struct *tty; 630 int room; 631 struct uart_port *port = &priv->port; 632 633 port = &priv->port; 634 tty = tty_port_tty_get(&port->state->port); 635 if (!tty) { 636 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 637 return 0; 638 } 639 640 room = tty_buffer_request_room(tty, size); 641 642 if (room < size) 643 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 644 size - room); 645 if (!room) 646 return room; 647 648 tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size); 649 650 port->icount.rx += room; 651 tty_kref_put(tty); 652 653 return room; 654 } 655 656 static void pch_free_dma(struct uart_port *port) 657 { 658 struct eg20t_port *priv; 659 priv = container_of(port, struct eg20t_port, port); 660 661 if (priv->chan_tx) { 662 dma_release_channel(priv->chan_tx); 663 priv->chan_tx = NULL; 664 } 665 if (priv->chan_rx) { 666 dma_release_channel(priv->chan_rx); 667 priv->chan_rx = NULL; 668 } 669 670 if (priv->rx_buf_dma) { 671 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt, 672 priv->rx_buf_dma); 673 priv->rx_buf_virt = NULL; 674 priv->rx_buf_dma = 0; 675 } 676 677 return; 678 } 679 680 static bool filter(struct dma_chan *chan, void *slave) 681 { 682 struct pch_dma_slave *param = slave; 683 684 if ((chan->chan_id == param->chan_id) && (param->dma_dev == 685 chan->device->dev)) { 686 chan->private = param; 687 return true; 688 } else { 689 return false; 690 } 691 } 692 693 static void pch_request_dma(struct uart_port *port) 694 { 695 dma_cap_mask_t mask; 696 struct dma_chan *chan; 697 struct pci_dev *dma_dev; 698 struct pch_dma_slave *param; 699 struct eg20t_port *priv = 700 container_of(port, struct eg20t_port, port); 701 dma_cap_zero(mask); 702 dma_cap_set(DMA_SLAVE, mask); 703 704 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number, 705 PCI_DEVFN(0xa, 0)); /* Get DMA's dev 706 information */ 707 /* Set Tx DMA */ 708 param = &priv->param_tx; 709 param->dma_dev = &dma_dev->dev; 710 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ 711 712 param->tx_reg = port->mapbase + UART_TX; 713 chan = dma_request_channel(mask, filter, param); 714 if (!chan) { 715 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", 716 __func__); 717 return; 718 } 719 priv->chan_tx = chan; 720 721 /* Set Rx DMA */ 722 param = &priv->param_rx; 723 param->dma_dev = &dma_dev->dev; 724 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ 725 726 param->rx_reg = port->mapbase + UART_RX; 727 chan = dma_request_channel(mask, filter, param); 728 if (!chan) { 729 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", 730 __func__); 731 dma_release_channel(priv->chan_tx); 732 priv->chan_tx = NULL; 733 return; 734 } 735 736 /* Get Consistent memory for DMA */ 737 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, 738 &priv->rx_buf_dma, GFP_KERNEL); 739 priv->chan_rx = chan; 740 } 741 742 static void pch_dma_rx_complete(void *arg) 743 { 744 struct eg20t_port *priv = arg; 745 struct uart_port *port = &priv->port; 746 struct tty_struct *tty = tty_port_tty_get(&port->state->port); 747 int count; 748 749 if (!tty) { 750 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 751 return; 752 } 753 754 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); 755 count = dma_push_rx(priv, priv->trigger_level); 756 if (count) 757 tty_flip_buffer_push(tty); 758 tty_kref_put(tty); 759 async_tx_ack(priv->desc_rx); 760 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | 761 PCH_UART_HAL_RX_ERR_INT); 762 } 763 764 static void pch_dma_tx_complete(void *arg) 765 { 766 struct eg20t_port *priv = arg; 767 struct uart_port *port = &priv->port; 768 struct circ_buf *xmit = &port->state->xmit; 769 struct scatterlist *sg = priv->sg_tx_p; 770 int i; 771 772 for (i = 0; i < priv->nent; i++, sg++) { 773 xmit->tail += sg_dma_len(sg); 774 port->icount.tx += sg_dma_len(sg); 775 } 776 xmit->tail &= UART_XMIT_SIZE - 1; 777 async_tx_ack(priv->desc_tx); 778 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE); 779 priv->tx_dma_use = 0; 780 priv->nent = 0; 781 kfree(priv->sg_tx_p); 782 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 783 } 784 785 static int pop_tx(struct eg20t_port *priv, int size) 786 { 787 int count = 0; 788 struct uart_port *port = &priv->port; 789 struct circ_buf *xmit = &port->state->xmit; 790 791 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size) 792 goto pop_tx_end; 793 794 do { 795 int cnt_to_end = 796 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 797 int sz = min(size - count, cnt_to_end); 798 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz); 799 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1); 800 count += sz; 801 } while (!uart_circ_empty(xmit) && count < size); 802 803 pop_tx_end: 804 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n", 805 count, size - count, jiffies); 806 807 return count; 808 } 809 810 static int handle_rx_to(struct eg20t_port *priv) 811 { 812 struct pch_uart_buffer *buf; 813 int rx_size; 814 int ret; 815 if (!priv->start_rx) { 816 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | 817 PCH_UART_HAL_RX_ERR_INT); 818 return 0; 819 } 820 buf = &priv->rxbuf; 821 do { 822 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); 823 ret = push_rx(priv, buf->buf, rx_size); 824 if (ret) 825 return 0; 826 } while (rx_size == buf->size); 827 828 return PCH_UART_HANDLED_RX_INT; 829 } 830 831 static int handle_rx(struct eg20t_port *priv) 832 { 833 return handle_rx_to(priv); 834 } 835 836 static int dma_handle_rx(struct eg20t_port *priv) 837 { 838 struct uart_port *port = &priv->port; 839 struct dma_async_tx_descriptor *desc; 840 struct scatterlist *sg; 841 842 priv = container_of(port, struct eg20t_port, port); 843 sg = &priv->sg_rx; 844 845 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ 846 847 sg_dma_len(sg) = priv->trigger_level; 848 849 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), 850 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt & 851 ~PAGE_MASK); 852 853 sg_dma_address(sg) = priv->rx_buf_dma; 854 855 desc = dmaengine_prep_slave_sg(priv->chan_rx, 856 sg, 1, DMA_DEV_TO_MEM, 857 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 858 859 if (!desc) 860 return 0; 861 862 priv->desc_rx = desc; 863 desc->callback = pch_dma_rx_complete; 864 desc->callback_param = priv; 865 desc->tx_submit(desc); 866 dma_async_issue_pending(priv->chan_rx); 867 868 return PCH_UART_HANDLED_RX_INT; 869 } 870 871 static unsigned int handle_tx(struct eg20t_port *priv) 872 { 873 struct uart_port *port = &priv->port; 874 struct circ_buf *xmit = &port->state->xmit; 875 int fifo_size; 876 int tx_size; 877 int size; 878 int tx_empty; 879 880 if (!priv->start_tx) { 881 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 882 __func__, jiffies); 883 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 884 priv->tx_empty = 1; 885 return 0; 886 } 887 888 fifo_size = max(priv->fifo_size, 1); 889 tx_empty = 1; 890 if (pop_tx_x(priv, xmit->buf)) { 891 pch_uart_hal_write(priv, xmit->buf, 1); 892 port->icount.tx++; 893 tx_empty = 0; 894 fifo_size--; 895 } 896 size = min(xmit->head - xmit->tail, fifo_size); 897 if (size < 0) 898 size = fifo_size; 899 900 tx_size = pop_tx(priv, size); 901 if (tx_size > 0) { 902 port->icount.tx += tx_size; 903 tx_empty = 0; 904 } 905 906 priv->tx_empty = tx_empty; 907 908 if (tx_empty) { 909 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 910 uart_write_wakeup(port); 911 } 912 913 return PCH_UART_HANDLED_TX_INT; 914 } 915 916 static unsigned int dma_handle_tx(struct eg20t_port *priv) 917 { 918 struct uart_port *port = &priv->port; 919 struct circ_buf *xmit = &port->state->xmit; 920 struct scatterlist *sg; 921 int nent; 922 int fifo_size; 923 int tx_empty; 924 struct dma_async_tx_descriptor *desc; 925 int num; 926 int i; 927 int bytes; 928 int size; 929 int rem; 930 931 if (!priv->start_tx) { 932 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 933 __func__, jiffies); 934 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 935 priv->tx_empty = 1; 936 return 0; 937 } 938 939 if (priv->tx_dma_use) { 940 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", 941 __func__, jiffies); 942 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 943 priv->tx_empty = 1; 944 return 0; 945 } 946 947 fifo_size = max(priv->fifo_size, 1); 948 tx_empty = 1; 949 if (pop_tx_x(priv, xmit->buf)) { 950 pch_uart_hal_write(priv, xmit->buf, 1); 951 port->icount.tx++; 952 tx_empty = 0; 953 fifo_size--; 954 } 955 956 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail, 957 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head, 958 xmit->tail, UART_XMIT_SIZE)); 959 if (!bytes) { 960 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); 961 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 962 uart_write_wakeup(port); 963 return 0; 964 } 965 966 if (bytes > fifo_size) { 967 num = bytes / fifo_size + 1; 968 size = fifo_size; 969 rem = bytes % fifo_size; 970 } else { 971 num = 1; 972 size = bytes; 973 rem = bytes; 974 } 975 976 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", 977 __func__, num, size, rem); 978 979 priv->tx_dma_use = 1; 980 981 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); 982 if (!priv->sg_tx_p) { 983 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__); 984 return 0; 985 } 986 987 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ 988 sg = priv->sg_tx_p; 989 990 for (i = 0; i < num; i++, sg++) { 991 if (i == (num - 1)) 992 sg_set_page(sg, virt_to_page(xmit->buf), 993 rem, fifo_size * i); 994 else 995 sg_set_page(sg, virt_to_page(xmit->buf), 996 size, fifo_size * i); 997 } 998 999 sg = priv->sg_tx_p; 1000 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); 1001 if (!nent) { 1002 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); 1003 return 0; 1004 } 1005 priv->nent = nent; 1006 1007 for (i = 0; i < nent; i++, sg++) { 1008 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + 1009 fifo_size * i; 1010 sg_dma_address(sg) = (sg_dma_address(sg) & 1011 ~(UART_XMIT_SIZE - 1)) + sg->offset; 1012 if (i == (nent - 1)) 1013 sg_dma_len(sg) = rem; 1014 else 1015 sg_dma_len(sg) = size; 1016 } 1017 1018 desc = dmaengine_prep_slave_sg(priv->chan_tx, 1019 priv->sg_tx_p, nent, DMA_MEM_TO_DEV, 1020 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1021 if (!desc) { 1022 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n", 1023 __func__); 1024 return 0; 1025 } 1026 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); 1027 priv->desc_tx = desc; 1028 desc->callback = pch_dma_tx_complete; 1029 desc->callback_param = priv; 1030 1031 desc->tx_submit(desc); 1032 1033 dma_async_issue_pending(priv->chan_tx); 1034 1035 return PCH_UART_HANDLED_TX_INT; 1036 } 1037 1038 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) 1039 { 1040 u8 fcr = ioread8(priv->membase + UART_FCR); 1041 1042 /* Reset FIFO */ 1043 fcr |= UART_FCR_CLEAR_RCVR; 1044 iowrite8(fcr, priv->membase + UART_FCR); 1045 1046 if (lsr & PCH_UART_LSR_ERR) 1047 dev_err(&priv->pdev->dev, "Error data in FIFO\n"); 1048 1049 if (lsr & UART_LSR_FE) 1050 dev_err(&priv->pdev->dev, "Framing Error\n"); 1051 1052 if (lsr & UART_LSR_PE) 1053 dev_err(&priv->pdev->dev, "Parity Error\n"); 1054 1055 if (lsr & UART_LSR_OE) 1056 dev_err(&priv->pdev->dev, "Overrun Error\n"); 1057 } 1058 1059 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) 1060 { 1061 struct eg20t_port *priv = dev_id; 1062 unsigned int handled; 1063 u8 lsr; 1064 int ret = 0; 1065 unsigned char iid; 1066 unsigned long flags; 1067 int next = 1; 1068 u8 msr; 1069 1070 spin_lock_irqsave(&priv->lock, flags); 1071 handled = 0; 1072 while (next) { 1073 iid = pch_uart_hal_get_iid(priv); 1074 if (iid & PCH_UART_IIR_IP) /* No Interrupt */ 1075 break; 1076 switch (iid) { 1077 case PCH_UART_IID_RLS: /* Receiver Line Status */ 1078 lsr = pch_uart_hal_get_line_status(priv); 1079 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | 1080 UART_LSR_PE | UART_LSR_OE)) { 1081 pch_uart_err_ir(priv, lsr); 1082 ret = PCH_UART_HANDLED_RX_ERR_INT; 1083 } else { 1084 ret = PCH_UART_HANDLED_LS_INT; 1085 } 1086 break; 1087 case PCH_UART_IID_RDR: /* Received Data Ready */ 1088 if (priv->use_dma) { 1089 pch_uart_hal_disable_interrupt(priv, 1090 PCH_UART_HAL_RX_INT | 1091 PCH_UART_HAL_RX_ERR_INT); 1092 ret = dma_handle_rx(priv); 1093 if (!ret) 1094 pch_uart_hal_enable_interrupt(priv, 1095 PCH_UART_HAL_RX_INT | 1096 PCH_UART_HAL_RX_ERR_INT); 1097 } else { 1098 ret = handle_rx(priv); 1099 } 1100 break; 1101 case PCH_UART_IID_RDR_TO: /* Received Data Ready 1102 (FIFO Timeout) */ 1103 ret = handle_rx_to(priv); 1104 break; 1105 case PCH_UART_IID_THRE: /* Transmitter Holding Register 1106 Empty */ 1107 if (priv->use_dma) 1108 ret = dma_handle_tx(priv); 1109 else 1110 ret = handle_tx(priv); 1111 break; 1112 case PCH_UART_IID_MS: /* Modem Status */ 1113 msr = pch_uart_hal_get_modem(priv); 1114 next = 0; /* MS ir prioirty is the lowest. So, MS ir 1115 means final interrupt */ 1116 if ((msr & UART_MSR_ANY_DELTA) == 0) 1117 break; 1118 ret |= PCH_UART_HANDLED_MS_INT; 1119 break; 1120 default: /* Never junp to this label */ 1121 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__, 1122 iid, jiffies); 1123 ret = -1; 1124 next = 0; 1125 break; 1126 } 1127 handled |= (unsigned int)ret; 1128 } 1129 1130 spin_unlock_irqrestore(&priv->lock, flags); 1131 return IRQ_RETVAL(handled); 1132 } 1133 1134 /* This function tests whether the transmitter fifo and shifter for the port 1135 described by 'port' is empty. */ 1136 static unsigned int pch_uart_tx_empty(struct uart_port *port) 1137 { 1138 struct eg20t_port *priv; 1139 1140 priv = container_of(port, struct eg20t_port, port); 1141 if (priv->tx_empty) 1142 return TIOCSER_TEMT; 1143 else 1144 return 0; 1145 } 1146 1147 /* Returns the current state of modem control inputs. */ 1148 static unsigned int pch_uart_get_mctrl(struct uart_port *port) 1149 { 1150 struct eg20t_port *priv; 1151 u8 modem; 1152 unsigned int ret = 0; 1153 1154 priv = container_of(port, struct eg20t_port, port); 1155 modem = pch_uart_hal_get_modem(priv); 1156 1157 if (modem & UART_MSR_DCD) 1158 ret |= TIOCM_CAR; 1159 1160 if (modem & UART_MSR_RI) 1161 ret |= TIOCM_RNG; 1162 1163 if (modem & UART_MSR_DSR) 1164 ret |= TIOCM_DSR; 1165 1166 if (modem & UART_MSR_CTS) 1167 ret |= TIOCM_CTS; 1168 1169 return ret; 1170 } 1171 1172 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1173 { 1174 u32 mcr = 0; 1175 struct eg20t_port *priv = container_of(port, struct eg20t_port, port); 1176 1177 if (mctrl & TIOCM_DTR) 1178 mcr |= UART_MCR_DTR; 1179 if (mctrl & TIOCM_RTS) 1180 mcr |= UART_MCR_RTS; 1181 if (mctrl & TIOCM_LOOP) 1182 mcr |= UART_MCR_LOOP; 1183 1184 if (priv->mcr & UART_MCR_AFE) 1185 mcr |= UART_MCR_AFE; 1186 1187 if (mctrl) 1188 iowrite8(mcr, priv->membase + UART_MCR); 1189 } 1190 1191 static void pch_uart_stop_tx(struct uart_port *port) 1192 { 1193 struct eg20t_port *priv; 1194 priv = container_of(port, struct eg20t_port, port); 1195 priv->start_tx = 0; 1196 priv->tx_dma_use = 0; 1197 } 1198 1199 static void pch_uart_start_tx(struct uart_port *port) 1200 { 1201 struct eg20t_port *priv; 1202 1203 priv = container_of(port, struct eg20t_port, port); 1204 1205 if (priv->use_dma) { 1206 if (priv->tx_dma_use) { 1207 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", 1208 __func__); 1209 return; 1210 } 1211 } 1212 1213 priv->start_tx = 1; 1214 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 1215 } 1216 1217 static void pch_uart_stop_rx(struct uart_port *port) 1218 { 1219 struct eg20t_port *priv; 1220 priv = container_of(port, struct eg20t_port, port); 1221 priv->start_rx = 0; 1222 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | 1223 PCH_UART_HAL_RX_ERR_INT); 1224 } 1225 1226 /* Enable the modem status interrupts. */ 1227 static void pch_uart_enable_ms(struct uart_port *port) 1228 { 1229 struct eg20t_port *priv; 1230 priv = container_of(port, struct eg20t_port, port); 1231 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); 1232 } 1233 1234 /* Control the transmission of a break signal. */ 1235 static void pch_uart_break_ctl(struct uart_port *port, int ctl) 1236 { 1237 struct eg20t_port *priv; 1238 unsigned long flags; 1239 1240 priv = container_of(port, struct eg20t_port, port); 1241 spin_lock_irqsave(&priv->lock, flags); 1242 pch_uart_hal_set_break(priv, ctl); 1243 spin_unlock_irqrestore(&priv->lock, flags); 1244 } 1245 1246 /* Grab any interrupt resources and initialise any low level driver state. */ 1247 static int pch_uart_startup(struct uart_port *port) 1248 { 1249 struct eg20t_port *priv; 1250 int ret; 1251 int fifo_size; 1252 int trigger_level; 1253 1254 priv = container_of(port, struct eg20t_port, port); 1255 priv->tx_empty = 1; 1256 1257 if (port->uartclk) 1258 priv->uartclk = port->uartclk; 1259 else 1260 port->uartclk = priv->uartclk; 1261 1262 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1263 ret = pch_uart_hal_set_line(priv, default_baud, 1264 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, 1265 PCH_UART_HAL_STB1); 1266 if (ret) 1267 return ret; 1268 1269 switch (priv->fifo_size) { 1270 case 256: 1271 fifo_size = PCH_UART_HAL_FIFO256; 1272 break; 1273 case 64: 1274 fifo_size = PCH_UART_HAL_FIFO64; 1275 break; 1276 case 16: 1277 fifo_size = PCH_UART_HAL_FIFO16; 1278 break; 1279 case 1: 1280 default: 1281 fifo_size = PCH_UART_HAL_FIFO_DIS; 1282 break; 1283 } 1284 1285 switch (priv->trigger) { 1286 case PCH_UART_HAL_TRIGGER1: 1287 trigger_level = 1; 1288 break; 1289 case PCH_UART_HAL_TRIGGER_L: 1290 trigger_level = priv->fifo_size / 4; 1291 break; 1292 case PCH_UART_HAL_TRIGGER_M: 1293 trigger_level = priv->fifo_size / 2; 1294 break; 1295 case PCH_UART_HAL_TRIGGER_H: 1296 default: 1297 trigger_level = priv->fifo_size - (priv->fifo_size / 8); 1298 break; 1299 } 1300 1301 priv->trigger_level = trigger_level; 1302 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1303 fifo_size, priv->trigger); 1304 if (ret < 0) 1305 return ret; 1306 1307 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, 1308 KBUILD_MODNAME, priv); 1309 if (ret < 0) 1310 return ret; 1311 1312 if (priv->use_dma) 1313 pch_request_dma(port); 1314 1315 priv->start_rx = 1; 1316 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | 1317 PCH_UART_HAL_RX_ERR_INT); 1318 uart_update_timeout(port, CS8, default_baud); 1319 1320 return 0; 1321 } 1322 1323 static void pch_uart_shutdown(struct uart_port *port) 1324 { 1325 struct eg20t_port *priv; 1326 int ret; 1327 1328 priv = container_of(port, struct eg20t_port, port); 1329 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1330 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); 1331 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1332 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); 1333 if (ret) 1334 dev_err(priv->port.dev, 1335 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); 1336 1337 pch_free_dma(port); 1338 1339 free_irq(priv->port.irq, priv); 1340 } 1341 1342 /* Change the port parameters, including word length, parity, stop 1343 *bits. Update read_status_mask and ignore_status_mask to indicate 1344 *the types of events we are interested in receiving. */ 1345 static void pch_uart_set_termios(struct uart_port *port, 1346 struct ktermios *termios, struct ktermios *old) 1347 { 1348 int baud; 1349 int rtn; 1350 unsigned int parity, bits, stb; 1351 struct eg20t_port *priv; 1352 unsigned long flags; 1353 1354 priv = container_of(port, struct eg20t_port, port); 1355 switch (termios->c_cflag & CSIZE) { 1356 case CS5: 1357 bits = PCH_UART_HAL_5BIT; 1358 break; 1359 case CS6: 1360 bits = PCH_UART_HAL_6BIT; 1361 break; 1362 case CS7: 1363 bits = PCH_UART_HAL_7BIT; 1364 break; 1365 default: /* CS8 */ 1366 bits = PCH_UART_HAL_8BIT; 1367 break; 1368 } 1369 if (termios->c_cflag & CSTOPB) 1370 stb = PCH_UART_HAL_STB2; 1371 else 1372 stb = PCH_UART_HAL_STB1; 1373 1374 if (termios->c_cflag & PARENB) { 1375 if (termios->c_cflag & PARODD) 1376 parity = PCH_UART_HAL_PARITY_ODD; 1377 else 1378 parity = PCH_UART_HAL_PARITY_EVEN; 1379 1380 } else 1381 parity = PCH_UART_HAL_PARITY_NONE; 1382 1383 /* Only UART0 has auto hardware flow function */ 1384 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) 1385 priv->mcr |= UART_MCR_AFE; 1386 else 1387 priv->mcr &= ~UART_MCR_AFE; 1388 1389 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 1390 1391 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1392 1393 spin_lock_irqsave(&priv->lock, flags); 1394 spin_lock(&port->lock); 1395 1396 uart_update_timeout(port, termios->c_cflag, baud); 1397 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); 1398 if (rtn) 1399 goto out; 1400 1401 pch_uart_set_mctrl(&priv->port, priv->port.mctrl); 1402 /* Don't rewrite B0 */ 1403 if (tty_termios_baud_rate(termios)) 1404 tty_termios_encode_baud_rate(termios, baud, baud); 1405 1406 out: 1407 spin_unlock(&port->lock); 1408 spin_unlock_irqrestore(&priv->lock, flags); 1409 } 1410 1411 static const char *pch_uart_type(struct uart_port *port) 1412 { 1413 return KBUILD_MODNAME; 1414 } 1415 1416 static void pch_uart_release_port(struct uart_port *port) 1417 { 1418 struct eg20t_port *priv; 1419 1420 priv = container_of(port, struct eg20t_port, port); 1421 pci_iounmap(priv->pdev, priv->membase); 1422 pci_release_regions(priv->pdev); 1423 } 1424 1425 static int pch_uart_request_port(struct uart_port *port) 1426 { 1427 struct eg20t_port *priv; 1428 int ret; 1429 void __iomem *membase; 1430 1431 priv = container_of(port, struct eg20t_port, port); 1432 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); 1433 if (ret < 0) 1434 return -EBUSY; 1435 1436 membase = pci_iomap(priv->pdev, 1, 0); 1437 if (!membase) { 1438 pci_release_regions(priv->pdev); 1439 return -EBUSY; 1440 } 1441 priv->membase = port->membase = membase; 1442 1443 return 0; 1444 } 1445 1446 static void pch_uart_config_port(struct uart_port *port, int type) 1447 { 1448 struct eg20t_port *priv; 1449 1450 priv = container_of(port, struct eg20t_port, port); 1451 if (type & UART_CONFIG_TYPE) { 1452 port->type = priv->port_type; 1453 pch_uart_request_port(port); 1454 } 1455 } 1456 1457 static int pch_uart_verify_port(struct uart_port *port, 1458 struct serial_struct *serinfo) 1459 { 1460 struct eg20t_port *priv; 1461 1462 priv = container_of(port, struct eg20t_port, port); 1463 if (serinfo->flags & UPF_LOW_LATENCY) { 1464 dev_info(priv->port.dev, 1465 "PCH UART : Use PIO Mode (without DMA)\n"); 1466 priv->use_dma = 0; 1467 serinfo->flags &= ~UPF_LOW_LATENCY; 1468 } else { 1469 #ifndef CONFIG_PCH_DMA 1470 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", 1471 __func__); 1472 return -EOPNOTSUPP; 1473 #endif 1474 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n"); 1475 if (!priv->use_dma) 1476 pch_request_dma(port); 1477 priv->use_dma = 1; 1478 } 1479 1480 return 0; 1481 } 1482 1483 static struct uart_ops pch_uart_ops = { 1484 .tx_empty = pch_uart_tx_empty, 1485 .set_mctrl = pch_uart_set_mctrl, 1486 .get_mctrl = pch_uart_get_mctrl, 1487 .stop_tx = pch_uart_stop_tx, 1488 .start_tx = pch_uart_start_tx, 1489 .stop_rx = pch_uart_stop_rx, 1490 .enable_ms = pch_uart_enable_ms, 1491 .break_ctl = pch_uart_break_ctl, 1492 .startup = pch_uart_startup, 1493 .shutdown = pch_uart_shutdown, 1494 .set_termios = pch_uart_set_termios, 1495 /* .pm = pch_uart_pm, Not supported yet */ 1496 /* .set_wake = pch_uart_set_wake, Not supported yet */ 1497 .type = pch_uart_type, 1498 .release_port = pch_uart_release_port, 1499 .request_port = pch_uart_request_port, 1500 .config_port = pch_uart_config_port, 1501 .verify_port = pch_uart_verify_port 1502 }; 1503 1504 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1505 1506 /* 1507 * Wait for transmitter & holding register to empty 1508 */ 1509 static void wait_for_xmitr(struct eg20t_port *up, int bits) 1510 { 1511 unsigned int status, tmout = 10000; 1512 1513 /* Wait up to 10ms for the character(s) to be sent. */ 1514 for (;;) { 1515 status = ioread8(up->membase + UART_LSR); 1516 1517 if ((status & bits) == bits) 1518 break; 1519 if (--tmout == 0) 1520 break; 1521 udelay(1); 1522 } 1523 1524 /* Wait up to 1s for flow control if necessary */ 1525 if (up->port.flags & UPF_CONS_FLOW) { 1526 unsigned int tmout; 1527 for (tmout = 1000000; tmout; tmout--) { 1528 unsigned int msr = ioread8(up->membase + UART_MSR); 1529 if (msr & UART_MSR_CTS) 1530 break; 1531 udelay(1); 1532 touch_nmi_watchdog(); 1533 } 1534 } 1535 } 1536 1537 static void pch_console_putchar(struct uart_port *port, int ch) 1538 { 1539 struct eg20t_port *priv = 1540 container_of(port, struct eg20t_port, port); 1541 1542 wait_for_xmitr(priv, UART_LSR_THRE); 1543 iowrite8(ch, priv->membase + PCH_UART_THR); 1544 } 1545 1546 /* 1547 * Print a string to the serial port trying not to disturb 1548 * any possible real use of the port... 1549 * 1550 * The console_lock must be held when we get here. 1551 */ 1552 static void 1553 pch_console_write(struct console *co, const char *s, unsigned int count) 1554 { 1555 struct eg20t_port *priv; 1556 unsigned long flags; 1557 int priv_locked = 1; 1558 int port_locked = 1; 1559 u8 ier; 1560 1561 priv = pch_uart_ports[co->index]; 1562 1563 touch_nmi_watchdog(); 1564 1565 local_irq_save(flags); 1566 if (priv->port.sysrq) { 1567 spin_lock(&priv->lock); 1568 /* serial8250_handle_port() already took the port lock */ 1569 port_locked = 0; 1570 } else if (oops_in_progress) { 1571 priv_locked = spin_trylock(&priv->lock); 1572 port_locked = spin_trylock(&priv->port.lock); 1573 } else { 1574 spin_lock(&priv->lock); 1575 spin_lock(&priv->port.lock); 1576 } 1577 1578 /* 1579 * First save the IER then disable the interrupts 1580 */ 1581 ier = ioread8(priv->membase + UART_IER); 1582 1583 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1584 1585 uart_console_write(&priv->port, s, count, pch_console_putchar); 1586 1587 /* 1588 * Finally, wait for transmitter to become empty 1589 * and restore the IER 1590 */ 1591 wait_for_xmitr(priv, BOTH_EMPTY); 1592 iowrite8(ier, priv->membase + UART_IER); 1593 1594 if (port_locked) 1595 spin_unlock(&priv->port.lock); 1596 if (priv_locked) 1597 spin_unlock(&priv->lock); 1598 local_irq_restore(flags); 1599 } 1600 1601 static int __init pch_console_setup(struct console *co, char *options) 1602 { 1603 struct uart_port *port; 1604 int baud = default_baud; 1605 int bits = 8; 1606 int parity = 'n'; 1607 int flow = 'n'; 1608 1609 /* 1610 * Check whether an invalid uart number has been specified, and 1611 * if so, search for the first available port that does have 1612 * console support. 1613 */ 1614 if (co->index >= PCH_UART_NR) 1615 co->index = 0; 1616 port = &pch_uart_ports[co->index]->port; 1617 1618 if (!port || (!port->iobase && !port->membase)) 1619 return -ENODEV; 1620 1621 port->uartclk = pch_uart_get_uartclk(); 1622 1623 if (options) 1624 uart_parse_options(options, &baud, &parity, &bits, &flow); 1625 1626 return uart_set_options(port, co, baud, parity, bits, flow); 1627 } 1628 1629 static struct uart_driver pch_uart_driver; 1630 1631 static struct console pch_console = { 1632 .name = PCH_UART_DRIVER_DEVICE, 1633 .write = pch_console_write, 1634 .device = uart_console_device, 1635 .setup = pch_console_setup, 1636 .flags = CON_PRINTBUFFER | CON_ANYTIME, 1637 .index = -1, 1638 .data = &pch_uart_driver, 1639 }; 1640 1641 #define PCH_CONSOLE (&pch_console) 1642 #else 1643 #define PCH_CONSOLE NULL 1644 #endif 1645 1646 static struct uart_driver pch_uart_driver = { 1647 .owner = THIS_MODULE, 1648 .driver_name = KBUILD_MODNAME, 1649 .dev_name = PCH_UART_DRIVER_DEVICE, 1650 .major = 0, 1651 .minor = 0, 1652 .nr = PCH_UART_NR, 1653 .cons = PCH_CONSOLE, 1654 }; 1655 1656 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, 1657 const struct pci_device_id *id) 1658 { 1659 struct eg20t_port *priv; 1660 int ret; 1661 unsigned int iobase; 1662 unsigned int mapbase; 1663 unsigned char *rxbuf; 1664 int fifosize; 1665 int port_type; 1666 struct pch_uart_driver_data *board; 1667 char name[32]; /* for debugfs file name */ 1668 1669 board = &drv_dat[id->driver_data]; 1670 port_type = board->port_type; 1671 1672 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); 1673 if (priv == NULL) 1674 goto init_port_alloc_err; 1675 1676 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); 1677 if (!rxbuf) 1678 goto init_port_free_txbuf; 1679 1680 switch (port_type) { 1681 case PORT_UNKNOWN: 1682 fifosize = 256; /* EG20T/ML7213: UART0 */ 1683 break; 1684 case PORT_8250: 1685 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ 1686 break; 1687 default: 1688 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); 1689 goto init_port_hal_free; 1690 } 1691 1692 pci_enable_msi(pdev); 1693 pci_set_master(pdev); 1694 1695 spin_lock_init(&priv->lock); 1696 1697 iobase = pci_resource_start(pdev, 0); 1698 mapbase = pci_resource_start(pdev, 1); 1699 priv->mapbase = mapbase; 1700 priv->iobase = iobase; 1701 priv->pdev = pdev; 1702 priv->tx_empty = 1; 1703 priv->rxbuf.buf = rxbuf; 1704 priv->rxbuf.size = PAGE_SIZE; 1705 1706 priv->fifo_size = fifosize; 1707 priv->uartclk = pch_uart_get_uartclk(); 1708 priv->port_type = PORT_MAX_8250 + port_type + 1; 1709 priv->port.dev = &pdev->dev; 1710 priv->port.iobase = iobase; 1711 priv->port.membase = NULL; 1712 priv->port.mapbase = mapbase; 1713 priv->port.irq = pdev->irq; 1714 priv->port.iotype = UPIO_PORT; 1715 priv->port.ops = &pch_uart_ops; 1716 priv->port.flags = UPF_BOOT_AUTOCONF; 1717 priv->port.fifosize = fifosize; 1718 priv->port.line = board->line_no; 1719 priv->trigger = PCH_UART_HAL_TRIGGER_M; 1720 1721 spin_lock_init(&priv->port.lock); 1722 1723 pci_set_drvdata(pdev, priv); 1724 priv->trigger_level = 1; 1725 priv->fcr = 0; 1726 1727 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1728 pch_uart_ports[board->line_no] = priv; 1729 #endif 1730 ret = uart_add_one_port(&pch_uart_driver, &priv->port); 1731 if (ret < 0) 1732 goto init_port_hal_free; 1733 1734 #ifdef CONFIG_DEBUG_FS 1735 snprintf(name, sizeof(name), "uart%d_regs", board->line_no); 1736 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO, 1737 NULL, priv, &port_regs_ops); 1738 #endif 1739 1740 return priv; 1741 1742 init_port_hal_free: 1743 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1744 pch_uart_ports[board->line_no] = NULL; 1745 #endif 1746 free_page((unsigned long)rxbuf); 1747 init_port_free_txbuf: 1748 kfree(priv); 1749 init_port_alloc_err: 1750 1751 return NULL; 1752 } 1753 1754 static void pch_uart_exit_port(struct eg20t_port *priv) 1755 { 1756 1757 #ifdef CONFIG_DEBUG_FS 1758 if (priv->debugfs) 1759 debugfs_remove(priv->debugfs); 1760 #endif 1761 uart_remove_one_port(&pch_uart_driver, &priv->port); 1762 pci_set_drvdata(priv->pdev, NULL); 1763 free_page((unsigned long)priv->rxbuf.buf); 1764 } 1765 1766 static void pch_uart_pci_remove(struct pci_dev *pdev) 1767 { 1768 struct eg20t_port *priv = pci_get_drvdata(pdev); 1769 1770 pci_disable_msi(pdev); 1771 1772 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1773 pch_uart_ports[priv->port.line] = NULL; 1774 #endif 1775 pch_uart_exit_port(priv); 1776 pci_disable_device(pdev); 1777 kfree(priv); 1778 return; 1779 } 1780 #ifdef CONFIG_PM 1781 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1782 { 1783 struct eg20t_port *priv = pci_get_drvdata(pdev); 1784 1785 uart_suspend_port(&pch_uart_driver, &priv->port); 1786 1787 pci_save_state(pdev); 1788 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1789 return 0; 1790 } 1791 1792 static int pch_uart_pci_resume(struct pci_dev *pdev) 1793 { 1794 struct eg20t_port *priv = pci_get_drvdata(pdev); 1795 int ret; 1796 1797 pci_set_power_state(pdev, PCI_D0); 1798 pci_restore_state(pdev); 1799 1800 ret = pci_enable_device(pdev); 1801 if (ret) { 1802 dev_err(&pdev->dev, 1803 "%s-pci_enable_device failed(ret=%d) ", __func__, ret); 1804 return ret; 1805 } 1806 1807 uart_resume_port(&pch_uart_driver, &priv->port); 1808 1809 return 0; 1810 } 1811 #else 1812 #define pch_uart_pci_suspend NULL 1813 #define pch_uart_pci_resume NULL 1814 #endif 1815 1816 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = { 1817 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), 1818 .driver_data = pch_et20t_uart0}, 1819 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), 1820 .driver_data = pch_et20t_uart1}, 1821 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), 1822 .driver_data = pch_et20t_uart2}, 1823 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), 1824 .driver_data = pch_et20t_uart3}, 1825 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), 1826 .driver_data = pch_ml7213_uart0}, 1827 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), 1828 .driver_data = pch_ml7213_uart1}, 1829 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), 1830 .driver_data = pch_ml7213_uart2}, 1831 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C), 1832 .driver_data = pch_ml7223_uart0}, 1833 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D), 1834 .driver_data = pch_ml7223_uart1}, 1835 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811), 1836 .driver_data = pch_ml7831_uart0}, 1837 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812), 1838 .driver_data = pch_ml7831_uart1}, 1839 {0,}, 1840 }; 1841 1842 static int pch_uart_pci_probe(struct pci_dev *pdev, 1843 const struct pci_device_id *id) 1844 { 1845 int ret; 1846 struct eg20t_port *priv; 1847 1848 ret = pci_enable_device(pdev); 1849 if (ret < 0) 1850 goto probe_error; 1851 1852 priv = pch_uart_init_port(pdev, id); 1853 if (!priv) { 1854 ret = -EBUSY; 1855 goto probe_disable_device; 1856 } 1857 pci_set_drvdata(pdev, priv); 1858 1859 return ret; 1860 1861 probe_disable_device: 1862 pci_disable_msi(pdev); 1863 pci_disable_device(pdev); 1864 probe_error: 1865 return ret; 1866 } 1867 1868 static struct pci_driver pch_uart_pci_driver = { 1869 .name = "pch_uart", 1870 .id_table = pch_uart_pci_id, 1871 .probe = pch_uart_pci_probe, 1872 .remove = pch_uart_pci_remove, 1873 .suspend = pch_uart_pci_suspend, 1874 .resume = pch_uart_pci_resume, 1875 }; 1876 1877 static int __init pch_uart_module_init(void) 1878 { 1879 int ret; 1880 1881 /* register as UART driver */ 1882 ret = uart_register_driver(&pch_uart_driver); 1883 if (ret < 0) 1884 return ret; 1885 1886 /* register as PCI driver */ 1887 ret = pci_register_driver(&pch_uart_pci_driver); 1888 if (ret < 0) 1889 uart_unregister_driver(&pch_uart_driver); 1890 1891 return ret; 1892 } 1893 module_init(pch_uart_module_init); 1894 1895 static void __exit pch_uart_module_exit(void) 1896 { 1897 pci_unregister_driver(&pch_uart_pci_driver); 1898 uart_unregister_driver(&pch_uart_driver); 1899 } 1900 module_exit(pch_uart_module_exit); 1901 1902 MODULE_LICENSE("GPL v2"); 1903 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); 1904 module_param(default_baud, uint, S_IRUGO); 1905 MODULE_PARM_DESC(default_baud, 1906 "Default BAUD for initial driver state and console (default 9600)"); 1907 module_param(user_uartclk, uint, S_IRUGO); 1908 MODULE_PARM_DESC(user_uartclk, 1909 "Override UART default or board specific UART clock"); 1910