1 /* 2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 3 * 4 *This program is free software; you can redistribute it and/or modify 5 *it under the terms of the GNU General Public License as published by 6 *the Free Software Foundation; version 2 of the License. 7 * 8 *This program is distributed in the hope that it will be useful, 9 *but WITHOUT ANY WARRANTY; without even the implied warranty of 10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 *GNU General Public License for more details. 12 * 13 *You should have received a copy of the GNU General Public License 14 *along with this program; if not, write to the Free Software 15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 16 */ 17 #include <linux/kernel.h> 18 #include <linux/serial_reg.h> 19 #include <linux/slab.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/serial_core.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/dmi.h> 28 #include <linux/console.h> 29 #include <linux/nmi.h> 30 #include <linux/delay.h> 31 32 #include <linux/debugfs.h> 33 #include <linux/dmaengine.h> 34 #include <linux/pch_dma.h> 35 36 enum { 37 PCH_UART_HANDLED_RX_INT_SHIFT, 38 PCH_UART_HANDLED_TX_INT_SHIFT, 39 PCH_UART_HANDLED_RX_ERR_INT_SHIFT, 40 PCH_UART_HANDLED_RX_TRG_INT_SHIFT, 41 PCH_UART_HANDLED_MS_INT_SHIFT, 42 PCH_UART_HANDLED_LS_INT_SHIFT, 43 }; 44 45 enum { 46 PCH_UART_8LINE, 47 PCH_UART_2LINE, 48 }; 49 50 #define PCH_UART_DRIVER_DEVICE "ttyPCH" 51 52 /* Set the max number of UART port 53 * Intel EG20T PCH: 4 port 54 * LAPIS Semiconductor ML7213 IOH: 3 port 55 * LAPIS Semiconductor ML7223 IOH: 2 port 56 */ 57 #define PCH_UART_NR 4 58 59 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) 60 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) 61 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ 62 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) 63 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ 64 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) 65 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) 66 67 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1)) 68 69 #define PCH_UART_RBR 0x00 70 #define PCH_UART_THR 0x00 71 72 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ 73 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) 74 #define PCH_UART_IER_ERBFI 0x00000001 75 #define PCH_UART_IER_ETBEI 0x00000002 76 #define PCH_UART_IER_ELSI 0x00000004 77 #define PCH_UART_IER_EDSSI 0x00000008 78 79 #define PCH_UART_IIR_IP 0x00000001 80 #define PCH_UART_IIR_IID 0x00000006 81 #define PCH_UART_IIR_MSI 0x00000000 82 #define PCH_UART_IIR_TRI 0x00000002 83 #define PCH_UART_IIR_RRI 0x00000004 84 #define PCH_UART_IIR_REI 0x00000006 85 #define PCH_UART_IIR_TOI 0x00000008 86 #define PCH_UART_IIR_FIFO256 0x00000020 87 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 88 #define PCH_UART_IIR_FE 0x000000C0 89 90 #define PCH_UART_FCR_FIFOE 0x00000001 91 #define PCH_UART_FCR_RFR 0x00000002 92 #define PCH_UART_FCR_TFR 0x00000004 93 #define PCH_UART_FCR_DMS 0x00000008 94 #define PCH_UART_FCR_FIFO256 0x00000020 95 #define PCH_UART_FCR_RFTL 0x000000C0 96 97 #define PCH_UART_FCR_RFTL1 0x00000000 98 #define PCH_UART_FCR_RFTL64 0x00000040 99 #define PCH_UART_FCR_RFTL128 0x00000080 100 #define PCH_UART_FCR_RFTL224 0x000000C0 101 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 102 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 103 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 104 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 105 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 106 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 107 #define PCH_UART_FCR_RFTL_SHIFT 6 108 109 #define PCH_UART_LCR_WLS 0x00000003 110 #define PCH_UART_LCR_STB 0x00000004 111 #define PCH_UART_LCR_PEN 0x00000008 112 #define PCH_UART_LCR_EPS 0x00000010 113 #define PCH_UART_LCR_SP 0x00000020 114 #define PCH_UART_LCR_SB 0x00000040 115 #define PCH_UART_LCR_DLAB 0x00000080 116 #define PCH_UART_LCR_NP 0x00000000 117 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN 118 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) 119 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) 120 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ 121 PCH_UART_LCR_SP) 122 123 #define PCH_UART_LCR_5BIT 0x00000000 124 #define PCH_UART_LCR_6BIT 0x00000001 125 #define PCH_UART_LCR_7BIT 0x00000002 126 #define PCH_UART_LCR_8BIT 0x00000003 127 128 #define PCH_UART_MCR_DTR 0x00000001 129 #define PCH_UART_MCR_RTS 0x00000002 130 #define PCH_UART_MCR_OUT 0x0000000C 131 #define PCH_UART_MCR_LOOP 0x00000010 132 #define PCH_UART_MCR_AFE 0x00000020 133 134 #define PCH_UART_LSR_DR 0x00000001 135 #define PCH_UART_LSR_ERR (1<<7) 136 137 #define PCH_UART_MSR_DCTS 0x00000001 138 #define PCH_UART_MSR_DDSR 0x00000002 139 #define PCH_UART_MSR_TERI 0x00000004 140 #define PCH_UART_MSR_DDCD 0x00000008 141 #define PCH_UART_MSR_CTS 0x00000010 142 #define PCH_UART_MSR_DSR 0x00000020 143 #define PCH_UART_MSR_RI 0x00000040 144 #define PCH_UART_MSR_DCD 0x00000080 145 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ 146 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) 147 148 #define PCH_UART_DLL 0x00 149 #define PCH_UART_DLM 0x01 150 151 #define PCH_UART_BRCSR 0x0E 152 153 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) 154 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) 155 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) 156 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) 157 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) 158 159 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) 160 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) 161 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) 162 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) 163 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) 164 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) 165 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) 166 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) 167 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) 168 #define PCH_UART_HAL_STB1 0 169 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) 170 171 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) 172 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) 173 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ 174 PCH_UART_HAL_CLR_RX_FIFO) 175 176 #define PCH_UART_HAL_DMA_MODE0 0 177 #define PCH_UART_HAL_FIFO_DIS 0 178 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) 179 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ 180 PCH_UART_FCR_FIFO256) 181 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) 182 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) 183 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) 184 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) 185 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) 186 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) 187 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) 188 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) 189 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) 190 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) 191 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) 192 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) 193 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) 194 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) 195 196 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) 197 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) 198 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) 199 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) 200 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) 201 202 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) 203 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) 204 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) 205 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) 206 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) 207 208 #define PCI_VENDOR_ID_ROHM 0x10DB 209 210 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 211 212 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */ 213 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */ 214 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */ 215 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */ 216 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */ 217 218 struct pch_uart_buffer { 219 unsigned char *buf; 220 int size; 221 }; 222 223 struct eg20t_port { 224 struct uart_port port; 225 int port_type; 226 void __iomem *membase; 227 resource_size_t mapbase; 228 unsigned int iobase; 229 struct pci_dev *pdev; 230 int fifo_size; 231 int uartclk; 232 int start_tx; 233 int start_rx; 234 int tx_empty; 235 int trigger; 236 int trigger_level; 237 struct pch_uart_buffer rxbuf; 238 unsigned int dmsr; 239 unsigned int fcr; 240 unsigned int mcr; 241 unsigned int use_dma; 242 struct dma_async_tx_descriptor *desc_tx; 243 struct dma_async_tx_descriptor *desc_rx; 244 struct pch_dma_slave param_tx; 245 struct pch_dma_slave param_rx; 246 struct dma_chan *chan_tx; 247 struct dma_chan *chan_rx; 248 struct scatterlist *sg_tx_p; 249 int nent; 250 struct scatterlist sg_rx; 251 int tx_dma_use; 252 void *rx_buf_virt; 253 dma_addr_t rx_buf_dma; 254 255 struct dentry *debugfs; 256 257 /* protect the eg20t_port private structure and io access to membase */ 258 spinlock_t lock; 259 }; 260 261 /** 262 * struct pch_uart_driver_data - private data structure for UART-DMA 263 * @port_type: The number of DMA channel 264 * @line_no: UART port line number (0, 1, 2...) 265 */ 266 struct pch_uart_driver_data { 267 int port_type; 268 int line_no; 269 }; 270 271 enum pch_uart_num_t { 272 pch_et20t_uart0 = 0, 273 pch_et20t_uart1, 274 pch_et20t_uart2, 275 pch_et20t_uart3, 276 pch_ml7213_uart0, 277 pch_ml7213_uart1, 278 pch_ml7213_uart2, 279 pch_ml7223_uart0, 280 pch_ml7223_uart1, 281 pch_ml7831_uart0, 282 pch_ml7831_uart1, 283 }; 284 285 static struct pch_uart_driver_data drv_dat[] = { 286 [pch_et20t_uart0] = {PCH_UART_8LINE, 0}, 287 [pch_et20t_uart1] = {PCH_UART_2LINE, 1}, 288 [pch_et20t_uart2] = {PCH_UART_2LINE, 2}, 289 [pch_et20t_uart3] = {PCH_UART_2LINE, 3}, 290 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0}, 291 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1}, 292 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2}, 293 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0}, 294 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1}, 295 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0}, 296 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1}, 297 }; 298 299 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 300 static struct eg20t_port *pch_uart_ports[PCH_UART_NR]; 301 #endif 302 static unsigned int default_baud = 9600; 303 static unsigned int user_uartclk = 0; 304 static const int trigger_level_256[4] = { 1, 64, 128, 224 }; 305 static const int trigger_level_64[4] = { 1, 16, 32, 56 }; 306 static const int trigger_level_16[4] = { 1, 4, 8, 14 }; 307 static const int trigger_level_1[4] = { 1, 1, 1, 1 }; 308 309 #ifdef CONFIG_DEBUG_FS 310 311 #define PCH_REGS_BUFSIZE 1024 312 313 314 static ssize_t port_show_regs(struct file *file, char __user *user_buf, 315 size_t count, loff_t *ppos) 316 { 317 struct eg20t_port *priv = file->private_data; 318 char *buf; 319 u32 len = 0; 320 ssize_t ret; 321 unsigned char lcr; 322 323 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL); 324 if (!buf) 325 return 0; 326 327 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 328 "PCH EG20T port[%d] regs:\n", priv->port.line); 329 330 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 331 "=================================\n"); 332 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 333 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); 334 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 335 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); 336 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 337 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); 338 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 339 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); 340 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 341 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); 342 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 343 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); 344 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 345 "BRCSR: \t0x%02x\n", 346 ioread8(priv->membase + PCH_UART_BRCSR)); 347 348 lcr = ioread8(priv->membase + UART_LCR); 349 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 350 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 351 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); 352 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 353 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); 354 iowrite8(lcr, priv->membase + UART_LCR); 355 356 if (len > PCH_REGS_BUFSIZE) 357 len = PCH_REGS_BUFSIZE; 358 359 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 360 kfree(buf); 361 return ret; 362 } 363 364 static const struct file_operations port_regs_ops = { 365 .owner = THIS_MODULE, 366 .open = simple_open, 367 .read = port_show_regs, 368 .llseek = default_llseek, 369 }; 370 #endif /* CONFIG_DEBUG_FS */ 371 372 /* Return UART clock, checking for board specific clocks. */ 373 static int pch_uart_get_uartclk(void) 374 { 375 const char *cmp; 376 377 if (user_uartclk) 378 return user_uartclk; 379 380 cmp = dmi_get_system_info(DMI_BOARD_NAME); 381 if (cmp && strstr(cmp, "CM-iTC")) 382 return CMITC_UARTCLK; 383 384 cmp = dmi_get_system_info(DMI_BIOS_VERSION); 385 if (cmp && strnstr(cmp, "FRI2", 4)) 386 return FRI2_64_UARTCLK; 387 388 cmp = dmi_get_system_info(DMI_PRODUCT_NAME); 389 if (cmp && strstr(cmp, "Fish River Island II")) 390 return FRI2_48_UARTCLK; 391 392 /* Kontron COMe-mTT10 (nanoETXexpress-TT) */ 393 cmp = dmi_get_system_info(DMI_BOARD_NAME); 394 if (cmp && (strstr(cmp, "COMe-mTT") || 395 strstr(cmp, "nanoETXexpress-TT"))) 396 return NTC1_UARTCLK; 397 398 return DEFAULT_UARTCLK; 399 } 400 401 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, 402 unsigned int flag) 403 { 404 u8 ier = ioread8(priv->membase + UART_IER); 405 ier |= flag & PCH_UART_IER_MASK; 406 iowrite8(ier, priv->membase + UART_IER); 407 } 408 409 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, 410 unsigned int flag) 411 { 412 u8 ier = ioread8(priv->membase + UART_IER); 413 ier &= ~(flag & PCH_UART_IER_MASK); 414 iowrite8(ier, priv->membase + UART_IER); 415 } 416 417 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud, 418 unsigned int parity, unsigned int bits, 419 unsigned int stb) 420 { 421 unsigned int dll, dlm, lcr; 422 int div; 423 424 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); 425 if (div < 0 || USHRT_MAX <= div) { 426 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); 427 return -EINVAL; 428 } 429 430 dll = (unsigned int)div & 0x00FFU; 431 dlm = ((unsigned int)div >> 8) & 0x00FFU; 432 433 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { 434 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); 435 return -EINVAL; 436 } 437 438 if (bits & ~PCH_UART_LCR_WLS) { 439 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); 440 return -EINVAL; 441 } 442 443 if (stb & ~PCH_UART_LCR_STB) { 444 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); 445 return -EINVAL; 446 } 447 448 lcr = parity; 449 lcr |= bits; 450 lcr |= stb; 451 452 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n", 453 __func__, baud, div, lcr, jiffies); 454 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 455 iowrite8(dll, priv->membase + PCH_UART_DLL); 456 iowrite8(dlm, priv->membase + PCH_UART_DLM); 457 iowrite8(lcr, priv->membase + UART_LCR); 458 459 return 0; 460 } 461 462 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, 463 unsigned int flag) 464 { 465 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { 466 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", 467 __func__, flag); 468 return -EINVAL; 469 } 470 471 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); 472 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, 473 priv->membase + UART_FCR); 474 iowrite8(priv->fcr, priv->membase + UART_FCR); 475 476 return 0; 477 } 478 479 static int pch_uart_hal_set_fifo(struct eg20t_port *priv, 480 unsigned int dmamode, 481 unsigned int fifo_size, unsigned int trigger) 482 { 483 u8 fcr; 484 485 if (dmamode & ~PCH_UART_FCR_DMS) { 486 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", 487 __func__, dmamode); 488 return -EINVAL; 489 } 490 491 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { 492 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", 493 __func__, fifo_size); 494 return -EINVAL; 495 } 496 497 if (trigger & ~PCH_UART_FCR_RFTL) { 498 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", 499 __func__, trigger); 500 return -EINVAL; 501 } 502 503 switch (priv->fifo_size) { 504 case 256: 505 priv->trigger_level = 506 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 507 break; 508 case 64: 509 priv->trigger_level = 510 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 511 break; 512 case 16: 513 priv->trigger_level = 514 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 515 break; 516 default: 517 priv->trigger_level = 518 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 519 break; 520 } 521 fcr = 522 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; 523 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); 524 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, 525 priv->membase + UART_FCR); 526 iowrite8(fcr, priv->membase + UART_FCR); 527 priv->fcr = fcr; 528 529 return 0; 530 } 531 532 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) 533 { 534 unsigned int msr = ioread8(priv->membase + UART_MSR); 535 priv->dmsr = msr & PCH_UART_MSR_DELTA; 536 return (u8)msr; 537 } 538 539 static void pch_uart_hal_write(struct eg20t_port *priv, 540 const unsigned char *buf, int tx_size) 541 { 542 int i; 543 unsigned int thr; 544 545 for (i = 0; i < tx_size;) { 546 thr = buf[i++]; 547 iowrite8(thr, priv->membase + PCH_UART_THR); 548 } 549 } 550 551 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, 552 int rx_size) 553 { 554 int i; 555 u8 rbr, lsr; 556 557 lsr = ioread8(priv->membase + UART_LSR); 558 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); 559 i < rx_size && lsr & UART_LSR_DR; 560 lsr = ioread8(priv->membase + UART_LSR)) { 561 rbr = ioread8(priv->membase + PCH_UART_RBR); 562 buf[i++] = rbr; 563 } 564 return i; 565 } 566 567 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv) 568 { 569 return ioread8(priv->membase + UART_IIR) &\ 570 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP); 571 } 572 573 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) 574 { 575 return ioread8(priv->membase + UART_LSR); 576 } 577 578 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) 579 { 580 unsigned int lcr; 581 582 lcr = ioread8(priv->membase + UART_LCR); 583 if (on) 584 lcr |= PCH_UART_LCR_SB; 585 else 586 lcr &= ~PCH_UART_LCR_SB; 587 588 iowrite8(lcr, priv->membase + UART_LCR); 589 } 590 591 static int push_rx(struct eg20t_port *priv, const unsigned char *buf, 592 int size) 593 { 594 struct uart_port *port; 595 struct tty_struct *tty; 596 597 port = &priv->port; 598 tty = tty_port_tty_get(&port->state->port); 599 if (!tty) { 600 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 601 return -EBUSY; 602 } 603 604 tty_insert_flip_string(tty, buf, size); 605 tty_flip_buffer_push(tty); 606 tty_kref_put(tty); 607 608 return 0; 609 } 610 611 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) 612 { 613 int ret = 0; 614 struct uart_port *port = &priv->port; 615 616 if (port->x_char) { 617 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n", 618 __func__, port->x_char, jiffies); 619 buf[0] = port->x_char; 620 port->x_char = 0; 621 ret = 1; 622 } 623 624 return ret; 625 } 626 627 static int dma_push_rx(struct eg20t_port *priv, int size) 628 { 629 struct tty_struct *tty; 630 int room; 631 struct uart_port *port = &priv->port; 632 633 port = &priv->port; 634 tty = tty_port_tty_get(&port->state->port); 635 if (!tty) { 636 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 637 return 0; 638 } 639 640 room = tty_buffer_request_room(tty, size); 641 642 if (room < size) 643 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 644 size - room); 645 if (!room) 646 return room; 647 648 tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size); 649 650 port->icount.rx += room; 651 tty_kref_put(tty); 652 653 return room; 654 } 655 656 static void pch_free_dma(struct uart_port *port) 657 { 658 struct eg20t_port *priv; 659 priv = container_of(port, struct eg20t_port, port); 660 661 if (priv->chan_tx) { 662 dma_release_channel(priv->chan_tx); 663 priv->chan_tx = NULL; 664 } 665 if (priv->chan_rx) { 666 dma_release_channel(priv->chan_rx); 667 priv->chan_rx = NULL; 668 } 669 670 if (priv->rx_buf_dma) { 671 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt, 672 priv->rx_buf_dma); 673 priv->rx_buf_virt = NULL; 674 priv->rx_buf_dma = 0; 675 } 676 677 return; 678 } 679 680 static bool filter(struct dma_chan *chan, void *slave) 681 { 682 struct pch_dma_slave *param = slave; 683 684 if ((chan->chan_id == param->chan_id) && (param->dma_dev == 685 chan->device->dev)) { 686 chan->private = param; 687 return true; 688 } else { 689 return false; 690 } 691 } 692 693 static void pch_request_dma(struct uart_port *port) 694 { 695 dma_cap_mask_t mask; 696 struct dma_chan *chan; 697 struct pci_dev *dma_dev; 698 struct pch_dma_slave *param; 699 struct eg20t_port *priv = 700 container_of(port, struct eg20t_port, port); 701 dma_cap_zero(mask); 702 dma_cap_set(DMA_SLAVE, mask); 703 704 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number, 705 PCI_DEVFN(0xa, 0)); /* Get DMA's dev 706 information */ 707 /* Set Tx DMA */ 708 param = &priv->param_tx; 709 param->dma_dev = &dma_dev->dev; 710 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ 711 712 param->tx_reg = port->mapbase + UART_TX; 713 chan = dma_request_channel(mask, filter, param); 714 if (!chan) { 715 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", 716 __func__); 717 return; 718 } 719 priv->chan_tx = chan; 720 721 /* Set Rx DMA */ 722 param = &priv->param_rx; 723 param->dma_dev = &dma_dev->dev; 724 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ 725 726 param->rx_reg = port->mapbase + UART_RX; 727 chan = dma_request_channel(mask, filter, param); 728 if (!chan) { 729 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", 730 __func__); 731 dma_release_channel(priv->chan_tx); 732 priv->chan_tx = NULL; 733 return; 734 } 735 736 /* Get Consistent memory for DMA */ 737 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, 738 &priv->rx_buf_dma, GFP_KERNEL); 739 priv->chan_rx = chan; 740 } 741 742 static void pch_dma_rx_complete(void *arg) 743 { 744 struct eg20t_port *priv = arg; 745 struct uart_port *port = &priv->port; 746 struct tty_struct *tty = tty_port_tty_get(&port->state->port); 747 int count; 748 749 if (!tty) { 750 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 751 return; 752 } 753 754 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); 755 count = dma_push_rx(priv, priv->trigger_level); 756 if (count) 757 tty_flip_buffer_push(tty); 758 tty_kref_put(tty); 759 async_tx_ack(priv->desc_rx); 760 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT); 761 } 762 763 static void pch_dma_tx_complete(void *arg) 764 { 765 struct eg20t_port *priv = arg; 766 struct uart_port *port = &priv->port; 767 struct circ_buf *xmit = &port->state->xmit; 768 struct scatterlist *sg = priv->sg_tx_p; 769 int i; 770 771 for (i = 0; i < priv->nent; i++, sg++) { 772 xmit->tail += sg_dma_len(sg); 773 port->icount.tx += sg_dma_len(sg); 774 } 775 xmit->tail &= UART_XMIT_SIZE - 1; 776 async_tx_ack(priv->desc_tx); 777 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE); 778 priv->tx_dma_use = 0; 779 priv->nent = 0; 780 kfree(priv->sg_tx_p); 781 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 782 } 783 784 static int pop_tx(struct eg20t_port *priv, int size) 785 { 786 int count = 0; 787 struct uart_port *port = &priv->port; 788 struct circ_buf *xmit = &port->state->xmit; 789 790 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size) 791 goto pop_tx_end; 792 793 do { 794 int cnt_to_end = 795 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 796 int sz = min(size - count, cnt_to_end); 797 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz); 798 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1); 799 count += sz; 800 } while (!uart_circ_empty(xmit) && count < size); 801 802 pop_tx_end: 803 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n", 804 count, size - count, jiffies); 805 806 return count; 807 } 808 809 static int handle_rx_to(struct eg20t_port *priv) 810 { 811 struct pch_uart_buffer *buf; 812 int rx_size; 813 int ret; 814 if (!priv->start_rx) { 815 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT); 816 return 0; 817 } 818 buf = &priv->rxbuf; 819 do { 820 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); 821 ret = push_rx(priv, buf->buf, rx_size); 822 if (ret) 823 return 0; 824 } while (rx_size == buf->size); 825 826 return PCH_UART_HANDLED_RX_INT; 827 } 828 829 static int handle_rx(struct eg20t_port *priv) 830 { 831 return handle_rx_to(priv); 832 } 833 834 static int dma_handle_rx(struct eg20t_port *priv) 835 { 836 struct uart_port *port = &priv->port; 837 struct dma_async_tx_descriptor *desc; 838 struct scatterlist *sg; 839 840 priv = container_of(port, struct eg20t_port, port); 841 sg = &priv->sg_rx; 842 843 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ 844 845 sg_dma_len(sg) = priv->trigger_level; 846 847 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), 848 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt & 849 ~PAGE_MASK); 850 851 sg_dma_address(sg) = priv->rx_buf_dma; 852 853 desc = dmaengine_prep_slave_sg(priv->chan_rx, 854 sg, 1, DMA_DEV_TO_MEM, 855 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 856 857 if (!desc) 858 return 0; 859 860 priv->desc_rx = desc; 861 desc->callback = pch_dma_rx_complete; 862 desc->callback_param = priv; 863 desc->tx_submit(desc); 864 dma_async_issue_pending(priv->chan_rx); 865 866 return PCH_UART_HANDLED_RX_INT; 867 } 868 869 static unsigned int handle_tx(struct eg20t_port *priv) 870 { 871 struct uart_port *port = &priv->port; 872 struct circ_buf *xmit = &port->state->xmit; 873 int fifo_size; 874 int tx_size; 875 int size; 876 int tx_empty; 877 878 if (!priv->start_tx) { 879 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 880 __func__, jiffies); 881 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 882 priv->tx_empty = 1; 883 return 0; 884 } 885 886 fifo_size = max(priv->fifo_size, 1); 887 tx_empty = 1; 888 if (pop_tx_x(priv, xmit->buf)) { 889 pch_uart_hal_write(priv, xmit->buf, 1); 890 port->icount.tx++; 891 tx_empty = 0; 892 fifo_size--; 893 } 894 size = min(xmit->head - xmit->tail, fifo_size); 895 if (size < 0) 896 size = fifo_size; 897 898 tx_size = pop_tx(priv, size); 899 if (tx_size > 0) { 900 port->icount.tx += tx_size; 901 tx_empty = 0; 902 } 903 904 priv->tx_empty = tx_empty; 905 906 if (tx_empty) { 907 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 908 uart_write_wakeup(port); 909 } 910 911 return PCH_UART_HANDLED_TX_INT; 912 } 913 914 static unsigned int dma_handle_tx(struct eg20t_port *priv) 915 { 916 struct uart_port *port = &priv->port; 917 struct circ_buf *xmit = &port->state->xmit; 918 struct scatterlist *sg; 919 int nent; 920 int fifo_size; 921 int tx_empty; 922 struct dma_async_tx_descriptor *desc; 923 int num; 924 int i; 925 int bytes; 926 int size; 927 int rem; 928 929 if (!priv->start_tx) { 930 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 931 __func__, jiffies); 932 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 933 priv->tx_empty = 1; 934 return 0; 935 } 936 937 if (priv->tx_dma_use) { 938 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", 939 __func__, jiffies); 940 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 941 priv->tx_empty = 1; 942 return 0; 943 } 944 945 fifo_size = max(priv->fifo_size, 1); 946 tx_empty = 1; 947 if (pop_tx_x(priv, xmit->buf)) { 948 pch_uart_hal_write(priv, xmit->buf, 1); 949 port->icount.tx++; 950 tx_empty = 0; 951 fifo_size--; 952 } 953 954 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail, 955 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head, 956 xmit->tail, UART_XMIT_SIZE)); 957 if (!bytes) { 958 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); 959 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 960 uart_write_wakeup(port); 961 return 0; 962 } 963 964 if (bytes > fifo_size) { 965 num = bytes / fifo_size + 1; 966 size = fifo_size; 967 rem = bytes % fifo_size; 968 } else { 969 num = 1; 970 size = bytes; 971 rem = bytes; 972 } 973 974 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", 975 __func__, num, size, rem); 976 977 priv->tx_dma_use = 1; 978 979 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); 980 981 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ 982 sg = priv->sg_tx_p; 983 984 for (i = 0; i < num; i++, sg++) { 985 if (i == (num - 1)) 986 sg_set_page(sg, virt_to_page(xmit->buf), 987 rem, fifo_size * i); 988 else 989 sg_set_page(sg, virt_to_page(xmit->buf), 990 size, fifo_size * i); 991 } 992 993 sg = priv->sg_tx_p; 994 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); 995 if (!nent) { 996 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); 997 return 0; 998 } 999 priv->nent = nent; 1000 1001 for (i = 0; i < nent; i++, sg++) { 1002 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + 1003 fifo_size * i; 1004 sg_dma_address(sg) = (sg_dma_address(sg) & 1005 ~(UART_XMIT_SIZE - 1)) + sg->offset; 1006 if (i == (nent - 1)) 1007 sg_dma_len(sg) = rem; 1008 else 1009 sg_dma_len(sg) = size; 1010 } 1011 1012 desc = dmaengine_prep_slave_sg(priv->chan_tx, 1013 priv->sg_tx_p, nent, DMA_MEM_TO_DEV, 1014 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1015 if (!desc) { 1016 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n", 1017 __func__); 1018 return 0; 1019 } 1020 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); 1021 priv->desc_tx = desc; 1022 desc->callback = pch_dma_tx_complete; 1023 desc->callback_param = priv; 1024 1025 desc->tx_submit(desc); 1026 1027 dma_async_issue_pending(priv->chan_tx); 1028 1029 return PCH_UART_HANDLED_TX_INT; 1030 } 1031 1032 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) 1033 { 1034 u8 fcr = ioread8(priv->membase + UART_FCR); 1035 1036 /* Reset FIFO */ 1037 fcr |= UART_FCR_CLEAR_RCVR; 1038 iowrite8(fcr, priv->membase + UART_FCR); 1039 1040 if (lsr & PCH_UART_LSR_ERR) 1041 dev_err(&priv->pdev->dev, "Error data in FIFO\n"); 1042 1043 if (lsr & UART_LSR_FE) 1044 dev_err(&priv->pdev->dev, "Framing Error\n"); 1045 1046 if (lsr & UART_LSR_PE) 1047 dev_err(&priv->pdev->dev, "Parity Error\n"); 1048 1049 if (lsr & UART_LSR_OE) 1050 dev_err(&priv->pdev->dev, "Overrun Error\n"); 1051 } 1052 1053 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) 1054 { 1055 struct eg20t_port *priv = dev_id; 1056 unsigned int handled; 1057 u8 lsr; 1058 int ret = 0; 1059 unsigned char iid; 1060 unsigned long flags; 1061 int next = 1; 1062 u8 msr; 1063 1064 spin_lock_irqsave(&priv->lock, flags); 1065 handled = 0; 1066 while (next) { 1067 iid = pch_uart_hal_get_iid(priv); 1068 if (iid & PCH_UART_IIR_IP) /* No Interrupt */ 1069 break; 1070 switch (iid) { 1071 case PCH_UART_IID_RLS: /* Receiver Line Status */ 1072 lsr = pch_uart_hal_get_line_status(priv); 1073 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | 1074 UART_LSR_PE | UART_LSR_OE)) { 1075 pch_uart_err_ir(priv, lsr); 1076 ret = PCH_UART_HANDLED_RX_ERR_INT; 1077 } else { 1078 ret = PCH_UART_HANDLED_LS_INT; 1079 } 1080 break; 1081 case PCH_UART_IID_RDR: /* Received Data Ready */ 1082 if (priv->use_dma) { 1083 pch_uart_hal_disable_interrupt(priv, 1084 PCH_UART_HAL_RX_INT); 1085 ret = dma_handle_rx(priv); 1086 if (!ret) 1087 pch_uart_hal_enable_interrupt(priv, 1088 PCH_UART_HAL_RX_INT); 1089 } else { 1090 ret = handle_rx(priv); 1091 } 1092 break; 1093 case PCH_UART_IID_RDR_TO: /* Received Data Ready 1094 (FIFO Timeout) */ 1095 ret = handle_rx_to(priv); 1096 break; 1097 case PCH_UART_IID_THRE: /* Transmitter Holding Register 1098 Empty */ 1099 if (priv->use_dma) 1100 ret = dma_handle_tx(priv); 1101 else 1102 ret = handle_tx(priv); 1103 break; 1104 case PCH_UART_IID_MS: /* Modem Status */ 1105 msr = pch_uart_hal_get_modem(priv); 1106 next = 0; /* MS ir prioirty is the lowest. So, MS ir 1107 means final interrupt */ 1108 if ((msr & UART_MSR_ANY_DELTA) == 0) 1109 break; 1110 ret |= PCH_UART_HANDLED_MS_INT; 1111 break; 1112 default: /* Never junp to this label */ 1113 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__, 1114 iid, jiffies); 1115 ret = -1; 1116 next = 0; 1117 break; 1118 } 1119 handled |= (unsigned int)ret; 1120 } 1121 1122 spin_unlock_irqrestore(&priv->lock, flags); 1123 return IRQ_RETVAL(handled); 1124 } 1125 1126 /* This function tests whether the transmitter fifo and shifter for the port 1127 described by 'port' is empty. */ 1128 static unsigned int pch_uart_tx_empty(struct uart_port *port) 1129 { 1130 struct eg20t_port *priv; 1131 1132 priv = container_of(port, struct eg20t_port, port); 1133 if (priv->tx_empty) 1134 return TIOCSER_TEMT; 1135 else 1136 return 0; 1137 } 1138 1139 /* Returns the current state of modem control inputs. */ 1140 static unsigned int pch_uart_get_mctrl(struct uart_port *port) 1141 { 1142 struct eg20t_port *priv; 1143 u8 modem; 1144 unsigned int ret = 0; 1145 1146 priv = container_of(port, struct eg20t_port, port); 1147 modem = pch_uart_hal_get_modem(priv); 1148 1149 if (modem & UART_MSR_DCD) 1150 ret |= TIOCM_CAR; 1151 1152 if (modem & UART_MSR_RI) 1153 ret |= TIOCM_RNG; 1154 1155 if (modem & UART_MSR_DSR) 1156 ret |= TIOCM_DSR; 1157 1158 if (modem & UART_MSR_CTS) 1159 ret |= TIOCM_CTS; 1160 1161 return ret; 1162 } 1163 1164 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1165 { 1166 u32 mcr = 0; 1167 struct eg20t_port *priv = container_of(port, struct eg20t_port, port); 1168 1169 if (mctrl & TIOCM_DTR) 1170 mcr |= UART_MCR_DTR; 1171 if (mctrl & TIOCM_RTS) 1172 mcr |= UART_MCR_RTS; 1173 if (mctrl & TIOCM_LOOP) 1174 mcr |= UART_MCR_LOOP; 1175 1176 if (priv->mcr & UART_MCR_AFE) 1177 mcr |= UART_MCR_AFE; 1178 1179 if (mctrl) 1180 iowrite8(mcr, priv->membase + UART_MCR); 1181 } 1182 1183 static void pch_uart_stop_tx(struct uart_port *port) 1184 { 1185 struct eg20t_port *priv; 1186 priv = container_of(port, struct eg20t_port, port); 1187 priv->start_tx = 0; 1188 priv->tx_dma_use = 0; 1189 } 1190 1191 static void pch_uart_start_tx(struct uart_port *port) 1192 { 1193 struct eg20t_port *priv; 1194 1195 priv = container_of(port, struct eg20t_port, port); 1196 1197 if (priv->use_dma) { 1198 if (priv->tx_dma_use) { 1199 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", 1200 __func__); 1201 return; 1202 } 1203 } 1204 1205 priv->start_tx = 1; 1206 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 1207 } 1208 1209 static void pch_uart_stop_rx(struct uart_port *port) 1210 { 1211 struct eg20t_port *priv; 1212 priv = container_of(port, struct eg20t_port, port); 1213 priv->start_rx = 0; 1214 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT); 1215 } 1216 1217 /* Enable the modem status interrupts. */ 1218 static void pch_uart_enable_ms(struct uart_port *port) 1219 { 1220 struct eg20t_port *priv; 1221 priv = container_of(port, struct eg20t_port, port); 1222 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); 1223 } 1224 1225 /* Control the transmission of a break signal. */ 1226 static void pch_uart_break_ctl(struct uart_port *port, int ctl) 1227 { 1228 struct eg20t_port *priv; 1229 unsigned long flags; 1230 1231 priv = container_of(port, struct eg20t_port, port); 1232 spin_lock_irqsave(&priv->lock, flags); 1233 pch_uart_hal_set_break(priv, ctl); 1234 spin_unlock_irqrestore(&priv->lock, flags); 1235 } 1236 1237 /* Grab any interrupt resources and initialise any low level driver state. */ 1238 static int pch_uart_startup(struct uart_port *port) 1239 { 1240 struct eg20t_port *priv; 1241 int ret; 1242 int fifo_size; 1243 int trigger_level; 1244 1245 priv = container_of(port, struct eg20t_port, port); 1246 priv->tx_empty = 1; 1247 1248 if (port->uartclk) 1249 priv->uartclk = port->uartclk; 1250 else 1251 port->uartclk = priv->uartclk; 1252 1253 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1254 ret = pch_uart_hal_set_line(priv, default_baud, 1255 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, 1256 PCH_UART_HAL_STB1); 1257 if (ret) 1258 return ret; 1259 1260 switch (priv->fifo_size) { 1261 case 256: 1262 fifo_size = PCH_UART_HAL_FIFO256; 1263 break; 1264 case 64: 1265 fifo_size = PCH_UART_HAL_FIFO64; 1266 break; 1267 case 16: 1268 fifo_size = PCH_UART_HAL_FIFO16; 1269 case 1: 1270 default: 1271 fifo_size = PCH_UART_HAL_FIFO_DIS; 1272 break; 1273 } 1274 1275 switch (priv->trigger) { 1276 case PCH_UART_HAL_TRIGGER1: 1277 trigger_level = 1; 1278 break; 1279 case PCH_UART_HAL_TRIGGER_L: 1280 trigger_level = priv->fifo_size / 4; 1281 break; 1282 case PCH_UART_HAL_TRIGGER_M: 1283 trigger_level = priv->fifo_size / 2; 1284 break; 1285 case PCH_UART_HAL_TRIGGER_H: 1286 default: 1287 trigger_level = priv->fifo_size - (priv->fifo_size / 8); 1288 break; 1289 } 1290 1291 priv->trigger_level = trigger_level; 1292 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1293 fifo_size, priv->trigger); 1294 if (ret < 0) 1295 return ret; 1296 1297 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, 1298 KBUILD_MODNAME, priv); 1299 if (ret < 0) 1300 return ret; 1301 1302 if (priv->use_dma) 1303 pch_request_dma(port); 1304 1305 priv->start_rx = 1; 1306 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT); 1307 uart_update_timeout(port, CS8, default_baud); 1308 1309 return 0; 1310 } 1311 1312 static void pch_uart_shutdown(struct uart_port *port) 1313 { 1314 struct eg20t_port *priv; 1315 int ret; 1316 1317 priv = container_of(port, struct eg20t_port, port); 1318 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1319 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); 1320 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1321 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); 1322 if (ret) 1323 dev_err(priv->port.dev, 1324 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); 1325 1326 pch_free_dma(port); 1327 1328 free_irq(priv->port.irq, priv); 1329 } 1330 1331 /* Change the port parameters, including word length, parity, stop 1332 *bits. Update read_status_mask and ignore_status_mask to indicate 1333 *the types of events we are interested in receiving. */ 1334 static void pch_uart_set_termios(struct uart_port *port, 1335 struct ktermios *termios, struct ktermios *old) 1336 { 1337 int baud; 1338 int rtn; 1339 unsigned int parity, bits, stb; 1340 struct eg20t_port *priv; 1341 unsigned long flags; 1342 1343 priv = container_of(port, struct eg20t_port, port); 1344 switch (termios->c_cflag & CSIZE) { 1345 case CS5: 1346 bits = PCH_UART_HAL_5BIT; 1347 break; 1348 case CS6: 1349 bits = PCH_UART_HAL_6BIT; 1350 break; 1351 case CS7: 1352 bits = PCH_UART_HAL_7BIT; 1353 break; 1354 default: /* CS8 */ 1355 bits = PCH_UART_HAL_8BIT; 1356 break; 1357 } 1358 if (termios->c_cflag & CSTOPB) 1359 stb = PCH_UART_HAL_STB2; 1360 else 1361 stb = PCH_UART_HAL_STB1; 1362 1363 if (termios->c_cflag & PARENB) { 1364 if (!(termios->c_cflag & PARODD)) 1365 parity = PCH_UART_HAL_PARITY_ODD; 1366 else 1367 parity = PCH_UART_HAL_PARITY_EVEN; 1368 1369 } else 1370 parity = PCH_UART_HAL_PARITY_NONE; 1371 1372 /* Only UART0 has auto hardware flow function */ 1373 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) 1374 priv->mcr |= UART_MCR_AFE; 1375 else 1376 priv->mcr &= ~UART_MCR_AFE; 1377 1378 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 1379 1380 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1381 1382 spin_lock_irqsave(&priv->lock, flags); 1383 spin_lock(&port->lock); 1384 1385 uart_update_timeout(port, termios->c_cflag, baud); 1386 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); 1387 if (rtn) 1388 goto out; 1389 1390 pch_uart_set_mctrl(&priv->port, priv->port.mctrl); 1391 /* Don't rewrite B0 */ 1392 if (tty_termios_baud_rate(termios)) 1393 tty_termios_encode_baud_rate(termios, baud, baud); 1394 1395 out: 1396 spin_unlock(&port->lock); 1397 spin_unlock_irqrestore(&priv->lock, flags); 1398 } 1399 1400 static const char *pch_uart_type(struct uart_port *port) 1401 { 1402 return KBUILD_MODNAME; 1403 } 1404 1405 static void pch_uart_release_port(struct uart_port *port) 1406 { 1407 struct eg20t_port *priv; 1408 1409 priv = container_of(port, struct eg20t_port, port); 1410 pci_iounmap(priv->pdev, priv->membase); 1411 pci_release_regions(priv->pdev); 1412 } 1413 1414 static int pch_uart_request_port(struct uart_port *port) 1415 { 1416 struct eg20t_port *priv; 1417 int ret; 1418 void __iomem *membase; 1419 1420 priv = container_of(port, struct eg20t_port, port); 1421 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); 1422 if (ret < 0) 1423 return -EBUSY; 1424 1425 membase = pci_iomap(priv->pdev, 1, 0); 1426 if (!membase) { 1427 pci_release_regions(priv->pdev); 1428 return -EBUSY; 1429 } 1430 priv->membase = port->membase = membase; 1431 1432 return 0; 1433 } 1434 1435 static void pch_uart_config_port(struct uart_port *port, int type) 1436 { 1437 struct eg20t_port *priv; 1438 1439 priv = container_of(port, struct eg20t_port, port); 1440 if (type & UART_CONFIG_TYPE) { 1441 port->type = priv->port_type; 1442 pch_uart_request_port(port); 1443 } 1444 } 1445 1446 static int pch_uart_verify_port(struct uart_port *port, 1447 struct serial_struct *serinfo) 1448 { 1449 struct eg20t_port *priv; 1450 1451 priv = container_of(port, struct eg20t_port, port); 1452 if (serinfo->flags & UPF_LOW_LATENCY) { 1453 dev_info(priv->port.dev, 1454 "PCH UART : Use PIO Mode (without DMA)\n"); 1455 priv->use_dma = 0; 1456 serinfo->flags &= ~UPF_LOW_LATENCY; 1457 } else { 1458 #ifndef CONFIG_PCH_DMA 1459 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", 1460 __func__); 1461 return -EOPNOTSUPP; 1462 #endif 1463 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n"); 1464 if (!priv->use_dma) 1465 pch_request_dma(port); 1466 priv->use_dma = 1; 1467 } 1468 1469 return 0; 1470 } 1471 1472 static struct uart_ops pch_uart_ops = { 1473 .tx_empty = pch_uart_tx_empty, 1474 .set_mctrl = pch_uart_set_mctrl, 1475 .get_mctrl = pch_uart_get_mctrl, 1476 .stop_tx = pch_uart_stop_tx, 1477 .start_tx = pch_uart_start_tx, 1478 .stop_rx = pch_uart_stop_rx, 1479 .enable_ms = pch_uart_enable_ms, 1480 .break_ctl = pch_uart_break_ctl, 1481 .startup = pch_uart_startup, 1482 .shutdown = pch_uart_shutdown, 1483 .set_termios = pch_uart_set_termios, 1484 /* .pm = pch_uart_pm, Not supported yet */ 1485 /* .set_wake = pch_uart_set_wake, Not supported yet */ 1486 .type = pch_uart_type, 1487 .release_port = pch_uart_release_port, 1488 .request_port = pch_uart_request_port, 1489 .config_port = pch_uart_config_port, 1490 .verify_port = pch_uart_verify_port 1491 }; 1492 1493 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1494 1495 /* 1496 * Wait for transmitter & holding register to empty 1497 */ 1498 static void wait_for_xmitr(struct eg20t_port *up, int bits) 1499 { 1500 unsigned int status, tmout = 10000; 1501 1502 /* Wait up to 10ms for the character(s) to be sent. */ 1503 for (;;) { 1504 status = ioread8(up->membase + UART_LSR); 1505 1506 if ((status & bits) == bits) 1507 break; 1508 if (--tmout == 0) 1509 break; 1510 udelay(1); 1511 } 1512 1513 /* Wait up to 1s for flow control if necessary */ 1514 if (up->port.flags & UPF_CONS_FLOW) { 1515 unsigned int tmout; 1516 for (tmout = 1000000; tmout; tmout--) { 1517 unsigned int msr = ioread8(up->membase + UART_MSR); 1518 if (msr & UART_MSR_CTS) 1519 break; 1520 udelay(1); 1521 touch_nmi_watchdog(); 1522 } 1523 } 1524 } 1525 1526 static void pch_console_putchar(struct uart_port *port, int ch) 1527 { 1528 struct eg20t_port *priv = 1529 container_of(port, struct eg20t_port, port); 1530 1531 wait_for_xmitr(priv, UART_LSR_THRE); 1532 iowrite8(ch, priv->membase + PCH_UART_THR); 1533 } 1534 1535 /* 1536 * Print a string to the serial port trying not to disturb 1537 * any possible real use of the port... 1538 * 1539 * The console_lock must be held when we get here. 1540 */ 1541 static void 1542 pch_console_write(struct console *co, const char *s, unsigned int count) 1543 { 1544 struct eg20t_port *priv; 1545 unsigned long flags; 1546 int priv_locked = 1; 1547 int port_locked = 1; 1548 u8 ier; 1549 1550 priv = pch_uart_ports[co->index]; 1551 1552 touch_nmi_watchdog(); 1553 1554 local_irq_save(flags); 1555 if (priv->port.sysrq) { 1556 spin_lock(&priv->lock); 1557 /* serial8250_handle_port() already took the port lock */ 1558 port_locked = 0; 1559 } else if (oops_in_progress) { 1560 priv_locked = spin_trylock(&priv->lock); 1561 port_locked = spin_trylock(&priv->port.lock); 1562 } else { 1563 spin_lock(&priv->lock); 1564 spin_lock(&priv->port.lock); 1565 } 1566 1567 /* 1568 * First save the IER then disable the interrupts 1569 */ 1570 ier = ioread8(priv->membase + UART_IER); 1571 1572 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1573 1574 uart_console_write(&priv->port, s, count, pch_console_putchar); 1575 1576 /* 1577 * Finally, wait for transmitter to become empty 1578 * and restore the IER 1579 */ 1580 wait_for_xmitr(priv, BOTH_EMPTY); 1581 iowrite8(ier, priv->membase + UART_IER); 1582 1583 if (port_locked) 1584 spin_unlock(&priv->port.lock); 1585 if (priv_locked) 1586 spin_unlock(&priv->lock); 1587 local_irq_restore(flags); 1588 } 1589 1590 static int __init pch_console_setup(struct console *co, char *options) 1591 { 1592 struct uart_port *port; 1593 int baud = default_baud; 1594 int bits = 8; 1595 int parity = 'n'; 1596 int flow = 'n'; 1597 1598 /* 1599 * Check whether an invalid uart number has been specified, and 1600 * if so, search for the first available port that does have 1601 * console support. 1602 */ 1603 if (co->index >= PCH_UART_NR) 1604 co->index = 0; 1605 port = &pch_uart_ports[co->index]->port; 1606 1607 if (!port || (!port->iobase && !port->membase)) 1608 return -ENODEV; 1609 1610 port->uartclk = pch_uart_get_uartclk(); 1611 1612 if (options) 1613 uart_parse_options(options, &baud, &parity, &bits, &flow); 1614 1615 return uart_set_options(port, co, baud, parity, bits, flow); 1616 } 1617 1618 static struct uart_driver pch_uart_driver; 1619 1620 static struct console pch_console = { 1621 .name = PCH_UART_DRIVER_DEVICE, 1622 .write = pch_console_write, 1623 .device = uart_console_device, 1624 .setup = pch_console_setup, 1625 .flags = CON_PRINTBUFFER | CON_ANYTIME, 1626 .index = -1, 1627 .data = &pch_uart_driver, 1628 }; 1629 1630 #define PCH_CONSOLE (&pch_console) 1631 #else 1632 #define PCH_CONSOLE NULL 1633 #endif 1634 1635 static struct uart_driver pch_uart_driver = { 1636 .owner = THIS_MODULE, 1637 .driver_name = KBUILD_MODNAME, 1638 .dev_name = PCH_UART_DRIVER_DEVICE, 1639 .major = 0, 1640 .minor = 0, 1641 .nr = PCH_UART_NR, 1642 .cons = PCH_CONSOLE, 1643 }; 1644 1645 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, 1646 const struct pci_device_id *id) 1647 { 1648 struct eg20t_port *priv; 1649 int ret; 1650 unsigned int iobase; 1651 unsigned int mapbase; 1652 unsigned char *rxbuf; 1653 int fifosize; 1654 int port_type; 1655 struct pch_uart_driver_data *board; 1656 char name[32]; /* for debugfs file name */ 1657 1658 board = &drv_dat[id->driver_data]; 1659 port_type = board->port_type; 1660 1661 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); 1662 if (priv == NULL) 1663 goto init_port_alloc_err; 1664 1665 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); 1666 if (!rxbuf) 1667 goto init_port_free_txbuf; 1668 1669 switch (port_type) { 1670 case PORT_UNKNOWN: 1671 fifosize = 256; /* EG20T/ML7213: UART0 */ 1672 break; 1673 case PORT_8250: 1674 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ 1675 break; 1676 default: 1677 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); 1678 goto init_port_hal_free; 1679 } 1680 1681 pci_enable_msi(pdev); 1682 pci_set_master(pdev); 1683 1684 spin_lock_init(&priv->lock); 1685 1686 iobase = pci_resource_start(pdev, 0); 1687 mapbase = pci_resource_start(pdev, 1); 1688 priv->mapbase = mapbase; 1689 priv->iobase = iobase; 1690 priv->pdev = pdev; 1691 priv->tx_empty = 1; 1692 priv->rxbuf.buf = rxbuf; 1693 priv->rxbuf.size = PAGE_SIZE; 1694 1695 priv->fifo_size = fifosize; 1696 priv->uartclk = pch_uart_get_uartclk(); 1697 priv->port_type = PORT_MAX_8250 + port_type + 1; 1698 priv->port.dev = &pdev->dev; 1699 priv->port.iobase = iobase; 1700 priv->port.membase = NULL; 1701 priv->port.mapbase = mapbase; 1702 priv->port.irq = pdev->irq; 1703 priv->port.iotype = UPIO_PORT; 1704 priv->port.ops = &pch_uart_ops; 1705 priv->port.flags = UPF_BOOT_AUTOCONF; 1706 priv->port.fifosize = fifosize; 1707 priv->port.line = board->line_no; 1708 priv->trigger = PCH_UART_HAL_TRIGGER_M; 1709 1710 spin_lock_init(&priv->port.lock); 1711 1712 pci_set_drvdata(pdev, priv); 1713 priv->trigger_level = 1; 1714 priv->fcr = 0; 1715 1716 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1717 pch_uart_ports[board->line_no] = priv; 1718 #endif 1719 ret = uart_add_one_port(&pch_uart_driver, &priv->port); 1720 if (ret < 0) 1721 goto init_port_hal_free; 1722 1723 #ifdef CONFIG_DEBUG_FS 1724 snprintf(name, sizeof(name), "uart%d_regs", board->line_no); 1725 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO, 1726 NULL, priv, &port_regs_ops); 1727 #endif 1728 1729 return priv; 1730 1731 init_port_hal_free: 1732 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1733 pch_uart_ports[board->line_no] = NULL; 1734 #endif 1735 free_page((unsigned long)rxbuf); 1736 init_port_free_txbuf: 1737 kfree(priv); 1738 init_port_alloc_err: 1739 1740 return NULL; 1741 } 1742 1743 static void pch_uart_exit_port(struct eg20t_port *priv) 1744 { 1745 1746 #ifdef CONFIG_DEBUG_FS 1747 if (priv->debugfs) 1748 debugfs_remove(priv->debugfs); 1749 #endif 1750 uart_remove_one_port(&pch_uart_driver, &priv->port); 1751 pci_set_drvdata(priv->pdev, NULL); 1752 free_page((unsigned long)priv->rxbuf.buf); 1753 } 1754 1755 static void pch_uart_pci_remove(struct pci_dev *pdev) 1756 { 1757 struct eg20t_port *priv = pci_get_drvdata(pdev); 1758 1759 pci_disable_msi(pdev); 1760 1761 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1762 pch_uart_ports[priv->port.line] = NULL; 1763 #endif 1764 pch_uart_exit_port(priv); 1765 pci_disable_device(pdev); 1766 kfree(priv); 1767 return; 1768 } 1769 #ifdef CONFIG_PM 1770 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1771 { 1772 struct eg20t_port *priv = pci_get_drvdata(pdev); 1773 1774 uart_suspend_port(&pch_uart_driver, &priv->port); 1775 1776 pci_save_state(pdev); 1777 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1778 return 0; 1779 } 1780 1781 static int pch_uart_pci_resume(struct pci_dev *pdev) 1782 { 1783 struct eg20t_port *priv = pci_get_drvdata(pdev); 1784 int ret; 1785 1786 pci_set_power_state(pdev, PCI_D0); 1787 pci_restore_state(pdev); 1788 1789 ret = pci_enable_device(pdev); 1790 if (ret) { 1791 dev_err(&pdev->dev, 1792 "%s-pci_enable_device failed(ret=%d) ", __func__, ret); 1793 return ret; 1794 } 1795 1796 uart_resume_port(&pch_uart_driver, &priv->port); 1797 1798 return 0; 1799 } 1800 #else 1801 #define pch_uart_pci_suspend NULL 1802 #define pch_uart_pci_resume NULL 1803 #endif 1804 1805 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = { 1806 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), 1807 .driver_data = pch_et20t_uart0}, 1808 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), 1809 .driver_data = pch_et20t_uart1}, 1810 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), 1811 .driver_data = pch_et20t_uart2}, 1812 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), 1813 .driver_data = pch_et20t_uart3}, 1814 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), 1815 .driver_data = pch_ml7213_uart0}, 1816 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), 1817 .driver_data = pch_ml7213_uart1}, 1818 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), 1819 .driver_data = pch_ml7213_uart2}, 1820 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C), 1821 .driver_data = pch_ml7223_uart0}, 1822 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D), 1823 .driver_data = pch_ml7223_uart1}, 1824 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811), 1825 .driver_data = pch_ml7831_uart0}, 1826 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812), 1827 .driver_data = pch_ml7831_uart1}, 1828 {0,}, 1829 }; 1830 1831 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev, 1832 const struct pci_device_id *id) 1833 { 1834 int ret; 1835 struct eg20t_port *priv; 1836 1837 ret = pci_enable_device(pdev); 1838 if (ret < 0) 1839 goto probe_error; 1840 1841 priv = pch_uart_init_port(pdev, id); 1842 if (!priv) { 1843 ret = -EBUSY; 1844 goto probe_disable_device; 1845 } 1846 pci_set_drvdata(pdev, priv); 1847 1848 return ret; 1849 1850 probe_disable_device: 1851 pci_disable_msi(pdev); 1852 pci_disable_device(pdev); 1853 probe_error: 1854 return ret; 1855 } 1856 1857 static struct pci_driver pch_uart_pci_driver = { 1858 .name = "pch_uart", 1859 .id_table = pch_uart_pci_id, 1860 .probe = pch_uart_pci_probe, 1861 .remove = __devexit_p(pch_uart_pci_remove), 1862 .suspend = pch_uart_pci_suspend, 1863 .resume = pch_uart_pci_resume, 1864 }; 1865 1866 static int __init pch_uart_module_init(void) 1867 { 1868 int ret; 1869 1870 /* register as UART driver */ 1871 ret = uart_register_driver(&pch_uart_driver); 1872 if (ret < 0) 1873 return ret; 1874 1875 /* register as PCI driver */ 1876 ret = pci_register_driver(&pch_uart_pci_driver); 1877 if (ret < 0) 1878 uart_unregister_driver(&pch_uart_driver); 1879 1880 return ret; 1881 } 1882 module_init(pch_uart_module_init); 1883 1884 static void __exit pch_uart_module_exit(void) 1885 { 1886 pci_unregister_driver(&pch_uart_pci_driver); 1887 uart_unregister_driver(&pch_uart_driver); 1888 } 1889 module_exit(pch_uart_module_exit); 1890 1891 MODULE_LICENSE("GPL v2"); 1892 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); 1893 module_param(default_baud, uint, S_IRUGO); 1894 MODULE_PARM_DESC(default_baud, 1895 "Default BAUD for initial driver state and console (default 9600)"); 1896 module_param(user_uartclk, uint, S_IRUGO); 1897 MODULE_PARM_DESC(user_uartclk, 1898 "Override UART default or board specific UART clock"); 1899