1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 4 */ 5 #include <linux/kernel.h> 6 #include <linux/serial_reg.h> 7 #include <linux/slab.h> 8 #include <linux/module.h> 9 #include <linux/pci.h> 10 #include <linux/console.h> 11 #include <linux/serial_core.h> 12 #include <linux/tty.h> 13 #include <linux/tty_flip.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/dmi.h> 17 #include <linux/nmi.h> 18 #include <linux/delay.h> 19 #include <linux/of.h> 20 21 #include <linux/debugfs.h> 22 #include <linux/dmaengine.h> 23 #include <linux/pch_dma.h> 24 25 enum { 26 PCH_UART_HANDLED_RX_INT_SHIFT, 27 PCH_UART_HANDLED_TX_INT_SHIFT, 28 PCH_UART_HANDLED_RX_ERR_INT_SHIFT, 29 PCH_UART_HANDLED_RX_TRG_INT_SHIFT, 30 PCH_UART_HANDLED_MS_INT_SHIFT, 31 PCH_UART_HANDLED_LS_INT_SHIFT, 32 }; 33 34 #define PCH_UART_DRIVER_DEVICE "ttyPCH" 35 36 /* Set the max number of UART port 37 * Intel EG20T PCH: 4 port 38 * LAPIS Semiconductor ML7213 IOH: 3 port 39 * LAPIS Semiconductor ML7223 IOH: 2 port 40 */ 41 #define PCH_UART_NR 4 42 43 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) 44 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) 45 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ 46 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) 47 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ 48 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) 49 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) 50 51 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1)) 52 53 #define PCH_UART_RBR 0x00 54 #define PCH_UART_THR 0x00 55 56 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ 57 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) 58 #define PCH_UART_IER_ERBFI 0x00000001 59 #define PCH_UART_IER_ETBEI 0x00000002 60 #define PCH_UART_IER_ELSI 0x00000004 61 #define PCH_UART_IER_EDSSI 0x00000008 62 63 #define PCH_UART_IIR_IP 0x00000001 64 #define PCH_UART_IIR_IID 0x00000006 65 #define PCH_UART_IIR_MSI 0x00000000 66 #define PCH_UART_IIR_TRI 0x00000002 67 #define PCH_UART_IIR_RRI 0x00000004 68 #define PCH_UART_IIR_REI 0x00000006 69 #define PCH_UART_IIR_TOI 0x00000008 70 #define PCH_UART_IIR_FIFO256 0x00000020 71 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 72 #define PCH_UART_IIR_FE 0x000000C0 73 74 #define PCH_UART_FCR_FIFOE 0x00000001 75 #define PCH_UART_FCR_RFR 0x00000002 76 #define PCH_UART_FCR_TFR 0x00000004 77 #define PCH_UART_FCR_DMS 0x00000008 78 #define PCH_UART_FCR_FIFO256 0x00000020 79 #define PCH_UART_FCR_RFTL 0x000000C0 80 81 #define PCH_UART_FCR_RFTL1 0x00000000 82 #define PCH_UART_FCR_RFTL64 0x00000040 83 #define PCH_UART_FCR_RFTL128 0x00000080 84 #define PCH_UART_FCR_RFTL224 0x000000C0 85 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 86 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 87 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 88 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 89 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 90 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 91 #define PCH_UART_FCR_RFTL_SHIFT 6 92 93 #define PCH_UART_LCR_WLS 0x00000003 94 #define PCH_UART_LCR_STB 0x00000004 95 #define PCH_UART_LCR_PEN 0x00000008 96 #define PCH_UART_LCR_EPS 0x00000010 97 #define PCH_UART_LCR_SP 0x00000020 98 #define PCH_UART_LCR_SB 0x00000040 99 #define PCH_UART_LCR_DLAB 0x00000080 100 #define PCH_UART_LCR_NP 0x00000000 101 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN 102 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) 103 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) 104 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ 105 PCH_UART_LCR_SP) 106 107 #define PCH_UART_LCR_5BIT 0x00000000 108 #define PCH_UART_LCR_6BIT 0x00000001 109 #define PCH_UART_LCR_7BIT 0x00000002 110 #define PCH_UART_LCR_8BIT 0x00000003 111 112 #define PCH_UART_MCR_DTR 0x00000001 113 #define PCH_UART_MCR_RTS 0x00000002 114 #define PCH_UART_MCR_OUT 0x0000000C 115 #define PCH_UART_MCR_LOOP 0x00000010 116 #define PCH_UART_MCR_AFE 0x00000020 117 118 #define PCH_UART_LSR_DR 0x00000001 119 #define PCH_UART_LSR_ERR (1<<7) 120 121 #define PCH_UART_MSR_DCTS 0x00000001 122 #define PCH_UART_MSR_DDSR 0x00000002 123 #define PCH_UART_MSR_TERI 0x00000004 124 #define PCH_UART_MSR_DDCD 0x00000008 125 #define PCH_UART_MSR_CTS 0x00000010 126 #define PCH_UART_MSR_DSR 0x00000020 127 #define PCH_UART_MSR_RI 0x00000040 128 #define PCH_UART_MSR_DCD 0x00000080 129 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ 130 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) 131 132 #define PCH_UART_DLL 0x00 133 #define PCH_UART_DLM 0x01 134 135 #define PCH_UART_BRCSR 0x0E 136 137 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) 138 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) 139 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) 140 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) 141 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) 142 143 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) 144 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) 145 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) 146 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) 147 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) 148 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) 149 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) 150 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) 151 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) 152 #define PCH_UART_HAL_STB1 0 153 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) 154 155 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) 156 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) 157 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ 158 PCH_UART_HAL_CLR_RX_FIFO) 159 160 #define PCH_UART_HAL_DMA_MODE0 0 161 #define PCH_UART_HAL_FIFO_DIS 0 162 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) 163 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ 164 PCH_UART_FCR_FIFO256) 165 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) 166 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) 167 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) 168 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) 169 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) 170 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) 171 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) 172 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) 173 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) 174 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) 175 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) 176 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) 177 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) 178 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) 179 180 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) 181 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) 182 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) 183 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) 184 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) 185 186 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) 187 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) 188 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) 189 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) 190 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) 191 192 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 193 194 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */ 195 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */ 196 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */ 197 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */ 198 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */ 199 #define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */ 200 201 struct pch_uart_buffer { 202 unsigned char *buf; 203 int size; 204 }; 205 206 struct eg20t_port { 207 struct uart_port port; 208 int port_type; 209 void __iomem *membase; 210 resource_size_t mapbase; 211 unsigned int iobase; 212 struct pci_dev *pdev; 213 int fifo_size; 214 unsigned int uartclk; 215 int start_tx; 216 int start_rx; 217 int tx_empty; 218 int trigger; 219 int trigger_level; 220 struct pch_uart_buffer rxbuf; 221 unsigned int dmsr; 222 unsigned int fcr; 223 unsigned int mcr; 224 unsigned int use_dma; 225 struct dma_async_tx_descriptor *desc_tx; 226 struct dma_async_tx_descriptor *desc_rx; 227 struct pch_dma_slave param_tx; 228 struct pch_dma_slave param_rx; 229 struct dma_chan *chan_tx; 230 struct dma_chan *chan_rx; 231 struct scatterlist *sg_tx_p; 232 int nent; 233 int orig_nent; 234 struct scatterlist sg_rx; 235 int tx_dma_use; 236 void *rx_buf_virt; 237 dma_addr_t rx_buf_dma; 238 239 #define IRQ_NAME_SIZE 17 240 char irq_name[IRQ_NAME_SIZE]; 241 242 /* protect the eg20t_port private structure and io access to membase */ 243 spinlock_t lock; 244 }; 245 246 /** 247 * struct pch_uart_driver_data - private data structure for UART-DMA 248 * @port_type: The type of UART port 249 * @line_no: UART port line number (0, 1, 2...) 250 */ 251 struct pch_uart_driver_data { 252 int port_type; 253 int line_no; 254 }; 255 256 enum pch_uart_num_t { 257 pch_et20t_uart0 = 0, 258 pch_et20t_uart1, 259 pch_et20t_uart2, 260 pch_et20t_uart3, 261 pch_ml7213_uart0, 262 pch_ml7213_uart1, 263 pch_ml7213_uart2, 264 pch_ml7223_uart0, 265 pch_ml7223_uart1, 266 pch_ml7831_uart0, 267 pch_ml7831_uart1, 268 }; 269 270 static struct pch_uart_driver_data drv_dat[] = { 271 [pch_et20t_uart0] = {PORT_PCH_8LINE, 0}, 272 [pch_et20t_uart1] = {PORT_PCH_2LINE, 1}, 273 [pch_et20t_uart2] = {PORT_PCH_2LINE, 2}, 274 [pch_et20t_uart3] = {PORT_PCH_2LINE, 3}, 275 [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0}, 276 [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1}, 277 [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2}, 278 [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0}, 279 [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1}, 280 [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0}, 281 [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1}, 282 }; 283 284 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 285 static struct eg20t_port *pch_uart_ports[PCH_UART_NR]; 286 #endif 287 static unsigned int default_baud = 9600; 288 static unsigned int user_uartclk = 0; 289 static const int trigger_level_256[4] = { 1, 64, 128, 224 }; 290 static const int trigger_level_64[4] = { 1, 16, 32, 56 }; 291 static const int trigger_level_16[4] = { 1, 4, 8, 14 }; 292 static const int trigger_level_1[4] = { 1, 1, 1, 1 }; 293 294 #ifdef CONFIG_DEBUG_FS 295 296 #define PCH_REGS_BUFSIZE 1024 297 298 299 static ssize_t port_show_regs(struct file *file, char __user *user_buf, 300 size_t count, loff_t *ppos) 301 { 302 struct eg20t_port *priv = file->private_data; 303 char *buf; 304 u32 len = 0; 305 ssize_t ret; 306 unsigned char lcr; 307 308 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL); 309 if (!buf) 310 return 0; 311 312 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 313 "PCH EG20T port[%d] regs:\n", priv->port.line); 314 315 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 316 "=================================\n"); 317 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 318 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); 319 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 320 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); 321 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 322 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); 323 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 324 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); 325 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 326 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); 327 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 328 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); 329 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 330 "BRCSR: \t0x%02x\n", 331 ioread8(priv->membase + PCH_UART_BRCSR)); 332 333 lcr = ioread8(priv->membase + UART_LCR); 334 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 335 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 336 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); 337 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 338 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); 339 iowrite8(lcr, priv->membase + UART_LCR); 340 341 if (len > PCH_REGS_BUFSIZE) 342 len = PCH_REGS_BUFSIZE; 343 344 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 345 kfree(buf); 346 return ret; 347 } 348 349 static const struct file_operations port_regs_ops = { 350 .owner = THIS_MODULE, 351 .open = simple_open, 352 .read = port_show_regs, 353 .llseek = default_llseek, 354 }; 355 #endif /* CONFIG_DEBUG_FS */ 356 357 static const struct dmi_system_id pch_uart_dmi_table[] = { 358 { 359 .ident = "CM-iTC", 360 { 361 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"), 362 }, 363 (void *)CMITC_UARTCLK, 364 }, 365 { 366 .ident = "FRI2", 367 { 368 DMI_MATCH(DMI_BIOS_VERSION, "FRI2"), 369 }, 370 (void *)FRI2_64_UARTCLK, 371 }, 372 { 373 .ident = "Fish River Island II", 374 { 375 DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"), 376 }, 377 (void *)FRI2_48_UARTCLK, 378 }, 379 { 380 .ident = "COMe-mTT", 381 { 382 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"), 383 }, 384 (void *)NTC1_UARTCLK, 385 }, 386 { 387 .ident = "nanoETXexpress-TT", 388 { 389 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"), 390 }, 391 (void *)NTC1_UARTCLK, 392 }, 393 { 394 .ident = "MinnowBoard", 395 { 396 DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"), 397 }, 398 (void *)MINNOW_UARTCLK, 399 }, 400 { } 401 }; 402 403 /* Return UART clock, checking for board specific clocks. */ 404 static unsigned int pch_uart_get_uartclk(void) 405 { 406 const struct dmi_system_id *d; 407 408 if (user_uartclk) 409 return user_uartclk; 410 411 d = dmi_first_match(pch_uart_dmi_table); 412 if (d) 413 return (unsigned long)d->driver_data; 414 415 return DEFAULT_UARTCLK; 416 } 417 418 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, 419 unsigned int flag) 420 { 421 u8 ier = ioread8(priv->membase + UART_IER); 422 ier |= flag & PCH_UART_IER_MASK; 423 iowrite8(ier, priv->membase + UART_IER); 424 } 425 426 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, 427 unsigned int flag) 428 { 429 u8 ier = ioread8(priv->membase + UART_IER); 430 ier &= ~(flag & PCH_UART_IER_MASK); 431 iowrite8(ier, priv->membase + UART_IER); 432 } 433 434 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud, 435 unsigned int parity, unsigned int bits, 436 unsigned int stb) 437 { 438 unsigned int dll, dlm, lcr; 439 int div; 440 441 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); 442 if (div < 0 || USHRT_MAX <= div) { 443 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); 444 return -EINVAL; 445 } 446 447 dll = (unsigned int)div & 0x00FFU; 448 dlm = ((unsigned int)div >> 8) & 0x00FFU; 449 450 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { 451 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); 452 return -EINVAL; 453 } 454 455 if (bits & ~PCH_UART_LCR_WLS) { 456 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); 457 return -EINVAL; 458 } 459 460 if (stb & ~PCH_UART_LCR_STB) { 461 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); 462 return -EINVAL; 463 } 464 465 lcr = parity; 466 lcr |= bits; 467 lcr |= stb; 468 469 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n", 470 __func__, baud, div, lcr, jiffies); 471 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 472 iowrite8(dll, priv->membase + PCH_UART_DLL); 473 iowrite8(dlm, priv->membase + PCH_UART_DLM); 474 iowrite8(lcr, priv->membase + UART_LCR); 475 476 return 0; 477 } 478 479 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, 480 unsigned int flag) 481 { 482 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { 483 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", 484 __func__, flag); 485 return -EINVAL; 486 } 487 488 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); 489 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, 490 priv->membase + UART_FCR); 491 iowrite8(priv->fcr, priv->membase + UART_FCR); 492 493 return 0; 494 } 495 496 static int pch_uart_hal_set_fifo(struct eg20t_port *priv, 497 unsigned int dmamode, 498 unsigned int fifo_size, unsigned int trigger) 499 { 500 u8 fcr; 501 502 if (dmamode & ~PCH_UART_FCR_DMS) { 503 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", 504 __func__, dmamode); 505 return -EINVAL; 506 } 507 508 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { 509 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", 510 __func__, fifo_size); 511 return -EINVAL; 512 } 513 514 if (trigger & ~PCH_UART_FCR_RFTL) { 515 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", 516 __func__, trigger); 517 return -EINVAL; 518 } 519 520 switch (priv->fifo_size) { 521 case 256: 522 priv->trigger_level = 523 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 524 break; 525 case 64: 526 priv->trigger_level = 527 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 528 break; 529 case 16: 530 priv->trigger_level = 531 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 532 break; 533 default: 534 priv->trigger_level = 535 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 536 break; 537 } 538 fcr = 539 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; 540 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); 541 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, 542 priv->membase + UART_FCR); 543 iowrite8(fcr, priv->membase + UART_FCR); 544 priv->fcr = fcr; 545 546 return 0; 547 } 548 549 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) 550 { 551 unsigned int msr = ioread8(priv->membase + UART_MSR); 552 priv->dmsr = msr & PCH_UART_MSR_DELTA; 553 return (u8)msr; 554 } 555 556 static void pch_uart_hal_write(struct eg20t_port *priv, 557 const unsigned char *buf, int tx_size) 558 { 559 int i; 560 unsigned int thr; 561 562 for (i = 0; i < tx_size;) { 563 thr = buf[i++]; 564 iowrite8(thr, priv->membase + PCH_UART_THR); 565 } 566 } 567 568 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, 569 int rx_size) 570 { 571 int i; 572 u8 rbr, lsr; 573 struct uart_port *port = &priv->port; 574 575 lsr = ioread8(priv->membase + UART_LSR); 576 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); 577 i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI); 578 lsr = ioread8(priv->membase + UART_LSR)) { 579 rbr = ioread8(priv->membase + PCH_UART_RBR); 580 581 if (lsr & UART_LSR_BI) { 582 port->icount.brk++; 583 if (uart_handle_break(port)) 584 continue; 585 } 586 if (uart_handle_sysrq_char(port, rbr)) 587 continue; 588 589 buf[i++] = rbr; 590 } 591 return i; 592 } 593 594 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv) 595 { 596 return ioread8(priv->membase + UART_IIR) &\ 597 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP); 598 } 599 600 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) 601 { 602 return ioread8(priv->membase + UART_LSR); 603 } 604 605 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) 606 { 607 unsigned int lcr; 608 609 lcr = ioread8(priv->membase + UART_LCR); 610 if (on) 611 lcr |= PCH_UART_LCR_SB; 612 else 613 lcr &= ~PCH_UART_LCR_SB; 614 615 iowrite8(lcr, priv->membase + UART_LCR); 616 } 617 618 static int push_rx(struct eg20t_port *priv, const unsigned char *buf, 619 int size) 620 { 621 struct uart_port *port = &priv->port; 622 struct tty_port *tport = &port->state->port; 623 624 tty_insert_flip_string(tport, buf, size); 625 tty_flip_buffer_push(tport); 626 627 return 0; 628 } 629 630 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) 631 { 632 int ret = 0; 633 struct uart_port *port = &priv->port; 634 635 if (port->x_char) { 636 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n", 637 __func__, port->x_char, jiffies); 638 buf[0] = port->x_char; 639 port->x_char = 0; 640 ret = 1; 641 } 642 643 return ret; 644 } 645 646 static int dma_push_rx(struct eg20t_port *priv, int size) 647 { 648 int room; 649 struct uart_port *port = &priv->port; 650 struct tty_port *tport = &port->state->port; 651 652 room = tty_buffer_request_room(tport, size); 653 654 if (room < size) 655 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 656 size - room); 657 if (!room) 658 return 0; 659 660 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size); 661 662 port->icount.rx += room; 663 664 return room; 665 } 666 667 static void pch_free_dma(struct uart_port *port) 668 { 669 struct eg20t_port *priv; 670 priv = container_of(port, struct eg20t_port, port); 671 672 if (priv->chan_tx) { 673 dma_release_channel(priv->chan_tx); 674 priv->chan_tx = NULL; 675 } 676 if (priv->chan_rx) { 677 dma_release_channel(priv->chan_rx); 678 priv->chan_rx = NULL; 679 } 680 681 if (priv->rx_buf_dma) { 682 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt, 683 priv->rx_buf_dma); 684 priv->rx_buf_virt = NULL; 685 priv->rx_buf_dma = 0; 686 } 687 688 return; 689 } 690 691 static bool filter(struct dma_chan *chan, void *slave) 692 { 693 struct pch_dma_slave *param = slave; 694 695 if ((chan->chan_id == param->chan_id) && (param->dma_dev == 696 chan->device->dev)) { 697 chan->private = param; 698 return true; 699 } else { 700 return false; 701 } 702 } 703 704 static void pch_request_dma(struct uart_port *port) 705 { 706 dma_cap_mask_t mask; 707 struct dma_chan *chan; 708 struct pci_dev *dma_dev; 709 struct pch_dma_slave *param; 710 struct eg20t_port *priv = 711 container_of(port, struct eg20t_port, port); 712 dma_cap_zero(mask); 713 dma_cap_set(DMA_SLAVE, mask); 714 715 /* Get DMA's dev information */ 716 dma_dev = pci_get_slot(priv->pdev->bus, 717 PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0)); 718 719 /* Set Tx DMA */ 720 param = &priv->param_tx; 721 param->dma_dev = &dma_dev->dev; 722 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ 723 724 param->tx_reg = port->mapbase + UART_TX; 725 chan = dma_request_channel(mask, filter, param); 726 if (!chan) { 727 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", 728 __func__); 729 return; 730 } 731 priv->chan_tx = chan; 732 733 /* Set Rx DMA */ 734 param = &priv->param_rx; 735 param->dma_dev = &dma_dev->dev; 736 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ 737 738 param->rx_reg = port->mapbase + UART_RX; 739 chan = dma_request_channel(mask, filter, param); 740 if (!chan) { 741 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", 742 __func__); 743 dma_release_channel(priv->chan_tx); 744 priv->chan_tx = NULL; 745 return; 746 } 747 748 /* Get Consistent memory for DMA */ 749 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, 750 &priv->rx_buf_dma, GFP_KERNEL); 751 priv->chan_rx = chan; 752 } 753 754 static void pch_dma_rx_complete(void *arg) 755 { 756 struct eg20t_port *priv = arg; 757 struct uart_port *port = &priv->port; 758 int count; 759 760 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); 761 count = dma_push_rx(priv, priv->trigger_level); 762 if (count) 763 tty_flip_buffer_push(&port->state->port); 764 async_tx_ack(priv->desc_rx); 765 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | 766 PCH_UART_HAL_RX_ERR_INT); 767 } 768 769 static void pch_dma_tx_complete(void *arg) 770 { 771 struct eg20t_port *priv = arg; 772 struct uart_port *port = &priv->port; 773 struct circ_buf *xmit = &port->state->xmit; 774 struct scatterlist *sg = priv->sg_tx_p; 775 int i; 776 777 for (i = 0; i < priv->nent; i++, sg++) { 778 xmit->tail += sg_dma_len(sg); 779 port->icount.tx += sg_dma_len(sg); 780 } 781 xmit->tail &= UART_XMIT_SIZE - 1; 782 async_tx_ack(priv->desc_tx); 783 dma_unmap_sg(port->dev, sg, priv->orig_nent, DMA_TO_DEVICE); 784 priv->tx_dma_use = 0; 785 priv->nent = 0; 786 priv->orig_nent = 0; 787 kfree(priv->sg_tx_p); 788 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 789 } 790 791 static int pop_tx(struct eg20t_port *priv, int size) 792 { 793 int count = 0; 794 struct uart_port *port = &priv->port; 795 struct circ_buf *xmit = &port->state->xmit; 796 797 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size) 798 goto pop_tx_end; 799 800 do { 801 int cnt_to_end = 802 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 803 int sz = min(size - count, cnt_to_end); 804 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz); 805 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1); 806 count += sz; 807 } while (!uart_circ_empty(xmit) && count < size); 808 809 pop_tx_end: 810 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n", 811 count, size - count, jiffies); 812 813 return count; 814 } 815 816 static int handle_rx_to(struct eg20t_port *priv) 817 { 818 struct pch_uart_buffer *buf; 819 int rx_size; 820 int ret; 821 if (!priv->start_rx) { 822 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | 823 PCH_UART_HAL_RX_ERR_INT); 824 return 0; 825 } 826 buf = &priv->rxbuf; 827 do { 828 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); 829 ret = push_rx(priv, buf->buf, rx_size); 830 if (ret) 831 return 0; 832 } while (rx_size == buf->size); 833 834 return PCH_UART_HANDLED_RX_INT; 835 } 836 837 static int handle_rx(struct eg20t_port *priv) 838 { 839 return handle_rx_to(priv); 840 } 841 842 static int dma_handle_rx(struct eg20t_port *priv) 843 { 844 struct uart_port *port = &priv->port; 845 struct dma_async_tx_descriptor *desc; 846 struct scatterlist *sg; 847 848 priv = container_of(port, struct eg20t_port, port); 849 sg = &priv->sg_rx; 850 851 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ 852 853 sg_dma_len(sg) = priv->trigger_level; 854 855 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), 856 sg_dma_len(sg), offset_in_page(priv->rx_buf_virt)); 857 858 sg_dma_address(sg) = priv->rx_buf_dma; 859 860 desc = dmaengine_prep_slave_sg(priv->chan_rx, 861 sg, 1, DMA_DEV_TO_MEM, 862 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 863 864 if (!desc) 865 return 0; 866 867 priv->desc_rx = desc; 868 desc->callback = pch_dma_rx_complete; 869 desc->callback_param = priv; 870 desc->tx_submit(desc); 871 dma_async_issue_pending(priv->chan_rx); 872 873 return PCH_UART_HANDLED_RX_INT; 874 } 875 876 static unsigned int handle_tx(struct eg20t_port *priv) 877 { 878 struct uart_port *port = &priv->port; 879 struct circ_buf *xmit = &port->state->xmit; 880 int fifo_size; 881 int tx_size; 882 int size; 883 int tx_empty; 884 885 if (!priv->start_tx) { 886 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 887 __func__, jiffies); 888 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 889 priv->tx_empty = 1; 890 return 0; 891 } 892 893 fifo_size = max(priv->fifo_size, 1); 894 tx_empty = 1; 895 if (pop_tx_x(priv, xmit->buf)) { 896 pch_uart_hal_write(priv, xmit->buf, 1); 897 port->icount.tx++; 898 tx_empty = 0; 899 fifo_size--; 900 } 901 size = min(xmit->head - xmit->tail, fifo_size); 902 if (size < 0) 903 size = fifo_size; 904 905 tx_size = pop_tx(priv, size); 906 if (tx_size > 0) { 907 port->icount.tx += tx_size; 908 tx_empty = 0; 909 } 910 911 priv->tx_empty = tx_empty; 912 913 if (tx_empty) { 914 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 915 uart_write_wakeup(port); 916 } 917 918 return PCH_UART_HANDLED_TX_INT; 919 } 920 921 static unsigned int dma_handle_tx(struct eg20t_port *priv) 922 { 923 struct uart_port *port = &priv->port; 924 struct circ_buf *xmit = &port->state->xmit; 925 struct scatterlist *sg; 926 int nent; 927 int fifo_size; 928 struct dma_async_tx_descriptor *desc; 929 int num; 930 int i; 931 int bytes; 932 int size; 933 int rem; 934 935 if (!priv->start_tx) { 936 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 937 __func__, jiffies); 938 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 939 priv->tx_empty = 1; 940 return 0; 941 } 942 943 if (priv->tx_dma_use) { 944 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", 945 __func__, jiffies); 946 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 947 priv->tx_empty = 1; 948 return 0; 949 } 950 951 fifo_size = max(priv->fifo_size, 1); 952 if (pop_tx_x(priv, xmit->buf)) { 953 pch_uart_hal_write(priv, xmit->buf, 1); 954 port->icount.tx++; 955 fifo_size--; 956 } 957 958 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail, 959 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head, 960 xmit->tail, UART_XMIT_SIZE)); 961 if (!bytes) { 962 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); 963 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 964 uart_write_wakeup(port); 965 return 0; 966 } 967 968 if (bytes > fifo_size) { 969 num = bytes / fifo_size + 1; 970 size = fifo_size; 971 rem = bytes % fifo_size; 972 } else { 973 num = 1; 974 size = bytes; 975 rem = bytes; 976 } 977 978 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", 979 __func__, num, size, rem); 980 981 priv->tx_dma_use = 1; 982 983 priv->sg_tx_p = kmalloc_array(num, sizeof(struct scatterlist), GFP_ATOMIC); 984 if (!priv->sg_tx_p) { 985 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__); 986 return 0; 987 } 988 989 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ 990 sg = priv->sg_tx_p; 991 992 for (i = 0; i < num; i++, sg++) { 993 if (i == (num - 1)) 994 sg_set_page(sg, virt_to_page(xmit->buf), 995 rem, fifo_size * i); 996 else 997 sg_set_page(sg, virt_to_page(xmit->buf), 998 size, fifo_size * i); 999 } 1000 1001 sg = priv->sg_tx_p; 1002 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); 1003 if (!nent) { 1004 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); 1005 return 0; 1006 } 1007 priv->orig_nent = num; 1008 priv->nent = nent; 1009 1010 for (i = 0; i < nent; i++, sg++) { 1011 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + 1012 fifo_size * i; 1013 sg_dma_address(sg) = (sg_dma_address(sg) & 1014 ~(UART_XMIT_SIZE - 1)) + sg->offset; 1015 if (i == (nent - 1)) 1016 sg_dma_len(sg) = rem; 1017 else 1018 sg_dma_len(sg) = size; 1019 } 1020 1021 desc = dmaengine_prep_slave_sg(priv->chan_tx, 1022 priv->sg_tx_p, nent, DMA_MEM_TO_DEV, 1023 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1024 if (!desc) { 1025 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n", 1026 __func__); 1027 return 0; 1028 } 1029 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); 1030 priv->desc_tx = desc; 1031 desc->callback = pch_dma_tx_complete; 1032 desc->callback_param = priv; 1033 1034 desc->tx_submit(desc); 1035 1036 dma_async_issue_pending(priv->chan_tx); 1037 1038 return PCH_UART_HANDLED_TX_INT; 1039 } 1040 1041 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) 1042 { 1043 struct uart_port *port = &priv->port; 1044 struct tty_struct *tty = tty_port_tty_get(&port->state->port); 1045 char *error_msg[5] = {}; 1046 int i = 0; 1047 1048 if (lsr & PCH_UART_LSR_ERR) 1049 error_msg[i++] = "Error data in FIFO\n"; 1050 1051 if (lsr & UART_LSR_FE) { 1052 port->icount.frame++; 1053 error_msg[i++] = " Framing Error\n"; 1054 } 1055 1056 if (lsr & UART_LSR_PE) { 1057 port->icount.parity++; 1058 error_msg[i++] = " Parity Error\n"; 1059 } 1060 1061 if (lsr & UART_LSR_OE) { 1062 port->icount.overrun++; 1063 error_msg[i++] = " Overrun Error\n"; 1064 } 1065 1066 if (tty == NULL) { 1067 for (i = 0; error_msg[i] != NULL; i++) 1068 dev_err(&priv->pdev->dev, error_msg[i]); 1069 } else { 1070 tty_kref_put(tty); 1071 } 1072 } 1073 1074 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) 1075 { 1076 struct eg20t_port *priv = dev_id; 1077 unsigned int handled; 1078 u8 lsr; 1079 int ret = 0; 1080 unsigned char iid; 1081 unsigned long flags; 1082 int next = 1; 1083 u8 msr; 1084 1085 spin_lock_irqsave(&priv->lock, flags); 1086 handled = 0; 1087 while (next) { 1088 iid = pch_uart_hal_get_iid(priv); 1089 if (iid & PCH_UART_IIR_IP) /* No Interrupt */ 1090 break; 1091 switch (iid) { 1092 case PCH_UART_IID_RLS: /* Receiver Line Status */ 1093 lsr = pch_uart_hal_get_line_status(priv); 1094 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | 1095 UART_LSR_PE | UART_LSR_OE)) { 1096 pch_uart_err_ir(priv, lsr); 1097 ret = PCH_UART_HANDLED_RX_ERR_INT; 1098 } else { 1099 ret = PCH_UART_HANDLED_LS_INT; 1100 } 1101 break; 1102 case PCH_UART_IID_RDR: /* Received Data Ready */ 1103 if (priv->use_dma) { 1104 pch_uart_hal_disable_interrupt(priv, 1105 PCH_UART_HAL_RX_INT | 1106 PCH_UART_HAL_RX_ERR_INT); 1107 ret = dma_handle_rx(priv); 1108 if (!ret) 1109 pch_uart_hal_enable_interrupt(priv, 1110 PCH_UART_HAL_RX_INT | 1111 PCH_UART_HAL_RX_ERR_INT); 1112 } else { 1113 ret = handle_rx(priv); 1114 } 1115 break; 1116 case PCH_UART_IID_RDR_TO: /* Received Data Ready 1117 (FIFO Timeout) */ 1118 ret = handle_rx_to(priv); 1119 break; 1120 case PCH_UART_IID_THRE: /* Transmitter Holding Register 1121 Empty */ 1122 if (priv->use_dma) 1123 ret = dma_handle_tx(priv); 1124 else 1125 ret = handle_tx(priv); 1126 break; 1127 case PCH_UART_IID_MS: /* Modem Status */ 1128 msr = pch_uart_hal_get_modem(priv); 1129 next = 0; /* MS ir prioirty is the lowest. So, MS ir 1130 means final interrupt */ 1131 if ((msr & UART_MSR_ANY_DELTA) == 0) 1132 break; 1133 ret |= PCH_UART_HANDLED_MS_INT; 1134 break; 1135 default: /* Never junp to this label */ 1136 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__, 1137 iid, jiffies); 1138 ret = -1; 1139 next = 0; 1140 break; 1141 } 1142 handled |= (unsigned int)ret; 1143 } 1144 1145 spin_unlock_irqrestore(&priv->lock, flags); 1146 return IRQ_RETVAL(handled); 1147 } 1148 1149 /* This function tests whether the transmitter fifo and shifter for the port 1150 described by 'port' is empty. */ 1151 static unsigned int pch_uart_tx_empty(struct uart_port *port) 1152 { 1153 struct eg20t_port *priv; 1154 1155 priv = container_of(port, struct eg20t_port, port); 1156 if (priv->tx_empty) 1157 return TIOCSER_TEMT; 1158 else 1159 return 0; 1160 } 1161 1162 /* Returns the current state of modem control inputs. */ 1163 static unsigned int pch_uart_get_mctrl(struct uart_port *port) 1164 { 1165 struct eg20t_port *priv; 1166 u8 modem; 1167 unsigned int ret = 0; 1168 1169 priv = container_of(port, struct eg20t_port, port); 1170 modem = pch_uart_hal_get_modem(priv); 1171 1172 if (modem & UART_MSR_DCD) 1173 ret |= TIOCM_CAR; 1174 1175 if (modem & UART_MSR_RI) 1176 ret |= TIOCM_RNG; 1177 1178 if (modem & UART_MSR_DSR) 1179 ret |= TIOCM_DSR; 1180 1181 if (modem & UART_MSR_CTS) 1182 ret |= TIOCM_CTS; 1183 1184 return ret; 1185 } 1186 1187 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1188 { 1189 u32 mcr = 0; 1190 struct eg20t_port *priv = container_of(port, struct eg20t_port, port); 1191 1192 if (mctrl & TIOCM_DTR) 1193 mcr |= UART_MCR_DTR; 1194 if (mctrl & TIOCM_RTS) 1195 mcr |= UART_MCR_RTS; 1196 if (mctrl & TIOCM_LOOP) 1197 mcr |= UART_MCR_LOOP; 1198 1199 if (priv->mcr & UART_MCR_AFE) 1200 mcr |= UART_MCR_AFE; 1201 1202 if (mctrl) 1203 iowrite8(mcr, priv->membase + UART_MCR); 1204 } 1205 1206 static void pch_uart_stop_tx(struct uart_port *port) 1207 { 1208 struct eg20t_port *priv; 1209 priv = container_of(port, struct eg20t_port, port); 1210 priv->start_tx = 0; 1211 priv->tx_dma_use = 0; 1212 } 1213 1214 static void pch_uart_start_tx(struct uart_port *port) 1215 { 1216 struct eg20t_port *priv; 1217 1218 priv = container_of(port, struct eg20t_port, port); 1219 1220 if (priv->use_dma) { 1221 if (priv->tx_dma_use) { 1222 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", 1223 __func__); 1224 return; 1225 } 1226 } 1227 1228 priv->start_tx = 1; 1229 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 1230 } 1231 1232 static void pch_uart_stop_rx(struct uart_port *port) 1233 { 1234 struct eg20t_port *priv; 1235 priv = container_of(port, struct eg20t_port, port); 1236 priv->start_rx = 0; 1237 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | 1238 PCH_UART_HAL_RX_ERR_INT); 1239 } 1240 1241 /* Enable the modem status interrupts. */ 1242 static void pch_uart_enable_ms(struct uart_port *port) 1243 { 1244 struct eg20t_port *priv; 1245 priv = container_of(port, struct eg20t_port, port); 1246 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); 1247 } 1248 1249 /* Control the transmission of a break signal. */ 1250 static void pch_uart_break_ctl(struct uart_port *port, int ctl) 1251 { 1252 struct eg20t_port *priv; 1253 unsigned long flags; 1254 1255 priv = container_of(port, struct eg20t_port, port); 1256 spin_lock_irqsave(&priv->lock, flags); 1257 pch_uart_hal_set_break(priv, ctl); 1258 spin_unlock_irqrestore(&priv->lock, flags); 1259 } 1260 1261 /* Grab any interrupt resources and initialise any low level driver state. */ 1262 static int pch_uart_startup(struct uart_port *port) 1263 { 1264 struct eg20t_port *priv; 1265 int ret; 1266 int fifo_size; 1267 int trigger_level; 1268 1269 priv = container_of(port, struct eg20t_port, port); 1270 priv->tx_empty = 1; 1271 1272 if (port->uartclk) 1273 priv->uartclk = port->uartclk; 1274 else 1275 port->uartclk = priv->uartclk; 1276 1277 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1278 ret = pch_uart_hal_set_line(priv, default_baud, 1279 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, 1280 PCH_UART_HAL_STB1); 1281 if (ret) 1282 return ret; 1283 1284 switch (priv->fifo_size) { 1285 case 256: 1286 fifo_size = PCH_UART_HAL_FIFO256; 1287 break; 1288 case 64: 1289 fifo_size = PCH_UART_HAL_FIFO64; 1290 break; 1291 case 16: 1292 fifo_size = PCH_UART_HAL_FIFO16; 1293 break; 1294 case 1: 1295 default: 1296 fifo_size = PCH_UART_HAL_FIFO_DIS; 1297 break; 1298 } 1299 1300 switch (priv->trigger) { 1301 case PCH_UART_HAL_TRIGGER1: 1302 trigger_level = 1; 1303 break; 1304 case PCH_UART_HAL_TRIGGER_L: 1305 trigger_level = priv->fifo_size / 4; 1306 break; 1307 case PCH_UART_HAL_TRIGGER_M: 1308 trigger_level = priv->fifo_size / 2; 1309 break; 1310 case PCH_UART_HAL_TRIGGER_H: 1311 default: 1312 trigger_level = priv->fifo_size - (priv->fifo_size / 8); 1313 break; 1314 } 1315 1316 priv->trigger_level = trigger_level; 1317 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1318 fifo_size, priv->trigger); 1319 if (ret < 0) 1320 return ret; 1321 1322 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, 1323 priv->irq_name, priv); 1324 if (ret < 0) 1325 return ret; 1326 1327 if (priv->use_dma) 1328 pch_request_dma(port); 1329 1330 priv->start_rx = 1; 1331 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | 1332 PCH_UART_HAL_RX_ERR_INT); 1333 uart_update_timeout(port, CS8, default_baud); 1334 1335 return 0; 1336 } 1337 1338 static void pch_uart_shutdown(struct uart_port *port) 1339 { 1340 struct eg20t_port *priv; 1341 int ret; 1342 1343 priv = container_of(port, struct eg20t_port, port); 1344 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1345 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); 1346 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1347 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); 1348 if (ret) 1349 dev_err(priv->port.dev, 1350 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); 1351 1352 pch_free_dma(port); 1353 1354 free_irq(priv->port.irq, priv); 1355 } 1356 1357 /* Change the port parameters, including word length, parity, stop 1358 *bits. Update read_status_mask and ignore_status_mask to indicate 1359 *the types of events we are interested in receiving. */ 1360 static void pch_uart_set_termios(struct uart_port *port, 1361 struct ktermios *termios, struct ktermios *old) 1362 { 1363 int rtn; 1364 unsigned int baud, parity, bits, stb; 1365 struct eg20t_port *priv; 1366 unsigned long flags; 1367 1368 priv = container_of(port, struct eg20t_port, port); 1369 switch (termios->c_cflag & CSIZE) { 1370 case CS5: 1371 bits = PCH_UART_HAL_5BIT; 1372 break; 1373 case CS6: 1374 bits = PCH_UART_HAL_6BIT; 1375 break; 1376 case CS7: 1377 bits = PCH_UART_HAL_7BIT; 1378 break; 1379 default: /* CS8 */ 1380 bits = PCH_UART_HAL_8BIT; 1381 break; 1382 } 1383 if (termios->c_cflag & CSTOPB) 1384 stb = PCH_UART_HAL_STB2; 1385 else 1386 stb = PCH_UART_HAL_STB1; 1387 1388 if (termios->c_cflag & PARENB) { 1389 if (termios->c_cflag & PARODD) 1390 parity = PCH_UART_HAL_PARITY_ODD; 1391 else 1392 parity = PCH_UART_HAL_PARITY_EVEN; 1393 1394 } else 1395 parity = PCH_UART_HAL_PARITY_NONE; 1396 1397 /* Only UART0 has auto hardware flow function */ 1398 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) 1399 priv->mcr |= UART_MCR_AFE; 1400 else 1401 priv->mcr &= ~UART_MCR_AFE; 1402 1403 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 1404 1405 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1406 1407 spin_lock_irqsave(&priv->lock, flags); 1408 spin_lock(&port->lock); 1409 1410 uart_update_timeout(port, termios->c_cflag, baud); 1411 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); 1412 if (rtn) 1413 goto out; 1414 1415 pch_uart_set_mctrl(&priv->port, priv->port.mctrl); 1416 /* Don't rewrite B0 */ 1417 if (tty_termios_baud_rate(termios)) 1418 tty_termios_encode_baud_rate(termios, baud, baud); 1419 1420 out: 1421 spin_unlock(&port->lock); 1422 spin_unlock_irqrestore(&priv->lock, flags); 1423 } 1424 1425 static const char *pch_uart_type(struct uart_port *port) 1426 { 1427 return KBUILD_MODNAME; 1428 } 1429 1430 static void pch_uart_release_port(struct uart_port *port) 1431 { 1432 struct eg20t_port *priv; 1433 1434 priv = container_of(port, struct eg20t_port, port); 1435 pci_iounmap(priv->pdev, priv->membase); 1436 pci_release_regions(priv->pdev); 1437 } 1438 1439 static int pch_uart_request_port(struct uart_port *port) 1440 { 1441 struct eg20t_port *priv; 1442 int ret; 1443 void __iomem *membase; 1444 1445 priv = container_of(port, struct eg20t_port, port); 1446 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); 1447 if (ret < 0) 1448 return -EBUSY; 1449 1450 membase = pci_iomap(priv->pdev, 1, 0); 1451 if (!membase) { 1452 pci_release_regions(priv->pdev); 1453 return -EBUSY; 1454 } 1455 priv->membase = port->membase = membase; 1456 1457 return 0; 1458 } 1459 1460 static void pch_uart_config_port(struct uart_port *port, int type) 1461 { 1462 struct eg20t_port *priv; 1463 1464 priv = container_of(port, struct eg20t_port, port); 1465 if (type & UART_CONFIG_TYPE) { 1466 port->type = priv->port_type; 1467 pch_uart_request_port(port); 1468 } 1469 } 1470 1471 static int pch_uart_verify_port(struct uart_port *port, 1472 struct serial_struct *serinfo) 1473 { 1474 struct eg20t_port *priv; 1475 1476 priv = container_of(port, struct eg20t_port, port); 1477 if (serinfo->flags & UPF_LOW_LATENCY) { 1478 dev_info(priv->port.dev, 1479 "PCH UART : Use PIO Mode (without DMA)\n"); 1480 priv->use_dma = 0; 1481 serinfo->flags &= ~UPF_LOW_LATENCY; 1482 } else { 1483 #ifndef CONFIG_PCH_DMA 1484 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", 1485 __func__); 1486 return -EOPNOTSUPP; 1487 #endif 1488 if (!priv->use_dma) { 1489 pch_request_dma(port); 1490 if (priv->chan_rx) 1491 priv->use_dma = 1; 1492 } 1493 dev_info(priv->port.dev, "PCH UART: %s\n", 1494 priv->use_dma ? 1495 "Use DMA Mode" : "No DMA"); 1496 } 1497 1498 return 0; 1499 } 1500 1501 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE) 1502 /* 1503 * Wait for transmitter & holding register to empty 1504 */ 1505 static void wait_for_xmitr(struct eg20t_port *up, int bits) 1506 { 1507 unsigned int status, tmout = 10000; 1508 1509 /* Wait up to 10ms for the character(s) to be sent. */ 1510 for (;;) { 1511 status = ioread8(up->membase + UART_LSR); 1512 1513 if ((status & bits) == bits) 1514 break; 1515 if (--tmout == 0) 1516 break; 1517 udelay(1); 1518 } 1519 1520 /* Wait up to 1s for flow control if necessary */ 1521 if (up->port.flags & UPF_CONS_FLOW) { 1522 unsigned int tmout; 1523 for (tmout = 1000000; tmout; tmout--) { 1524 unsigned int msr = ioread8(up->membase + UART_MSR); 1525 if (msr & UART_MSR_CTS) 1526 break; 1527 udelay(1); 1528 touch_nmi_watchdog(); 1529 } 1530 } 1531 } 1532 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */ 1533 1534 #ifdef CONFIG_CONSOLE_POLL 1535 /* 1536 * Console polling routines for communicate via uart while 1537 * in an interrupt or debug context. 1538 */ 1539 static int pch_uart_get_poll_char(struct uart_port *port) 1540 { 1541 struct eg20t_port *priv = 1542 container_of(port, struct eg20t_port, port); 1543 u8 lsr = ioread8(priv->membase + UART_LSR); 1544 1545 if (!(lsr & UART_LSR_DR)) 1546 return NO_POLL_CHAR; 1547 1548 return ioread8(priv->membase + PCH_UART_RBR); 1549 } 1550 1551 1552 static void pch_uart_put_poll_char(struct uart_port *port, 1553 unsigned char c) 1554 { 1555 unsigned int ier; 1556 struct eg20t_port *priv = 1557 container_of(port, struct eg20t_port, port); 1558 1559 /* 1560 * First save the IER then disable the interrupts 1561 */ 1562 ier = ioread8(priv->membase + UART_IER); 1563 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1564 1565 wait_for_xmitr(priv, UART_LSR_THRE); 1566 /* 1567 * Send the character out. 1568 */ 1569 iowrite8(c, priv->membase + PCH_UART_THR); 1570 1571 /* 1572 * Finally, wait for transmitter to become empty 1573 * and restore the IER 1574 */ 1575 wait_for_xmitr(priv, BOTH_EMPTY); 1576 iowrite8(ier, priv->membase + UART_IER); 1577 } 1578 #endif /* CONFIG_CONSOLE_POLL */ 1579 1580 static const struct uart_ops pch_uart_ops = { 1581 .tx_empty = pch_uart_tx_empty, 1582 .set_mctrl = pch_uart_set_mctrl, 1583 .get_mctrl = pch_uart_get_mctrl, 1584 .stop_tx = pch_uart_stop_tx, 1585 .start_tx = pch_uart_start_tx, 1586 .stop_rx = pch_uart_stop_rx, 1587 .enable_ms = pch_uart_enable_ms, 1588 .break_ctl = pch_uart_break_ctl, 1589 .startup = pch_uart_startup, 1590 .shutdown = pch_uart_shutdown, 1591 .set_termios = pch_uart_set_termios, 1592 /* .pm = pch_uart_pm, Not supported yet */ 1593 .type = pch_uart_type, 1594 .release_port = pch_uart_release_port, 1595 .request_port = pch_uart_request_port, 1596 .config_port = pch_uart_config_port, 1597 .verify_port = pch_uart_verify_port, 1598 #ifdef CONFIG_CONSOLE_POLL 1599 .poll_get_char = pch_uart_get_poll_char, 1600 .poll_put_char = pch_uart_put_poll_char, 1601 #endif 1602 }; 1603 1604 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1605 1606 static void pch_console_putchar(struct uart_port *port, int ch) 1607 { 1608 struct eg20t_port *priv = 1609 container_of(port, struct eg20t_port, port); 1610 1611 wait_for_xmitr(priv, UART_LSR_THRE); 1612 iowrite8(ch, priv->membase + PCH_UART_THR); 1613 } 1614 1615 /* 1616 * Print a string to the serial port trying not to disturb 1617 * any possible real use of the port... 1618 * 1619 * The console_lock must be held when we get here. 1620 */ 1621 static void 1622 pch_console_write(struct console *co, const char *s, unsigned int count) 1623 { 1624 struct eg20t_port *priv; 1625 unsigned long flags; 1626 int priv_locked = 1; 1627 int port_locked = 1; 1628 u8 ier; 1629 1630 priv = pch_uart_ports[co->index]; 1631 1632 touch_nmi_watchdog(); 1633 1634 local_irq_save(flags); 1635 if (priv->port.sysrq) { 1636 /* call to uart_handle_sysrq_char already took the priv lock */ 1637 priv_locked = 0; 1638 /* serial8250_handle_port() already took the port lock */ 1639 port_locked = 0; 1640 } else if (oops_in_progress) { 1641 priv_locked = spin_trylock(&priv->lock); 1642 port_locked = spin_trylock(&priv->port.lock); 1643 } else { 1644 spin_lock(&priv->lock); 1645 spin_lock(&priv->port.lock); 1646 } 1647 1648 /* 1649 * First save the IER then disable the interrupts 1650 */ 1651 ier = ioread8(priv->membase + UART_IER); 1652 1653 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1654 1655 uart_console_write(&priv->port, s, count, pch_console_putchar); 1656 1657 /* 1658 * Finally, wait for transmitter to become empty 1659 * and restore the IER 1660 */ 1661 wait_for_xmitr(priv, BOTH_EMPTY); 1662 iowrite8(ier, priv->membase + UART_IER); 1663 1664 if (port_locked) 1665 spin_unlock(&priv->port.lock); 1666 if (priv_locked) 1667 spin_unlock(&priv->lock); 1668 local_irq_restore(flags); 1669 } 1670 1671 static int __init pch_console_setup(struct console *co, char *options) 1672 { 1673 struct uart_port *port; 1674 int baud = default_baud; 1675 int bits = 8; 1676 int parity = 'n'; 1677 int flow = 'n'; 1678 1679 /* 1680 * Check whether an invalid uart number has been specified, and 1681 * if so, search for the first available port that does have 1682 * console support. 1683 */ 1684 if (co->index >= PCH_UART_NR) 1685 co->index = 0; 1686 port = &pch_uart_ports[co->index]->port; 1687 1688 if (!port || (!port->iobase && !port->membase)) 1689 return -ENODEV; 1690 1691 port->uartclk = pch_uart_get_uartclk(); 1692 1693 if (options) 1694 uart_parse_options(options, &baud, &parity, &bits, &flow); 1695 1696 return uart_set_options(port, co, baud, parity, bits, flow); 1697 } 1698 1699 static struct uart_driver pch_uart_driver; 1700 1701 static struct console pch_console = { 1702 .name = PCH_UART_DRIVER_DEVICE, 1703 .write = pch_console_write, 1704 .device = uart_console_device, 1705 .setup = pch_console_setup, 1706 .flags = CON_PRINTBUFFER | CON_ANYTIME, 1707 .index = -1, 1708 .data = &pch_uart_driver, 1709 }; 1710 1711 #define PCH_CONSOLE (&pch_console) 1712 #else 1713 #define PCH_CONSOLE NULL 1714 #endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */ 1715 1716 static struct uart_driver pch_uart_driver = { 1717 .owner = THIS_MODULE, 1718 .driver_name = KBUILD_MODNAME, 1719 .dev_name = PCH_UART_DRIVER_DEVICE, 1720 .major = 0, 1721 .minor = 0, 1722 .nr = PCH_UART_NR, 1723 .cons = PCH_CONSOLE, 1724 }; 1725 1726 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, 1727 const struct pci_device_id *id) 1728 { 1729 struct eg20t_port *priv; 1730 int ret; 1731 unsigned int iobase; 1732 unsigned int mapbase; 1733 unsigned char *rxbuf; 1734 int fifosize; 1735 int port_type; 1736 struct pch_uart_driver_data *board; 1737 char name[32]; 1738 1739 board = &drv_dat[id->driver_data]; 1740 port_type = board->port_type; 1741 1742 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); 1743 if (priv == NULL) 1744 goto init_port_alloc_err; 1745 1746 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); 1747 if (!rxbuf) 1748 goto init_port_free_txbuf; 1749 1750 switch (port_type) { 1751 case PORT_PCH_8LINE: 1752 fifosize = 256; /* EG20T/ML7213: UART0 */ 1753 break; 1754 case PORT_PCH_2LINE: 1755 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ 1756 break; 1757 default: 1758 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); 1759 goto init_port_hal_free; 1760 } 1761 1762 pci_enable_msi(pdev); 1763 pci_set_master(pdev); 1764 1765 spin_lock_init(&priv->lock); 1766 1767 iobase = pci_resource_start(pdev, 0); 1768 mapbase = pci_resource_start(pdev, 1); 1769 priv->mapbase = mapbase; 1770 priv->iobase = iobase; 1771 priv->pdev = pdev; 1772 priv->tx_empty = 1; 1773 priv->rxbuf.buf = rxbuf; 1774 priv->rxbuf.size = PAGE_SIZE; 1775 1776 priv->fifo_size = fifosize; 1777 priv->uartclk = pch_uart_get_uartclk(); 1778 priv->port_type = port_type; 1779 priv->port.dev = &pdev->dev; 1780 priv->port.iobase = iobase; 1781 priv->port.membase = NULL; 1782 priv->port.mapbase = mapbase; 1783 priv->port.irq = pdev->irq; 1784 priv->port.iotype = UPIO_PORT; 1785 priv->port.ops = &pch_uart_ops; 1786 priv->port.flags = UPF_BOOT_AUTOCONF; 1787 priv->port.fifosize = fifosize; 1788 priv->port.line = board->line_no; 1789 priv->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PCH_UART_CONSOLE); 1790 priv->trigger = PCH_UART_HAL_TRIGGER_M; 1791 1792 snprintf(priv->irq_name, IRQ_NAME_SIZE, 1793 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d", 1794 priv->port.line); 1795 1796 spin_lock_init(&priv->port.lock); 1797 1798 pci_set_drvdata(pdev, priv); 1799 priv->trigger_level = 1; 1800 priv->fcr = 0; 1801 1802 if (pdev->dev.of_node) 1803 of_property_read_u32(pdev->dev.of_node, "clock-frequency" 1804 , &user_uartclk); 1805 1806 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1807 pch_uart_ports[board->line_no] = priv; 1808 #endif 1809 ret = uart_add_one_port(&pch_uart_driver, &priv->port); 1810 if (ret < 0) 1811 goto init_port_hal_free; 1812 1813 snprintf(name, sizeof(name), "uart%d_regs", priv->port.line); 1814 debugfs_create_file(name, S_IFREG | S_IRUGO, NULL, priv, 1815 &port_regs_ops); 1816 1817 return priv; 1818 1819 init_port_hal_free: 1820 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1821 pch_uart_ports[board->line_no] = NULL; 1822 #endif 1823 free_page((unsigned long)rxbuf); 1824 init_port_free_txbuf: 1825 kfree(priv); 1826 init_port_alloc_err: 1827 1828 return NULL; 1829 } 1830 1831 static void pch_uart_exit_port(struct eg20t_port *priv) 1832 { 1833 char name[32]; 1834 1835 snprintf(name, sizeof(name), "uart%d_regs", priv->port.line); 1836 debugfs_remove(debugfs_lookup(name, NULL)); 1837 uart_remove_one_port(&pch_uart_driver, &priv->port); 1838 free_page((unsigned long)priv->rxbuf.buf); 1839 } 1840 1841 static void pch_uart_pci_remove(struct pci_dev *pdev) 1842 { 1843 struct eg20t_port *priv = pci_get_drvdata(pdev); 1844 1845 pci_disable_msi(pdev); 1846 1847 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1848 pch_uart_ports[priv->port.line] = NULL; 1849 #endif 1850 pch_uart_exit_port(priv); 1851 pci_disable_device(pdev); 1852 kfree(priv); 1853 return; 1854 } 1855 1856 static int __maybe_unused pch_uart_pci_suspend(struct device *dev) 1857 { 1858 struct eg20t_port *priv = dev_get_drvdata(dev); 1859 1860 uart_suspend_port(&pch_uart_driver, &priv->port); 1861 1862 return 0; 1863 } 1864 1865 static int __maybe_unused pch_uart_pci_resume(struct device *dev) 1866 { 1867 struct eg20t_port *priv = dev_get_drvdata(dev); 1868 1869 uart_resume_port(&pch_uart_driver, &priv->port); 1870 1871 return 0; 1872 } 1873 1874 static const struct pci_device_id pch_uart_pci_id[] = { 1875 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), 1876 .driver_data = pch_et20t_uart0}, 1877 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), 1878 .driver_data = pch_et20t_uart1}, 1879 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), 1880 .driver_data = pch_et20t_uart2}, 1881 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), 1882 .driver_data = pch_et20t_uart3}, 1883 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), 1884 .driver_data = pch_ml7213_uart0}, 1885 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), 1886 .driver_data = pch_ml7213_uart1}, 1887 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), 1888 .driver_data = pch_ml7213_uart2}, 1889 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C), 1890 .driver_data = pch_ml7223_uart0}, 1891 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D), 1892 .driver_data = pch_ml7223_uart1}, 1893 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811), 1894 .driver_data = pch_ml7831_uart0}, 1895 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812), 1896 .driver_data = pch_ml7831_uart1}, 1897 {0,}, 1898 }; 1899 1900 static int pch_uart_pci_probe(struct pci_dev *pdev, 1901 const struct pci_device_id *id) 1902 { 1903 int ret; 1904 struct eg20t_port *priv; 1905 1906 ret = pci_enable_device(pdev); 1907 if (ret < 0) 1908 goto probe_error; 1909 1910 priv = pch_uart_init_port(pdev, id); 1911 if (!priv) { 1912 ret = -EBUSY; 1913 goto probe_disable_device; 1914 } 1915 pci_set_drvdata(pdev, priv); 1916 1917 return ret; 1918 1919 probe_disable_device: 1920 pci_disable_msi(pdev); 1921 pci_disable_device(pdev); 1922 probe_error: 1923 return ret; 1924 } 1925 1926 static SIMPLE_DEV_PM_OPS(pch_uart_pci_pm_ops, 1927 pch_uart_pci_suspend, 1928 pch_uart_pci_resume); 1929 1930 static struct pci_driver pch_uart_pci_driver = { 1931 .name = "pch_uart", 1932 .id_table = pch_uart_pci_id, 1933 .probe = pch_uart_pci_probe, 1934 .remove = pch_uart_pci_remove, 1935 .driver.pm = &pch_uart_pci_pm_ops, 1936 }; 1937 1938 static int __init pch_uart_module_init(void) 1939 { 1940 int ret; 1941 1942 /* register as UART driver */ 1943 ret = uart_register_driver(&pch_uart_driver); 1944 if (ret < 0) 1945 return ret; 1946 1947 /* register as PCI driver */ 1948 ret = pci_register_driver(&pch_uart_pci_driver); 1949 if (ret < 0) 1950 uart_unregister_driver(&pch_uart_driver); 1951 1952 return ret; 1953 } 1954 module_init(pch_uart_module_init); 1955 1956 static void __exit pch_uart_module_exit(void) 1957 { 1958 pci_unregister_driver(&pch_uart_pci_driver); 1959 uart_unregister_driver(&pch_uart_driver); 1960 } 1961 module_exit(pch_uart_module_exit); 1962 1963 MODULE_LICENSE("GPL v2"); 1964 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); 1965 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id); 1966 1967 module_param(default_baud, uint, S_IRUGO); 1968 MODULE_PARM_DESC(default_baud, 1969 "Default BAUD for initial driver state and console (default 9600)"); 1970 module_param(user_uartclk, uint, S_IRUGO); 1971 MODULE_PARM_DESC(user_uartclk, 1972 "Override UART default or board specific UART clock"); 1973