1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 4 */ 5 #include <linux/kernel.h> 6 #include <linux/serial.h> 7 #include <linux/serial_reg.h> 8 #include <linux/slab.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/console.h> 12 #include <linux/serial_core.h> 13 #include <linux/tty.h> 14 #include <linux/tty_flip.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/dmi.h> 18 #include <linux/nmi.h> 19 #include <linux/delay.h> 20 #include <linux/of.h> 21 22 #include <linux/debugfs.h> 23 #include <linux/dmaengine.h> 24 #include <linux/pch_dma.h> 25 26 enum { 27 PCH_UART_HANDLED_RX_INT_SHIFT, 28 PCH_UART_HANDLED_TX_INT_SHIFT, 29 PCH_UART_HANDLED_RX_ERR_INT_SHIFT, 30 PCH_UART_HANDLED_RX_TRG_INT_SHIFT, 31 PCH_UART_HANDLED_MS_INT_SHIFT, 32 PCH_UART_HANDLED_LS_INT_SHIFT, 33 }; 34 35 #define PCH_UART_DRIVER_DEVICE "ttyPCH" 36 37 /* Set the max number of UART port 38 * Intel EG20T PCH: 4 port 39 * LAPIS Semiconductor ML7213 IOH: 3 port 40 * LAPIS Semiconductor ML7223 IOH: 2 port 41 */ 42 #define PCH_UART_NR 4 43 44 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) 45 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) 46 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ 47 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) 48 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ 49 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) 50 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) 51 52 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1)) 53 54 #define PCH_UART_RBR 0x00 55 #define PCH_UART_THR 0x00 56 57 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ 58 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) 59 #define PCH_UART_IER_ERBFI 0x00000001 60 #define PCH_UART_IER_ETBEI 0x00000002 61 #define PCH_UART_IER_ELSI 0x00000004 62 #define PCH_UART_IER_EDSSI 0x00000008 63 64 #define PCH_UART_IIR_IP 0x00000001 65 #define PCH_UART_IIR_IID 0x00000006 66 #define PCH_UART_IIR_MSI 0x00000000 67 #define PCH_UART_IIR_TRI 0x00000002 68 #define PCH_UART_IIR_RRI 0x00000004 69 #define PCH_UART_IIR_REI 0x00000006 70 #define PCH_UART_IIR_TOI 0x00000008 71 #define PCH_UART_IIR_FIFO256 0x00000020 72 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 73 #define PCH_UART_IIR_FE 0x000000C0 74 75 #define PCH_UART_FCR_FIFOE 0x00000001 76 #define PCH_UART_FCR_RFR 0x00000002 77 #define PCH_UART_FCR_TFR 0x00000004 78 #define PCH_UART_FCR_DMS 0x00000008 79 #define PCH_UART_FCR_FIFO256 0x00000020 80 #define PCH_UART_FCR_RFTL 0x000000C0 81 82 #define PCH_UART_FCR_RFTL1 0x00000000 83 #define PCH_UART_FCR_RFTL64 0x00000040 84 #define PCH_UART_FCR_RFTL128 0x00000080 85 #define PCH_UART_FCR_RFTL224 0x000000C0 86 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 87 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 88 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 89 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 90 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 91 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 92 #define PCH_UART_FCR_RFTL_SHIFT 6 93 94 #define PCH_UART_LCR_WLS 0x00000003 95 #define PCH_UART_LCR_STB 0x00000004 96 #define PCH_UART_LCR_PEN 0x00000008 97 #define PCH_UART_LCR_EPS 0x00000010 98 #define PCH_UART_LCR_SP 0x00000020 99 #define PCH_UART_LCR_SB 0x00000040 100 #define PCH_UART_LCR_DLAB 0x00000080 101 #define PCH_UART_LCR_NP 0x00000000 102 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN 103 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) 104 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) 105 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ 106 PCH_UART_LCR_SP) 107 108 #define PCH_UART_LCR_5BIT 0x00000000 109 #define PCH_UART_LCR_6BIT 0x00000001 110 #define PCH_UART_LCR_7BIT 0x00000002 111 #define PCH_UART_LCR_8BIT 0x00000003 112 113 #define PCH_UART_MCR_DTR 0x00000001 114 #define PCH_UART_MCR_RTS 0x00000002 115 #define PCH_UART_MCR_OUT 0x0000000C 116 #define PCH_UART_MCR_LOOP 0x00000010 117 #define PCH_UART_MCR_AFE 0x00000020 118 119 #define PCH_UART_LSR_DR 0x00000001 120 #define PCH_UART_LSR_ERR (1<<7) 121 122 #define PCH_UART_MSR_DCTS 0x00000001 123 #define PCH_UART_MSR_DDSR 0x00000002 124 #define PCH_UART_MSR_TERI 0x00000004 125 #define PCH_UART_MSR_DDCD 0x00000008 126 #define PCH_UART_MSR_CTS 0x00000010 127 #define PCH_UART_MSR_DSR 0x00000020 128 #define PCH_UART_MSR_RI 0x00000040 129 #define PCH_UART_MSR_DCD 0x00000080 130 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ 131 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) 132 133 #define PCH_UART_DLL 0x00 134 #define PCH_UART_DLM 0x01 135 136 #define PCH_UART_BRCSR 0x0E 137 138 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) 139 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) 140 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) 141 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) 142 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) 143 144 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) 145 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) 146 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) 147 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) 148 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) 149 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) 150 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) 151 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) 152 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) 153 #define PCH_UART_HAL_STB1 0 154 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) 155 156 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) 157 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) 158 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ 159 PCH_UART_HAL_CLR_RX_FIFO) 160 161 #define PCH_UART_HAL_DMA_MODE0 0 162 #define PCH_UART_HAL_FIFO_DIS 0 163 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) 164 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ 165 PCH_UART_FCR_FIFO256) 166 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) 167 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) 168 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) 169 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) 170 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) 171 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) 172 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) 173 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) 174 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) 175 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) 176 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) 177 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) 178 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) 179 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) 180 181 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) 182 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) 183 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) 184 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) 185 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) 186 187 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) 188 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) 189 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) 190 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) 191 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) 192 193 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */ 194 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */ 195 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */ 196 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */ 197 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */ 198 #define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */ 199 200 struct pch_uart_buffer { 201 unsigned char *buf; 202 int size; 203 }; 204 205 struct eg20t_port { 206 struct uart_port port; 207 int port_type; 208 void __iomem *membase; 209 resource_size_t mapbase; 210 unsigned int iobase; 211 struct pci_dev *pdev; 212 int fifo_size; 213 unsigned int uartclk; 214 int start_tx; 215 int start_rx; 216 int tx_empty; 217 int trigger; 218 int trigger_level; 219 struct pch_uart_buffer rxbuf; 220 unsigned int dmsr; 221 unsigned int fcr; 222 unsigned int mcr; 223 unsigned int use_dma; 224 struct dma_async_tx_descriptor *desc_tx; 225 struct dma_async_tx_descriptor *desc_rx; 226 struct pch_dma_slave param_tx; 227 struct pch_dma_slave param_rx; 228 struct dma_chan *chan_tx; 229 struct dma_chan *chan_rx; 230 struct scatterlist *sg_tx_p; 231 int nent; 232 int orig_nent; 233 struct scatterlist sg_rx; 234 int tx_dma_use; 235 void *rx_buf_virt; 236 dma_addr_t rx_buf_dma; 237 238 #define IRQ_NAME_SIZE 17 239 char irq_name[IRQ_NAME_SIZE]; 240 }; 241 242 /** 243 * struct pch_uart_driver_data - private data structure for UART-DMA 244 * @port_type: The type of UART port 245 * @line_no: UART port line number (0, 1, 2...) 246 */ 247 struct pch_uart_driver_data { 248 int port_type; 249 int line_no; 250 }; 251 252 enum pch_uart_num_t { 253 pch_et20t_uart0 = 0, 254 pch_et20t_uart1, 255 pch_et20t_uart2, 256 pch_et20t_uart3, 257 pch_ml7213_uart0, 258 pch_ml7213_uart1, 259 pch_ml7213_uart2, 260 pch_ml7223_uart0, 261 pch_ml7223_uart1, 262 pch_ml7831_uart0, 263 pch_ml7831_uart1, 264 }; 265 266 static struct pch_uart_driver_data drv_dat[] = { 267 [pch_et20t_uart0] = {PORT_PCH_8LINE, 0}, 268 [pch_et20t_uart1] = {PORT_PCH_2LINE, 1}, 269 [pch_et20t_uart2] = {PORT_PCH_2LINE, 2}, 270 [pch_et20t_uart3] = {PORT_PCH_2LINE, 3}, 271 [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0}, 272 [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1}, 273 [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2}, 274 [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0}, 275 [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1}, 276 [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0}, 277 [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1}, 278 }; 279 280 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 281 static struct eg20t_port *pch_uart_ports[PCH_UART_NR]; 282 #endif 283 static unsigned int default_baud = 9600; 284 static unsigned int user_uartclk = 0; 285 static const int trigger_level_256[4] = { 1, 64, 128, 224 }; 286 static const int trigger_level_64[4] = { 1, 16, 32, 56 }; 287 static const int trigger_level_16[4] = { 1, 4, 8, 14 }; 288 static const int trigger_level_1[4] = { 1, 1, 1, 1 }; 289 290 #define PCH_REGS_BUFSIZE 1024 291 292 293 static ssize_t port_show_regs(struct file *file, char __user *user_buf, 294 size_t count, loff_t *ppos) 295 { 296 struct eg20t_port *priv = file->private_data; 297 char *buf; 298 u32 len = 0; 299 ssize_t ret; 300 unsigned char lcr; 301 302 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL); 303 if (!buf) 304 return 0; 305 306 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 307 "PCH EG20T port[%d] regs:\n", priv->port.line); 308 309 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 310 "=================================\n"); 311 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 312 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); 313 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 314 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); 315 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 316 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); 317 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 318 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); 319 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 320 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); 321 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 322 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); 323 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 324 "BRCSR: \t0x%02x\n", 325 ioread8(priv->membase + PCH_UART_BRCSR)); 326 327 lcr = ioread8(priv->membase + UART_LCR); 328 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 329 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 330 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); 331 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 332 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); 333 iowrite8(lcr, priv->membase + UART_LCR); 334 335 if (len > PCH_REGS_BUFSIZE) 336 len = PCH_REGS_BUFSIZE; 337 338 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 339 kfree(buf); 340 return ret; 341 } 342 343 static const struct file_operations port_regs_ops = { 344 .owner = THIS_MODULE, 345 .open = simple_open, 346 .read = port_show_regs, 347 .llseek = default_llseek, 348 }; 349 350 static const struct dmi_system_id pch_uart_dmi_table[] = { 351 { 352 .ident = "CM-iTC", 353 { 354 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"), 355 }, 356 (void *)CMITC_UARTCLK, 357 }, 358 { 359 .ident = "FRI2", 360 { 361 DMI_MATCH(DMI_BIOS_VERSION, "FRI2"), 362 }, 363 (void *)FRI2_64_UARTCLK, 364 }, 365 { 366 .ident = "Fish River Island II", 367 { 368 DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"), 369 }, 370 (void *)FRI2_48_UARTCLK, 371 }, 372 { 373 .ident = "COMe-mTT", 374 { 375 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"), 376 }, 377 (void *)NTC1_UARTCLK, 378 }, 379 { 380 .ident = "nanoETXexpress-TT", 381 { 382 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"), 383 }, 384 (void *)NTC1_UARTCLK, 385 }, 386 { 387 .ident = "MinnowBoard", 388 { 389 DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"), 390 }, 391 (void *)MINNOW_UARTCLK, 392 }, 393 { } 394 }; 395 396 /* Return UART clock, checking for board specific clocks. */ 397 static unsigned int pch_uart_get_uartclk(void) 398 { 399 const struct dmi_system_id *d; 400 401 if (user_uartclk) 402 return user_uartclk; 403 404 d = dmi_first_match(pch_uart_dmi_table); 405 if (d) 406 return (unsigned long)d->driver_data; 407 408 return DEFAULT_UARTCLK; 409 } 410 411 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, 412 unsigned int flag) 413 { 414 u8 ier = ioread8(priv->membase + UART_IER); 415 ier |= flag & PCH_UART_IER_MASK; 416 iowrite8(ier, priv->membase + UART_IER); 417 } 418 419 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, 420 unsigned int flag) 421 { 422 u8 ier = ioread8(priv->membase + UART_IER); 423 ier &= ~(flag & PCH_UART_IER_MASK); 424 iowrite8(ier, priv->membase + UART_IER); 425 } 426 427 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud, 428 unsigned int parity, unsigned int bits, 429 unsigned int stb) 430 { 431 unsigned int dll, dlm, lcr; 432 int div; 433 434 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); 435 if (div < 0 || USHRT_MAX <= div) { 436 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); 437 return -EINVAL; 438 } 439 440 dll = (unsigned int)div & 0x00FFU; 441 dlm = ((unsigned int)div >> 8) & 0x00FFU; 442 443 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { 444 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); 445 return -EINVAL; 446 } 447 448 if (bits & ~PCH_UART_LCR_WLS) { 449 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); 450 return -EINVAL; 451 } 452 453 if (stb & ~PCH_UART_LCR_STB) { 454 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); 455 return -EINVAL; 456 } 457 458 lcr = parity; 459 lcr |= bits; 460 lcr |= stb; 461 462 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n", 463 __func__, baud, div, lcr, jiffies); 464 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 465 iowrite8(dll, priv->membase + PCH_UART_DLL); 466 iowrite8(dlm, priv->membase + PCH_UART_DLM); 467 iowrite8(lcr, priv->membase + UART_LCR); 468 469 return 0; 470 } 471 472 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, 473 unsigned int flag) 474 { 475 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { 476 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", 477 __func__, flag); 478 return -EINVAL; 479 } 480 481 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); 482 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, 483 priv->membase + UART_FCR); 484 iowrite8(priv->fcr, priv->membase + UART_FCR); 485 486 return 0; 487 } 488 489 static int pch_uart_hal_set_fifo(struct eg20t_port *priv, 490 unsigned int dmamode, 491 unsigned int fifo_size, unsigned int trigger) 492 { 493 u8 fcr; 494 495 if (dmamode & ~PCH_UART_FCR_DMS) { 496 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", 497 __func__, dmamode); 498 return -EINVAL; 499 } 500 501 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { 502 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", 503 __func__, fifo_size); 504 return -EINVAL; 505 } 506 507 if (trigger & ~PCH_UART_FCR_RFTL) { 508 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", 509 __func__, trigger); 510 return -EINVAL; 511 } 512 513 switch (priv->fifo_size) { 514 case 256: 515 priv->trigger_level = 516 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 517 break; 518 case 64: 519 priv->trigger_level = 520 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 521 break; 522 case 16: 523 priv->trigger_level = 524 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 525 break; 526 default: 527 priv->trigger_level = 528 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 529 break; 530 } 531 fcr = 532 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; 533 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); 534 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, 535 priv->membase + UART_FCR); 536 iowrite8(fcr, priv->membase + UART_FCR); 537 priv->fcr = fcr; 538 539 return 0; 540 } 541 542 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) 543 { 544 unsigned int msr = ioread8(priv->membase + UART_MSR); 545 priv->dmsr = msr & PCH_UART_MSR_DELTA; 546 return (u8)msr; 547 } 548 549 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, 550 int rx_size) 551 { 552 int i; 553 u8 rbr, lsr; 554 struct uart_port *port = &priv->port; 555 556 lsr = ioread8(priv->membase + UART_LSR); 557 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); 558 i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI); 559 lsr = ioread8(priv->membase + UART_LSR)) { 560 rbr = ioread8(priv->membase + PCH_UART_RBR); 561 562 if (lsr & UART_LSR_BI) { 563 port->icount.brk++; 564 if (uart_handle_break(port)) 565 continue; 566 } 567 if (uart_prepare_sysrq_char(port, rbr)) 568 continue; 569 570 buf[i++] = rbr; 571 } 572 return i; 573 } 574 575 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv) 576 { 577 return ioread8(priv->membase + UART_IIR) &\ 578 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP); 579 } 580 581 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) 582 { 583 return ioread8(priv->membase + UART_LSR); 584 } 585 586 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) 587 { 588 unsigned int lcr; 589 590 lcr = ioread8(priv->membase + UART_LCR); 591 if (on) 592 lcr |= PCH_UART_LCR_SB; 593 else 594 lcr &= ~PCH_UART_LCR_SB; 595 596 iowrite8(lcr, priv->membase + UART_LCR); 597 } 598 599 static void push_rx(struct eg20t_port *priv, const unsigned char *buf, 600 int size) 601 { 602 struct uart_port *port = &priv->port; 603 struct tty_port *tport = &port->state->port; 604 605 tty_insert_flip_string(tport, buf, size); 606 tty_flip_buffer_push(tport); 607 } 608 609 static int dma_push_rx(struct eg20t_port *priv, int size) 610 { 611 int room; 612 struct uart_port *port = &priv->port; 613 struct tty_port *tport = &port->state->port; 614 615 room = tty_buffer_request_room(tport, size); 616 617 if (room < size) 618 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 619 size - room); 620 if (!room) 621 return 0; 622 623 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size); 624 625 port->icount.rx += room; 626 627 return room; 628 } 629 630 static void pch_free_dma(struct uart_port *port) 631 { 632 struct eg20t_port *priv; 633 priv = container_of(port, struct eg20t_port, port); 634 635 if (priv->chan_tx) { 636 dma_release_channel(priv->chan_tx); 637 priv->chan_tx = NULL; 638 } 639 if (priv->chan_rx) { 640 dma_release_channel(priv->chan_rx); 641 priv->chan_rx = NULL; 642 } 643 644 if (priv->rx_buf_dma) { 645 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt, 646 priv->rx_buf_dma); 647 priv->rx_buf_virt = NULL; 648 priv->rx_buf_dma = 0; 649 } 650 651 return; 652 } 653 654 static bool filter(struct dma_chan *chan, void *slave) 655 { 656 struct pch_dma_slave *param = slave; 657 658 if ((chan->chan_id == param->chan_id) && (param->dma_dev == 659 chan->device->dev)) { 660 chan->private = param; 661 return true; 662 } else { 663 return false; 664 } 665 } 666 667 static void pch_request_dma(struct uart_port *port) 668 { 669 dma_cap_mask_t mask; 670 struct dma_chan *chan; 671 struct pci_dev *dma_dev; 672 struct pch_dma_slave *param; 673 struct eg20t_port *priv = 674 container_of(port, struct eg20t_port, port); 675 dma_cap_zero(mask); 676 dma_cap_set(DMA_SLAVE, mask); 677 678 /* Get DMA's dev information */ 679 dma_dev = pci_get_slot(priv->pdev->bus, 680 PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0)); 681 if (!dma_dev) { 682 dev_err(priv->port.dev, "%s: failed to get DMA device\n", 683 __func__); 684 return; 685 } 686 687 /* Set Tx DMA */ 688 param = &priv->param_tx; 689 param->dma_dev = &dma_dev->dev; 690 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ 691 692 param->tx_reg = port->mapbase + UART_TX; 693 chan = dma_request_channel(mask, filter, param); 694 if (!chan) { 695 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", 696 __func__); 697 goto err_pci_get; 698 } 699 priv->chan_tx = chan; 700 701 /* Set Rx DMA */ 702 param = &priv->param_rx; 703 param->dma_dev = &dma_dev->dev; 704 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ 705 706 param->rx_reg = port->mapbase + UART_RX; 707 chan = dma_request_channel(mask, filter, param); 708 if (!chan) { 709 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", 710 __func__); 711 goto err_req_tx; 712 } 713 714 /* Get Consistent memory for DMA */ 715 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, 716 &priv->rx_buf_dma, GFP_KERNEL); 717 if (!priv->rx_buf_virt) 718 goto err_req_rx; 719 priv->chan_rx = chan; 720 721 pci_dev_put(dma_dev); 722 return; 723 724 err_req_rx: 725 dma_release_channel(chan); 726 err_req_tx: 727 dma_release_channel(priv->chan_tx); 728 priv->chan_tx = NULL; 729 err_pci_get: 730 pci_dev_put(dma_dev); 731 } 732 733 static void pch_dma_rx_complete(void *arg) 734 { 735 struct eg20t_port *priv = arg; 736 struct uart_port *port = &priv->port; 737 int count; 738 739 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); 740 count = dma_push_rx(priv, priv->trigger_level); 741 if (count) 742 tty_flip_buffer_push(&port->state->port); 743 async_tx_ack(priv->desc_rx); 744 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | 745 PCH_UART_HAL_RX_ERR_INT); 746 } 747 748 static void pch_dma_tx_complete(void *arg) 749 { 750 struct eg20t_port *priv = arg; 751 struct uart_port *port = &priv->port; 752 struct scatterlist *sg = priv->sg_tx_p; 753 int i; 754 755 for (i = 0; i < priv->nent; i++, sg++) 756 uart_xmit_advance(port, sg_dma_len(sg)); 757 758 async_tx_ack(priv->desc_tx); 759 dma_unmap_sg(port->dev, priv->sg_tx_p, priv->orig_nent, DMA_TO_DEVICE); 760 priv->tx_dma_use = 0; 761 priv->nent = 0; 762 priv->orig_nent = 0; 763 kfree(priv->sg_tx_p); 764 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 765 } 766 767 static int handle_rx_to(struct eg20t_port *priv) 768 { 769 struct pch_uart_buffer *buf; 770 int rx_size; 771 772 if (!priv->start_rx) { 773 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | 774 PCH_UART_HAL_RX_ERR_INT); 775 return 0; 776 } 777 buf = &priv->rxbuf; 778 do { 779 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); 780 push_rx(priv, buf->buf, rx_size); 781 } while (rx_size == buf->size); 782 783 return PCH_UART_HANDLED_RX_INT; 784 } 785 786 static int dma_handle_rx(struct eg20t_port *priv) 787 { 788 struct uart_port *port = &priv->port; 789 struct dma_async_tx_descriptor *desc; 790 struct scatterlist *sg; 791 792 priv = container_of(port, struct eg20t_port, port); 793 sg = &priv->sg_rx; 794 795 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ 796 797 sg_dma_len(sg) = priv->trigger_level; 798 799 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), 800 sg_dma_len(sg), offset_in_page(priv->rx_buf_virt)); 801 802 sg_dma_address(sg) = priv->rx_buf_dma; 803 804 desc = dmaengine_prep_slave_sg(priv->chan_rx, 805 sg, 1, DMA_DEV_TO_MEM, 806 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 807 808 if (!desc) 809 return 0; 810 811 priv->desc_rx = desc; 812 desc->callback = pch_dma_rx_complete; 813 desc->callback_param = priv; 814 desc->tx_submit(desc); 815 dma_async_issue_pending(priv->chan_rx); 816 817 return PCH_UART_HANDLED_RX_INT; 818 } 819 820 static unsigned int handle_tx(struct eg20t_port *priv) 821 { 822 struct uart_port *port = &priv->port; 823 unsigned char ch; 824 int fifo_size; 825 int tx_empty; 826 827 if (!priv->start_tx) { 828 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 829 __func__, jiffies); 830 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 831 priv->tx_empty = 1; 832 return 0; 833 } 834 835 fifo_size = max(priv->fifo_size, 1); 836 tx_empty = 1; 837 if (port->x_char) { 838 iowrite8(port->x_char, priv->membase + PCH_UART_THR); 839 port->icount.tx++; 840 port->x_char = 0; 841 tx_empty = 0; 842 fifo_size--; 843 } 844 845 while (!uart_tx_stopped(port) && fifo_size && 846 uart_fifo_get(port, &ch)) { 847 iowrite8(ch, priv->membase + PCH_UART_THR); 848 fifo_size--; 849 tx_empty = 0; 850 } 851 852 priv->tx_empty = tx_empty; 853 854 if (tx_empty) { 855 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 856 uart_write_wakeup(port); 857 } 858 859 return PCH_UART_HANDLED_TX_INT; 860 } 861 862 static unsigned int dma_handle_tx(struct eg20t_port *priv) 863 { 864 struct uart_port *port = &priv->port; 865 struct tty_port *tport = &port->state->port; 866 struct scatterlist *sg; 867 int nent; 868 int fifo_size; 869 struct dma_async_tx_descriptor *desc; 870 unsigned int bytes, tail; 871 int num; 872 int i; 873 int size; 874 int rem; 875 876 if (!priv->start_tx) { 877 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 878 __func__, jiffies); 879 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 880 priv->tx_empty = 1; 881 return 0; 882 } 883 884 if (priv->tx_dma_use) { 885 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", 886 __func__, jiffies); 887 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 888 priv->tx_empty = 1; 889 return 0; 890 } 891 892 fifo_size = max(priv->fifo_size, 1); 893 894 if (port->x_char) { 895 iowrite8(port->x_char, priv->membase + PCH_UART_THR); 896 port->icount.tx++; 897 port->x_char = 0; 898 fifo_size--; 899 } 900 901 bytes = kfifo_out_linear(&tport->xmit_fifo, &tail, UART_XMIT_SIZE); 902 if (!bytes) { 903 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); 904 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 905 uart_write_wakeup(port); 906 return 0; 907 } 908 909 if (bytes > fifo_size) { 910 num = bytes / fifo_size + 1; 911 size = fifo_size; 912 rem = bytes % fifo_size; 913 } else { 914 num = 1; 915 size = bytes; 916 rem = bytes; 917 } 918 919 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", 920 __func__, num, size, rem); 921 922 priv->tx_dma_use = 1; 923 924 priv->sg_tx_p = kmalloc_objs(struct scatterlist, num, GFP_ATOMIC); 925 if (!priv->sg_tx_p) { 926 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__); 927 return 0; 928 } 929 930 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ 931 sg = priv->sg_tx_p; 932 933 for (i = 0; i < num; i++, sg++) { 934 if (i == (num - 1)) 935 sg_set_page(sg, virt_to_page(tport->xmit_buf), 936 rem, fifo_size * i); 937 else 938 sg_set_page(sg, virt_to_page(tport->xmit_buf), 939 size, fifo_size * i); 940 } 941 942 sg = priv->sg_tx_p; 943 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); 944 if (!nent) { 945 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); 946 return 0; 947 } 948 priv->orig_nent = num; 949 priv->nent = nent; 950 951 for (i = 0; i < nent; i++, sg++) { 952 sg->offset = tail + fifo_size * i; 953 sg_dma_address(sg) = (sg_dma_address(sg) & 954 ~(UART_XMIT_SIZE - 1)) + sg->offset; 955 if (i == (nent - 1)) 956 sg_dma_len(sg) = rem; 957 else 958 sg_dma_len(sg) = size; 959 } 960 961 desc = dmaengine_prep_slave_sg(priv->chan_tx, 962 priv->sg_tx_p, nent, DMA_MEM_TO_DEV, 963 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 964 if (!desc) { 965 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n", 966 __func__); 967 return 0; 968 } 969 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, num, DMA_TO_DEVICE); 970 priv->desc_tx = desc; 971 desc->callback = pch_dma_tx_complete; 972 desc->callback_param = priv; 973 974 desc->tx_submit(desc); 975 976 dma_async_issue_pending(priv->chan_tx); 977 978 return PCH_UART_HANDLED_TX_INT; 979 } 980 981 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) 982 { 983 struct uart_port *port = &priv->port; 984 struct tty_struct *tty = tty_port_tty_get(&port->state->port); 985 char *error_msg[5] = {}; 986 int i = 0; 987 988 if (lsr & PCH_UART_LSR_ERR) 989 error_msg[i++] = "Error data in FIFO\n"; 990 991 if (lsr & UART_LSR_FE) { 992 port->icount.frame++; 993 error_msg[i++] = " Framing Error\n"; 994 } 995 996 if (lsr & UART_LSR_PE) { 997 port->icount.parity++; 998 error_msg[i++] = " Parity Error\n"; 999 } 1000 1001 if (lsr & UART_LSR_OE) { 1002 port->icount.overrun++; 1003 error_msg[i++] = " Overrun Error\n"; 1004 } 1005 1006 if (tty == NULL) { 1007 for (i = 0; error_msg[i] != NULL; i++) 1008 dev_err(&priv->pdev->dev, error_msg[i]); 1009 } else { 1010 tty_kref_put(tty); 1011 } 1012 } 1013 1014 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) 1015 { 1016 struct eg20t_port *priv = dev_id; 1017 unsigned int handled; 1018 u8 lsr; 1019 int ret = 0; 1020 unsigned char iid; 1021 int next = 1; 1022 u8 msr; 1023 1024 uart_port_lock(&priv->port); 1025 handled = 0; 1026 while (next) { 1027 iid = pch_uart_hal_get_iid(priv); 1028 if (iid & PCH_UART_IIR_IP) /* No Interrupt */ 1029 break; 1030 switch (iid) { 1031 case PCH_UART_IID_RLS: /* Receiver Line Status */ 1032 lsr = pch_uart_hal_get_line_status(priv); 1033 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | 1034 UART_LSR_PE | UART_LSR_OE)) { 1035 pch_uart_err_ir(priv, lsr); 1036 ret = PCH_UART_HANDLED_RX_ERR_INT; 1037 } else { 1038 ret = PCH_UART_HANDLED_LS_INT; 1039 } 1040 break; 1041 case PCH_UART_IID_RDR: /* Received Data Ready */ 1042 if (priv->use_dma) { 1043 pch_uart_hal_disable_interrupt(priv, 1044 PCH_UART_HAL_RX_INT | 1045 PCH_UART_HAL_RX_ERR_INT); 1046 ret = dma_handle_rx(priv); 1047 if (!ret) 1048 pch_uart_hal_enable_interrupt(priv, 1049 PCH_UART_HAL_RX_INT | 1050 PCH_UART_HAL_RX_ERR_INT); 1051 } else { 1052 ret = handle_rx_to(priv); 1053 } 1054 break; 1055 case PCH_UART_IID_RDR_TO: /* Received Data Ready 1056 (FIFO Timeout) */ 1057 ret = handle_rx_to(priv); 1058 break; 1059 case PCH_UART_IID_THRE: /* Transmitter Holding Register 1060 Empty */ 1061 if (priv->use_dma) 1062 ret = dma_handle_tx(priv); 1063 else 1064 ret = handle_tx(priv); 1065 break; 1066 case PCH_UART_IID_MS: /* Modem Status */ 1067 msr = pch_uart_hal_get_modem(priv); 1068 next = 0; /* MS ir prioirty is the lowest. So, MS ir 1069 means final interrupt */ 1070 if ((msr & UART_MSR_ANY_DELTA) == 0) 1071 break; 1072 ret |= PCH_UART_HANDLED_MS_INT; 1073 break; 1074 default: /* Never junp to this label */ 1075 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__, 1076 iid, jiffies); 1077 ret = -1; 1078 next = 0; 1079 break; 1080 } 1081 handled |= (unsigned int)ret; 1082 } 1083 1084 uart_unlock_and_check_sysrq(&priv->port); 1085 return IRQ_RETVAL(handled); 1086 } 1087 1088 /* This function tests whether the transmitter fifo and shifter for the port 1089 described by 'port' is empty. */ 1090 static unsigned int pch_uart_tx_empty(struct uart_port *port) 1091 { 1092 struct eg20t_port *priv; 1093 1094 priv = container_of(port, struct eg20t_port, port); 1095 if (priv->tx_empty) 1096 return TIOCSER_TEMT; 1097 else 1098 return 0; 1099 } 1100 1101 /* Returns the current state of modem control inputs. */ 1102 static unsigned int pch_uart_get_mctrl(struct uart_port *port) 1103 { 1104 struct eg20t_port *priv; 1105 u8 modem; 1106 unsigned int ret = 0; 1107 1108 priv = container_of(port, struct eg20t_port, port); 1109 modem = pch_uart_hal_get_modem(priv); 1110 1111 if (modem & UART_MSR_DCD) 1112 ret |= TIOCM_CAR; 1113 1114 if (modem & UART_MSR_RI) 1115 ret |= TIOCM_RNG; 1116 1117 if (modem & UART_MSR_DSR) 1118 ret |= TIOCM_DSR; 1119 1120 if (modem & UART_MSR_CTS) 1121 ret |= TIOCM_CTS; 1122 1123 return ret; 1124 } 1125 1126 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1127 { 1128 u32 mcr = 0; 1129 struct eg20t_port *priv = container_of(port, struct eg20t_port, port); 1130 1131 if (mctrl & TIOCM_DTR) 1132 mcr |= UART_MCR_DTR; 1133 if (mctrl & TIOCM_RTS) 1134 mcr |= UART_MCR_RTS; 1135 if (mctrl & TIOCM_LOOP) 1136 mcr |= UART_MCR_LOOP; 1137 1138 if (priv->mcr & UART_MCR_AFE) 1139 mcr |= UART_MCR_AFE; 1140 1141 if (mctrl) 1142 iowrite8(mcr, priv->membase + UART_MCR); 1143 } 1144 1145 static void pch_uart_stop_tx(struct uart_port *port) 1146 { 1147 struct eg20t_port *priv; 1148 priv = container_of(port, struct eg20t_port, port); 1149 priv->start_tx = 0; 1150 priv->tx_dma_use = 0; 1151 } 1152 1153 static void pch_uart_start_tx(struct uart_port *port) 1154 { 1155 struct eg20t_port *priv; 1156 1157 priv = container_of(port, struct eg20t_port, port); 1158 1159 if (priv->use_dma) { 1160 if (priv->tx_dma_use) { 1161 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", 1162 __func__); 1163 return; 1164 } 1165 } 1166 1167 priv->start_tx = 1; 1168 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 1169 } 1170 1171 static void pch_uart_stop_rx(struct uart_port *port) 1172 { 1173 struct eg20t_port *priv; 1174 priv = container_of(port, struct eg20t_port, port); 1175 priv->start_rx = 0; 1176 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | 1177 PCH_UART_HAL_RX_ERR_INT); 1178 } 1179 1180 /* Enable the modem status interrupts. */ 1181 static void pch_uart_enable_ms(struct uart_port *port) 1182 { 1183 struct eg20t_port *priv; 1184 priv = container_of(port, struct eg20t_port, port); 1185 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); 1186 } 1187 1188 /* Control the transmission of a break signal. */ 1189 static void pch_uart_break_ctl(struct uart_port *port, int ctl) 1190 { 1191 struct eg20t_port *priv; 1192 unsigned long flags; 1193 1194 priv = container_of(port, struct eg20t_port, port); 1195 uart_port_lock_irqsave(&priv->port, &flags); 1196 pch_uart_hal_set_break(priv, ctl); 1197 uart_port_unlock_irqrestore(&priv->port, flags); 1198 } 1199 1200 /* Grab any interrupt resources and initialise any low level driver state. */ 1201 static int pch_uart_startup(struct uart_port *port) 1202 { 1203 struct eg20t_port *priv; 1204 int ret; 1205 int fifo_size; 1206 int trigger_level; 1207 1208 priv = container_of(port, struct eg20t_port, port); 1209 priv->tx_empty = 1; 1210 1211 if (port->uartclk) 1212 priv->uartclk = port->uartclk; 1213 else 1214 port->uartclk = priv->uartclk; 1215 1216 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1217 ret = pch_uart_hal_set_line(priv, default_baud, 1218 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, 1219 PCH_UART_HAL_STB1); 1220 if (ret) 1221 return ret; 1222 1223 switch (priv->fifo_size) { 1224 case 256: 1225 fifo_size = PCH_UART_HAL_FIFO256; 1226 break; 1227 case 64: 1228 fifo_size = PCH_UART_HAL_FIFO64; 1229 break; 1230 case 16: 1231 fifo_size = PCH_UART_HAL_FIFO16; 1232 break; 1233 case 1: 1234 default: 1235 fifo_size = PCH_UART_HAL_FIFO_DIS; 1236 break; 1237 } 1238 1239 switch (priv->trigger) { 1240 case PCH_UART_HAL_TRIGGER1: 1241 trigger_level = 1; 1242 break; 1243 case PCH_UART_HAL_TRIGGER_L: 1244 trigger_level = priv->fifo_size / 4; 1245 break; 1246 case PCH_UART_HAL_TRIGGER_M: 1247 trigger_level = priv->fifo_size / 2; 1248 break; 1249 case PCH_UART_HAL_TRIGGER_H: 1250 default: 1251 trigger_level = priv->fifo_size - (priv->fifo_size / 8); 1252 break; 1253 } 1254 1255 priv->trigger_level = trigger_level; 1256 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1257 fifo_size, priv->trigger); 1258 if (ret < 0) 1259 return ret; 1260 1261 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, 1262 priv->irq_name, priv); 1263 if (ret < 0) 1264 return ret; 1265 1266 if (priv->use_dma) 1267 pch_request_dma(port); 1268 1269 priv->start_rx = 1; 1270 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | 1271 PCH_UART_HAL_RX_ERR_INT); 1272 uart_update_timeout(port, CS8, default_baud); 1273 1274 return 0; 1275 } 1276 1277 static void pch_uart_shutdown(struct uart_port *port) 1278 { 1279 struct eg20t_port *priv; 1280 int ret; 1281 1282 priv = container_of(port, struct eg20t_port, port); 1283 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1284 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); 1285 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1286 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); 1287 if (ret) 1288 dev_err(priv->port.dev, 1289 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); 1290 1291 pch_free_dma(port); 1292 1293 free_irq(priv->port.irq, priv); 1294 } 1295 1296 /* Change the port parameters, including word length, parity, stop 1297 *bits. Update read_status_mask and ignore_status_mask to indicate 1298 *the types of events we are interested in receiving. */ 1299 static void pch_uart_set_termios(struct uart_port *port, 1300 struct ktermios *termios, 1301 const struct ktermios *old) 1302 { 1303 int rtn; 1304 unsigned int baud, parity, bits, stb; 1305 struct eg20t_port *priv; 1306 unsigned long flags; 1307 1308 priv = container_of(port, struct eg20t_port, port); 1309 switch (termios->c_cflag & CSIZE) { 1310 case CS5: 1311 bits = PCH_UART_HAL_5BIT; 1312 break; 1313 case CS6: 1314 bits = PCH_UART_HAL_6BIT; 1315 break; 1316 case CS7: 1317 bits = PCH_UART_HAL_7BIT; 1318 break; 1319 default: /* CS8 */ 1320 bits = PCH_UART_HAL_8BIT; 1321 break; 1322 } 1323 if (termios->c_cflag & CSTOPB) 1324 stb = PCH_UART_HAL_STB2; 1325 else 1326 stb = PCH_UART_HAL_STB1; 1327 1328 if (termios->c_cflag & PARENB) { 1329 if (termios->c_cflag & PARODD) 1330 parity = PCH_UART_HAL_PARITY_ODD; 1331 else 1332 parity = PCH_UART_HAL_PARITY_EVEN; 1333 1334 } else 1335 parity = PCH_UART_HAL_PARITY_NONE; 1336 1337 /* Only UART0 has auto hardware flow function */ 1338 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) 1339 priv->mcr |= UART_MCR_AFE; 1340 else 1341 priv->mcr &= ~UART_MCR_AFE; 1342 1343 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 1344 1345 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1346 1347 uart_port_lock_irqsave(port, &flags); 1348 1349 uart_update_timeout(port, termios->c_cflag, baud); 1350 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); 1351 if (rtn) 1352 goto out; 1353 1354 pch_uart_set_mctrl(&priv->port, priv->port.mctrl); 1355 /* Don't rewrite B0 */ 1356 if (tty_termios_baud_rate(termios)) 1357 tty_termios_encode_baud_rate(termios, baud, baud); 1358 1359 out: 1360 uart_port_unlock_irqrestore(port, flags); 1361 } 1362 1363 static const char *pch_uart_type(struct uart_port *port) 1364 { 1365 return KBUILD_MODNAME; 1366 } 1367 1368 static void pch_uart_release_port(struct uart_port *port) 1369 { 1370 struct eg20t_port *priv; 1371 1372 priv = container_of(port, struct eg20t_port, port); 1373 pci_iounmap(priv->pdev, priv->membase); 1374 pci_release_regions(priv->pdev); 1375 } 1376 1377 static int pch_uart_request_port(struct uart_port *port) 1378 { 1379 struct eg20t_port *priv; 1380 int ret; 1381 void __iomem *membase; 1382 1383 priv = container_of(port, struct eg20t_port, port); 1384 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); 1385 if (ret < 0) 1386 return -EBUSY; 1387 1388 membase = pci_iomap(priv->pdev, 1, 0); 1389 if (!membase) { 1390 pci_release_regions(priv->pdev); 1391 return -EBUSY; 1392 } 1393 priv->membase = port->membase = membase; 1394 1395 return 0; 1396 } 1397 1398 static void pch_uart_config_port(struct uart_port *port, int type) 1399 { 1400 struct eg20t_port *priv; 1401 1402 priv = container_of(port, struct eg20t_port, port); 1403 if (type & UART_CONFIG_TYPE) { 1404 port->type = priv->port_type; 1405 pch_uart_request_port(port); 1406 } 1407 } 1408 1409 static int pch_uart_verify_port(struct uart_port *port, 1410 struct serial_struct *serinfo) 1411 { 1412 struct eg20t_port *priv; 1413 1414 priv = container_of(port, struct eg20t_port, port); 1415 if (serinfo->flags & UPF_LOW_LATENCY) { 1416 dev_info(priv->port.dev, 1417 "PCH UART : Use PIO Mode (without DMA)\n"); 1418 priv->use_dma = 0; 1419 serinfo->flags &= ~UPF_LOW_LATENCY; 1420 } else { 1421 #ifndef CONFIG_PCH_DMA 1422 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", 1423 __func__); 1424 return -EOPNOTSUPP; 1425 #endif 1426 if (!priv->use_dma) { 1427 pch_request_dma(port); 1428 if (priv->chan_rx) 1429 priv->use_dma = 1; 1430 } 1431 dev_info(priv->port.dev, "PCH UART: %s\n", 1432 priv->use_dma ? 1433 "Use DMA Mode" : "No DMA"); 1434 } 1435 1436 return 0; 1437 } 1438 1439 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE) 1440 /* 1441 * Wait for transmitter & holding register to empty 1442 */ 1443 static void wait_for_xmitr(struct eg20t_port *up, int bits) 1444 { 1445 unsigned int status, tmout = 10000; 1446 1447 /* Wait up to 10ms for the character(s) to be sent. */ 1448 for (;;) { 1449 status = ioread8(up->membase + UART_LSR); 1450 1451 if ((status & bits) == bits) 1452 break; 1453 if (--tmout == 0) 1454 break; 1455 udelay(1); 1456 } 1457 1458 /* Wait up to 1s for flow control if necessary */ 1459 if (uart_cons_flow_enabled(&up->port)) { 1460 unsigned int tmout; 1461 for (tmout = 1000000; tmout; tmout--) { 1462 unsigned int msr = ioread8(up->membase + UART_MSR); 1463 if (msr & UART_MSR_CTS) 1464 break; 1465 udelay(1); 1466 touch_nmi_watchdog(); 1467 } 1468 } 1469 } 1470 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */ 1471 1472 #ifdef CONFIG_CONSOLE_POLL 1473 /* 1474 * Console polling routines for communicate via uart while 1475 * in an interrupt or debug context. 1476 */ 1477 static int pch_uart_get_poll_char(struct uart_port *port) 1478 { 1479 struct eg20t_port *priv = 1480 container_of(port, struct eg20t_port, port); 1481 u8 lsr = ioread8(priv->membase + UART_LSR); 1482 1483 if (!(lsr & UART_LSR_DR)) 1484 return NO_POLL_CHAR; 1485 1486 return ioread8(priv->membase + PCH_UART_RBR); 1487 } 1488 1489 1490 static void pch_uart_put_poll_char(struct uart_port *port, 1491 unsigned char c) 1492 { 1493 unsigned int ier; 1494 struct eg20t_port *priv = 1495 container_of(port, struct eg20t_port, port); 1496 1497 /* 1498 * First save the IER then disable the interrupts 1499 */ 1500 ier = ioread8(priv->membase + UART_IER); 1501 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1502 1503 wait_for_xmitr(priv, UART_LSR_THRE); 1504 /* 1505 * Send the character out. 1506 */ 1507 iowrite8(c, priv->membase + PCH_UART_THR); 1508 1509 /* 1510 * Finally, wait for transmitter to become empty 1511 * and restore the IER 1512 */ 1513 wait_for_xmitr(priv, UART_LSR_BOTH_EMPTY); 1514 iowrite8(ier, priv->membase + UART_IER); 1515 } 1516 #endif /* CONFIG_CONSOLE_POLL */ 1517 1518 static const struct uart_ops pch_uart_ops = { 1519 .tx_empty = pch_uart_tx_empty, 1520 .set_mctrl = pch_uart_set_mctrl, 1521 .get_mctrl = pch_uart_get_mctrl, 1522 .stop_tx = pch_uart_stop_tx, 1523 .start_tx = pch_uart_start_tx, 1524 .stop_rx = pch_uart_stop_rx, 1525 .enable_ms = pch_uart_enable_ms, 1526 .break_ctl = pch_uart_break_ctl, 1527 .startup = pch_uart_startup, 1528 .shutdown = pch_uart_shutdown, 1529 .set_termios = pch_uart_set_termios, 1530 .type = pch_uart_type, 1531 .release_port = pch_uart_release_port, 1532 .request_port = pch_uart_request_port, 1533 .config_port = pch_uart_config_port, 1534 .verify_port = pch_uart_verify_port, 1535 #ifdef CONFIG_CONSOLE_POLL 1536 .poll_get_char = pch_uart_get_poll_char, 1537 .poll_put_char = pch_uart_put_poll_char, 1538 #endif 1539 }; 1540 1541 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1542 1543 static void pch_console_putchar(struct uart_port *port, unsigned char ch) 1544 { 1545 struct eg20t_port *priv = 1546 container_of(port, struct eg20t_port, port); 1547 1548 wait_for_xmitr(priv, UART_LSR_THRE); 1549 iowrite8(ch, priv->membase + PCH_UART_THR); 1550 } 1551 1552 /* 1553 * Print a string to the serial port trying not to disturb 1554 * any possible real use of the port... 1555 * 1556 * The console_lock must be held when we get here. 1557 */ 1558 static void 1559 pch_console_write(struct console *co, const char *s, unsigned int count) 1560 { 1561 struct eg20t_port *priv; 1562 unsigned long flags; 1563 int locked = 1; 1564 u8 ier; 1565 1566 priv = pch_uart_ports[co->index]; 1567 1568 touch_nmi_watchdog(); 1569 1570 if (oops_in_progress) 1571 locked = uart_port_trylock_irqsave(&priv->port, &flags); 1572 else 1573 uart_port_lock_irqsave(&priv->port, &flags); 1574 1575 /* 1576 * First save the IER then disable the interrupts 1577 */ 1578 ier = ioread8(priv->membase + UART_IER); 1579 1580 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1581 1582 uart_console_write(&priv->port, s, count, pch_console_putchar); 1583 1584 /* 1585 * Finally, wait for transmitter to become empty 1586 * and restore the IER 1587 */ 1588 wait_for_xmitr(priv, UART_LSR_BOTH_EMPTY); 1589 iowrite8(ier, priv->membase + UART_IER); 1590 1591 if (locked) 1592 uart_port_unlock_irqrestore(&priv->port, flags); 1593 } 1594 1595 static int __init pch_console_setup(struct console *co, char *options) 1596 { 1597 struct uart_port *port; 1598 int baud = default_baud; 1599 int bits = 8; 1600 int parity = 'n'; 1601 int flow = 'n'; 1602 1603 /* 1604 * Check whether an invalid uart number has been specified, and 1605 * if so, search for the first available port that does have 1606 * console support. 1607 */ 1608 if (co->index >= PCH_UART_NR) 1609 co->index = 0; 1610 port = &pch_uart_ports[co->index]->port; 1611 1612 if (!port || (!port->iobase && !port->membase)) 1613 return -ENODEV; 1614 1615 port->uartclk = pch_uart_get_uartclk(); 1616 1617 if (options) 1618 uart_parse_options(options, &baud, &parity, &bits, &flow); 1619 1620 return uart_set_options(port, co, baud, parity, bits, flow); 1621 } 1622 1623 static struct uart_driver pch_uart_driver; 1624 1625 static struct console pch_console = { 1626 .name = PCH_UART_DRIVER_DEVICE, 1627 .write = pch_console_write, 1628 .device = uart_console_device, 1629 .setup = pch_console_setup, 1630 .flags = CON_PRINTBUFFER | CON_ANYTIME, 1631 .index = -1, 1632 .data = &pch_uart_driver, 1633 }; 1634 1635 #define PCH_CONSOLE (&pch_console) 1636 #else 1637 #define PCH_CONSOLE NULL 1638 #endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */ 1639 1640 static struct uart_driver pch_uart_driver = { 1641 .owner = THIS_MODULE, 1642 .driver_name = KBUILD_MODNAME, 1643 .dev_name = PCH_UART_DRIVER_DEVICE, 1644 .major = 0, 1645 .minor = 0, 1646 .nr = PCH_UART_NR, 1647 .cons = PCH_CONSOLE, 1648 }; 1649 1650 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, 1651 const struct pci_device_id *id) 1652 { 1653 struct eg20t_port *priv; 1654 int ret; 1655 unsigned int iobase; 1656 unsigned int mapbase; 1657 unsigned char *rxbuf; 1658 int fifosize; 1659 int port_type; 1660 struct pch_uart_driver_data *board; 1661 char name[32]; 1662 1663 board = &drv_dat[id->driver_data]; 1664 port_type = board->port_type; 1665 1666 priv = kzalloc_obj(struct eg20t_port); 1667 if (priv == NULL) 1668 goto init_port_alloc_err; 1669 1670 rxbuf = kmalloc(PAGE_SIZE, GFP_KERNEL); 1671 if (!rxbuf) 1672 goto init_port_free_txbuf; 1673 1674 switch (port_type) { 1675 case PORT_PCH_8LINE: 1676 fifosize = 256; /* EG20T/ML7213: UART0 */ 1677 break; 1678 case PORT_PCH_2LINE: 1679 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ 1680 break; 1681 default: 1682 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); 1683 goto init_port_hal_free; 1684 } 1685 1686 pci_enable_msi(pdev); 1687 pci_set_master(pdev); 1688 1689 iobase = pci_resource_start(pdev, 0); 1690 mapbase = pci_resource_start(pdev, 1); 1691 priv->mapbase = mapbase; 1692 priv->iobase = iobase; 1693 priv->pdev = pdev; 1694 priv->tx_empty = 1; 1695 priv->rxbuf.buf = rxbuf; 1696 priv->rxbuf.size = PAGE_SIZE; 1697 1698 priv->fifo_size = fifosize; 1699 priv->uartclk = pch_uart_get_uartclk(); 1700 priv->port_type = port_type; 1701 priv->port.dev = &pdev->dev; 1702 priv->port.iobase = iobase; 1703 priv->port.membase = NULL; 1704 priv->port.mapbase = mapbase; 1705 priv->port.irq = pdev->irq; 1706 priv->port.iotype = UPIO_PORT; 1707 priv->port.ops = &pch_uart_ops; 1708 priv->port.flags = UPF_BOOT_AUTOCONF; 1709 priv->port.fifosize = fifosize; 1710 priv->port.line = board->line_no; 1711 priv->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PCH_UART_CONSOLE); 1712 priv->trigger = PCH_UART_HAL_TRIGGER_M; 1713 1714 snprintf(priv->irq_name, IRQ_NAME_SIZE, 1715 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d", 1716 priv->port.line); 1717 1718 pci_set_drvdata(pdev, priv); 1719 priv->trigger_level = 1; 1720 priv->fcr = 0; 1721 1722 if (pdev->dev.of_node) 1723 of_property_read_u32(pdev->dev.of_node, "clock-frequency" 1724 , &user_uartclk); 1725 1726 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1727 pch_uart_ports[board->line_no] = priv; 1728 #endif 1729 ret = uart_add_one_port(&pch_uart_driver, &priv->port); 1730 if (ret < 0) 1731 goto init_port_hal_free; 1732 1733 snprintf(name, sizeof(name), "uart%d_regs", priv->port.line); 1734 debugfs_create_file(name, S_IFREG | S_IRUGO, NULL, priv, 1735 &port_regs_ops); 1736 1737 return priv; 1738 1739 init_port_hal_free: 1740 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1741 pch_uart_ports[board->line_no] = NULL; 1742 #endif 1743 kfree(rxbuf); 1744 init_port_free_txbuf: 1745 kfree(priv); 1746 init_port_alloc_err: 1747 1748 return NULL; 1749 } 1750 1751 static void pch_uart_exit_port(struct eg20t_port *priv) 1752 { 1753 char name[32]; 1754 1755 snprintf(name, sizeof(name), "uart%d_regs", priv->port.line); 1756 debugfs_lookup_and_remove(name, NULL); 1757 uart_remove_one_port(&pch_uart_driver, &priv->port); 1758 kfree(priv->rxbuf.buf); 1759 } 1760 1761 static void pch_uart_pci_remove(struct pci_dev *pdev) 1762 { 1763 struct eg20t_port *priv = pci_get_drvdata(pdev); 1764 1765 pci_disable_msi(pdev); 1766 1767 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1768 pch_uart_ports[priv->port.line] = NULL; 1769 #endif 1770 pch_uart_exit_port(priv); 1771 pci_disable_device(pdev); 1772 kfree(priv); 1773 return; 1774 } 1775 1776 static int __maybe_unused pch_uart_pci_suspend(struct device *dev) 1777 { 1778 struct eg20t_port *priv = dev_get_drvdata(dev); 1779 1780 uart_suspend_port(&pch_uart_driver, &priv->port); 1781 1782 return 0; 1783 } 1784 1785 static int __maybe_unused pch_uart_pci_resume(struct device *dev) 1786 { 1787 struct eg20t_port *priv = dev_get_drvdata(dev); 1788 1789 uart_resume_port(&pch_uart_driver, &priv->port); 1790 1791 return 0; 1792 } 1793 1794 static const struct pci_device_id pch_uart_pci_id[] = { 1795 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), 1796 .driver_data = pch_et20t_uart0}, 1797 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), 1798 .driver_data = pch_et20t_uart1}, 1799 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), 1800 .driver_data = pch_et20t_uart2}, 1801 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), 1802 .driver_data = pch_et20t_uart3}, 1803 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), 1804 .driver_data = pch_ml7213_uart0}, 1805 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), 1806 .driver_data = pch_ml7213_uart1}, 1807 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), 1808 .driver_data = pch_ml7213_uart2}, 1809 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C), 1810 .driver_data = pch_ml7223_uart0}, 1811 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D), 1812 .driver_data = pch_ml7223_uart1}, 1813 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811), 1814 .driver_data = pch_ml7831_uart0}, 1815 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812), 1816 .driver_data = pch_ml7831_uart1}, 1817 {0,}, 1818 }; 1819 1820 static int pch_uart_pci_probe(struct pci_dev *pdev, 1821 const struct pci_device_id *id) 1822 { 1823 int ret; 1824 struct eg20t_port *priv; 1825 1826 ret = pci_enable_device(pdev); 1827 if (ret < 0) 1828 goto probe_error; 1829 1830 priv = pch_uart_init_port(pdev, id); 1831 if (!priv) { 1832 ret = -EBUSY; 1833 goto probe_disable_device; 1834 } 1835 pci_set_drvdata(pdev, priv); 1836 1837 return ret; 1838 1839 probe_disable_device: 1840 pci_disable_msi(pdev); 1841 pci_disable_device(pdev); 1842 probe_error: 1843 return ret; 1844 } 1845 1846 static SIMPLE_DEV_PM_OPS(pch_uart_pci_pm_ops, 1847 pch_uart_pci_suspend, 1848 pch_uart_pci_resume); 1849 1850 static struct pci_driver pch_uart_pci_driver = { 1851 .name = "pch_uart", 1852 .id_table = pch_uart_pci_id, 1853 .probe = pch_uart_pci_probe, 1854 .remove = pch_uart_pci_remove, 1855 .driver.pm = &pch_uart_pci_pm_ops, 1856 }; 1857 1858 static int __init pch_uart_module_init(void) 1859 { 1860 int ret; 1861 1862 /* register as UART driver */ 1863 ret = uart_register_driver(&pch_uart_driver); 1864 if (ret < 0) 1865 return ret; 1866 1867 /* register as PCI driver */ 1868 ret = pci_register_driver(&pch_uart_pci_driver); 1869 if (ret < 0) 1870 uart_unregister_driver(&pch_uart_driver); 1871 1872 return ret; 1873 } 1874 module_init(pch_uart_module_init); 1875 1876 static void __exit pch_uart_module_exit(void) 1877 { 1878 pci_unregister_driver(&pch_uart_pci_driver); 1879 uart_unregister_driver(&pch_uart_driver); 1880 } 1881 module_exit(pch_uart_module_exit); 1882 1883 MODULE_LICENSE("GPL v2"); 1884 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); 1885 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id); 1886 1887 module_param(default_baud, uint, S_IRUGO); 1888 MODULE_PARM_DESC(default_baud, 1889 "Default BAUD for initial driver state and console (default 9600)"); 1890 module_param(user_uartclk, uint, S_IRUGO); 1891 MODULE_PARM_DESC(user_uartclk, 1892 "Override UART default or board specific UART clock"); 1893