1 /* 2 *Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD. 3 * 4 *This program is free software; you can redistribute it and/or modify 5 *it under the terms of the GNU General Public License as published by 6 *the Free Software Foundation; version 2 of the License. 7 * 8 *This program is distributed in the hope that it will be useful, 9 *but WITHOUT ANY WARRANTY; without even the implied warranty of 10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 *GNU General Public License for more details. 12 * 13 *You should have received a copy of the GNU General Public License 14 *along with this program; if not, write to the Free Software 15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 16 */ 17 #include <linux/serial_reg.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <linux/pci.h> 21 #include <linux/serial_core.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/dmi.h> 25 26 #include <linux/dmaengine.h> 27 #include <linux/pch_dma.h> 28 29 enum { 30 PCH_UART_HANDLED_RX_INT_SHIFT, 31 PCH_UART_HANDLED_TX_INT_SHIFT, 32 PCH_UART_HANDLED_RX_ERR_INT_SHIFT, 33 PCH_UART_HANDLED_RX_TRG_INT_SHIFT, 34 PCH_UART_HANDLED_MS_INT_SHIFT, 35 }; 36 37 enum { 38 PCH_UART_8LINE, 39 PCH_UART_2LINE, 40 }; 41 42 #define PCH_UART_DRIVER_DEVICE "ttyPCH" 43 44 /* Set the max number of UART port 45 * Intel EG20T PCH: 4 port 46 * OKI SEMICONDUCTOR ML7213 IOH: 3 port 47 */ 48 #define PCH_UART_NR 4 49 50 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) 51 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) 52 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ 53 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) 54 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ 55 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) 56 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) 57 58 #define PCH_UART_RBR 0x00 59 #define PCH_UART_THR 0x00 60 61 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ 62 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) 63 #define PCH_UART_IER_ERBFI 0x00000001 64 #define PCH_UART_IER_ETBEI 0x00000002 65 #define PCH_UART_IER_ELSI 0x00000004 66 #define PCH_UART_IER_EDSSI 0x00000008 67 68 #define PCH_UART_IIR_IP 0x00000001 69 #define PCH_UART_IIR_IID 0x00000006 70 #define PCH_UART_IIR_MSI 0x00000000 71 #define PCH_UART_IIR_TRI 0x00000002 72 #define PCH_UART_IIR_RRI 0x00000004 73 #define PCH_UART_IIR_REI 0x00000006 74 #define PCH_UART_IIR_TOI 0x00000008 75 #define PCH_UART_IIR_FIFO256 0x00000020 76 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 77 #define PCH_UART_IIR_FE 0x000000C0 78 79 #define PCH_UART_FCR_FIFOE 0x00000001 80 #define PCH_UART_FCR_RFR 0x00000002 81 #define PCH_UART_FCR_TFR 0x00000004 82 #define PCH_UART_FCR_DMS 0x00000008 83 #define PCH_UART_FCR_FIFO256 0x00000020 84 #define PCH_UART_FCR_RFTL 0x000000C0 85 86 #define PCH_UART_FCR_RFTL1 0x00000000 87 #define PCH_UART_FCR_RFTL64 0x00000040 88 #define PCH_UART_FCR_RFTL128 0x00000080 89 #define PCH_UART_FCR_RFTL224 0x000000C0 90 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 91 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 92 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 93 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 94 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 95 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 96 #define PCH_UART_FCR_RFTL_SHIFT 6 97 98 #define PCH_UART_LCR_WLS 0x00000003 99 #define PCH_UART_LCR_STB 0x00000004 100 #define PCH_UART_LCR_PEN 0x00000008 101 #define PCH_UART_LCR_EPS 0x00000010 102 #define PCH_UART_LCR_SP 0x00000020 103 #define PCH_UART_LCR_SB 0x00000040 104 #define PCH_UART_LCR_DLAB 0x00000080 105 #define PCH_UART_LCR_NP 0x00000000 106 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN 107 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) 108 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) 109 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ 110 PCH_UART_LCR_SP) 111 112 #define PCH_UART_LCR_5BIT 0x00000000 113 #define PCH_UART_LCR_6BIT 0x00000001 114 #define PCH_UART_LCR_7BIT 0x00000002 115 #define PCH_UART_LCR_8BIT 0x00000003 116 117 #define PCH_UART_MCR_DTR 0x00000001 118 #define PCH_UART_MCR_RTS 0x00000002 119 #define PCH_UART_MCR_OUT 0x0000000C 120 #define PCH_UART_MCR_LOOP 0x00000010 121 #define PCH_UART_MCR_AFE 0x00000020 122 123 #define PCH_UART_LSR_DR 0x00000001 124 #define PCH_UART_LSR_ERR (1<<7) 125 126 #define PCH_UART_MSR_DCTS 0x00000001 127 #define PCH_UART_MSR_DDSR 0x00000002 128 #define PCH_UART_MSR_TERI 0x00000004 129 #define PCH_UART_MSR_DDCD 0x00000008 130 #define PCH_UART_MSR_CTS 0x00000010 131 #define PCH_UART_MSR_DSR 0x00000020 132 #define PCH_UART_MSR_RI 0x00000040 133 #define PCH_UART_MSR_DCD 0x00000080 134 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ 135 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) 136 137 #define PCH_UART_DLL 0x00 138 #define PCH_UART_DLM 0x01 139 140 #define DIV_ROUND(a, b) (((a) + ((b)/2)) / (b)) 141 142 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) 143 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) 144 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) 145 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) 146 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) 147 148 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) 149 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) 150 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) 151 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) 152 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) 153 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) 154 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) 155 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) 156 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) 157 #define PCH_UART_HAL_STB1 0 158 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) 159 160 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) 161 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) 162 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ 163 PCH_UART_HAL_CLR_RX_FIFO) 164 165 #define PCH_UART_HAL_DMA_MODE0 0 166 #define PCH_UART_HAL_FIFO_DIS 0 167 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) 168 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ 169 PCH_UART_FCR_FIFO256) 170 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) 171 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) 172 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) 173 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) 174 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) 175 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) 176 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) 177 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) 178 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) 179 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) 180 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) 181 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) 182 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) 183 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) 184 185 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) 186 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) 187 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) 188 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) 189 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) 190 191 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) 192 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) 193 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) 194 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) 195 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) 196 197 #define PCI_VENDOR_ID_ROHM 0x10DB 198 199 struct pch_uart_buffer { 200 unsigned char *buf; 201 int size; 202 }; 203 204 struct eg20t_port { 205 struct uart_port port; 206 int port_type; 207 void __iomem *membase; 208 resource_size_t mapbase; 209 unsigned int iobase; 210 struct pci_dev *pdev; 211 int fifo_size; 212 int base_baud; 213 int start_tx; 214 int start_rx; 215 int tx_empty; 216 int int_dis_flag; 217 int trigger; 218 int trigger_level; 219 struct pch_uart_buffer rxbuf; 220 unsigned int dmsr; 221 unsigned int fcr; 222 unsigned int mcr; 223 unsigned int use_dma; 224 unsigned int use_dma_flag; 225 struct dma_async_tx_descriptor *desc_tx; 226 struct dma_async_tx_descriptor *desc_rx; 227 struct pch_dma_slave param_tx; 228 struct pch_dma_slave param_rx; 229 struct dma_chan *chan_tx; 230 struct dma_chan *chan_rx; 231 struct scatterlist *sg_tx_p; 232 int nent; 233 struct scatterlist sg_rx; 234 int tx_dma_use; 235 void *rx_buf_virt; 236 dma_addr_t rx_buf_dma; 237 }; 238 239 /** 240 * struct pch_uart_driver_data - private data structure for UART-DMA 241 * @port_type: The number of DMA channel 242 * @line_no: UART port line number (0, 1, 2...) 243 */ 244 struct pch_uart_driver_data { 245 int port_type; 246 int line_no; 247 }; 248 249 enum pch_uart_num_t { 250 pch_et20t_uart0 = 0, 251 pch_et20t_uart1, 252 pch_et20t_uart2, 253 pch_et20t_uart3, 254 pch_ml7213_uart0, 255 pch_ml7213_uart1, 256 pch_ml7213_uart2, 257 pch_ml7223_uart0, 258 pch_ml7223_uart1, 259 }; 260 261 static struct pch_uart_driver_data drv_dat[] = { 262 [pch_et20t_uart0] = {PCH_UART_8LINE, 0}, 263 [pch_et20t_uart1] = {PCH_UART_2LINE, 1}, 264 [pch_et20t_uart2] = {PCH_UART_2LINE, 2}, 265 [pch_et20t_uart3] = {PCH_UART_2LINE, 3}, 266 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0}, 267 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1}, 268 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2}, 269 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0}, 270 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1}, 271 }; 272 273 static unsigned int default_baud = 9600; 274 static const int trigger_level_256[4] = { 1, 64, 128, 224 }; 275 static const int trigger_level_64[4] = { 1, 16, 32, 56 }; 276 static const int trigger_level_16[4] = { 1, 4, 8, 14 }; 277 static const int trigger_level_1[4] = { 1, 1, 1, 1 }; 278 279 static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize, 280 int base_baud) 281 { 282 struct eg20t_port *priv = pci_get_drvdata(pdev); 283 284 priv->trigger_level = 1; 285 priv->fcr = 0; 286 } 287 288 static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base) 289 { 290 unsigned int msr = ioread8(base + UART_MSR); 291 priv->dmsr |= msr & PCH_UART_MSR_DELTA; 292 293 return msr; 294 } 295 296 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, 297 unsigned int flag) 298 { 299 u8 ier = ioread8(priv->membase + UART_IER); 300 ier |= flag & PCH_UART_IER_MASK; 301 iowrite8(ier, priv->membase + UART_IER); 302 } 303 304 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, 305 unsigned int flag) 306 { 307 u8 ier = ioread8(priv->membase + UART_IER); 308 ier &= ~(flag & PCH_UART_IER_MASK); 309 iowrite8(ier, priv->membase + UART_IER); 310 } 311 312 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud, 313 unsigned int parity, unsigned int bits, 314 unsigned int stb) 315 { 316 unsigned int dll, dlm, lcr; 317 int div; 318 319 div = DIV_ROUND(priv->base_baud / 16, baud); 320 if (div < 0 || USHRT_MAX <= div) { 321 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); 322 return -EINVAL; 323 } 324 325 dll = (unsigned int)div & 0x00FFU; 326 dlm = ((unsigned int)div >> 8) & 0x00FFU; 327 328 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { 329 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); 330 return -EINVAL; 331 } 332 333 if (bits & ~PCH_UART_LCR_WLS) { 334 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); 335 return -EINVAL; 336 } 337 338 if (stb & ~PCH_UART_LCR_STB) { 339 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); 340 return -EINVAL; 341 } 342 343 lcr = parity; 344 lcr |= bits; 345 lcr |= stb; 346 347 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n", 348 __func__, baud, div, lcr, jiffies); 349 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 350 iowrite8(dll, priv->membase + PCH_UART_DLL); 351 iowrite8(dlm, priv->membase + PCH_UART_DLM); 352 iowrite8(lcr, priv->membase + UART_LCR); 353 354 return 0; 355 } 356 357 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, 358 unsigned int flag) 359 { 360 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { 361 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", 362 __func__, flag); 363 return -EINVAL; 364 } 365 366 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); 367 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, 368 priv->membase + UART_FCR); 369 iowrite8(priv->fcr, priv->membase + UART_FCR); 370 371 return 0; 372 } 373 374 static int pch_uart_hal_set_fifo(struct eg20t_port *priv, 375 unsigned int dmamode, 376 unsigned int fifo_size, unsigned int trigger) 377 { 378 u8 fcr; 379 380 if (dmamode & ~PCH_UART_FCR_DMS) { 381 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", 382 __func__, dmamode); 383 return -EINVAL; 384 } 385 386 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { 387 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", 388 __func__, fifo_size); 389 return -EINVAL; 390 } 391 392 if (trigger & ~PCH_UART_FCR_RFTL) { 393 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", 394 __func__, trigger); 395 return -EINVAL; 396 } 397 398 switch (priv->fifo_size) { 399 case 256: 400 priv->trigger_level = 401 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 402 break; 403 case 64: 404 priv->trigger_level = 405 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 406 break; 407 case 16: 408 priv->trigger_level = 409 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 410 break; 411 default: 412 priv->trigger_level = 413 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 414 break; 415 } 416 fcr = 417 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; 418 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); 419 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, 420 priv->membase + UART_FCR); 421 iowrite8(fcr, priv->membase + UART_FCR); 422 priv->fcr = fcr; 423 424 return 0; 425 } 426 427 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) 428 { 429 priv->dmsr = 0; 430 return get_msr(priv, priv->membase); 431 } 432 433 static void pch_uart_hal_write(struct eg20t_port *priv, 434 const unsigned char *buf, int tx_size) 435 { 436 int i; 437 unsigned int thr; 438 439 for (i = 0; i < tx_size;) { 440 thr = buf[i++]; 441 iowrite8(thr, priv->membase + PCH_UART_THR); 442 } 443 } 444 445 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, 446 int rx_size) 447 { 448 int i; 449 u8 rbr, lsr; 450 451 lsr = ioread8(priv->membase + UART_LSR); 452 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); 453 i < rx_size && lsr & UART_LSR_DR; 454 lsr = ioread8(priv->membase + UART_LSR)) { 455 rbr = ioread8(priv->membase + PCH_UART_RBR); 456 buf[i++] = rbr; 457 } 458 return i; 459 } 460 461 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv) 462 { 463 unsigned int iir; 464 int ret; 465 466 iir = ioread8(priv->membase + UART_IIR); 467 ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP)); 468 return ret; 469 } 470 471 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) 472 { 473 return ioread8(priv->membase + UART_LSR); 474 } 475 476 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) 477 { 478 unsigned int lcr; 479 480 lcr = ioread8(priv->membase + UART_LCR); 481 if (on) 482 lcr |= PCH_UART_LCR_SB; 483 else 484 lcr &= ~PCH_UART_LCR_SB; 485 486 iowrite8(lcr, priv->membase + UART_LCR); 487 } 488 489 static int push_rx(struct eg20t_port *priv, const unsigned char *buf, 490 int size) 491 { 492 struct uart_port *port; 493 struct tty_struct *tty; 494 495 port = &priv->port; 496 tty = tty_port_tty_get(&port->state->port); 497 if (!tty) { 498 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 499 return -EBUSY; 500 } 501 502 tty_insert_flip_string(tty, buf, size); 503 tty_flip_buffer_push(tty); 504 tty_kref_put(tty); 505 506 return 0; 507 } 508 509 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) 510 { 511 int ret; 512 struct uart_port *port = &priv->port; 513 514 if (port->x_char) { 515 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n", 516 __func__, port->x_char, jiffies); 517 buf[0] = port->x_char; 518 port->x_char = 0; 519 ret = 1; 520 } else { 521 ret = 0; 522 } 523 524 return ret; 525 } 526 527 static int dma_push_rx(struct eg20t_port *priv, int size) 528 { 529 struct tty_struct *tty; 530 int room; 531 struct uart_port *port = &priv->port; 532 533 port = &priv->port; 534 tty = tty_port_tty_get(&port->state->port); 535 if (!tty) { 536 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 537 return 0; 538 } 539 540 room = tty_buffer_request_room(tty, size); 541 542 if (room < size) 543 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 544 size - room); 545 if (!room) 546 return room; 547 548 tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size); 549 550 port->icount.rx += room; 551 tty_kref_put(tty); 552 553 return room; 554 } 555 556 static void pch_free_dma(struct uart_port *port) 557 { 558 struct eg20t_port *priv; 559 priv = container_of(port, struct eg20t_port, port); 560 561 if (priv->chan_tx) { 562 dma_release_channel(priv->chan_tx); 563 priv->chan_tx = NULL; 564 } 565 if (priv->chan_rx) { 566 dma_release_channel(priv->chan_rx); 567 priv->chan_rx = NULL; 568 } 569 if (sg_dma_address(&priv->sg_rx)) 570 dma_free_coherent(port->dev, port->fifosize, 571 sg_virt(&priv->sg_rx), 572 sg_dma_address(&priv->sg_rx)); 573 574 return; 575 } 576 577 static bool filter(struct dma_chan *chan, void *slave) 578 { 579 struct pch_dma_slave *param = slave; 580 581 if ((chan->chan_id == param->chan_id) && (param->dma_dev == 582 chan->device->dev)) { 583 chan->private = param; 584 return true; 585 } else { 586 return false; 587 } 588 } 589 590 static void pch_request_dma(struct uart_port *port) 591 { 592 dma_cap_mask_t mask; 593 struct dma_chan *chan; 594 struct pci_dev *dma_dev; 595 struct pch_dma_slave *param; 596 struct eg20t_port *priv = 597 container_of(port, struct eg20t_port, port); 598 dma_cap_zero(mask); 599 dma_cap_set(DMA_SLAVE, mask); 600 601 dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(0xa, 0)); /* Get DMA's dev 602 information */ 603 /* Set Tx DMA */ 604 param = &priv->param_tx; 605 param->dma_dev = &dma_dev->dev; 606 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ 607 608 param->tx_reg = port->mapbase + UART_TX; 609 chan = dma_request_channel(mask, filter, param); 610 if (!chan) { 611 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", 612 __func__); 613 return; 614 } 615 priv->chan_tx = chan; 616 617 /* Set Rx DMA */ 618 param = &priv->param_rx; 619 param->dma_dev = &dma_dev->dev; 620 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ 621 622 param->rx_reg = port->mapbase + UART_RX; 623 chan = dma_request_channel(mask, filter, param); 624 if (!chan) { 625 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", 626 __func__); 627 dma_release_channel(priv->chan_tx); 628 return; 629 } 630 631 /* Get Consistent memory for DMA */ 632 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, 633 &priv->rx_buf_dma, GFP_KERNEL); 634 priv->chan_rx = chan; 635 } 636 637 static void pch_dma_rx_complete(void *arg) 638 { 639 struct eg20t_port *priv = arg; 640 struct uart_port *port = &priv->port; 641 struct tty_struct *tty = tty_port_tty_get(&port->state->port); 642 int count; 643 644 if (!tty) { 645 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 646 return; 647 } 648 649 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); 650 count = dma_push_rx(priv, priv->trigger_level); 651 if (count) 652 tty_flip_buffer_push(tty); 653 tty_kref_put(tty); 654 async_tx_ack(priv->desc_rx); 655 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT); 656 } 657 658 static void pch_dma_tx_complete(void *arg) 659 { 660 struct eg20t_port *priv = arg; 661 struct uart_port *port = &priv->port; 662 struct circ_buf *xmit = &port->state->xmit; 663 struct scatterlist *sg = priv->sg_tx_p; 664 int i; 665 666 for (i = 0; i < priv->nent; i++, sg++) { 667 xmit->tail += sg_dma_len(sg); 668 port->icount.tx += sg_dma_len(sg); 669 } 670 xmit->tail &= UART_XMIT_SIZE - 1; 671 async_tx_ack(priv->desc_tx); 672 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE); 673 priv->tx_dma_use = 0; 674 priv->nent = 0; 675 kfree(priv->sg_tx_p); 676 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 677 } 678 679 static int pop_tx(struct eg20t_port *priv, int size) 680 { 681 int count = 0; 682 struct uart_port *port = &priv->port; 683 struct circ_buf *xmit = &port->state->xmit; 684 685 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size) 686 goto pop_tx_end; 687 688 do { 689 int cnt_to_end = 690 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 691 int sz = min(size - count, cnt_to_end); 692 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz); 693 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1); 694 count += sz; 695 } while (!uart_circ_empty(xmit) && count < size); 696 697 pop_tx_end: 698 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n", 699 count, size - count, jiffies); 700 701 return count; 702 } 703 704 static int handle_rx_to(struct eg20t_port *priv) 705 { 706 struct pch_uart_buffer *buf; 707 int rx_size; 708 int ret; 709 if (!priv->start_rx) { 710 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT); 711 return 0; 712 } 713 buf = &priv->rxbuf; 714 do { 715 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); 716 ret = push_rx(priv, buf->buf, rx_size); 717 if (ret) 718 return 0; 719 } while (rx_size == buf->size); 720 721 return PCH_UART_HANDLED_RX_INT; 722 } 723 724 static int handle_rx(struct eg20t_port *priv) 725 { 726 return handle_rx_to(priv); 727 } 728 729 static int dma_handle_rx(struct eg20t_port *priv) 730 { 731 struct uart_port *port = &priv->port; 732 struct dma_async_tx_descriptor *desc; 733 struct scatterlist *sg; 734 735 priv = container_of(port, struct eg20t_port, port); 736 sg = &priv->sg_rx; 737 738 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ 739 740 sg_dma_len(sg) = priv->trigger_level; 741 742 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), 743 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt & 744 ~PAGE_MASK); 745 746 sg_dma_address(sg) = priv->rx_buf_dma; 747 748 desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx, 749 sg, 1, DMA_FROM_DEVICE, 750 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 751 752 if (!desc) 753 return 0; 754 755 priv->desc_rx = desc; 756 desc->callback = pch_dma_rx_complete; 757 desc->callback_param = priv; 758 desc->tx_submit(desc); 759 dma_async_issue_pending(priv->chan_rx); 760 761 return PCH_UART_HANDLED_RX_INT; 762 } 763 764 static unsigned int handle_tx(struct eg20t_port *priv) 765 { 766 struct uart_port *port = &priv->port; 767 struct circ_buf *xmit = &port->state->xmit; 768 int fifo_size; 769 int tx_size; 770 int size; 771 int tx_empty; 772 773 if (!priv->start_tx) { 774 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 775 __func__, jiffies); 776 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 777 priv->tx_empty = 1; 778 return 0; 779 } 780 781 fifo_size = max(priv->fifo_size, 1); 782 tx_empty = 1; 783 if (pop_tx_x(priv, xmit->buf)) { 784 pch_uart_hal_write(priv, xmit->buf, 1); 785 port->icount.tx++; 786 tx_empty = 0; 787 fifo_size--; 788 } 789 size = min(xmit->head - xmit->tail, fifo_size); 790 if (size < 0) 791 size = fifo_size; 792 793 tx_size = pop_tx(priv, size); 794 if (tx_size > 0) { 795 port->icount.tx += tx_size; 796 tx_empty = 0; 797 } 798 799 priv->tx_empty = tx_empty; 800 801 if (tx_empty) { 802 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 803 uart_write_wakeup(port); 804 } 805 806 return PCH_UART_HANDLED_TX_INT; 807 } 808 809 static unsigned int dma_handle_tx(struct eg20t_port *priv) 810 { 811 struct uart_port *port = &priv->port; 812 struct circ_buf *xmit = &port->state->xmit; 813 struct scatterlist *sg; 814 int nent; 815 int fifo_size; 816 int tx_empty; 817 struct dma_async_tx_descriptor *desc; 818 int num; 819 int i; 820 int bytes; 821 int size; 822 int rem; 823 824 if (!priv->start_tx) { 825 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 826 __func__, jiffies); 827 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 828 priv->tx_empty = 1; 829 return 0; 830 } 831 832 if (priv->tx_dma_use) { 833 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", 834 __func__, jiffies); 835 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 836 priv->tx_empty = 1; 837 return 0; 838 } 839 840 fifo_size = max(priv->fifo_size, 1); 841 tx_empty = 1; 842 if (pop_tx_x(priv, xmit->buf)) { 843 pch_uart_hal_write(priv, xmit->buf, 1); 844 port->icount.tx++; 845 tx_empty = 0; 846 fifo_size--; 847 } 848 849 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail, 850 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head, 851 xmit->tail, UART_XMIT_SIZE)); 852 if (!bytes) { 853 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); 854 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 855 uart_write_wakeup(port); 856 return 0; 857 } 858 859 if (bytes > fifo_size) { 860 num = bytes / fifo_size + 1; 861 size = fifo_size; 862 rem = bytes % fifo_size; 863 } else { 864 num = 1; 865 size = bytes; 866 rem = bytes; 867 } 868 869 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", 870 __func__, num, size, rem); 871 872 priv->tx_dma_use = 1; 873 874 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); 875 876 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ 877 sg = priv->sg_tx_p; 878 879 for (i = 0; i < num; i++, sg++) { 880 if (i == (num - 1)) 881 sg_set_page(sg, virt_to_page(xmit->buf), 882 rem, fifo_size * i); 883 else 884 sg_set_page(sg, virt_to_page(xmit->buf), 885 size, fifo_size * i); 886 } 887 888 sg = priv->sg_tx_p; 889 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); 890 if (!nent) { 891 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); 892 return 0; 893 } 894 priv->nent = nent; 895 896 for (i = 0; i < nent; i++, sg++) { 897 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + 898 fifo_size * i; 899 sg_dma_address(sg) = (sg_dma_address(sg) & 900 ~(UART_XMIT_SIZE - 1)) + sg->offset; 901 if (i == (nent - 1)) 902 sg_dma_len(sg) = rem; 903 else 904 sg_dma_len(sg) = size; 905 } 906 907 desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx, 908 priv->sg_tx_p, nent, DMA_TO_DEVICE, 909 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 910 if (!desc) { 911 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n", 912 __func__); 913 return 0; 914 } 915 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); 916 priv->desc_tx = desc; 917 desc->callback = pch_dma_tx_complete; 918 desc->callback_param = priv; 919 920 desc->tx_submit(desc); 921 922 dma_async_issue_pending(priv->chan_tx); 923 924 return PCH_UART_HANDLED_TX_INT; 925 } 926 927 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) 928 { 929 u8 fcr = ioread8(priv->membase + UART_FCR); 930 931 /* Reset FIFO */ 932 fcr |= UART_FCR_CLEAR_RCVR; 933 iowrite8(fcr, priv->membase + UART_FCR); 934 935 if (lsr & PCH_UART_LSR_ERR) 936 dev_err(&priv->pdev->dev, "Error data in FIFO\n"); 937 938 if (lsr & UART_LSR_FE) 939 dev_err(&priv->pdev->dev, "Framing Error\n"); 940 941 if (lsr & UART_LSR_PE) 942 dev_err(&priv->pdev->dev, "Parity Error\n"); 943 944 if (lsr & UART_LSR_OE) 945 dev_err(&priv->pdev->dev, "Overrun Error\n"); 946 } 947 948 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) 949 { 950 struct eg20t_port *priv = dev_id; 951 unsigned int handled; 952 u8 lsr; 953 int ret = 0; 954 unsigned int iid; 955 unsigned long flags; 956 957 spin_lock_irqsave(&priv->port.lock, flags); 958 handled = 0; 959 while ((iid = pch_uart_hal_get_iid(priv)) > 1) { 960 switch (iid) { 961 case PCH_UART_IID_RLS: /* Receiver Line Status */ 962 lsr = pch_uart_hal_get_line_status(priv); 963 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | 964 UART_LSR_PE | UART_LSR_OE)) { 965 pch_uart_err_ir(priv, lsr); 966 ret = PCH_UART_HANDLED_RX_ERR_INT; 967 } 968 break; 969 case PCH_UART_IID_RDR: /* Received Data Ready */ 970 if (priv->use_dma) { 971 pch_uart_hal_disable_interrupt(priv, 972 PCH_UART_HAL_RX_INT); 973 ret = dma_handle_rx(priv); 974 if (!ret) 975 pch_uart_hal_enable_interrupt(priv, 976 PCH_UART_HAL_RX_INT); 977 } else { 978 ret = handle_rx(priv); 979 } 980 break; 981 case PCH_UART_IID_RDR_TO: /* Received Data Ready 982 (FIFO Timeout) */ 983 ret = handle_rx_to(priv); 984 break; 985 case PCH_UART_IID_THRE: /* Transmitter Holding Register 986 Empty */ 987 if (priv->use_dma) 988 ret = dma_handle_tx(priv); 989 else 990 ret = handle_tx(priv); 991 break; 992 case PCH_UART_IID_MS: /* Modem Status */ 993 ret = PCH_UART_HANDLED_MS_INT; 994 break; 995 default: /* Never junp to this label */ 996 dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__, 997 iid, jiffies); 998 ret = -1; 999 break; 1000 } 1001 handled |= (unsigned int)ret; 1002 } 1003 if (handled == 0 && iid <= 1) { 1004 if (priv->int_dis_flag) 1005 priv->int_dis_flag = 0; 1006 } 1007 1008 spin_unlock_irqrestore(&priv->port.lock, flags); 1009 return IRQ_RETVAL(handled); 1010 } 1011 1012 /* This function tests whether the transmitter fifo and shifter for the port 1013 described by 'port' is empty. */ 1014 static unsigned int pch_uart_tx_empty(struct uart_port *port) 1015 { 1016 struct eg20t_port *priv; 1017 int ret; 1018 priv = container_of(port, struct eg20t_port, port); 1019 if (priv->tx_empty) 1020 ret = TIOCSER_TEMT; 1021 else 1022 ret = 0; 1023 1024 return ret; 1025 } 1026 1027 /* Returns the current state of modem control inputs. */ 1028 static unsigned int pch_uart_get_mctrl(struct uart_port *port) 1029 { 1030 struct eg20t_port *priv; 1031 u8 modem; 1032 unsigned int ret = 0; 1033 1034 priv = container_of(port, struct eg20t_port, port); 1035 modem = pch_uart_hal_get_modem(priv); 1036 1037 if (modem & UART_MSR_DCD) 1038 ret |= TIOCM_CAR; 1039 1040 if (modem & UART_MSR_RI) 1041 ret |= TIOCM_RNG; 1042 1043 if (modem & UART_MSR_DSR) 1044 ret |= TIOCM_DSR; 1045 1046 if (modem & UART_MSR_CTS) 1047 ret |= TIOCM_CTS; 1048 1049 return ret; 1050 } 1051 1052 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1053 { 1054 u32 mcr = 0; 1055 struct eg20t_port *priv = container_of(port, struct eg20t_port, port); 1056 1057 if (mctrl & TIOCM_DTR) 1058 mcr |= UART_MCR_DTR; 1059 if (mctrl & TIOCM_RTS) 1060 mcr |= UART_MCR_RTS; 1061 if (mctrl & TIOCM_LOOP) 1062 mcr |= UART_MCR_LOOP; 1063 1064 if (priv->mcr & UART_MCR_AFE) 1065 mcr |= UART_MCR_AFE; 1066 1067 if (mctrl) 1068 iowrite8(mcr, priv->membase + UART_MCR); 1069 } 1070 1071 static void pch_uart_stop_tx(struct uart_port *port) 1072 { 1073 struct eg20t_port *priv; 1074 priv = container_of(port, struct eg20t_port, port); 1075 priv->start_tx = 0; 1076 priv->tx_dma_use = 0; 1077 } 1078 1079 static void pch_uart_start_tx(struct uart_port *port) 1080 { 1081 struct eg20t_port *priv; 1082 1083 priv = container_of(port, struct eg20t_port, port); 1084 1085 if (priv->use_dma) { 1086 if (priv->tx_dma_use) { 1087 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", 1088 __func__); 1089 return; 1090 } 1091 } 1092 1093 priv->start_tx = 1; 1094 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 1095 } 1096 1097 static void pch_uart_stop_rx(struct uart_port *port) 1098 { 1099 struct eg20t_port *priv; 1100 priv = container_of(port, struct eg20t_port, port); 1101 priv->start_rx = 0; 1102 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT); 1103 priv->int_dis_flag = 1; 1104 } 1105 1106 /* Enable the modem status interrupts. */ 1107 static void pch_uart_enable_ms(struct uart_port *port) 1108 { 1109 struct eg20t_port *priv; 1110 priv = container_of(port, struct eg20t_port, port); 1111 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); 1112 } 1113 1114 /* Control the transmission of a break signal. */ 1115 static void pch_uart_break_ctl(struct uart_port *port, int ctl) 1116 { 1117 struct eg20t_port *priv; 1118 unsigned long flags; 1119 1120 priv = container_of(port, struct eg20t_port, port); 1121 spin_lock_irqsave(&port->lock, flags); 1122 pch_uart_hal_set_break(priv, ctl); 1123 spin_unlock_irqrestore(&port->lock, flags); 1124 } 1125 1126 /* Grab any interrupt resources and initialise any low level driver state. */ 1127 static int pch_uart_startup(struct uart_port *port) 1128 { 1129 struct eg20t_port *priv; 1130 int ret; 1131 int fifo_size; 1132 int trigger_level; 1133 1134 priv = container_of(port, struct eg20t_port, port); 1135 priv->tx_empty = 1; 1136 1137 if (port->uartclk) 1138 priv->base_baud = port->uartclk; 1139 else 1140 port->uartclk = priv->base_baud; 1141 1142 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1143 ret = pch_uart_hal_set_line(priv, default_baud, 1144 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, 1145 PCH_UART_HAL_STB1); 1146 if (ret) 1147 return ret; 1148 1149 switch (priv->fifo_size) { 1150 case 256: 1151 fifo_size = PCH_UART_HAL_FIFO256; 1152 break; 1153 case 64: 1154 fifo_size = PCH_UART_HAL_FIFO64; 1155 break; 1156 case 16: 1157 fifo_size = PCH_UART_HAL_FIFO16; 1158 case 1: 1159 default: 1160 fifo_size = PCH_UART_HAL_FIFO_DIS; 1161 break; 1162 } 1163 1164 switch (priv->trigger) { 1165 case PCH_UART_HAL_TRIGGER1: 1166 trigger_level = 1; 1167 break; 1168 case PCH_UART_HAL_TRIGGER_L: 1169 trigger_level = priv->fifo_size / 4; 1170 break; 1171 case PCH_UART_HAL_TRIGGER_M: 1172 trigger_level = priv->fifo_size / 2; 1173 break; 1174 case PCH_UART_HAL_TRIGGER_H: 1175 default: 1176 trigger_level = priv->fifo_size - (priv->fifo_size / 8); 1177 break; 1178 } 1179 1180 priv->trigger_level = trigger_level; 1181 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1182 fifo_size, priv->trigger); 1183 if (ret < 0) 1184 return ret; 1185 1186 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, 1187 KBUILD_MODNAME, priv); 1188 if (ret < 0) 1189 return ret; 1190 1191 if (priv->use_dma) 1192 pch_request_dma(port); 1193 1194 priv->start_rx = 1; 1195 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT); 1196 uart_update_timeout(port, CS8, default_baud); 1197 1198 return 0; 1199 } 1200 1201 static void pch_uart_shutdown(struct uart_port *port) 1202 { 1203 struct eg20t_port *priv; 1204 int ret; 1205 1206 priv = container_of(port, struct eg20t_port, port); 1207 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1208 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); 1209 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1210 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); 1211 if (ret) 1212 dev_err(priv->port.dev, 1213 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); 1214 1215 if (priv->use_dma_flag) 1216 pch_free_dma(port); 1217 1218 free_irq(priv->port.irq, priv); 1219 } 1220 1221 /* Change the port parameters, including word length, parity, stop 1222 *bits. Update read_status_mask and ignore_status_mask to indicate 1223 *the types of events we are interested in receiving. */ 1224 static void pch_uart_set_termios(struct uart_port *port, 1225 struct ktermios *termios, struct ktermios *old) 1226 { 1227 int baud; 1228 int rtn; 1229 unsigned int parity, bits, stb; 1230 struct eg20t_port *priv; 1231 unsigned long flags; 1232 1233 priv = container_of(port, struct eg20t_port, port); 1234 switch (termios->c_cflag & CSIZE) { 1235 case CS5: 1236 bits = PCH_UART_HAL_5BIT; 1237 break; 1238 case CS6: 1239 bits = PCH_UART_HAL_6BIT; 1240 break; 1241 case CS7: 1242 bits = PCH_UART_HAL_7BIT; 1243 break; 1244 default: /* CS8 */ 1245 bits = PCH_UART_HAL_8BIT; 1246 break; 1247 } 1248 if (termios->c_cflag & CSTOPB) 1249 stb = PCH_UART_HAL_STB2; 1250 else 1251 stb = PCH_UART_HAL_STB1; 1252 1253 if (termios->c_cflag & PARENB) { 1254 if (!(termios->c_cflag & PARODD)) 1255 parity = PCH_UART_HAL_PARITY_ODD; 1256 else 1257 parity = PCH_UART_HAL_PARITY_EVEN; 1258 1259 } else { 1260 parity = PCH_UART_HAL_PARITY_NONE; 1261 } 1262 1263 /* Only UART0 has auto hardware flow function */ 1264 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) 1265 priv->mcr |= UART_MCR_AFE; 1266 else 1267 priv->mcr &= ~UART_MCR_AFE; 1268 1269 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 1270 1271 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1272 1273 spin_lock_irqsave(&port->lock, flags); 1274 1275 uart_update_timeout(port, termios->c_cflag, baud); 1276 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); 1277 if (rtn) 1278 goto out; 1279 1280 /* Don't rewrite B0 */ 1281 if (tty_termios_baud_rate(termios)) 1282 tty_termios_encode_baud_rate(termios, baud, baud); 1283 1284 out: 1285 spin_unlock_irqrestore(&port->lock, flags); 1286 } 1287 1288 static const char *pch_uart_type(struct uart_port *port) 1289 { 1290 return KBUILD_MODNAME; 1291 } 1292 1293 static void pch_uart_release_port(struct uart_port *port) 1294 { 1295 struct eg20t_port *priv; 1296 1297 priv = container_of(port, struct eg20t_port, port); 1298 pci_iounmap(priv->pdev, priv->membase); 1299 pci_release_regions(priv->pdev); 1300 } 1301 1302 static int pch_uart_request_port(struct uart_port *port) 1303 { 1304 struct eg20t_port *priv; 1305 int ret; 1306 void __iomem *membase; 1307 1308 priv = container_of(port, struct eg20t_port, port); 1309 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); 1310 if (ret < 0) 1311 return -EBUSY; 1312 1313 membase = pci_iomap(priv->pdev, 1, 0); 1314 if (!membase) { 1315 pci_release_regions(priv->pdev); 1316 return -EBUSY; 1317 } 1318 priv->membase = port->membase = membase; 1319 1320 return 0; 1321 } 1322 1323 static void pch_uart_config_port(struct uart_port *port, int type) 1324 { 1325 struct eg20t_port *priv; 1326 1327 priv = container_of(port, struct eg20t_port, port); 1328 if (type & UART_CONFIG_TYPE) { 1329 port->type = priv->port_type; 1330 pch_uart_request_port(port); 1331 } 1332 } 1333 1334 static int pch_uart_verify_port(struct uart_port *port, 1335 struct serial_struct *serinfo) 1336 { 1337 struct eg20t_port *priv; 1338 1339 priv = container_of(port, struct eg20t_port, port); 1340 if (serinfo->flags & UPF_LOW_LATENCY) { 1341 dev_info(priv->port.dev, 1342 "PCH UART : Use PIO Mode (without DMA)\n"); 1343 priv->use_dma = 0; 1344 serinfo->flags &= ~UPF_LOW_LATENCY; 1345 } else { 1346 #ifndef CONFIG_PCH_DMA 1347 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", 1348 __func__); 1349 return -EOPNOTSUPP; 1350 #endif 1351 priv->use_dma = 1; 1352 priv->use_dma_flag = 1; 1353 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n"); 1354 } 1355 1356 return 0; 1357 } 1358 1359 static struct uart_ops pch_uart_ops = { 1360 .tx_empty = pch_uart_tx_empty, 1361 .set_mctrl = pch_uart_set_mctrl, 1362 .get_mctrl = pch_uart_get_mctrl, 1363 .stop_tx = pch_uart_stop_tx, 1364 .start_tx = pch_uart_start_tx, 1365 .stop_rx = pch_uart_stop_rx, 1366 .enable_ms = pch_uart_enable_ms, 1367 .break_ctl = pch_uart_break_ctl, 1368 .startup = pch_uart_startup, 1369 .shutdown = pch_uart_shutdown, 1370 .set_termios = pch_uart_set_termios, 1371 /* .pm = pch_uart_pm, Not supported yet */ 1372 /* .set_wake = pch_uart_set_wake, Not supported yet */ 1373 .type = pch_uart_type, 1374 .release_port = pch_uart_release_port, 1375 .request_port = pch_uart_request_port, 1376 .config_port = pch_uart_config_port, 1377 .verify_port = pch_uart_verify_port 1378 }; 1379 1380 static struct uart_driver pch_uart_driver = { 1381 .owner = THIS_MODULE, 1382 .driver_name = KBUILD_MODNAME, 1383 .dev_name = PCH_UART_DRIVER_DEVICE, 1384 .major = 0, 1385 .minor = 0, 1386 .nr = PCH_UART_NR, 1387 }; 1388 1389 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, 1390 const struct pci_device_id *id) 1391 { 1392 struct eg20t_port *priv; 1393 int ret; 1394 unsigned int iobase; 1395 unsigned int mapbase; 1396 unsigned char *rxbuf; 1397 int fifosize, base_baud; 1398 int port_type; 1399 struct pch_uart_driver_data *board; 1400 1401 board = &drv_dat[id->driver_data]; 1402 port_type = board->port_type; 1403 1404 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); 1405 if (priv == NULL) 1406 goto init_port_alloc_err; 1407 1408 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); 1409 if (!rxbuf) 1410 goto init_port_free_txbuf; 1411 1412 base_baud = 1843200; /* 1.8432MHz */ 1413 1414 /* quirk for CM-iTC board */ 1415 if (strstr(dmi_get_system_info(DMI_BOARD_NAME), "CM-iTC")) 1416 base_baud = 192000000; /* 192.0MHz */ 1417 1418 switch (port_type) { 1419 case PORT_UNKNOWN: 1420 fifosize = 256; /* EG20T/ML7213: UART0 */ 1421 break; 1422 case PORT_8250: 1423 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ 1424 break; 1425 default: 1426 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); 1427 goto init_port_hal_free; 1428 } 1429 1430 iobase = pci_resource_start(pdev, 0); 1431 mapbase = pci_resource_start(pdev, 1); 1432 priv->mapbase = mapbase; 1433 priv->iobase = iobase; 1434 priv->pdev = pdev; 1435 priv->tx_empty = 1; 1436 priv->rxbuf.buf = rxbuf; 1437 priv->rxbuf.size = PAGE_SIZE; 1438 1439 priv->fifo_size = fifosize; 1440 priv->base_baud = base_baud; 1441 priv->port_type = PORT_MAX_8250 + port_type + 1; 1442 priv->port.dev = &pdev->dev; 1443 priv->port.iobase = iobase; 1444 priv->port.membase = NULL; 1445 priv->port.mapbase = mapbase; 1446 priv->port.irq = pdev->irq; 1447 priv->port.iotype = UPIO_PORT; 1448 priv->port.ops = &pch_uart_ops; 1449 priv->port.flags = UPF_BOOT_AUTOCONF; 1450 priv->port.fifosize = fifosize; 1451 priv->port.line = board->line_no; 1452 priv->trigger = PCH_UART_HAL_TRIGGER_M; 1453 1454 spin_lock_init(&priv->port.lock); 1455 1456 pci_set_drvdata(pdev, priv); 1457 pch_uart_hal_request(pdev, fifosize, base_baud); 1458 1459 ret = uart_add_one_port(&pch_uart_driver, &priv->port); 1460 if (ret < 0) 1461 goto init_port_hal_free; 1462 1463 return priv; 1464 1465 init_port_hal_free: 1466 free_page((unsigned long)rxbuf); 1467 init_port_free_txbuf: 1468 kfree(priv); 1469 init_port_alloc_err: 1470 1471 return NULL; 1472 } 1473 1474 static void pch_uart_exit_port(struct eg20t_port *priv) 1475 { 1476 uart_remove_one_port(&pch_uart_driver, &priv->port); 1477 pci_set_drvdata(priv->pdev, NULL); 1478 free_page((unsigned long)priv->rxbuf.buf); 1479 } 1480 1481 static void pch_uart_pci_remove(struct pci_dev *pdev) 1482 { 1483 struct eg20t_port *priv; 1484 1485 priv = (struct eg20t_port *)pci_get_drvdata(pdev); 1486 pch_uart_exit_port(priv); 1487 pci_disable_device(pdev); 1488 kfree(priv); 1489 return; 1490 } 1491 #ifdef CONFIG_PM 1492 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1493 { 1494 struct eg20t_port *priv = pci_get_drvdata(pdev); 1495 1496 uart_suspend_port(&pch_uart_driver, &priv->port); 1497 1498 pci_save_state(pdev); 1499 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1500 return 0; 1501 } 1502 1503 static int pch_uart_pci_resume(struct pci_dev *pdev) 1504 { 1505 struct eg20t_port *priv = pci_get_drvdata(pdev); 1506 int ret; 1507 1508 pci_set_power_state(pdev, PCI_D0); 1509 pci_restore_state(pdev); 1510 1511 ret = pci_enable_device(pdev); 1512 if (ret) { 1513 dev_err(&pdev->dev, 1514 "%s-pci_enable_device failed(ret=%d) ", __func__, ret); 1515 return ret; 1516 } 1517 1518 uart_resume_port(&pch_uart_driver, &priv->port); 1519 1520 return 0; 1521 } 1522 #else 1523 #define pch_uart_pci_suspend NULL 1524 #define pch_uart_pci_resume NULL 1525 #endif 1526 1527 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = { 1528 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), 1529 .driver_data = pch_et20t_uart0}, 1530 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), 1531 .driver_data = pch_et20t_uart1}, 1532 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), 1533 .driver_data = pch_et20t_uart2}, 1534 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), 1535 .driver_data = pch_et20t_uart3}, 1536 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), 1537 .driver_data = pch_ml7213_uart0}, 1538 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), 1539 .driver_data = pch_ml7213_uart1}, 1540 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), 1541 .driver_data = pch_ml7213_uart2}, 1542 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C), 1543 .driver_data = pch_ml7223_uart0}, 1544 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D), 1545 .driver_data = pch_ml7223_uart1}, 1546 {0,}, 1547 }; 1548 1549 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev, 1550 const struct pci_device_id *id) 1551 { 1552 int ret; 1553 struct eg20t_port *priv; 1554 1555 ret = pci_enable_device(pdev); 1556 if (ret < 0) 1557 goto probe_error; 1558 1559 priv = pch_uart_init_port(pdev, id); 1560 if (!priv) { 1561 ret = -EBUSY; 1562 goto probe_disable_device; 1563 } 1564 pci_set_drvdata(pdev, priv); 1565 1566 return ret; 1567 1568 probe_disable_device: 1569 pci_disable_device(pdev); 1570 probe_error: 1571 return ret; 1572 } 1573 1574 static struct pci_driver pch_uart_pci_driver = { 1575 .name = "pch_uart", 1576 .id_table = pch_uart_pci_id, 1577 .probe = pch_uart_pci_probe, 1578 .remove = __devexit_p(pch_uart_pci_remove), 1579 .suspend = pch_uart_pci_suspend, 1580 .resume = pch_uart_pci_resume, 1581 }; 1582 1583 static int __init pch_uart_module_init(void) 1584 { 1585 int ret; 1586 1587 /* register as UART driver */ 1588 ret = uart_register_driver(&pch_uart_driver); 1589 if (ret < 0) 1590 return ret; 1591 1592 /* register as PCI driver */ 1593 ret = pci_register_driver(&pch_uart_pci_driver); 1594 if (ret < 0) 1595 uart_unregister_driver(&pch_uart_driver); 1596 1597 return ret; 1598 } 1599 module_init(pch_uart_module_init); 1600 1601 static void __exit pch_uart_module_exit(void) 1602 { 1603 pci_unregister_driver(&pch_uart_pci_driver); 1604 uart_unregister_driver(&pch_uart_driver); 1605 } 1606 module_exit(pch_uart_module_exit); 1607 1608 MODULE_LICENSE("GPL v2"); 1609 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); 1610 module_param(default_baud, uint, S_IRUGO); 1611