1 /* 2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 3 * 4 *This program is free software; you can redistribute it and/or modify 5 *it under the terms of the GNU General Public License as published by 6 *the Free Software Foundation; version 2 of the License. 7 * 8 *This program is distributed in the hope that it will be useful, 9 *but WITHOUT ANY WARRANTY; without even the implied warranty of 10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 *GNU General Public License for more details. 12 * 13 *You should have received a copy of the GNU General Public License 14 *along with this program; if not, write to the Free Software 15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 16 */ 17 #include <linux/kernel.h> 18 #include <linux/serial_reg.h> 19 #include <linux/slab.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/serial_core.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/dmi.h> 28 #include <linux/console.h> 29 #include <linux/nmi.h> 30 #include <linux/delay.h> 31 32 #include <linux/debugfs.h> 33 #include <linux/dmaengine.h> 34 #include <linux/pch_dma.h> 35 36 enum { 37 PCH_UART_HANDLED_RX_INT_SHIFT, 38 PCH_UART_HANDLED_TX_INT_SHIFT, 39 PCH_UART_HANDLED_RX_ERR_INT_SHIFT, 40 PCH_UART_HANDLED_RX_TRG_INT_SHIFT, 41 PCH_UART_HANDLED_MS_INT_SHIFT, 42 }; 43 44 enum { 45 PCH_UART_8LINE, 46 PCH_UART_2LINE, 47 }; 48 49 #define PCH_UART_DRIVER_DEVICE "ttyPCH" 50 51 /* Set the max number of UART port 52 * Intel EG20T PCH: 4 port 53 * LAPIS Semiconductor ML7213 IOH: 3 port 54 * LAPIS Semiconductor ML7223 IOH: 2 port 55 */ 56 #define PCH_UART_NR 4 57 58 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) 59 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) 60 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ 61 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) 62 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ 63 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) 64 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) 65 66 #define PCH_UART_RBR 0x00 67 #define PCH_UART_THR 0x00 68 69 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ 70 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) 71 #define PCH_UART_IER_ERBFI 0x00000001 72 #define PCH_UART_IER_ETBEI 0x00000002 73 #define PCH_UART_IER_ELSI 0x00000004 74 #define PCH_UART_IER_EDSSI 0x00000008 75 76 #define PCH_UART_IIR_IP 0x00000001 77 #define PCH_UART_IIR_IID 0x00000006 78 #define PCH_UART_IIR_MSI 0x00000000 79 #define PCH_UART_IIR_TRI 0x00000002 80 #define PCH_UART_IIR_RRI 0x00000004 81 #define PCH_UART_IIR_REI 0x00000006 82 #define PCH_UART_IIR_TOI 0x00000008 83 #define PCH_UART_IIR_FIFO256 0x00000020 84 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 85 #define PCH_UART_IIR_FE 0x000000C0 86 87 #define PCH_UART_FCR_FIFOE 0x00000001 88 #define PCH_UART_FCR_RFR 0x00000002 89 #define PCH_UART_FCR_TFR 0x00000004 90 #define PCH_UART_FCR_DMS 0x00000008 91 #define PCH_UART_FCR_FIFO256 0x00000020 92 #define PCH_UART_FCR_RFTL 0x000000C0 93 94 #define PCH_UART_FCR_RFTL1 0x00000000 95 #define PCH_UART_FCR_RFTL64 0x00000040 96 #define PCH_UART_FCR_RFTL128 0x00000080 97 #define PCH_UART_FCR_RFTL224 0x000000C0 98 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 99 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 100 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 101 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 102 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 103 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 104 #define PCH_UART_FCR_RFTL_SHIFT 6 105 106 #define PCH_UART_LCR_WLS 0x00000003 107 #define PCH_UART_LCR_STB 0x00000004 108 #define PCH_UART_LCR_PEN 0x00000008 109 #define PCH_UART_LCR_EPS 0x00000010 110 #define PCH_UART_LCR_SP 0x00000020 111 #define PCH_UART_LCR_SB 0x00000040 112 #define PCH_UART_LCR_DLAB 0x00000080 113 #define PCH_UART_LCR_NP 0x00000000 114 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN 115 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) 116 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) 117 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ 118 PCH_UART_LCR_SP) 119 120 #define PCH_UART_LCR_5BIT 0x00000000 121 #define PCH_UART_LCR_6BIT 0x00000001 122 #define PCH_UART_LCR_7BIT 0x00000002 123 #define PCH_UART_LCR_8BIT 0x00000003 124 125 #define PCH_UART_MCR_DTR 0x00000001 126 #define PCH_UART_MCR_RTS 0x00000002 127 #define PCH_UART_MCR_OUT 0x0000000C 128 #define PCH_UART_MCR_LOOP 0x00000010 129 #define PCH_UART_MCR_AFE 0x00000020 130 131 #define PCH_UART_LSR_DR 0x00000001 132 #define PCH_UART_LSR_ERR (1<<7) 133 134 #define PCH_UART_MSR_DCTS 0x00000001 135 #define PCH_UART_MSR_DDSR 0x00000002 136 #define PCH_UART_MSR_TERI 0x00000004 137 #define PCH_UART_MSR_DDCD 0x00000008 138 #define PCH_UART_MSR_CTS 0x00000010 139 #define PCH_UART_MSR_DSR 0x00000020 140 #define PCH_UART_MSR_RI 0x00000040 141 #define PCH_UART_MSR_DCD 0x00000080 142 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ 143 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) 144 145 #define PCH_UART_DLL 0x00 146 #define PCH_UART_DLM 0x01 147 148 #define PCH_UART_BRCSR 0x0E 149 150 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) 151 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) 152 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) 153 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) 154 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) 155 156 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) 157 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) 158 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) 159 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) 160 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) 161 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) 162 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) 163 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) 164 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) 165 #define PCH_UART_HAL_STB1 0 166 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) 167 168 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) 169 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) 170 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ 171 PCH_UART_HAL_CLR_RX_FIFO) 172 173 #define PCH_UART_HAL_DMA_MODE0 0 174 #define PCH_UART_HAL_FIFO_DIS 0 175 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) 176 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ 177 PCH_UART_FCR_FIFO256) 178 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) 179 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) 180 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) 181 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) 182 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) 183 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) 184 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) 185 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) 186 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) 187 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) 188 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) 189 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) 190 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) 191 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) 192 193 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) 194 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) 195 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) 196 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) 197 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) 198 199 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) 200 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) 201 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) 202 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) 203 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) 204 205 #define PCI_VENDOR_ID_ROHM 0x10DB 206 207 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 208 209 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */ 210 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */ 211 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */ 212 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */ 213 214 struct pch_uart_buffer { 215 unsigned char *buf; 216 int size; 217 }; 218 219 struct eg20t_port { 220 struct uart_port port; 221 int port_type; 222 void __iomem *membase; 223 resource_size_t mapbase; 224 unsigned int iobase; 225 struct pci_dev *pdev; 226 int fifo_size; 227 int uartclk; 228 int start_tx; 229 int start_rx; 230 int tx_empty; 231 int int_dis_flag; 232 int trigger; 233 int trigger_level; 234 struct pch_uart_buffer rxbuf; 235 unsigned int dmsr; 236 unsigned int fcr; 237 unsigned int mcr; 238 unsigned int use_dma; 239 unsigned int use_dma_flag; 240 struct dma_async_tx_descriptor *desc_tx; 241 struct dma_async_tx_descriptor *desc_rx; 242 struct pch_dma_slave param_tx; 243 struct pch_dma_slave param_rx; 244 struct dma_chan *chan_tx; 245 struct dma_chan *chan_rx; 246 struct scatterlist *sg_tx_p; 247 int nent; 248 struct scatterlist sg_rx; 249 int tx_dma_use; 250 void *rx_buf_virt; 251 dma_addr_t rx_buf_dma; 252 253 struct dentry *debugfs; 254 }; 255 256 /** 257 * struct pch_uart_driver_data - private data structure for UART-DMA 258 * @port_type: The number of DMA channel 259 * @line_no: UART port line number (0, 1, 2...) 260 */ 261 struct pch_uart_driver_data { 262 int port_type; 263 int line_no; 264 }; 265 266 enum pch_uart_num_t { 267 pch_et20t_uart0 = 0, 268 pch_et20t_uart1, 269 pch_et20t_uart2, 270 pch_et20t_uart3, 271 pch_ml7213_uart0, 272 pch_ml7213_uart1, 273 pch_ml7213_uart2, 274 pch_ml7223_uart0, 275 pch_ml7223_uart1, 276 pch_ml7831_uart0, 277 pch_ml7831_uart1, 278 }; 279 280 static struct pch_uart_driver_data drv_dat[] = { 281 [pch_et20t_uart0] = {PCH_UART_8LINE, 0}, 282 [pch_et20t_uart1] = {PCH_UART_2LINE, 1}, 283 [pch_et20t_uart2] = {PCH_UART_2LINE, 2}, 284 [pch_et20t_uart3] = {PCH_UART_2LINE, 3}, 285 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0}, 286 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1}, 287 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2}, 288 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0}, 289 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1}, 290 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0}, 291 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1}, 292 }; 293 294 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 295 static struct eg20t_port *pch_uart_ports[PCH_UART_NR]; 296 #endif 297 static unsigned int default_baud = 9600; 298 static unsigned int user_uartclk = 0; 299 static const int trigger_level_256[4] = { 1, 64, 128, 224 }; 300 static const int trigger_level_64[4] = { 1, 16, 32, 56 }; 301 static const int trigger_level_16[4] = { 1, 4, 8, 14 }; 302 static const int trigger_level_1[4] = { 1, 1, 1, 1 }; 303 304 #ifdef CONFIG_DEBUG_FS 305 306 #define PCH_REGS_BUFSIZE 1024 307 308 309 static ssize_t port_show_regs(struct file *file, char __user *user_buf, 310 size_t count, loff_t *ppos) 311 { 312 struct eg20t_port *priv = file->private_data; 313 char *buf; 314 u32 len = 0; 315 ssize_t ret; 316 unsigned char lcr; 317 318 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL); 319 if (!buf) 320 return 0; 321 322 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 323 "PCH EG20T port[%d] regs:\n", priv->port.line); 324 325 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 326 "=================================\n"); 327 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 328 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); 329 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 330 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); 331 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 332 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); 333 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 334 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); 335 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 336 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); 337 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 338 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); 339 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 340 "BRCSR: \t0x%02x\n", 341 ioread8(priv->membase + PCH_UART_BRCSR)); 342 343 lcr = ioread8(priv->membase + UART_LCR); 344 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 345 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 346 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); 347 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 348 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); 349 iowrite8(lcr, priv->membase + UART_LCR); 350 351 if (len > PCH_REGS_BUFSIZE) 352 len = PCH_REGS_BUFSIZE; 353 354 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 355 kfree(buf); 356 return ret; 357 } 358 359 static const struct file_operations port_regs_ops = { 360 .owner = THIS_MODULE, 361 .open = simple_open, 362 .read = port_show_regs, 363 .llseek = default_llseek, 364 }; 365 #endif /* CONFIG_DEBUG_FS */ 366 367 /* Return UART clock, checking for board specific clocks. */ 368 static int pch_uart_get_uartclk(void) 369 { 370 const char *cmp; 371 372 if (user_uartclk) 373 return user_uartclk; 374 375 cmp = dmi_get_system_info(DMI_BOARD_NAME); 376 if (cmp && strstr(cmp, "CM-iTC")) 377 return CMITC_UARTCLK; 378 379 cmp = dmi_get_system_info(DMI_BIOS_VERSION); 380 if (cmp && strnstr(cmp, "FRI2", 4)) 381 return FRI2_64_UARTCLK; 382 383 cmp = dmi_get_system_info(DMI_PRODUCT_NAME); 384 if (cmp && strstr(cmp, "Fish River Island II")) 385 return FRI2_48_UARTCLK; 386 387 return DEFAULT_UARTCLK; 388 } 389 390 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, 391 unsigned int flag) 392 { 393 u8 ier = ioread8(priv->membase + UART_IER); 394 ier |= flag & PCH_UART_IER_MASK; 395 iowrite8(ier, priv->membase + UART_IER); 396 } 397 398 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, 399 unsigned int flag) 400 { 401 u8 ier = ioread8(priv->membase + UART_IER); 402 ier &= ~(flag & PCH_UART_IER_MASK); 403 iowrite8(ier, priv->membase + UART_IER); 404 } 405 406 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud, 407 unsigned int parity, unsigned int bits, 408 unsigned int stb) 409 { 410 unsigned int dll, dlm, lcr; 411 int div; 412 413 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); 414 if (div < 0 || USHRT_MAX <= div) { 415 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); 416 return -EINVAL; 417 } 418 419 dll = (unsigned int)div & 0x00FFU; 420 dlm = ((unsigned int)div >> 8) & 0x00FFU; 421 422 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { 423 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); 424 return -EINVAL; 425 } 426 427 if (bits & ~PCH_UART_LCR_WLS) { 428 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); 429 return -EINVAL; 430 } 431 432 if (stb & ~PCH_UART_LCR_STB) { 433 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); 434 return -EINVAL; 435 } 436 437 lcr = parity; 438 lcr |= bits; 439 lcr |= stb; 440 441 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n", 442 __func__, baud, div, lcr, jiffies); 443 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 444 iowrite8(dll, priv->membase + PCH_UART_DLL); 445 iowrite8(dlm, priv->membase + PCH_UART_DLM); 446 iowrite8(lcr, priv->membase + UART_LCR); 447 448 return 0; 449 } 450 451 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, 452 unsigned int flag) 453 { 454 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { 455 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", 456 __func__, flag); 457 return -EINVAL; 458 } 459 460 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); 461 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, 462 priv->membase + UART_FCR); 463 iowrite8(priv->fcr, priv->membase + UART_FCR); 464 465 return 0; 466 } 467 468 static int pch_uart_hal_set_fifo(struct eg20t_port *priv, 469 unsigned int dmamode, 470 unsigned int fifo_size, unsigned int trigger) 471 { 472 u8 fcr; 473 474 if (dmamode & ~PCH_UART_FCR_DMS) { 475 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", 476 __func__, dmamode); 477 return -EINVAL; 478 } 479 480 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { 481 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", 482 __func__, fifo_size); 483 return -EINVAL; 484 } 485 486 if (trigger & ~PCH_UART_FCR_RFTL) { 487 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", 488 __func__, trigger); 489 return -EINVAL; 490 } 491 492 switch (priv->fifo_size) { 493 case 256: 494 priv->trigger_level = 495 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 496 break; 497 case 64: 498 priv->trigger_level = 499 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 500 break; 501 case 16: 502 priv->trigger_level = 503 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 504 break; 505 default: 506 priv->trigger_level = 507 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 508 break; 509 } 510 fcr = 511 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; 512 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); 513 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, 514 priv->membase + UART_FCR); 515 iowrite8(fcr, priv->membase + UART_FCR); 516 priv->fcr = fcr; 517 518 return 0; 519 } 520 521 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) 522 { 523 unsigned int msr = ioread8(priv->membase + UART_MSR); 524 priv->dmsr = msr & PCH_UART_MSR_DELTA; 525 return (u8)msr; 526 } 527 528 static void pch_uart_hal_write(struct eg20t_port *priv, 529 const unsigned char *buf, int tx_size) 530 { 531 int i; 532 unsigned int thr; 533 534 for (i = 0; i < tx_size;) { 535 thr = buf[i++]; 536 iowrite8(thr, priv->membase + PCH_UART_THR); 537 } 538 } 539 540 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, 541 int rx_size) 542 { 543 int i; 544 u8 rbr, lsr; 545 546 lsr = ioread8(priv->membase + UART_LSR); 547 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); 548 i < rx_size && lsr & UART_LSR_DR; 549 lsr = ioread8(priv->membase + UART_LSR)) { 550 rbr = ioread8(priv->membase + PCH_UART_RBR); 551 buf[i++] = rbr; 552 } 553 return i; 554 } 555 556 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv) 557 { 558 unsigned int iir; 559 int ret; 560 561 iir = ioread8(priv->membase + UART_IIR); 562 ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP)); 563 return ret; 564 } 565 566 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) 567 { 568 return ioread8(priv->membase + UART_LSR); 569 } 570 571 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) 572 { 573 unsigned int lcr; 574 575 lcr = ioread8(priv->membase + UART_LCR); 576 if (on) 577 lcr |= PCH_UART_LCR_SB; 578 else 579 lcr &= ~PCH_UART_LCR_SB; 580 581 iowrite8(lcr, priv->membase + UART_LCR); 582 } 583 584 static int push_rx(struct eg20t_port *priv, const unsigned char *buf, 585 int size) 586 { 587 struct uart_port *port; 588 struct tty_struct *tty; 589 590 port = &priv->port; 591 tty = tty_port_tty_get(&port->state->port); 592 if (!tty) { 593 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 594 return -EBUSY; 595 } 596 597 tty_insert_flip_string(tty, buf, size); 598 tty_flip_buffer_push(tty); 599 tty_kref_put(tty); 600 601 return 0; 602 } 603 604 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) 605 { 606 int ret = 0; 607 struct uart_port *port = &priv->port; 608 609 if (port->x_char) { 610 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n", 611 __func__, port->x_char, jiffies); 612 buf[0] = port->x_char; 613 port->x_char = 0; 614 ret = 1; 615 } 616 617 return ret; 618 } 619 620 static int dma_push_rx(struct eg20t_port *priv, int size) 621 { 622 struct tty_struct *tty; 623 int room; 624 struct uart_port *port = &priv->port; 625 626 port = &priv->port; 627 tty = tty_port_tty_get(&port->state->port); 628 if (!tty) { 629 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 630 return 0; 631 } 632 633 room = tty_buffer_request_room(tty, size); 634 635 if (room < size) 636 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 637 size - room); 638 if (!room) 639 return room; 640 641 tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size); 642 643 port->icount.rx += room; 644 tty_kref_put(tty); 645 646 return room; 647 } 648 649 static void pch_free_dma(struct uart_port *port) 650 { 651 struct eg20t_port *priv; 652 priv = container_of(port, struct eg20t_port, port); 653 654 if (priv->chan_tx) { 655 dma_release_channel(priv->chan_tx); 656 priv->chan_tx = NULL; 657 } 658 if (priv->chan_rx) { 659 dma_release_channel(priv->chan_rx); 660 priv->chan_rx = NULL; 661 } 662 if (sg_dma_address(&priv->sg_rx)) 663 dma_free_coherent(port->dev, port->fifosize, 664 sg_virt(&priv->sg_rx), 665 sg_dma_address(&priv->sg_rx)); 666 667 return; 668 } 669 670 static bool filter(struct dma_chan *chan, void *slave) 671 { 672 struct pch_dma_slave *param = slave; 673 674 if ((chan->chan_id == param->chan_id) && (param->dma_dev == 675 chan->device->dev)) { 676 chan->private = param; 677 return true; 678 } else { 679 return false; 680 } 681 } 682 683 static void pch_request_dma(struct uart_port *port) 684 { 685 dma_cap_mask_t mask; 686 struct dma_chan *chan; 687 struct pci_dev *dma_dev; 688 struct pch_dma_slave *param; 689 struct eg20t_port *priv = 690 container_of(port, struct eg20t_port, port); 691 dma_cap_zero(mask); 692 dma_cap_set(DMA_SLAVE, mask); 693 694 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number, 695 PCI_DEVFN(0xa, 0)); /* Get DMA's dev 696 information */ 697 /* Set Tx DMA */ 698 param = &priv->param_tx; 699 param->dma_dev = &dma_dev->dev; 700 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ 701 702 param->tx_reg = port->mapbase + UART_TX; 703 chan = dma_request_channel(mask, filter, param); 704 if (!chan) { 705 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", 706 __func__); 707 return; 708 } 709 priv->chan_tx = chan; 710 711 /* Set Rx DMA */ 712 param = &priv->param_rx; 713 param->dma_dev = &dma_dev->dev; 714 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ 715 716 param->rx_reg = port->mapbase + UART_RX; 717 chan = dma_request_channel(mask, filter, param); 718 if (!chan) { 719 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", 720 __func__); 721 dma_release_channel(priv->chan_tx); 722 priv->chan_tx = NULL; 723 return; 724 } 725 726 /* Get Consistent memory for DMA */ 727 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, 728 &priv->rx_buf_dma, GFP_KERNEL); 729 priv->chan_rx = chan; 730 } 731 732 static void pch_dma_rx_complete(void *arg) 733 { 734 struct eg20t_port *priv = arg; 735 struct uart_port *port = &priv->port; 736 struct tty_struct *tty = tty_port_tty_get(&port->state->port); 737 int count; 738 739 if (!tty) { 740 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 741 return; 742 } 743 744 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); 745 count = dma_push_rx(priv, priv->trigger_level); 746 if (count) 747 tty_flip_buffer_push(tty); 748 tty_kref_put(tty); 749 async_tx_ack(priv->desc_rx); 750 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT); 751 } 752 753 static void pch_dma_tx_complete(void *arg) 754 { 755 struct eg20t_port *priv = arg; 756 struct uart_port *port = &priv->port; 757 struct circ_buf *xmit = &port->state->xmit; 758 struct scatterlist *sg = priv->sg_tx_p; 759 int i; 760 761 for (i = 0; i < priv->nent; i++, sg++) { 762 xmit->tail += sg_dma_len(sg); 763 port->icount.tx += sg_dma_len(sg); 764 } 765 xmit->tail &= UART_XMIT_SIZE - 1; 766 async_tx_ack(priv->desc_tx); 767 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE); 768 priv->tx_dma_use = 0; 769 priv->nent = 0; 770 kfree(priv->sg_tx_p); 771 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 772 } 773 774 static int pop_tx(struct eg20t_port *priv, int size) 775 { 776 int count = 0; 777 struct uart_port *port = &priv->port; 778 struct circ_buf *xmit = &port->state->xmit; 779 780 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size) 781 goto pop_tx_end; 782 783 do { 784 int cnt_to_end = 785 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 786 int sz = min(size - count, cnt_to_end); 787 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz); 788 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1); 789 count += sz; 790 } while (!uart_circ_empty(xmit) && count < size); 791 792 pop_tx_end: 793 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n", 794 count, size - count, jiffies); 795 796 return count; 797 } 798 799 static int handle_rx_to(struct eg20t_port *priv) 800 { 801 struct pch_uart_buffer *buf; 802 int rx_size; 803 int ret; 804 if (!priv->start_rx) { 805 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT); 806 return 0; 807 } 808 buf = &priv->rxbuf; 809 do { 810 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); 811 ret = push_rx(priv, buf->buf, rx_size); 812 if (ret) 813 return 0; 814 } while (rx_size == buf->size); 815 816 return PCH_UART_HANDLED_RX_INT; 817 } 818 819 static int handle_rx(struct eg20t_port *priv) 820 { 821 return handle_rx_to(priv); 822 } 823 824 static int dma_handle_rx(struct eg20t_port *priv) 825 { 826 struct uart_port *port = &priv->port; 827 struct dma_async_tx_descriptor *desc; 828 struct scatterlist *sg; 829 830 priv = container_of(port, struct eg20t_port, port); 831 sg = &priv->sg_rx; 832 833 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ 834 835 sg_dma_len(sg) = priv->trigger_level; 836 837 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), 838 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt & 839 ~PAGE_MASK); 840 841 sg_dma_address(sg) = priv->rx_buf_dma; 842 843 desc = dmaengine_prep_slave_sg(priv->chan_rx, 844 sg, 1, DMA_DEV_TO_MEM, 845 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 846 847 if (!desc) 848 return 0; 849 850 priv->desc_rx = desc; 851 desc->callback = pch_dma_rx_complete; 852 desc->callback_param = priv; 853 desc->tx_submit(desc); 854 dma_async_issue_pending(priv->chan_rx); 855 856 return PCH_UART_HANDLED_RX_INT; 857 } 858 859 static unsigned int handle_tx(struct eg20t_port *priv) 860 { 861 struct uart_port *port = &priv->port; 862 struct circ_buf *xmit = &port->state->xmit; 863 int fifo_size; 864 int tx_size; 865 int size; 866 int tx_empty; 867 868 if (!priv->start_tx) { 869 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 870 __func__, jiffies); 871 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 872 priv->tx_empty = 1; 873 return 0; 874 } 875 876 fifo_size = max(priv->fifo_size, 1); 877 tx_empty = 1; 878 if (pop_tx_x(priv, xmit->buf)) { 879 pch_uart_hal_write(priv, xmit->buf, 1); 880 port->icount.tx++; 881 tx_empty = 0; 882 fifo_size--; 883 } 884 size = min(xmit->head - xmit->tail, fifo_size); 885 if (size < 0) 886 size = fifo_size; 887 888 tx_size = pop_tx(priv, size); 889 if (tx_size > 0) { 890 port->icount.tx += tx_size; 891 tx_empty = 0; 892 } 893 894 priv->tx_empty = tx_empty; 895 896 if (tx_empty) { 897 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 898 uart_write_wakeup(port); 899 } 900 901 return PCH_UART_HANDLED_TX_INT; 902 } 903 904 static unsigned int dma_handle_tx(struct eg20t_port *priv) 905 { 906 struct uart_port *port = &priv->port; 907 struct circ_buf *xmit = &port->state->xmit; 908 struct scatterlist *sg; 909 int nent; 910 int fifo_size; 911 int tx_empty; 912 struct dma_async_tx_descriptor *desc; 913 int num; 914 int i; 915 int bytes; 916 int size; 917 int rem; 918 919 if (!priv->start_tx) { 920 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 921 __func__, jiffies); 922 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 923 priv->tx_empty = 1; 924 return 0; 925 } 926 927 if (priv->tx_dma_use) { 928 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", 929 __func__, jiffies); 930 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 931 priv->tx_empty = 1; 932 return 0; 933 } 934 935 fifo_size = max(priv->fifo_size, 1); 936 tx_empty = 1; 937 if (pop_tx_x(priv, xmit->buf)) { 938 pch_uart_hal_write(priv, xmit->buf, 1); 939 port->icount.tx++; 940 tx_empty = 0; 941 fifo_size--; 942 } 943 944 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail, 945 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head, 946 xmit->tail, UART_XMIT_SIZE)); 947 if (!bytes) { 948 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); 949 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 950 uart_write_wakeup(port); 951 return 0; 952 } 953 954 if (bytes > fifo_size) { 955 num = bytes / fifo_size + 1; 956 size = fifo_size; 957 rem = bytes % fifo_size; 958 } else { 959 num = 1; 960 size = bytes; 961 rem = bytes; 962 } 963 964 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", 965 __func__, num, size, rem); 966 967 priv->tx_dma_use = 1; 968 969 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); 970 971 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ 972 sg = priv->sg_tx_p; 973 974 for (i = 0; i < num; i++, sg++) { 975 if (i == (num - 1)) 976 sg_set_page(sg, virt_to_page(xmit->buf), 977 rem, fifo_size * i); 978 else 979 sg_set_page(sg, virt_to_page(xmit->buf), 980 size, fifo_size * i); 981 } 982 983 sg = priv->sg_tx_p; 984 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); 985 if (!nent) { 986 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); 987 return 0; 988 } 989 priv->nent = nent; 990 991 for (i = 0; i < nent; i++, sg++) { 992 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + 993 fifo_size * i; 994 sg_dma_address(sg) = (sg_dma_address(sg) & 995 ~(UART_XMIT_SIZE - 1)) + sg->offset; 996 if (i == (nent - 1)) 997 sg_dma_len(sg) = rem; 998 else 999 sg_dma_len(sg) = size; 1000 } 1001 1002 desc = dmaengine_prep_slave_sg(priv->chan_tx, 1003 priv->sg_tx_p, nent, DMA_MEM_TO_DEV, 1004 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1005 if (!desc) { 1006 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n", 1007 __func__); 1008 return 0; 1009 } 1010 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); 1011 priv->desc_tx = desc; 1012 desc->callback = pch_dma_tx_complete; 1013 desc->callback_param = priv; 1014 1015 desc->tx_submit(desc); 1016 1017 dma_async_issue_pending(priv->chan_tx); 1018 1019 return PCH_UART_HANDLED_TX_INT; 1020 } 1021 1022 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) 1023 { 1024 u8 fcr = ioread8(priv->membase + UART_FCR); 1025 1026 /* Reset FIFO */ 1027 fcr |= UART_FCR_CLEAR_RCVR; 1028 iowrite8(fcr, priv->membase + UART_FCR); 1029 1030 if (lsr & PCH_UART_LSR_ERR) 1031 dev_err(&priv->pdev->dev, "Error data in FIFO\n"); 1032 1033 if (lsr & UART_LSR_FE) 1034 dev_err(&priv->pdev->dev, "Framing Error\n"); 1035 1036 if (lsr & UART_LSR_PE) 1037 dev_err(&priv->pdev->dev, "Parity Error\n"); 1038 1039 if (lsr & UART_LSR_OE) 1040 dev_err(&priv->pdev->dev, "Overrun Error\n"); 1041 } 1042 1043 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) 1044 { 1045 struct eg20t_port *priv = dev_id; 1046 unsigned int handled; 1047 u8 lsr; 1048 int ret = 0; 1049 unsigned int iid; 1050 unsigned long flags; 1051 1052 spin_lock_irqsave(&priv->port.lock, flags); 1053 handled = 0; 1054 while ((iid = pch_uart_hal_get_iid(priv)) > 1) { 1055 switch (iid) { 1056 case PCH_UART_IID_RLS: /* Receiver Line Status */ 1057 lsr = pch_uart_hal_get_line_status(priv); 1058 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | 1059 UART_LSR_PE | UART_LSR_OE)) { 1060 pch_uart_err_ir(priv, lsr); 1061 ret = PCH_UART_HANDLED_RX_ERR_INT; 1062 } 1063 break; 1064 case PCH_UART_IID_RDR: /* Received Data Ready */ 1065 if (priv->use_dma) { 1066 pch_uart_hal_disable_interrupt(priv, 1067 PCH_UART_HAL_RX_INT); 1068 ret = dma_handle_rx(priv); 1069 if (!ret) 1070 pch_uart_hal_enable_interrupt(priv, 1071 PCH_UART_HAL_RX_INT); 1072 } else { 1073 ret = handle_rx(priv); 1074 } 1075 break; 1076 case PCH_UART_IID_RDR_TO: /* Received Data Ready 1077 (FIFO Timeout) */ 1078 ret = handle_rx_to(priv); 1079 break; 1080 case PCH_UART_IID_THRE: /* Transmitter Holding Register 1081 Empty */ 1082 if (priv->use_dma) 1083 ret = dma_handle_tx(priv); 1084 else 1085 ret = handle_tx(priv); 1086 break; 1087 case PCH_UART_IID_MS: /* Modem Status */ 1088 ret = PCH_UART_HANDLED_MS_INT; 1089 break; 1090 default: /* Never junp to this label */ 1091 dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__, 1092 iid, jiffies); 1093 ret = -1; 1094 break; 1095 } 1096 handled |= (unsigned int)ret; 1097 } 1098 if (handled == 0 && iid <= 1) { 1099 if (priv->int_dis_flag) 1100 priv->int_dis_flag = 0; 1101 } 1102 1103 spin_unlock_irqrestore(&priv->port.lock, flags); 1104 return IRQ_RETVAL(handled); 1105 } 1106 1107 /* This function tests whether the transmitter fifo and shifter for the port 1108 described by 'port' is empty. */ 1109 static unsigned int pch_uart_tx_empty(struct uart_port *port) 1110 { 1111 struct eg20t_port *priv; 1112 1113 priv = container_of(port, struct eg20t_port, port); 1114 if (priv->tx_empty) 1115 return TIOCSER_TEMT; 1116 else 1117 return 0; 1118 } 1119 1120 /* Returns the current state of modem control inputs. */ 1121 static unsigned int pch_uart_get_mctrl(struct uart_port *port) 1122 { 1123 struct eg20t_port *priv; 1124 u8 modem; 1125 unsigned int ret = 0; 1126 1127 priv = container_of(port, struct eg20t_port, port); 1128 modem = pch_uart_hal_get_modem(priv); 1129 1130 if (modem & UART_MSR_DCD) 1131 ret |= TIOCM_CAR; 1132 1133 if (modem & UART_MSR_RI) 1134 ret |= TIOCM_RNG; 1135 1136 if (modem & UART_MSR_DSR) 1137 ret |= TIOCM_DSR; 1138 1139 if (modem & UART_MSR_CTS) 1140 ret |= TIOCM_CTS; 1141 1142 return ret; 1143 } 1144 1145 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1146 { 1147 u32 mcr = 0; 1148 struct eg20t_port *priv = container_of(port, struct eg20t_port, port); 1149 1150 if (mctrl & TIOCM_DTR) 1151 mcr |= UART_MCR_DTR; 1152 if (mctrl & TIOCM_RTS) 1153 mcr |= UART_MCR_RTS; 1154 if (mctrl & TIOCM_LOOP) 1155 mcr |= UART_MCR_LOOP; 1156 1157 if (priv->mcr & UART_MCR_AFE) 1158 mcr |= UART_MCR_AFE; 1159 1160 if (mctrl) 1161 iowrite8(mcr, priv->membase + UART_MCR); 1162 } 1163 1164 static void pch_uart_stop_tx(struct uart_port *port) 1165 { 1166 struct eg20t_port *priv; 1167 priv = container_of(port, struct eg20t_port, port); 1168 priv->start_tx = 0; 1169 priv->tx_dma_use = 0; 1170 } 1171 1172 static void pch_uart_start_tx(struct uart_port *port) 1173 { 1174 struct eg20t_port *priv; 1175 1176 priv = container_of(port, struct eg20t_port, port); 1177 1178 if (priv->use_dma) { 1179 if (priv->tx_dma_use) { 1180 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", 1181 __func__); 1182 return; 1183 } 1184 } 1185 1186 priv->start_tx = 1; 1187 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 1188 } 1189 1190 static void pch_uart_stop_rx(struct uart_port *port) 1191 { 1192 struct eg20t_port *priv; 1193 priv = container_of(port, struct eg20t_port, port); 1194 priv->start_rx = 0; 1195 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT); 1196 priv->int_dis_flag = 1; 1197 } 1198 1199 /* Enable the modem status interrupts. */ 1200 static void pch_uart_enable_ms(struct uart_port *port) 1201 { 1202 struct eg20t_port *priv; 1203 priv = container_of(port, struct eg20t_port, port); 1204 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); 1205 } 1206 1207 /* Control the transmission of a break signal. */ 1208 static void pch_uart_break_ctl(struct uart_port *port, int ctl) 1209 { 1210 struct eg20t_port *priv; 1211 unsigned long flags; 1212 1213 priv = container_of(port, struct eg20t_port, port); 1214 spin_lock_irqsave(&port->lock, flags); 1215 pch_uart_hal_set_break(priv, ctl); 1216 spin_unlock_irqrestore(&port->lock, flags); 1217 } 1218 1219 /* Grab any interrupt resources and initialise any low level driver state. */ 1220 static int pch_uart_startup(struct uart_port *port) 1221 { 1222 struct eg20t_port *priv; 1223 int ret; 1224 int fifo_size; 1225 int trigger_level; 1226 1227 priv = container_of(port, struct eg20t_port, port); 1228 priv->tx_empty = 1; 1229 1230 if (port->uartclk) 1231 priv->uartclk = port->uartclk; 1232 else 1233 port->uartclk = priv->uartclk; 1234 1235 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1236 ret = pch_uart_hal_set_line(priv, default_baud, 1237 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, 1238 PCH_UART_HAL_STB1); 1239 if (ret) 1240 return ret; 1241 1242 switch (priv->fifo_size) { 1243 case 256: 1244 fifo_size = PCH_UART_HAL_FIFO256; 1245 break; 1246 case 64: 1247 fifo_size = PCH_UART_HAL_FIFO64; 1248 break; 1249 case 16: 1250 fifo_size = PCH_UART_HAL_FIFO16; 1251 case 1: 1252 default: 1253 fifo_size = PCH_UART_HAL_FIFO_DIS; 1254 break; 1255 } 1256 1257 switch (priv->trigger) { 1258 case PCH_UART_HAL_TRIGGER1: 1259 trigger_level = 1; 1260 break; 1261 case PCH_UART_HAL_TRIGGER_L: 1262 trigger_level = priv->fifo_size / 4; 1263 break; 1264 case PCH_UART_HAL_TRIGGER_M: 1265 trigger_level = priv->fifo_size / 2; 1266 break; 1267 case PCH_UART_HAL_TRIGGER_H: 1268 default: 1269 trigger_level = priv->fifo_size - (priv->fifo_size / 8); 1270 break; 1271 } 1272 1273 priv->trigger_level = trigger_level; 1274 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1275 fifo_size, priv->trigger); 1276 if (ret < 0) 1277 return ret; 1278 1279 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, 1280 KBUILD_MODNAME, priv); 1281 if (ret < 0) 1282 return ret; 1283 1284 if (priv->use_dma) 1285 pch_request_dma(port); 1286 1287 priv->start_rx = 1; 1288 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT); 1289 uart_update_timeout(port, CS8, default_baud); 1290 1291 return 0; 1292 } 1293 1294 static void pch_uart_shutdown(struct uart_port *port) 1295 { 1296 struct eg20t_port *priv; 1297 int ret; 1298 1299 priv = container_of(port, struct eg20t_port, port); 1300 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1301 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); 1302 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1303 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); 1304 if (ret) 1305 dev_err(priv->port.dev, 1306 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); 1307 1308 pch_free_dma(port); 1309 1310 free_irq(priv->port.irq, priv); 1311 } 1312 1313 /* Change the port parameters, including word length, parity, stop 1314 *bits. Update read_status_mask and ignore_status_mask to indicate 1315 *the types of events we are interested in receiving. */ 1316 static void pch_uart_set_termios(struct uart_port *port, 1317 struct ktermios *termios, struct ktermios *old) 1318 { 1319 int baud; 1320 int rtn; 1321 unsigned int parity, bits, stb; 1322 struct eg20t_port *priv; 1323 unsigned long flags; 1324 1325 priv = container_of(port, struct eg20t_port, port); 1326 switch (termios->c_cflag & CSIZE) { 1327 case CS5: 1328 bits = PCH_UART_HAL_5BIT; 1329 break; 1330 case CS6: 1331 bits = PCH_UART_HAL_6BIT; 1332 break; 1333 case CS7: 1334 bits = PCH_UART_HAL_7BIT; 1335 break; 1336 default: /* CS8 */ 1337 bits = PCH_UART_HAL_8BIT; 1338 break; 1339 } 1340 if (termios->c_cflag & CSTOPB) 1341 stb = PCH_UART_HAL_STB2; 1342 else 1343 stb = PCH_UART_HAL_STB1; 1344 1345 if (termios->c_cflag & PARENB) { 1346 if (!(termios->c_cflag & PARODD)) 1347 parity = PCH_UART_HAL_PARITY_ODD; 1348 else 1349 parity = PCH_UART_HAL_PARITY_EVEN; 1350 1351 } else 1352 parity = PCH_UART_HAL_PARITY_NONE; 1353 1354 /* Only UART0 has auto hardware flow function */ 1355 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) 1356 priv->mcr |= UART_MCR_AFE; 1357 else 1358 priv->mcr &= ~UART_MCR_AFE; 1359 1360 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 1361 1362 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1363 1364 spin_lock_irqsave(&port->lock, flags); 1365 1366 uart_update_timeout(port, termios->c_cflag, baud); 1367 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); 1368 if (rtn) 1369 goto out; 1370 1371 pch_uart_set_mctrl(&priv->port, priv->port.mctrl); 1372 /* Don't rewrite B0 */ 1373 if (tty_termios_baud_rate(termios)) 1374 tty_termios_encode_baud_rate(termios, baud, baud); 1375 1376 out: 1377 spin_unlock_irqrestore(&port->lock, flags); 1378 } 1379 1380 static const char *pch_uart_type(struct uart_port *port) 1381 { 1382 return KBUILD_MODNAME; 1383 } 1384 1385 static void pch_uart_release_port(struct uart_port *port) 1386 { 1387 struct eg20t_port *priv; 1388 1389 priv = container_of(port, struct eg20t_port, port); 1390 pci_iounmap(priv->pdev, priv->membase); 1391 pci_release_regions(priv->pdev); 1392 } 1393 1394 static int pch_uart_request_port(struct uart_port *port) 1395 { 1396 struct eg20t_port *priv; 1397 int ret; 1398 void __iomem *membase; 1399 1400 priv = container_of(port, struct eg20t_port, port); 1401 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); 1402 if (ret < 0) 1403 return -EBUSY; 1404 1405 membase = pci_iomap(priv->pdev, 1, 0); 1406 if (!membase) { 1407 pci_release_regions(priv->pdev); 1408 return -EBUSY; 1409 } 1410 priv->membase = port->membase = membase; 1411 1412 return 0; 1413 } 1414 1415 static void pch_uart_config_port(struct uart_port *port, int type) 1416 { 1417 struct eg20t_port *priv; 1418 1419 priv = container_of(port, struct eg20t_port, port); 1420 if (type & UART_CONFIG_TYPE) { 1421 port->type = priv->port_type; 1422 pch_uart_request_port(port); 1423 } 1424 } 1425 1426 static int pch_uart_verify_port(struct uart_port *port, 1427 struct serial_struct *serinfo) 1428 { 1429 struct eg20t_port *priv; 1430 1431 priv = container_of(port, struct eg20t_port, port); 1432 if (serinfo->flags & UPF_LOW_LATENCY) { 1433 dev_info(priv->port.dev, 1434 "PCH UART : Use PIO Mode (without DMA)\n"); 1435 priv->use_dma = 0; 1436 serinfo->flags &= ~UPF_LOW_LATENCY; 1437 } else { 1438 #ifndef CONFIG_PCH_DMA 1439 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", 1440 __func__); 1441 return -EOPNOTSUPP; 1442 #endif 1443 priv->use_dma = 1; 1444 priv->use_dma_flag = 1; 1445 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n"); 1446 } 1447 1448 return 0; 1449 } 1450 1451 static struct uart_ops pch_uart_ops = { 1452 .tx_empty = pch_uart_tx_empty, 1453 .set_mctrl = pch_uart_set_mctrl, 1454 .get_mctrl = pch_uart_get_mctrl, 1455 .stop_tx = pch_uart_stop_tx, 1456 .start_tx = pch_uart_start_tx, 1457 .stop_rx = pch_uart_stop_rx, 1458 .enable_ms = pch_uart_enable_ms, 1459 .break_ctl = pch_uart_break_ctl, 1460 .startup = pch_uart_startup, 1461 .shutdown = pch_uart_shutdown, 1462 .set_termios = pch_uart_set_termios, 1463 /* .pm = pch_uart_pm, Not supported yet */ 1464 /* .set_wake = pch_uart_set_wake, Not supported yet */ 1465 .type = pch_uart_type, 1466 .release_port = pch_uart_release_port, 1467 .request_port = pch_uart_request_port, 1468 .config_port = pch_uart_config_port, 1469 .verify_port = pch_uart_verify_port 1470 }; 1471 1472 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1473 1474 /* 1475 * Wait for transmitter & holding register to empty 1476 */ 1477 static void wait_for_xmitr(struct eg20t_port *up, int bits) 1478 { 1479 unsigned int status, tmout = 10000; 1480 1481 /* Wait up to 10ms for the character(s) to be sent. */ 1482 for (;;) { 1483 status = ioread8(up->membase + UART_LSR); 1484 1485 if ((status & bits) == bits) 1486 break; 1487 if (--tmout == 0) 1488 break; 1489 udelay(1); 1490 } 1491 1492 /* Wait up to 1s for flow control if necessary */ 1493 if (up->port.flags & UPF_CONS_FLOW) { 1494 unsigned int tmout; 1495 for (tmout = 1000000; tmout; tmout--) { 1496 unsigned int msr = ioread8(up->membase + UART_MSR); 1497 if (msr & UART_MSR_CTS) 1498 break; 1499 udelay(1); 1500 touch_nmi_watchdog(); 1501 } 1502 } 1503 } 1504 1505 static void pch_console_putchar(struct uart_port *port, int ch) 1506 { 1507 struct eg20t_port *priv = 1508 container_of(port, struct eg20t_port, port); 1509 1510 wait_for_xmitr(priv, UART_LSR_THRE); 1511 iowrite8(ch, priv->membase + PCH_UART_THR); 1512 } 1513 1514 /* 1515 * Print a string to the serial port trying not to disturb 1516 * any possible real use of the port... 1517 * 1518 * The console_lock must be held when we get here. 1519 */ 1520 static void 1521 pch_console_write(struct console *co, const char *s, unsigned int count) 1522 { 1523 struct eg20t_port *priv; 1524 unsigned long flags; 1525 u8 ier; 1526 int locked = 1; 1527 1528 priv = pch_uart_ports[co->index]; 1529 1530 touch_nmi_watchdog(); 1531 1532 local_irq_save(flags); 1533 if (priv->port.sysrq) { 1534 /* serial8250_handle_port() already took the lock */ 1535 locked = 0; 1536 } else if (oops_in_progress) { 1537 locked = spin_trylock(&priv->port.lock); 1538 } else 1539 spin_lock(&priv->port.lock); 1540 1541 /* 1542 * First save the IER then disable the interrupts 1543 */ 1544 ier = ioread8(priv->membase + UART_IER); 1545 1546 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1547 1548 uart_console_write(&priv->port, s, count, pch_console_putchar); 1549 1550 /* 1551 * Finally, wait for transmitter to become empty 1552 * and restore the IER 1553 */ 1554 wait_for_xmitr(priv, BOTH_EMPTY); 1555 iowrite8(ier, priv->membase + UART_IER); 1556 1557 if (locked) 1558 spin_unlock(&priv->port.lock); 1559 local_irq_restore(flags); 1560 } 1561 1562 static int __init pch_console_setup(struct console *co, char *options) 1563 { 1564 struct uart_port *port; 1565 int baud = default_baud; 1566 int bits = 8; 1567 int parity = 'n'; 1568 int flow = 'n'; 1569 1570 /* 1571 * Check whether an invalid uart number has been specified, and 1572 * if so, search for the first available port that does have 1573 * console support. 1574 */ 1575 if (co->index >= PCH_UART_NR) 1576 co->index = 0; 1577 port = &pch_uart_ports[co->index]->port; 1578 1579 if (!port || (!port->iobase && !port->membase)) 1580 return -ENODEV; 1581 1582 port->uartclk = pch_uart_get_uartclk(); 1583 1584 if (options) 1585 uart_parse_options(options, &baud, &parity, &bits, &flow); 1586 1587 return uart_set_options(port, co, baud, parity, bits, flow); 1588 } 1589 1590 static struct uart_driver pch_uart_driver; 1591 1592 static struct console pch_console = { 1593 .name = PCH_UART_DRIVER_DEVICE, 1594 .write = pch_console_write, 1595 .device = uart_console_device, 1596 .setup = pch_console_setup, 1597 .flags = CON_PRINTBUFFER | CON_ANYTIME, 1598 .index = -1, 1599 .data = &pch_uart_driver, 1600 }; 1601 1602 #define PCH_CONSOLE (&pch_console) 1603 #else 1604 #define PCH_CONSOLE NULL 1605 #endif 1606 1607 static struct uart_driver pch_uart_driver = { 1608 .owner = THIS_MODULE, 1609 .driver_name = KBUILD_MODNAME, 1610 .dev_name = PCH_UART_DRIVER_DEVICE, 1611 .major = 0, 1612 .minor = 0, 1613 .nr = PCH_UART_NR, 1614 .cons = PCH_CONSOLE, 1615 }; 1616 1617 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, 1618 const struct pci_device_id *id) 1619 { 1620 struct eg20t_port *priv; 1621 int ret; 1622 unsigned int iobase; 1623 unsigned int mapbase; 1624 unsigned char *rxbuf; 1625 int fifosize; 1626 int port_type; 1627 struct pch_uart_driver_data *board; 1628 char name[32]; /* for debugfs file name */ 1629 1630 board = &drv_dat[id->driver_data]; 1631 port_type = board->port_type; 1632 1633 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); 1634 if (priv == NULL) 1635 goto init_port_alloc_err; 1636 1637 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); 1638 if (!rxbuf) 1639 goto init_port_free_txbuf; 1640 1641 switch (port_type) { 1642 case PORT_UNKNOWN: 1643 fifosize = 256; /* EG20T/ML7213: UART0 */ 1644 break; 1645 case PORT_8250: 1646 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ 1647 break; 1648 default: 1649 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); 1650 goto init_port_hal_free; 1651 } 1652 1653 pci_enable_msi(pdev); 1654 1655 iobase = pci_resource_start(pdev, 0); 1656 mapbase = pci_resource_start(pdev, 1); 1657 priv->mapbase = mapbase; 1658 priv->iobase = iobase; 1659 priv->pdev = pdev; 1660 priv->tx_empty = 1; 1661 priv->rxbuf.buf = rxbuf; 1662 priv->rxbuf.size = PAGE_SIZE; 1663 1664 priv->fifo_size = fifosize; 1665 priv->uartclk = pch_uart_get_uartclk(); 1666 priv->port_type = PORT_MAX_8250 + port_type + 1; 1667 priv->port.dev = &pdev->dev; 1668 priv->port.iobase = iobase; 1669 priv->port.membase = NULL; 1670 priv->port.mapbase = mapbase; 1671 priv->port.irq = pdev->irq; 1672 priv->port.iotype = UPIO_PORT; 1673 priv->port.ops = &pch_uart_ops; 1674 priv->port.flags = UPF_BOOT_AUTOCONF; 1675 priv->port.fifosize = fifosize; 1676 priv->port.line = board->line_no; 1677 priv->trigger = PCH_UART_HAL_TRIGGER_M; 1678 1679 spin_lock_init(&priv->port.lock); 1680 1681 pci_set_drvdata(pdev, priv); 1682 priv->trigger_level = 1; 1683 priv->fcr = 0; 1684 1685 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1686 pch_uart_ports[board->line_no] = priv; 1687 #endif 1688 ret = uart_add_one_port(&pch_uart_driver, &priv->port); 1689 if (ret < 0) 1690 goto init_port_hal_free; 1691 1692 #ifdef CONFIG_DEBUG_FS 1693 snprintf(name, sizeof(name), "uart%d_regs", board->line_no); 1694 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO, 1695 NULL, priv, &port_regs_ops); 1696 #endif 1697 1698 return priv; 1699 1700 init_port_hal_free: 1701 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1702 pch_uart_ports[board->line_no] = NULL; 1703 #endif 1704 free_page((unsigned long)rxbuf); 1705 init_port_free_txbuf: 1706 kfree(priv); 1707 init_port_alloc_err: 1708 1709 return NULL; 1710 } 1711 1712 static void pch_uart_exit_port(struct eg20t_port *priv) 1713 { 1714 1715 #ifdef CONFIG_DEBUG_FS 1716 if (priv->debugfs) 1717 debugfs_remove(priv->debugfs); 1718 #endif 1719 uart_remove_one_port(&pch_uart_driver, &priv->port); 1720 pci_set_drvdata(priv->pdev, NULL); 1721 free_page((unsigned long)priv->rxbuf.buf); 1722 } 1723 1724 static void pch_uart_pci_remove(struct pci_dev *pdev) 1725 { 1726 struct eg20t_port *priv = pci_get_drvdata(pdev); 1727 1728 pci_disable_msi(pdev); 1729 1730 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1731 pch_uart_ports[priv->port.line] = NULL; 1732 #endif 1733 pch_uart_exit_port(priv); 1734 pci_disable_device(pdev); 1735 kfree(priv); 1736 return; 1737 } 1738 #ifdef CONFIG_PM 1739 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1740 { 1741 struct eg20t_port *priv = pci_get_drvdata(pdev); 1742 1743 uart_suspend_port(&pch_uart_driver, &priv->port); 1744 1745 pci_save_state(pdev); 1746 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1747 return 0; 1748 } 1749 1750 static int pch_uart_pci_resume(struct pci_dev *pdev) 1751 { 1752 struct eg20t_port *priv = pci_get_drvdata(pdev); 1753 int ret; 1754 1755 pci_set_power_state(pdev, PCI_D0); 1756 pci_restore_state(pdev); 1757 1758 ret = pci_enable_device(pdev); 1759 if (ret) { 1760 dev_err(&pdev->dev, 1761 "%s-pci_enable_device failed(ret=%d) ", __func__, ret); 1762 return ret; 1763 } 1764 1765 uart_resume_port(&pch_uart_driver, &priv->port); 1766 1767 return 0; 1768 } 1769 #else 1770 #define pch_uart_pci_suspend NULL 1771 #define pch_uart_pci_resume NULL 1772 #endif 1773 1774 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = { 1775 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), 1776 .driver_data = pch_et20t_uart0}, 1777 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), 1778 .driver_data = pch_et20t_uart1}, 1779 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), 1780 .driver_data = pch_et20t_uart2}, 1781 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), 1782 .driver_data = pch_et20t_uart3}, 1783 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), 1784 .driver_data = pch_ml7213_uart0}, 1785 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), 1786 .driver_data = pch_ml7213_uart1}, 1787 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), 1788 .driver_data = pch_ml7213_uart2}, 1789 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C), 1790 .driver_data = pch_ml7223_uart0}, 1791 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D), 1792 .driver_data = pch_ml7223_uart1}, 1793 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811), 1794 .driver_data = pch_ml7831_uart0}, 1795 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812), 1796 .driver_data = pch_ml7831_uart1}, 1797 {0,}, 1798 }; 1799 1800 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev, 1801 const struct pci_device_id *id) 1802 { 1803 int ret; 1804 struct eg20t_port *priv; 1805 1806 ret = pci_enable_device(pdev); 1807 if (ret < 0) 1808 goto probe_error; 1809 1810 priv = pch_uart_init_port(pdev, id); 1811 if (!priv) { 1812 ret = -EBUSY; 1813 goto probe_disable_device; 1814 } 1815 pci_set_drvdata(pdev, priv); 1816 1817 return ret; 1818 1819 probe_disable_device: 1820 pci_disable_msi(pdev); 1821 pci_disable_device(pdev); 1822 probe_error: 1823 return ret; 1824 } 1825 1826 static struct pci_driver pch_uart_pci_driver = { 1827 .name = "pch_uart", 1828 .id_table = pch_uart_pci_id, 1829 .probe = pch_uart_pci_probe, 1830 .remove = __devexit_p(pch_uart_pci_remove), 1831 .suspend = pch_uart_pci_suspend, 1832 .resume = pch_uart_pci_resume, 1833 }; 1834 1835 static int __init pch_uart_module_init(void) 1836 { 1837 int ret; 1838 1839 /* register as UART driver */ 1840 ret = uart_register_driver(&pch_uart_driver); 1841 if (ret < 0) 1842 return ret; 1843 1844 /* register as PCI driver */ 1845 ret = pci_register_driver(&pch_uart_pci_driver); 1846 if (ret < 0) 1847 uart_unregister_driver(&pch_uart_driver); 1848 1849 return ret; 1850 } 1851 module_init(pch_uart_module_init); 1852 1853 static void __exit pch_uart_module_exit(void) 1854 { 1855 pci_unregister_driver(&pch_uart_pci_driver); 1856 uart_unregister_driver(&pch_uart_driver); 1857 } 1858 module_exit(pch_uart_module_exit); 1859 1860 MODULE_LICENSE("GPL v2"); 1861 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); 1862 module_param(default_baud, uint, S_IRUGO); 1863 MODULE_PARM_DESC(default_baud, 1864 "Default BAUD for initial driver state and console (default 9600)"); 1865 module_param(user_uartclk, uint, S_IRUGO); 1866 MODULE_PARM_DESC(user_uartclk, 1867 "Override UART default or board specific UART clock"); 1868