1 /* 2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 3 * 4 *This program is free software; you can redistribute it and/or modify 5 *it under the terms of the GNU General Public License as published by 6 *the Free Software Foundation; version 2 of the License. 7 * 8 *This program is distributed in the hope that it will be useful, 9 *but WITHOUT ANY WARRANTY; without even the implied warranty of 10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 *GNU General Public License for more details. 12 * 13 *You should have received a copy of the GNU General Public License 14 *along with this program; if not, write to the Free Software 15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 16 */ 17 #include <linux/kernel.h> 18 #include <linux/serial_reg.h> 19 #include <linux/slab.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/serial_core.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/dmi.h> 28 #include <linux/console.h> 29 #include <linux/nmi.h> 30 #include <linux/delay.h> 31 32 #include <linux/debugfs.h> 33 #include <linux/dmaengine.h> 34 #include <linux/pch_dma.h> 35 36 enum { 37 PCH_UART_HANDLED_RX_INT_SHIFT, 38 PCH_UART_HANDLED_TX_INT_SHIFT, 39 PCH_UART_HANDLED_RX_ERR_INT_SHIFT, 40 PCH_UART_HANDLED_RX_TRG_INT_SHIFT, 41 PCH_UART_HANDLED_MS_INT_SHIFT, 42 }; 43 44 enum { 45 PCH_UART_8LINE, 46 PCH_UART_2LINE, 47 }; 48 49 #define PCH_UART_DRIVER_DEVICE "ttyPCH" 50 51 /* Set the max number of UART port 52 * Intel EG20T PCH: 4 port 53 * LAPIS Semiconductor ML7213 IOH: 3 port 54 * LAPIS Semiconductor ML7223 IOH: 2 port 55 */ 56 #define PCH_UART_NR 4 57 58 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) 59 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) 60 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ 61 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) 62 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ 63 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) 64 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) 65 66 #define PCH_UART_RBR 0x00 67 #define PCH_UART_THR 0x00 68 69 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ 70 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) 71 #define PCH_UART_IER_ERBFI 0x00000001 72 #define PCH_UART_IER_ETBEI 0x00000002 73 #define PCH_UART_IER_ELSI 0x00000004 74 #define PCH_UART_IER_EDSSI 0x00000008 75 76 #define PCH_UART_IIR_IP 0x00000001 77 #define PCH_UART_IIR_IID 0x00000006 78 #define PCH_UART_IIR_MSI 0x00000000 79 #define PCH_UART_IIR_TRI 0x00000002 80 #define PCH_UART_IIR_RRI 0x00000004 81 #define PCH_UART_IIR_REI 0x00000006 82 #define PCH_UART_IIR_TOI 0x00000008 83 #define PCH_UART_IIR_FIFO256 0x00000020 84 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 85 #define PCH_UART_IIR_FE 0x000000C0 86 87 #define PCH_UART_FCR_FIFOE 0x00000001 88 #define PCH_UART_FCR_RFR 0x00000002 89 #define PCH_UART_FCR_TFR 0x00000004 90 #define PCH_UART_FCR_DMS 0x00000008 91 #define PCH_UART_FCR_FIFO256 0x00000020 92 #define PCH_UART_FCR_RFTL 0x000000C0 93 94 #define PCH_UART_FCR_RFTL1 0x00000000 95 #define PCH_UART_FCR_RFTL64 0x00000040 96 #define PCH_UART_FCR_RFTL128 0x00000080 97 #define PCH_UART_FCR_RFTL224 0x000000C0 98 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 99 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 100 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 101 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 102 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 103 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 104 #define PCH_UART_FCR_RFTL_SHIFT 6 105 106 #define PCH_UART_LCR_WLS 0x00000003 107 #define PCH_UART_LCR_STB 0x00000004 108 #define PCH_UART_LCR_PEN 0x00000008 109 #define PCH_UART_LCR_EPS 0x00000010 110 #define PCH_UART_LCR_SP 0x00000020 111 #define PCH_UART_LCR_SB 0x00000040 112 #define PCH_UART_LCR_DLAB 0x00000080 113 #define PCH_UART_LCR_NP 0x00000000 114 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN 115 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) 116 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) 117 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ 118 PCH_UART_LCR_SP) 119 120 #define PCH_UART_LCR_5BIT 0x00000000 121 #define PCH_UART_LCR_6BIT 0x00000001 122 #define PCH_UART_LCR_7BIT 0x00000002 123 #define PCH_UART_LCR_8BIT 0x00000003 124 125 #define PCH_UART_MCR_DTR 0x00000001 126 #define PCH_UART_MCR_RTS 0x00000002 127 #define PCH_UART_MCR_OUT 0x0000000C 128 #define PCH_UART_MCR_LOOP 0x00000010 129 #define PCH_UART_MCR_AFE 0x00000020 130 131 #define PCH_UART_LSR_DR 0x00000001 132 #define PCH_UART_LSR_ERR (1<<7) 133 134 #define PCH_UART_MSR_DCTS 0x00000001 135 #define PCH_UART_MSR_DDSR 0x00000002 136 #define PCH_UART_MSR_TERI 0x00000004 137 #define PCH_UART_MSR_DDCD 0x00000008 138 #define PCH_UART_MSR_CTS 0x00000010 139 #define PCH_UART_MSR_DSR 0x00000020 140 #define PCH_UART_MSR_RI 0x00000040 141 #define PCH_UART_MSR_DCD 0x00000080 142 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ 143 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) 144 145 #define PCH_UART_DLL 0x00 146 #define PCH_UART_DLM 0x01 147 148 #define PCH_UART_BRCSR 0x0E 149 150 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) 151 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) 152 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) 153 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) 154 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) 155 156 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) 157 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) 158 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) 159 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) 160 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) 161 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) 162 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) 163 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) 164 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) 165 #define PCH_UART_HAL_STB1 0 166 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) 167 168 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) 169 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) 170 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ 171 PCH_UART_HAL_CLR_RX_FIFO) 172 173 #define PCH_UART_HAL_DMA_MODE0 0 174 #define PCH_UART_HAL_FIFO_DIS 0 175 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) 176 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ 177 PCH_UART_FCR_FIFO256) 178 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) 179 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) 180 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) 181 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) 182 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) 183 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) 184 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) 185 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) 186 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) 187 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) 188 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) 189 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) 190 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) 191 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) 192 193 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) 194 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) 195 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) 196 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) 197 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) 198 199 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) 200 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) 201 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) 202 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) 203 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) 204 205 #define PCI_VENDOR_ID_ROHM 0x10DB 206 207 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 208 209 #define DEFAULT_BAUD_RATE 1843200 /* 1.8432MHz */ 210 211 struct pch_uart_buffer { 212 unsigned char *buf; 213 int size; 214 }; 215 216 struct eg20t_port { 217 struct uart_port port; 218 int port_type; 219 void __iomem *membase; 220 resource_size_t mapbase; 221 unsigned int iobase; 222 struct pci_dev *pdev; 223 int fifo_size; 224 int base_baud; 225 int start_tx; 226 int start_rx; 227 int tx_empty; 228 int int_dis_flag; 229 int trigger; 230 int trigger_level; 231 struct pch_uart_buffer rxbuf; 232 unsigned int dmsr; 233 unsigned int fcr; 234 unsigned int mcr; 235 unsigned int use_dma; 236 unsigned int use_dma_flag; 237 struct dma_async_tx_descriptor *desc_tx; 238 struct dma_async_tx_descriptor *desc_rx; 239 struct pch_dma_slave param_tx; 240 struct pch_dma_slave param_rx; 241 struct dma_chan *chan_tx; 242 struct dma_chan *chan_rx; 243 struct scatterlist *sg_tx_p; 244 int nent; 245 struct scatterlist sg_rx; 246 int tx_dma_use; 247 void *rx_buf_virt; 248 dma_addr_t rx_buf_dma; 249 250 struct dentry *debugfs; 251 }; 252 253 /** 254 * struct pch_uart_driver_data - private data structure for UART-DMA 255 * @port_type: The number of DMA channel 256 * @line_no: UART port line number (0, 1, 2...) 257 */ 258 struct pch_uart_driver_data { 259 int port_type; 260 int line_no; 261 }; 262 263 enum pch_uart_num_t { 264 pch_et20t_uart0 = 0, 265 pch_et20t_uart1, 266 pch_et20t_uart2, 267 pch_et20t_uart3, 268 pch_ml7213_uart0, 269 pch_ml7213_uart1, 270 pch_ml7213_uart2, 271 pch_ml7223_uart0, 272 pch_ml7223_uart1, 273 pch_ml7831_uart0, 274 pch_ml7831_uart1, 275 }; 276 277 static struct pch_uart_driver_data drv_dat[] = { 278 [pch_et20t_uart0] = {PCH_UART_8LINE, 0}, 279 [pch_et20t_uart1] = {PCH_UART_2LINE, 1}, 280 [pch_et20t_uart2] = {PCH_UART_2LINE, 2}, 281 [pch_et20t_uart3] = {PCH_UART_2LINE, 3}, 282 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0}, 283 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1}, 284 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2}, 285 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0}, 286 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1}, 287 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0}, 288 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1}, 289 }; 290 291 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 292 static struct eg20t_port *pch_uart_ports[PCH_UART_NR]; 293 #endif 294 static unsigned int default_baud = 9600; 295 static const int trigger_level_256[4] = { 1, 64, 128, 224 }; 296 static const int trigger_level_64[4] = { 1, 16, 32, 56 }; 297 static const int trigger_level_16[4] = { 1, 4, 8, 14 }; 298 static const int trigger_level_1[4] = { 1, 1, 1, 1 }; 299 300 #ifdef CONFIG_DEBUG_FS 301 302 #define PCH_REGS_BUFSIZE 1024 303 static int pch_show_regs_open(struct inode *inode, struct file *file) 304 { 305 file->private_data = inode->i_private; 306 return 0; 307 } 308 309 static ssize_t port_show_regs(struct file *file, char __user *user_buf, 310 size_t count, loff_t *ppos) 311 { 312 struct eg20t_port *priv = file->private_data; 313 char *buf; 314 u32 len = 0; 315 ssize_t ret; 316 unsigned char lcr; 317 318 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL); 319 if (!buf) 320 return 0; 321 322 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 323 "PCH EG20T port[%d] regs:\n", priv->port.line); 324 325 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 326 "=================================\n"); 327 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 328 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); 329 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 330 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); 331 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 332 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); 333 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 334 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); 335 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 336 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); 337 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 338 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); 339 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 340 "BRCSR: \t0x%02x\n", 341 ioread8(priv->membase + PCH_UART_BRCSR)); 342 343 lcr = ioread8(priv->membase + UART_LCR); 344 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 345 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 346 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); 347 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 348 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); 349 iowrite8(lcr, priv->membase + UART_LCR); 350 351 if (len > PCH_REGS_BUFSIZE) 352 len = PCH_REGS_BUFSIZE; 353 354 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 355 kfree(buf); 356 return ret; 357 } 358 359 static const struct file_operations port_regs_ops = { 360 .owner = THIS_MODULE, 361 .open = pch_show_regs_open, 362 .read = port_show_regs, 363 .llseek = default_llseek, 364 }; 365 #endif /* CONFIG_DEBUG_FS */ 366 367 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, 368 unsigned int flag) 369 { 370 u8 ier = ioread8(priv->membase + UART_IER); 371 ier |= flag & PCH_UART_IER_MASK; 372 iowrite8(ier, priv->membase + UART_IER); 373 } 374 375 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, 376 unsigned int flag) 377 { 378 u8 ier = ioread8(priv->membase + UART_IER); 379 ier &= ~(flag & PCH_UART_IER_MASK); 380 iowrite8(ier, priv->membase + UART_IER); 381 } 382 383 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud, 384 unsigned int parity, unsigned int bits, 385 unsigned int stb) 386 { 387 unsigned int dll, dlm, lcr; 388 int div; 389 390 div = DIV_ROUND_CLOSEST(priv->base_baud / 16, baud); 391 if (div < 0 || USHRT_MAX <= div) { 392 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); 393 return -EINVAL; 394 } 395 396 dll = (unsigned int)div & 0x00FFU; 397 dlm = ((unsigned int)div >> 8) & 0x00FFU; 398 399 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { 400 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); 401 return -EINVAL; 402 } 403 404 if (bits & ~PCH_UART_LCR_WLS) { 405 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); 406 return -EINVAL; 407 } 408 409 if (stb & ~PCH_UART_LCR_STB) { 410 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); 411 return -EINVAL; 412 } 413 414 lcr = parity; 415 lcr |= bits; 416 lcr |= stb; 417 418 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n", 419 __func__, baud, div, lcr, jiffies); 420 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 421 iowrite8(dll, priv->membase + PCH_UART_DLL); 422 iowrite8(dlm, priv->membase + PCH_UART_DLM); 423 iowrite8(lcr, priv->membase + UART_LCR); 424 425 return 0; 426 } 427 428 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, 429 unsigned int flag) 430 { 431 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { 432 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", 433 __func__, flag); 434 return -EINVAL; 435 } 436 437 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); 438 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, 439 priv->membase + UART_FCR); 440 iowrite8(priv->fcr, priv->membase + UART_FCR); 441 442 return 0; 443 } 444 445 static int pch_uart_hal_set_fifo(struct eg20t_port *priv, 446 unsigned int dmamode, 447 unsigned int fifo_size, unsigned int trigger) 448 { 449 u8 fcr; 450 451 if (dmamode & ~PCH_UART_FCR_DMS) { 452 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", 453 __func__, dmamode); 454 return -EINVAL; 455 } 456 457 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { 458 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", 459 __func__, fifo_size); 460 return -EINVAL; 461 } 462 463 if (trigger & ~PCH_UART_FCR_RFTL) { 464 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", 465 __func__, trigger); 466 return -EINVAL; 467 } 468 469 switch (priv->fifo_size) { 470 case 256: 471 priv->trigger_level = 472 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 473 break; 474 case 64: 475 priv->trigger_level = 476 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 477 break; 478 case 16: 479 priv->trigger_level = 480 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 481 break; 482 default: 483 priv->trigger_level = 484 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 485 break; 486 } 487 fcr = 488 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; 489 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); 490 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, 491 priv->membase + UART_FCR); 492 iowrite8(fcr, priv->membase + UART_FCR); 493 priv->fcr = fcr; 494 495 return 0; 496 } 497 498 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) 499 { 500 unsigned int msr = ioread8(priv->membase + UART_MSR); 501 priv->dmsr = msr & PCH_UART_MSR_DELTA; 502 return (u8)msr; 503 } 504 505 static void pch_uart_hal_write(struct eg20t_port *priv, 506 const unsigned char *buf, int tx_size) 507 { 508 int i; 509 unsigned int thr; 510 511 for (i = 0; i < tx_size;) { 512 thr = buf[i++]; 513 iowrite8(thr, priv->membase + PCH_UART_THR); 514 } 515 } 516 517 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, 518 int rx_size) 519 { 520 int i; 521 u8 rbr, lsr; 522 523 lsr = ioread8(priv->membase + UART_LSR); 524 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); 525 i < rx_size && lsr & UART_LSR_DR; 526 lsr = ioread8(priv->membase + UART_LSR)) { 527 rbr = ioread8(priv->membase + PCH_UART_RBR); 528 buf[i++] = rbr; 529 } 530 return i; 531 } 532 533 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv) 534 { 535 unsigned int iir; 536 int ret; 537 538 iir = ioread8(priv->membase + UART_IIR); 539 ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP)); 540 return ret; 541 } 542 543 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) 544 { 545 return ioread8(priv->membase + UART_LSR); 546 } 547 548 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) 549 { 550 unsigned int lcr; 551 552 lcr = ioread8(priv->membase + UART_LCR); 553 if (on) 554 lcr |= PCH_UART_LCR_SB; 555 else 556 lcr &= ~PCH_UART_LCR_SB; 557 558 iowrite8(lcr, priv->membase + UART_LCR); 559 } 560 561 static int push_rx(struct eg20t_port *priv, const unsigned char *buf, 562 int size) 563 { 564 struct uart_port *port; 565 struct tty_struct *tty; 566 567 port = &priv->port; 568 tty = tty_port_tty_get(&port->state->port); 569 if (!tty) { 570 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 571 return -EBUSY; 572 } 573 574 tty_insert_flip_string(tty, buf, size); 575 tty_flip_buffer_push(tty); 576 tty_kref_put(tty); 577 578 return 0; 579 } 580 581 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) 582 { 583 int ret = 0; 584 struct uart_port *port = &priv->port; 585 586 if (port->x_char) { 587 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n", 588 __func__, port->x_char, jiffies); 589 buf[0] = port->x_char; 590 port->x_char = 0; 591 ret = 1; 592 } 593 594 return ret; 595 } 596 597 static int dma_push_rx(struct eg20t_port *priv, int size) 598 { 599 struct tty_struct *tty; 600 int room; 601 struct uart_port *port = &priv->port; 602 603 port = &priv->port; 604 tty = tty_port_tty_get(&port->state->port); 605 if (!tty) { 606 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 607 return 0; 608 } 609 610 room = tty_buffer_request_room(tty, size); 611 612 if (room < size) 613 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 614 size - room); 615 if (!room) 616 return room; 617 618 tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size); 619 620 port->icount.rx += room; 621 tty_kref_put(tty); 622 623 return room; 624 } 625 626 static void pch_free_dma(struct uart_port *port) 627 { 628 struct eg20t_port *priv; 629 priv = container_of(port, struct eg20t_port, port); 630 631 if (priv->chan_tx) { 632 dma_release_channel(priv->chan_tx); 633 priv->chan_tx = NULL; 634 } 635 if (priv->chan_rx) { 636 dma_release_channel(priv->chan_rx); 637 priv->chan_rx = NULL; 638 } 639 if (sg_dma_address(&priv->sg_rx)) 640 dma_free_coherent(port->dev, port->fifosize, 641 sg_virt(&priv->sg_rx), 642 sg_dma_address(&priv->sg_rx)); 643 644 return; 645 } 646 647 static bool filter(struct dma_chan *chan, void *slave) 648 { 649 struct pch_dma_slave *param = slave; 650 651 if ((chan->chan_id == param->chan_id) && (param->dma_dev == 652 chan->device->dev)) { 653 chan->private = param; 654 return true; 655 } else { 656 return false; 657 } 658 } 659 660 static void pch_request_dma(struct uart_port *port) 661 { 662 dma_cap_mask_t mask; 663 struct dma_chan *chan; 664 struct pci_dev *dma_dev; 665 struct pch_dma_slave *param; 666 struct eg20t_port *priv = 667 container_of(port, struct eg20t_port, port); 668 dma_cap_zero(mask); 669 dma_cap_set(DMA_SLAVE, mask); 670 671 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number, 672 PCI_DEVFN(0xa, 0)); /* Get DMA's dev 673 information */ 674 /* Set Tx DMA */ 675 param = &priv->param_tx; 676 param->dma_dev = &dma_dev->dev; 677 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ 678 679 param->tx_reg = port->mapbase + UART_TX; 680 chan = dma_request_channel(mask, filter, param); 681 if (!chan) { 682 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", 683 __func__); 684 return; 685 } 686 priv->chan_tx = chan; 687 688 /* Set Rx DMA */ 689 param = &priv->param_rx; 690 param->dma_dev = &dma_dev->dev; 691 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ 692 693 param->rx_reg = port->mapbase + UART_RX; 694 chan = dma_request_channel(mask, filter, param); 695 if (!chan) { 696 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", 697 __func__); 698 dma_release_channel(priv->chan_tx); 699 priv->chan_tx = NULL; 700 return; 701 } 702 703 /* Get Consistent memory for DMA */ 704 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, 705 &priv->rx_buf_dma, GFP_KERNEL); 706 priv->chan_rx = chan; 707 } 708 709 static void pch_dma_rx_complete(void *arg) 710 { 711 struct eg20t_port *priv = arg; 712 struct uart_port *port = &priv->port; 713 struct tty_struct *tty = tty_port_tty_get(&port->state->port); 714 int count; 715 716 if (!tty) { 717 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 718 return; 719 } 720 721 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); 722 count = dma_push_rx(priv, priv->trigger_level); 723 if (count) 724 tty_flip_buffer_push(tty); 725 tty_kref_put(tty); 726 async_tx_ack(priv->desc_rx); 727 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT); 728 } 729 730 static void pch_dma_tx_complete(void *arg) 731 { 732 struct eg20t_port *priv = arg; 733 struct uart_port *port = &priv->port; 734 struct circ_buf *xmit = &port->state->xmit; 735 struct scatterlist *sg = priv->sg_tx_p; 736 int i; 737 738 for (i = 0; i < priv->nent; i++, sg++) { 739 xmit->tail += sg_dma_len(sg); 740 port->icount.tx += sg_dma_len(sg); 741 } 742 xmit->tail &= UART_XMIT_SIZE - 1; 743 async_tx_ack(priv->desc_tx); 744 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE); 745 priv->tx_dma_use = 0; 746 priv->nent = 0; 747 kfree(priv->sg_tx_p); 748 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 749 } 750 751 static int pop_tx(struct eg20t_port *priv, int size) 752 { 753 int count = 0; 754 struct uart_port *port = &priv->port; 755 struct circ_buf *xmit = &port->state->xmit; 756 757 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size) 758 goto pop_tx_end; 759 760 do { 761 int cnt_to_end = 762 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 763 int sz = min(size - count, cnt_to_end); 764 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz); 765 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1); 766 count += sz; 767 } while (!uart_circ_empty(xmit) && count < size); 768 769 pop_tx_end: 770 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n", 771 count, size - count, jiffies); 772 773 return count; 774 } 775 776 static int handle_rx_to(struct eg20t_port *priv) 777 { 778 struct pch_uart_buffer *buf; 779 int rx_size; 780 int ret; 781 if (!priv->start_rx) { 782 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT); 783 return 0; 784 } 785 buf = &priv->rxbuf; 786 do { 787 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); 788 ret = push_rx(priv, buf->buf, rx_size); 789 if (ret) 790 return 0; 791 } while (rx_size == buf->size); 792 793 return PCH_UART_HANDLED_RX_INT; 794 } 795 796 static int handle_rx(struct eg20t_port *priv) 797 { 798 return handle_rx_to(priv); 799 } 800 801 static int dma_handle_rx(struct eg20t_port *priv) 802 { 803 struct uart_port *port = &priv->port; 804 struct dma_async_tx_descriptor *desc; 805 struct scatterlist *sg; 806 807 priv = container_of(port, struct eg20t_port, port); 808 sg = &priv->sg_rx; 809 810 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ 811 812 sg_dma_len(sg) = priv->trigger_level; 813 814 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), 815 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt & 816 ~PAGE_MASK); 817 818 sg_dma_address(sg) = priv->rx_buf_dma; 819 820 desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx, 821 sg, 1, DMA_DEV_TO_MEM, 822 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 823 824 if (!desc) 825 return 0; 826 827 priv->desc_rx = desc; 828 desc->callback = pch_dma_rx_complete; 829 desc->callback_param = priv; 830 desc->tx_submit(desc); 831 dma_async_issue_pending(priv->chan_rx); 832 833 return PCH_UART_HANDLED_RX_INT; 834 } 835 836 static unsigned int handle_tx(struct eg20t_port *priv) 837 { 838 struct uart_port *port = &priv->port; 839 struct circ_buf *xmit = &port->state->xmit; 840 int fifo_size; 841 int tx_size; 842 int size; 843 int tx_empty; 844 845 if (!priv->start_tx) { 846 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 847 __func__, jiffies); 848 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 849 priv->tx_empty = 1; 850 return 0; 851 } 852 853 fifo_size = max(priv->fifo_size, 1); 854 tx_empty = 1; 855 if (pop_tx_x(priv, xmit->buf)) { 856 pch_uart_hal_write(priv, xmit->buf, 1); 857 port->icount.tx++; 858 tx_empty = 0; 859 fifo_size--; 860 } 861 size = min(xmit->head - xmit->tail, fifo_size); 862 if (size < 0) 863 size = fifo_size; 864 865 tx_size = pop_tx(priv, size); 866 if (tx_size > 0) { 867 port->icount.tx += tx_size; 868 tx_empty = 0; 869 } 870 871 priv->tx_empty = tx_empty; 872 873 if (tx_empty) { 874 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 875 uart_write_wakeup(port); 876 } 877 878 return PCH_UART_HANDLED_TX_INT; 879 } 880 881 static unsigned int dma_handle_tx(struct eg20t_port *priv) 882 { 883 struct uart_port *port = &priv->port; 884 struct circ_buf *xmit = &port->state->xmit; 885 struct scatterlist *sg; 886 int nent; 887 int fifo_size; 888 int tx_empty; 889 struct dma_async_tx_descriptor *desc; 890 int num; 891 int i; 892 int bytes; 893 int size; 894 int rem; 895 896 if (!priv->start_tx) { 897 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 898 __func__, jiffies); 899 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 900 priv->tx_empty = 1; 901 return 0; 902 } 903 904 if (priv->tx_dma_use) { 905 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", 906 __func__, jiffies); 907 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 908 priv->tx_empty = 1; 909 return 0; 910 } 911 912 fifo_size = max(priv->fifo_size, 1); 913 tx_empty = 1; 914 if (pop_tx_x(priv, xmit->buf)) { 915 pch_uart_hal_write(priv, xmit->buf, 1); 916 port->icount.tx++; 917 tx_empty = 0; 918 fifo_size--; 919 } 920 921 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail, 922 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head, 923 xmit->tail, UART_XMIT_SIZE)); 924 if (!bytes) { 925 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); 926 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 927 uart_write_wakeup(port); 928 return 0; 929 } 930 931 if (bytes > fifo_size) { 932 num = bytes / fifo_size + 1; 933 size = fifo_size; 934 rem = bytes % fifo_size; 935 } else { 936 num = 1; 937 size = bytes; 938 rem = bytes; 939 } 940 941 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", 942 __func__, num, size, rem); 943 944 priv->tx_dma_use = 1; 945 946 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); 947 948 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ 949 sg = priv->sg_tx_p; 950 951 for (i = 0; i < num; i++, sg++) { 952 if (i == (num - 1)) 953 sg_set_page(sg, virt_to_page(xmit->buf), 954 rem, fifo_size * i); 955 else 956 sg_set_page(sg, virt_to_page(xmit->buf), 957 size, fifo_size * i); 958 } 959 960 sg = priv->sg_tx_p; 961 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); 962 if (!nent) { 963 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); 964 return 0; 965 } 966 priv->nent = nent; 967 968 for (i = 0; i < nent; i++, sg++) { 969 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + 970 fifo_size * i; 971 sg_dma_address(sg) = (sg_dma_address(sg) & 972 ~(UART_XMIT_SIZE - 1)) + sg->offset; 973 if (i == (nent - 1)) 974 sg_dma_len(sg) = rem; 975 else 976 sg_dma_len(sg) = size; 977 } 978 979 desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx, 980 priv->sg_tx_p, nent, DMA_MEM_TO_DEV, 981 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 982 if (!desc) { 983 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n", 984 __func__); 985 return 0; 986 } 987 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); 988 priv->desc_tx = desc; 989 desc->callback = pch_dma_tx_complete; 990 desc->callback_param = priv; 991 992 desc->tx_submit(desc); 993 994 dma_async_issue_pending(priv->chan_tx); 995 996 return PCH_UART_HANDLED_TX_INT; 997 } 998 999 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) 1000 { 1001 u8 fcr = ioread8(priv->membase + UART_FCR); 1002 1003 /* Reset FIFO */ 1004 fcr |= UART_FCR_CLEAR_RCVR; 1005 iowrite8(fcr, priv->membase + UART_FCR); 1006 1007 if (lsr & PCH_UART_LSR_ERR) 1008 dev_err(&priv->pdev->dev, "Error data in FIFO\n"); 1009 1010 if (lsr & UART_LSR_FE) 1011 dev_err(&priv->pdev->dev, "Framing Error\n"); 1012 1013 if (lsr & UART_LSR_PE) 1014 dev_err(&priv->pdev->dev, "Parity Error\n"); 1015 1016 if (lsr & UART_LSR_OE) 1017 dev_err(&priv->pdev->dev, "Overrun Error\n"); 1018 } 1019 1020 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) 1021 { 1022 struct eg20t_port *priv = dev_id; 1023 unsigned int handled; 1024 u8 lsr; 1025 int ret = 0; 1026 unsigned int iid; 1027 unsigned long flags; 1028 1029 spin_lock_irqsave(&priv->port.lock, flags); 1030 handled = 0; 1031 while ((iid = pch_uart_hal_get_iid(priv)) > 1) { 1032 switch (iid) { 1033 case PCH_UART_IID_RLS: /* Receiver Line Status */ 1034 lsr = pch_uart_hal_get_line_status(priv); 1035 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | 1036 UART_LSR_PE | UART_LSR_OE)) { 1037 pch_uart_err_ir(priv, lsr); 1038 ret = PCH_UART_HANDLED_RX_ERR_INT; 1039 } 1040 break; 1041 case PCH_UART_IID_RDR: /* Received Data Ready */ 1042 if (priv->use_dma) { 1043 pch_uart_hal_disable_interrupt(priv, 1044 PCH_UART_HAL_RX_INT); 1045 ret = dma_handle_rx(priv); 1046 if (!ret) 1047 pch_uart_hal_enable_interrupt(priv, 1048 PCH_UART_HAL_RX_INT); 1049 } else { 1050 ret = handle_rx(priv); 1051 } 1052 break; 1053 case PCH_UART_IID_RDR_TO: /* Received Data Ready 1054 (FIFO Timeout) */ 1055 ret = handle_rx_to(priv); 1056 break; 1057 case PCH_UART_IID_THRE: /* Transmitter Holding Register 1058 Empty */ 1059 if (priv->use_dma) 1060 ret = dma_handle_tx(priv); 1061 else 1062 ret = handle_tx(priv); 1063 break; 1064 case PCH_UART_IID_MS: /* Modem Status */ 1065 ret = PCH_UART_HANDLED_MS_INT; 1066 break; 1067 default: /* Never junp to this label */ 1068 dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__, 1069 iid, jiffies); 1070 ret = -1; 1071 break; 1072 } 1073 handled |= (unsigned int)ret; 1074 } 1075 if (handled == 0 && iid <= 1) { 1076 if (priv->int_dis_flag) 1077 priv->int_dis_flag = 0; 1078 } 1079 1080 spin_unlock_irqrestore(&priv->port.lock, flags); 1081 return IRQ_RETVAL(handled); 1082 } 1083 1084 /* This function tests whether the transmitter fifo and shifter for the port 1085 described by 'port' is empty. */ 1086 static unsigned int pch_uart_tx_empty(struct uart_port *port) 1087 { 1088 struct eg20t_port *priv; 1089 1090 priv = container_of(port, struct eg20t_port, port); 1091 if (priv->tx_empty) 1092 return TIOCSER_TEMT; 1093 else 1094 return 0; 1095 } 1096 1097 /* Returns the current state of modem control inputs. */ 1098 static unsigned int pch_uart_get_mctrl(struct uart_port *port) 1099 { 1100 struct eg20t_port *priv; 1101 u8 modem; 1102 unsigned int ret = 0; 1103 1104 priv = container_of(port, struct eg20t_port, port); 1105 modem = pch_uart_hal_get_modem(priv); 1106 1107 if (modem & UART_MSR_DCD) 1108 ret |= TIOCM_CAR; 1109 1110 if (modem & UART_MSR_RI) 1111 ret |= TIOCM_RNG; 1112 1113 if (modem & UART_MSR_DSR) 1114 ret |= TIOCM_DSR; 1115 1116 if (modem & UART_MSR_CTS) 1117 ret |= TIOCM_CTS; 1118 1119 return ret; 1120 } 1121 1122 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1123 { 1124 u32 mcr = 0; 1125 struct eg20t_port *priv = container_of(port, struct eg20t_port, port); 1126 1127 if (mctrl & TIOCM_DTR) 1128 mcr |= UART_MCR_DTR; 1129 if (mctrl & TIOCM_RTS) 1130 mcr |= UART_MCR_RTS; 1131 if (mctrl & TIOCM_LOOP) 1132 mcr |= UART_MCR_LOOP; 1133 1134 if (priv->mcr & UART_MCR_AFE) 1135 mcr |= UART_MCR_AFE; 1136 1137 if (mctrl) 1138 iowrite8(mcr, priv->membase + UART_MCR); 1139 } 1140 1141 static void pch_uart_stop_tx(struct uart_port *port) 1142 { 1143 struct eg20t_port *priv; 1144 priv = container_of(port, struct eg20t_port, port); 1145 priv->start_tx = 0; 1146 priv->tx_dma_use = 0; 1147 } 1148 1149 static void pch_uart_start_tx(struct uart_port *port) 1150 { 1151 struct eg20t_port *priv; 1152 1153 priv = container_of(port, struct eg20t_port, port); 1154 1155 if (priv->use_dma) { 1156 if (priv->tx_dma_use) { 1157 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", 1158 __func__); 1159 return; 1160 } 1161 } 1162 1163 priv->start_tx = 1; 1164 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 1165 } 1166 1167 static void pch_uart_stop_rx(struct uart_port *port) 1168 { 1169 struct eg20t_port *priv; 1170 priv = container_of(port, struct eg20t_port, port); 1171 priv->start_rx = 0; 1172 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT); 1173 priv->int_dis_flag = 1; 1174 } 1175 1176 /* Enable the modem status interrupts. */ 1177 static void pch_uart_enable_ms(struct uart_port *port) 1178 { 1179 struct eg20t_port *priv; 1180 priv = container_of(port, struct eg20t_port, port); 1181 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); 1182 } 1183 1184 /* Control the transmission of a break signal. */ 1185 static void pch_uart_break_ctl(struct uart_port *port, int ctl) 1186 { 1187 struct eg20t_port *priv; 1188 unsigned long flags; 1189 1190 priv = container_of(port, struct eg20t_port, port); 1191 spin_lock_irqsave(&port->lock, flags); 1192 pch_uart_hal_set_break(priv, ctl); 1193 spin_unlock_irqrestore(&port->lock, flags); 1194 } 1195 1196 /* Grab any interrupt resources and initialise any low level driver state. */ 1197 static int pch_uart_startup(struct uart_port *port) 1198 { 1199 struct eg20t_port *priv; 1200 int ret; 1201 int fifo_size; 1202 int trigger_level; 1203 1204 priv = container_of(port, struct eg20t_port, port); 1205 priv->tx_empty = 1; 1206 1207 if (port->uartclk) 1208 priv->base_baud = port->uartclk; 1209 else 1210 port->uartclk = priv->base_baud; 1211 1212 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1213 ret = pch_uart_hal_set_line(priv, default_baud, 1214 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, 1215 PCH_UART_HAL_STB1); 1216 if (ret) 1217 return ret; 1218 1219 switch (priv->fifo_size) { 1220 case 256: 1221 fifo_size = PCH_UART_HAL_FIFO256; 1222 break; 1223 case 64: 1224 fifo_size = PCH_UART_HAL_FIFO64; 1225 break; 1226 case 16: 1227 fifo_size = PCH_UART_HAL_FIFO16; 1228 case 1: 1229 default: 1230 fifo_size = PCH_UART_HAL_FIFO_DIS; 1231 break; 1232 } 1233 1234 switch (priv->trigger) { 1235 case PCH_UART_HAL_TRIGGER1: 1236 trigger_level = 1; 1237 break; 1238 case PCH_UART_HAL_TRIGGER_L: 1239 trigger_level = priv->fifo_size / 4; 1240 break; 1241 case PCH_UART_HAL_TRIGGER_M: 1242 trigger_level = priv->fifo_size / 2; 1243 break; 1244 case PCH_UART_HAL_TRIGGER_H: 1245 default: 1246 trigger_level = priv->fifo_size - (priv->fifo_size / 8); 1247 break; 1248 } 1249 1250 priv->trigger_level = trigger_level; 1251 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1252 fifo_size, priv->trigger); 1253 if (ret < 0) 1254 return ret; 1255 1256 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, 1257 KBUILD_MODNAME, priv); 1258 if (ret < 0) 1259 return ret; 1260 1261 if (priv->use_dma) 1262 pch_request_dma(port); 1263 1264 priv->start_rx = 1; 1265 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT); 1266 uart_update_timeout(port, CS8, default_baud); 1267 1268 return 0; 1269 } 1270 1271 static void pch_uart_shutdown(struct uart_port *port) 1272 { 1273 struct eg20t_port *priv; 1274 int ret; 1275 1276 priv = container_of(port, struct eg20t_port, port); 1277 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1278 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); 1279 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1280 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); 1281 if (ret) 1282 dev_err(priv->port.dev, 1283 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); 1284 1285 pch_free_dma(port); 1286 1287 free_irq(priv->port.irq, priv); 1288 } 1289 1290 /* Change the port parameters, including word length, parity, stop 1291 *bits. Update read_status_mask and ignore_status_mask to indicate 1292 *the types of events we are interested in receiving. */ 1293 static void pch_uart_set_termios(struct uart_port *port, 1294 struct ktermios *termios, struct ktermios *old) 1295 { 1296 int baud; 1297 int rtn; 1298 unsigned int parity, bits, stb; 1299 struct eg20t_port *priv; 1300 unsigned long flags; 1301 1302 priv = container_of(port, struct eg20t_port, port); 1303 switch (termios->c_cflag & CSIZE) { 1304 case CS5: 1305 bits = PCH_UART_HAL_5BIT; 1306 break; 1307 case CS6: 1308 bits = PCH_UART_HAL_6BIT; 1309 break; 1310 case CS7: 1311 bits = PCH_UART_HAL_7BIT; 1312 break; 1313 default: /* CS8 */ 1314 bits = PCH_UART_HAL_8BIT; 1315 break; 1316 } 1317 if (termios->c_cflag & CSTOPB) 1318 stb = PCH_UART_HAL_STB2; 1319 else 1320 stb = PCH_UART_HAL_STB1; 1321 1322 if (termios->c_cflag & PARENB) { 1323 if (!(termios->c_cflag & PARODD)) 1324 parity = PCH_UART_HAL_PARITY_ODD; 1325 else 1326 parity = PCH_UART_HAL_PARITY_EVEN; 1327 1328 } else 1329 parity = PCH_UART_HAL_PARITY_NONE; 1330 1331 /* Only UART0 has auto hardware flow function */ 1332 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) 1333 priv->mcr |= UART_MCR_AFE; 1334 else 1335 priv->mcr &= ~UART_MCR_AFE; 1336 1337 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 1338 1339 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1340 1341 spin_lock_irqsave(&port->lock, flags); 1342 1343 uart_update_timeout(port, termios->c_cflag, baud); 1344 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); 1345 if (rtn) 1346 goto out; 1347 1348 pch_uart_set_mctrl(&priv->port, priv->port.mctrl); 1349 /* Don't rewrite B0 */ 1350 if (tty_termios_baud_rate(termios)) 1351 tty_termios_encode_baud_rate(termios, baud, baud); 1352 1353 out: 1354 spin_unlock_irqrestore(&port->lock, flags); 1355 } 1356 1357 static const char *pch_uart_type(struct uart_port *port) 1358 { 1359 return KBUILD_MODNAME; 1360 } 1361 1362 static void pch_uart_release_port(struct uart_port *port) 1363 { 1364 struct eg20t_port *priv; 1365 1366 priv = container_of(port, struct eg20t_port, port); 1367 pci_iounmap(priv->pdev, priv->membase); 1368 pci_release_regions(priv->pdev); 1369 } 1370 1371 static int pch_uart_request_port(struct uart_port *port) 1372 { 1373 struct eg20t_port *priv; 1374 int ret; 1375 void __iomem *membase; 1376 1377 priv = container_of(port, struct eg20t_port, port); 1378 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); 1379 if (ret < 0) 1380 return -EBUSY; 1381 1382 membase = pci_iomap(priv->pdev, 1, 0); 1383 if (!membase) { 1384 pci_release_regions(priv->pdev); 1385 return -EBUSY; 1386 } 1387 priv->membase = port->membase = membase; 1388 1389 return 0; 1390 } 1391 1392 static void pch_uart_config_port(struct uart_port *port, int type) 1393 { 1394 struct eg20t_port *priv; 1395 1396 priv = container_of(port, struct eg20t_port, port); 1397 if (type & UART_CONFIG_TYPE) { 1398 port->type = priv->port_type; 1399 pch_uart_request_port(port); 1400 } 1401 } 1402 1403 static int pch_uart_verify_port(struct uart_port *port, 1404 struct serial_struct *serinfo) 1405 { 1406 struct eg20t_port *priv; 1407 1408 priv = container_of(port, struct eg20t_port, port); 1409 if (serinfo->flags & UPF_LOW_LATENCY) { 1410 dev_info(priv->port.dev, 1411 "PCH UART : Use PIO Mode (without DMA)\n"); 1412 priv->use_dma = 0; 1413 serinfo->flags &= ~UPF_LOW_LATENCY; 1414 } else { 1415 #ifndef CONFIG_PCH_DMA 1416 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", 1417 __func__); 1418 return -EOPNOTSUPP; 1419 #endif 1420 priv->use_dma = 1; 1421 priv->use_dma_flag = 1; 1422 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n"); 1423 } 1424 1425 return 0; 1426 } 1427 1428 static struct uart_ops pch_uart_ops = { 1429 .tx_empty = pch_uart_tx_empty, 1430 .set_mctrl = pch_uart_set_mctrl, 1431 .get_mctrl = pch_uart_get_mctrl, 1432 .stop_tx = pch_uart_stop_tx, 1433 .start_tx = pch_uart_start_tx, 1434 .stop_rx = pch_uart_stop_rx, 1435 .enable_ms = pch_uart_enable_ms, 1436 .break_ctl = pch_uart_break_ctl, 1437 .startup = pch_uart_startup, 1438 .shutdown = pch_uart_shutdown, 1439 .set_termios = pch_uart_set_termios, 1440 /* .pm = pch_uart_pm, Not supported yet */ 1441 /* .set_wake = pch_uart_set_wake, Not supported yet */ 1442 .type = pch_uart_type, 1443 .release_port = pch_uart_release_port, 1444 .request_port = pch_uart_request_port, 1445 .config_port = pch_uart_config_port, 1446 .verify_port = pch_uart_verify_port 1447 }; 1448 1449 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1450 1451 /* 1452 * Wait for transmitter & holding register to empty 1453 */ 1454 static void wait_for_xmitr(struct eg20t_port *up, int bits) 1455 { 1456 unsigned int status, tmout = 10000; 1457 1458 /* Wait up to 10ms for the character(s) to be sent. */ 1459 for (;;) { 1460 status = ioread8(up->membase + UART_LSR); 1461 1462 if ((status & bits) == bits) 1463 break; 1464 if (--tmout == 0) 1465 break; 1466 udelay(1); 1467 } 1468 1469 /* Wait up to 1s for flow control if necessary */ 1470 if (up->port.flags & UPF_CONS_FLOW) { 1471 unsigned int tmout; 1472 for (tmout = 1000000; tmout; tmout--) { 1473 unsigned int msr = ioread8(up->membase + UART_MSR); 1474 if (msr & UART_MSR_CTS) 1475 break; 1476 udelay(1); 1477 touch_nmi_watchdog(); 1478 } 1479 } 1480 } 1481 1482 static void pch_console_putchar(struct uart_port *port, int ch) 1483 { 1484 struct eg20t_port *priv = 1485 container_of(port, struct eg20t_port, port); 1486 1487 wait_for_xmitr(priv, UART_LSR_THRE); 1488 iowrite8(ch, priv->membase + PCH_UART_THR); 1489 } 1490 1491 /* 1492 * Print a string to the serial port trying not to disturb 1493 * any possible real use of the port... 1494 * 1495 * The console_lock must be held when we get here. 1496 */ 1497 static void 1498 pch_console_write(struct console *co, const char *s, unsigned int count) 1499 { 1500 struct eg20t_port *priv; 1501 unsigned long flags; 1502 u8 ier; 1503 int locked = 1; 1504 1505 priv = pch_uart_ports[co->index]; 1506 1507 touch_nmi_watchdog(); 1508 1509 local_irq_save(flags); 1510 if (priv->port.sysrq) { 1511 /* serial8250_handle_port() already took the lock */ 1512 locked = 0; 1513 } else if (oops_in_progress) { 1514 locked = spin_trylock(&priv->port.lock); 1515 } else 1516 spin_lock(&priv->port.lock); 1517 1518 /* 1519 * First save the IER then disable the interrupts 1520 */ 1521 ier = ioread8(priv->membase + UART_IER); 1522 1523 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1524 1525 uart_console_write(&priv->port, s, count, pch_console_putchar); 1526 1527 /* 1528 * Finally, wait for transmitter to become empty 1529 * and restore the IER 1530 */ 1531 wait_for_xmitr(priv, BOTH_EMPTY); 1532 iowrite8(ier, priv->membase + UART_IER); 1533 1534 if (locked) 1535 spin_unlock(&priv->port.lock); 1536 local_irq_restore(flags); 1537 } 1538 1539 static int __init pch_console_setup(struct console *co, char *options) 1540 { 1541 struct uart_port *port; 1542 int baud = 9600; 1543 int bits = 8; 1544 int parity = 'n'; 1545 int flow = 'n'; 1546 1547 /* 1548 * Check whether an invalid uart number has been specified, and 1549 * if so, search for the first available port that does have 1550 * console support. 1551 */ 1552 if (co->index >= PCH_UART_NR) 1553 co->index = 0; 1554 port = &pch_uart_ports[co->index]->port; 1555 1556 if (!port || (!port->iobase && !port->membase)) 1557 return -ENODEV; 1558 1559 /* setup uartclock */ 1560 port->uartclk = DEFAULT_BAUD_RATE; 1561 1562 if (options) 1563 uart_parse_options(options, &baud, &parity, &bits, &flow); 1564 1565 return uart_set_options(port, co, baud, parity, bits, flow); 1566 } 1567 1568 static struct uart_driver pch_uart_driver; 1569 1570 static struct console pch_console = { 1571 .name = PCH_UART_DRIVER_DEVICE, 1572 .write = pch_console_write, 1573 .device = uart_console_device, 1574 .setup = pch_console_setup, 1575 .flags = CON_PRINTBUFFER | CON_ANYTIME, 1576 .index = -1, 1577 .data = &pch_uart_driver, 1578 }; 1579 1580 #define PCH_CONSOLE (&pch_console) 1581 #else 1582 #define PCH_CONSOLE NULL 1583 #endif 1584 1585 static struct uart_driver pch_uart_driver = { 1586 .owner = THIS_MODULE, 1587 .driver_name = KBUILD_MODNAME, 1588 .dev_name = PCH_UART_DRIVER_DEVICE, 1589 .major = 0, 1590 .minor = 0, 1591 .nr = PCH_UART_NR, 1592 .cons = PCH_CONSOLE, 1593 }; 1594 1595 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, 1596 const struct pci_device_id *id) 1597 { 1598 struct eg20t_port *priv; 1599 int ret; 1600 unsigned int iobase; 1601 unsigned int mapbase; 1602 unsigned char *rxbuf; 1603 int fifosize, base_baud; 1604 int port_type; 1605 struct pch_uart_driver_data *board; 1606 const char *board_name; 1607 char name[32]; /* for debugfs file name */ 1608 1609 board = &drv_dat[id->driver_data]; 1610 port_type = board->port_type; 1611 1612 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); 1613 if (priv == NULL) 1614 goto init_port_alloc_err; 1615 1616 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); 1617 if (!rxbuf) 1618 goto init_port_free_txbuf; 1619 1620 base_baud = DEFAULT_BAUD_RATE; 1621 1622 /* quirk for CM-iTC board */ 1623 board_name = dmi_get_system_info(DMI_BOARD_NAME); 1624 if (board_name && strstr(board_name, "CM-iTC")) 1625 base_baud = 192000000; /* 192.0MHz */ 1626 1627 switch (port_type) { 1628 case PORT_UNKNOWN: 1629 fifosize = 256; /* EG20T/ML7213: UART0 */ 1630 break; 1631 case PORT_8250: 1632 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ 1633 break; 1634 default: 1635 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); 1636 goto init_port_hal_free; 1637 } 1638 1639 pci_enable_msi(pdev); 1640 1641 iobase = pci_resource_start(pdev, 0); 1642 mapbase = pci_resource_start(pdev, 1); 1643 priv->mapbase = mapbase; 1644 priv->iobase = iobase; 1645 priv->pdev = pdev; 1646 priv->tx_empty = 1; 1647 priv->rxbuf.buf = rxbuf; 1648 priv->rxbuf.size = PAGE_SIZE; 1649 1650 priv->fifo_size = fifosize; 1651 priv->base_baud = base_baud; 1652 priv->port_type = PORT_MAX_8250 + port_type + 1; 1653 priv->port.dev = &pdev->dev; 1654 priv->port.iobase = iobase; 1655 priv->port.membase = NULL; 1656 priv->port.mapbase = mapbase; 1657 priv->port.irq = pdev->irq; 1658 priv->port.iotype = UPIO_PORT; 1659 priv->port.ops = &pch_uart_ops; 1660 priv->port.flags = UPF_BOOT_AUTOCONF; 1661 priv->port.fifosize = fifosize; 1662 priv->port.line = board->line_no; 1663 priv->trigger = PCH_UART_HAL_TRIGGER_M; 1664 1665 spin_lock_init(&priv->port.lock); 1666 1667 pci_set_drvdata(pdev, priv); 1668 priv->trigger_level = 1; 1669 priv->fcr = 0; 1670 1671 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1672 pch_uart_ports[board->line_no] = priv; 1673 #endif 1674 ret = uart_add_one_port(&pch_uart_driver, &priv->port); 1675 if (ret < 0) 1676 goto init_port_hal_free; 1677 1678 #ifdef CONFIG_DEBUG_FS 1679 snprintf(name, sizeof(name), "uart%d_regs", board->line_no); 1680 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO, 1681 NULL, priv, &port_regs_ops); 1682 #endif 1683 1684 return priv; 1685 1686 init_port_hal_free: 1687 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1688 pch_uart_ports[board->line_no] = NULL; 1689 #endif 1690 free_page((unsigned long)rxbuf); 1691 init_port_free_txbuf: 1692 kfree(priv); 1693 init_port_alloc_err: 1694 1695 return NULL; 1696 } 1697 1698 static void pch_uart_exit_port(struct eg20t_port *priv) 1699 { 1700 1701 #ifdef CONFIG_DEBUG_FS 1702 if (priv->debugfs) 1703 debugfs_remove(priv->debugfs); 1704 #endif 1705 uart_remove_one_port(&pch_uart_driver, &priv->port); 1706 pci_set_drvdata(priv->pdev, NULL); 1707 free_page((unsigned long)priv->rxbuf.buf); 1708 } 1709 1710 static void pch_uart_pci_remove(struct pci_dev *pdev) 1711 { 1712 struct eg20t_port *priv = pci_get_drvdata(pdev); 1713 1714 pci_disable_msi(pdev); 1715 1716 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1717 pch_uart_ports[priv->port.line] = NULL; 1718 #endif 1719 pch_uart_exit_port(priv); 1720 pci_disable_device(pdev); 1721 kfree(priv); 1722 return; 1723 } 1724 #ifdef CONFIG_PM 1725 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1726 { 1727 struct eg20t_port *priv = pci_get_drvdata(pdev); 1728 1729 uart_suspend_port(&pch_uart_driver, &priv->port); 1730 1731 pci_save_state(pdev); 1732 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1733 return 0; 1734 } 1735 1736 static int pch_uart_pci_resume(struct pci_dev *pdev) 1737 { 1738 struct eg20t_port *priv = pci_get_drvdata(pdev); 1739 int ret; 1740 1741 pci_set_power_state(pdev, PCI_D0); 1742 pci_restore_state(pdev); 1743 1744 ret = pci_enable_device(pdev); 1745 if (ret) { 1746 dev_err(&pdev->dev, 1747 "%s-pci_enable_device failed(ret=%d) ", __func__, ret); 1748 return ret; 1749 } 1750 1751 uart_resume_port(&pch_uart_driver, &priv->port); 1752 1753 return 0; 1754 } 1755 #else 1756 #define pch_uart_pci_suspend NULL 1757 #define pch_uart_pci_resume NULL 1758 #endif 1759 1760 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = { 1761 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), 1762 .driver_data = pch_et20t_uart0}, 1763 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), 1764 .driver_data = pch_et20t_uart1}, 1765 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), 1766 .driver_data = pch_et20t_uart2}, 1767 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), 1768 .driver_data = pch_et20t_uart3}, 1769 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), 1770 .driver_data = pch_ml7213_uart0}, 1771 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), 1772 .driver_data = pch_ml7213_uart1}, 1773 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), 1774 .driver_data = pch_ml7213_uart2}, 1775 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C), 1776 .driver_data = pch_ml7223_uart0}, 1777 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D), 1778 .driver_data = pch_ml7223_uart1}, 1779 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811), 1780 .driver_data = pch_ml7831_uart0}, 1781 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812), 1782 .driver_data = pch_ml7831_uart1}, 1783 {0,}, 1784 }; 1785 1786 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev, 1787 const struct pci_device_id *id) 1788 { 1789 int ret; 1790 struct eg20t_port *priv; 1791 1792 ret = pci_enable_device(pdev); 1793 if (ret < 0) 1794 goto probe_error; 1795 1796 priv = pch_uart_init_port(pdev, id); 1797 if (!priv) { 1798 ret = -EBUSY; 1799 goto probe_disable_device; 1800 } 1801 pci_set_drvdata(pdev, priv); 1802 1803 return ret; 1804 1805 probe_disable_device: 1806 pci_disable_msi(pdev); 1807 pci_disable_device(pdev); 1808 probe_error: 1809 return ret; 1810 } 1811 1812 static struct pci_driver pch_uart_pci_driver = { 1813 .name = "pch_uart", 1814 .id_table = pch_uart_pci_id, 1815 .probe = pch_uart_pci_probe, 1816 .remove = __devexit_p(pch_uart_pci_remove), 1817 .suspend = pch_uart_pci_suspend, 1818 .resume = pch_uart_pci_resume, 1819 }; 1820 1821 static int __init pch_uart_module_init(void) 1822 { 1823 int ret; 1824 1825 /* register as UART driver */ 1826 ret = uart_register_driver(&pch_uart_driver); 1827 if (ret < 0) 1828 return ret; 1829 1830 /* register as PCI driver */ 1831 ret = pci_register_driver(&pch_uart_pci_driver); 1832 if (ret < 0) 1833 uart_unregister_driver(&pch_uart_driver); 1834 1835 return ret; 1836 } 1837 module_init(pch_uart_module_init); 1838 1839 static void __exit pch_uart_module_exit(void) 1840 { 1841 pci_unregister_driver(&pch_uart_pci_driver); 1842 uart_unregister_driver(&pch_uart_driver); 1843 } 1844 module_exit(pch_uart_module_exit); 1845 1846 MODULE_LICENSE("GPL v2"); 1847 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); 1848 module_param(default_baud, uint, S_IRUGO); 1849