1 /* 2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 3 * 4 *This program is free software; you can redistribute it and/or modify 5 *it under the terms of the GNU General Public License as published by 6 *the Free Software Foundation; version 2 of the License. 7 * 8 *This program is distributed in the hope that it will be useful, 9 *but WITHOUT ANY WARRANTY; without even the implied warranty of 10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 *GNU General Public License for more details. 12 * 13 *You should have received a copy of the GNU General Public License 14 *along with this program; if not, write to the Free Software 15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 16 */ 17 #include <linux/kernel.h> 18 #include <linux/serial_reg.h> 19 #include <linux/slab.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/serial_core.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/dmi.h> 28 29 #include <linux/dmaengine.h> 30 #include <linux/pch_dma.h> 31 32 enum { 33 PCH_UART_HANDLED_RX_INT_SHIFT, 34 PCH_UART_HANDLED_TX_INT_SHIFT, 35 PCH_UART_HANDLED_RX_ERR_INT_SHIFT, 36 PCH_UART_HANDLED_RX_TRG_INT_SHIFT, 37 PCH_UART_HANDLED_MS_INT_SHIFT, 38 }; 39 40 enum { 41 PCH_UART_8LINE, 42 PCH_UART_2LINE, 43 }; 44 45 #define PCH_UART_DRIVER_DEVICE "ttyPCH" 46 47 /* Set the max number of UART port 48 * Intel EG20T PCH: 4 port 49 * LAPIS Semiconductor ML7213 IOH: 3 port 50 * LAPIS Semiconductor ML7223 IOH: 2 port 51 */ 52 #define PCH_UART_NR 4 53 54 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) 55 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) 56 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ 57 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) 58 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ 59 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) 60 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) 61 62 #define PCH_UART_RBR 0x00 63 #define PCH_UART_THR 0x00 64 65 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ 66 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) 67 #define PCH_UART_IER_ERBFI 0x00000001 68 #define PCH_UART_IER_ETBEI 0x00000002 69 #define PCH_UART_IER_ELSI 0x00000004 70 #define PCH_UART_IER_EDSSI 0x00000008 71 72 #define PCH_UART_IIR_IP 0x00000001 73 #define PCH_UART_IIR_IID 0x00000006 74 #define PCH_UART_IIR_MSI 0x00000000 75 #define PCH_UART_IIR_TRI 0x00000002 76 #define PCH_UART_IIR_RRI 0x00000004 77 #define PCH_UART_IIR_REI 0x00000006 78 #define PCH_UART_IIR_TOI 0x00000008 79 #define PCH_UART_IIR_FIFO256 0x00000020 80 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 81 #define PCH_UART_IIR_FE 0x000000C0 82 83 #define PCH_UART_FCR_FIFOE 0x00000001 84 #define PCH_UART_FCR_RFR 0x00000002 85 #define PCH_UART_FCR_TFR 0x00000004 86 #define PCH_UART_FCR_DMS 0x00000008 87 #define PCH_UART_FCR_FIFO256 0x00000020 88 #define PCH_UART_FCR_RFTL 0x000000C0 89 90 #define PCH_UART_FCR_RFTL1 0x00000000 91 #define PCH_UART_FCR_RFTL64 0x00000040 92 #define PCH_UART_FCR_RFTL128 0x00000080 93 #define PCH_UART_FCR_RFTL224 0x000000C0 94 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 95 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 96 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 97 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 98 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 99 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 100 #define PCH_UART_FCR_RFTL_SHIFT 6 101 102 #define PCH_UART_LCR_WLS 0x00000003 103 #define PCH_UART_LCR_STB 0x00000004 104 #define PCH_UART_LCR_PEN 0x00000008 105 #define PCH_UART_LCR_EPS 0x00000010 106 #define PCH_UART_LCR_SP 0x00000020 107 #define PCH_UART_LCR_SB 0x00000040 108 #define PCH_UART_LCR_DLAB 0x00000080 109 #define PCH_UART_LCR_NP 0x00000000 110 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN 111 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) 112 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) 113 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ 114 PCH_UART_LCR_SP) 115 116 #define PCH_UART_LCR_5BIT 0x00000000 117 #define PCH_UART_LCR_6BIT 0x00000001 118 #define PCH_UART_LCR_7BIT 0x00000002 119 #define PCH_UART_LCR_8BIT 0x00000003 120 121 #define PCH_UART_MCR_DTR 0x00000001 122 #define PCH_UART_MCR_RTS 0x00000002 123 #define PCH_UART_MCR_OUT 0x0000000C 124 #define PCH_UART_MCR_LOOP 0x00000010 125 #define PCH_UART_MCR_AFE 0x00000020 126 127 #define PCH_UART_LSR_DR 0x00000001 128 #define PCH_UART_LSR_ERR (1<<7) 129 130 #define PCH_UART_MSR_DCTS 0x00000001 131 #define PCH_UART_MSR_DDSR 0x00000002 132 #define PCH_UART_MSR_TERI 0x00000004 133 #define PCH_UART_MSR_DDCD 0x00000008 134 #define PCH_UART_MSR_CTS 0x00000010 135 #define PCH_UART_MSR_DSR 0x00000020 136 #define PCH_UART_MSR_RI 0x00000040 137 #define PCH_UART_MSR_DCD 0x00000080 138 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ 139 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) 140 141 #define PCH_UART_DLL 0x00 142 #define PCH_UART_DLM 0x01 143 144 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) 145 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) 146 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) 147 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) 148 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) 149 150 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) 151 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) 152 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) 153 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) 154 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) 155 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) 156 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) 157 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) 158 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) 159 #define PCH_UART_HAL_STB1 0 160 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) 161 162 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) 163 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) 164 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ 165 PCH_UART_HAL_CLR_RX_FIFO) 166 167 #define PCH_UART_HAL_DMA_MODE0 0 168 #define PCH_UART_HAL_FIFO_DIS 0 169 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) 170 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ 171 PCH_UART_FCR_FIFO256) 172 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) 173 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) 174 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) 175 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) 176 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) 177 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) 178 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) 179 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) 180 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) 181 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) 182 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) 183 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) 184 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) 185 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) 186 187 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) 188 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) 189 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) 190 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) 191 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) 192 193 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) 194 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) 195 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) 196 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) 197 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) 198 199 #define PCI_VENDOR_ID_ROHM 0x10DB 200 201 struct pch_uart_buffer { 202 unsigned char *buf; 203 int size; 204 }; 205 206 struct eg20t_port { 207 struct uart_port port; 208 int port_type; 209 void __iomem *membase; 210 resource_size_t mapbase; 211 unsigned int iobase; 212 struct pci_dev *pdev; 213 int fifo_size; 214 int base_baud; 215 int start_tx; 216 int start_rx; 217 int tx_empty; 218 int int_dis_flag; 219 int trigger; 220 int trigger_level; 221 struct pch_uart_buffer rxbuf; 222 unsigned int dmsr; 223 unsigned int fcr; 224 unsigned int mcr; 225 unsigned int use_dma; 226 unsigned int use_dma_flag; 227 struct dma_async_tx_descriptor *desc_tx; 228 struct dma_async_tx_descriptor *desc_rx; 229 struct pch_dma_slave param_tx; 230 struct pch_dma_slave param_rx; 231 struct dma_chan *chan_tx; 232 struct dma_chan *chan_rx; 233 struct scatterlist *sg_tx_p; 234 int nent; 235 struct scatterlist sg_rx; 236 int tx_dma_use; 237 void *rx_buf_virt; 238 dma_addr_t rx_buf_dma; 239 }; 240 241 /** 242 * struct pch_uart_driver_data - private data structure for UART-DMA 243 * @port_type: The number of DMA channel 244 * @line_no: UART port line number (0, 1, 2...) 245 */ 246 struct pch_uart_driver_data { 247 int port_type; 248 int line_no; 249 }; 250 251 enum pch_uart_num_t { 252 pch_et20t_uart0 = 0, 253 pch_et20t_uart1, 254 pch_et20t_uart2, 255 pch_et20t_uart3, 256 pch_ml7213_uart0, 257 pch_ml7213_uart1, 258 pch_ml7213_uart2, 259 pch_ml7223_uart0, 260 pch_ml7223_uart1, 261 pch_ml7831_uart0, 262 pch_ml7831_uart1, 263 }; 264 265 static struct pch_uart_driver_data drv_dat[] = { 266 [pch_et20t_uart0] = {PCH_UART_8LINE, 0}, 267 [pch_et20t_uart1] = {PCH_UART_2LINE, 1}, 268 [pch_et20t_uart2] = {PCH_UART_2LINE, 2}, 269 [pch_et20t_uart3] = {PCH_UART_2LINE, 3}, 270 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0}, 271 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1}, 272 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2}, 273 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0}, 274 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1}, 275 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0}, 276 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1}, 277 }; 278 279 static unsigned int default_baud = 9600; 280 static const int trigger_level_256[4] = { 1, 64, 128, 224 }; 281 static const int trigger_level_64[4] = { 1, 16, 32, 56 }; 282 static const int trigger_level_16[4] = { 1, 4, 8, 14 }; 283 static const int trigger_level_1[4] = { 1, 1, 1, 1 }; 284 285 static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize, 286 int base_baud) 287 { 288 struct eg20t_port *priv = pci_get_drvdata(pdev); 289 290 priv->trigger_level = 1; 291 priv->fcr = 0; 292 } 293 294 static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base) 295 { 296 unsigned int msr = ioread8(base + UART_MSR); 297 priv->dmsr |= msr & PCH_UART_MSR_DELTA; 298 299 return msr; 300 } 301 302 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, 303 unsigned int flag) 304 { 305 u8 ier = ioread8(priv->membase + UART_IER); 306 ier |= flag & PCH_UART_IER_MASK; 307 iowrite8(ier, priv->membase + UART_IER); 308 } 309 310 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, 311 unsigned int flag) 312 { 313 u8 ier = ioread8(priv->membase + UART_IER); 314 ier &= ~(flag & PCH_UART_IER_MASK); 315 iowrite8(ier, priv->membase + UART_IER); 316 } 317 318 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud, 319 unsigned int parity, unsigned int bits, 320 unsigned int stb) 321 { 322 unsigned int dll, dlm, lcr; 323 int div; 324 325 div = DIV_ROUND_CLOSEST(priv->base_baud / 16, baud); 326 if (div < 0 || USHRT_MAX <= div) { 327 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); 328 return -EINVAL; 329 } 330 331 dll = (unsigned int)div & 0x00FFU; 332 dlm = ((unsigned int)div >> 8) & 0x00FFU; 333 334 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { 335 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); 336 return -EINVAL; 337 } 338 339 if (bits & ~PCH_UART_LCR_WLS) { 340 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); 341 return -EINVAL; 342 } 343 344 if (stb & ~PCH_UART_LCR_STB) { 345 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); 346 return -EINVAL; 347 } 348 349 lcr = parity; 350 lcr |= bits; 351 lcr |= stb; 352 353 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n", 354 __func__, baud, div, lcr, jiffies); 355 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 356 iowrite8(dll, priv->membase + PCH_UART_DLL); 357 iowrite8(dlm, priv->membase + PCH_UART_DLM); 358 iowrite8(lcr, priv->membase + UART_LCR); 359 360 return 0; 361 } 362 363 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, 364 unsigned int flag) 365 { 366 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { 367 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", 368 __func__, flag); 369 return -EINVAL; 370 } 371 372 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); 373 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, 374 priv->membase + UART_FCR); 375 iowrite8(priv->fcr, priv->membase + UART_FCR); 376 377 return 0; 378 } 379 380 static int pch_uart_hal_set_fifo(struct eg20t_port *priv, 381 unsigned int dmamode, 382 unsigned int fifo_size, unsigned int trigger) 383 { 384 u8 fcr; 385 386 if (dmamode & ~PCH_UART_FCR_DMS) { 387 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", 388 __func__, dmamode); 389 return -EINVAL; 390 } 391 392 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { 393 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", 394 __func__, fifo_size); 395 return -EINVAL; 396 } 397 398 if (trigger & ~PCH_UART_FCR_RFTL) { 399 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", 400 __func__, trigger); 401 return -EINVAL; 402 } 403 404 switch (priv->fifo_size) { 405 case 256: 406 priv->trigger_level = 407 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 408 break; 409 case 64: 410 priv->trigger_level = 411 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 412 break; 413 case 16: 414 priv->trigger_level = 415 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 416 break; 417 default: 418 priv->trigger_level = 419 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 420 break; 421 } 422 fcr = 423 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; 424 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); 425 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, 426 priv->membase + UART_FCR); 427 iowrite8(fcr, priv->membase + UART_FCR); 428 priv->fcr = fcr; 429 430 return 0; 431 } 432 433 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) 434 { 435 priv->dmsr = 0; 436 return get_msr(priv, priv->membase); 437 } 438 439 static void pch_uart_hal_write(struct eg20t_port *priv, 440 const unsigned char *buf, int tx_size) 441 { 442 int i; 443 unsigned int thr; 444 445 for (i = 0; i < tx_size;) { 446 thr = buf[i++]; 447 iowrite8(thr, priv->membase + PCH_UART_THR); 448 } 449 } 450 451 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, 452 int rx_size) 453 { 454 int i; 455 u8 rbr, lsr; 456 457 lsr = ioread8(priv->membase + UART_LSR); 458 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); 459 i < rx_size && lsr & UART_LSR_DR; 460 lsr = ioread8(priv->membase + UART_LSR)) { 461 rbr = ioread8(priv->membase + PCH_UART_RBR); 462 buf[i++] = rbr; 463 } 464 return i; 465 } 466 467 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv) 468 { 469 unsigned int iir; 470 int ret; 471 472 iir = ioread8(priv->membase + UART_IIR); 473 ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP)); 474 return ret; 475 } 476 477 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) 478 { 479 return ioread8(priv->membase + UART_LSR); 480 } 481 482 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) 483 { 484 unsigned int lcr; 485 486 lcr = ioread8(priv->membase + UART_LCR); 487 if (on) 488 lcr |= PCH_UART_LCR_SB; 489 else 490 lcr &= ~PCH_UART_LCR_SB; 491 492 iowrite8(lcr, priv->membase + UART_LCR); 493 } 494 495 static int push_rx(struct eg20t_port *priv, const unsigned char *buf, 496 int size) 497 { 498 struct uart_port *port; 499 struct tty_struct *tty; 500 501 port = &priv->port; 502 tty = tty_port_tty_get(&port->state->port); 503 if (!tty) { 504 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 505 return -EBUSY; 506 } 507 508 tty_insert_flip_string(tty, buf, size); 509 tty_flip_buffer_push(tty); 510 tty_kref_put(tty); 511 512 return 0; 513 } 514 515 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) 516 { 517 int ret; 518 struct uart_port *port = &priv->port; 519 520 if (port->x_char) { 521 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n", 522 __func__, port->x_char, jiffies); 523 buf[0] = port->x_char; 524 port->x_char = 0; 525 ret = 1; 526 } else { 527 ret = 0; 528 } 529 530 return ret; 531 } 532 533 static int dma_push_rx(struct eg20t_port *priv, int size) 534 { 535 struct tty_struct *tty; 536 int room; 537 struct uart_port *port = &priv->port; 538 539 port = &priv->port; 540 tty = tty_port_tty_get(&port->state->port); 541 if (!tty) { 542 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 543 return 0; 544 } 545 546 room = tty_buffer_request_room(tty, size); 547 548 if (room < size) 549 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 550 size - room); 551 if (!room) 552 return room; 553 554 tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size); 555 556 port->icount.rx += room; 557 tty_kref_put(tty); 558 559 return room; 560 } 561 562 static void pch_free_dma(struct uart_port *port) 563 { 564 struct eg20t_port *priv; 565 priv = container_of(port, struct eg20t_port, port); 566 567 if (priv->chan_tx) { 568 dma_release_channel(priv->chan_tx); 569 priv->chan_tx = NULL; 570 } 571 if (priv->chan_rx) { 572 dma_release_channel(priv->chan_rx); 573 priv->chan_rx = NULL; 574 } 575 if (sg_dma_address(&priv->sg_rx)) 576 dma_free_coherent(port->dev, port->fifosize, 577 sg_virt(&priv->sg_rx), 578 sg_dma_address(&priv->sg_rx)); 579 580 return; 581 } 582 583 static bool filter(struct dma_chan *chan, void *slave) 584 { 585 struct pch_dma_slave *param = slave; 586 587 if ((chan->chan_id == param->chan_id) && (param->dma_dev == 588 chan->device->dev)) { 589 chan->private = param; 590 return true; 591 } else { 592 return false; 593 } 594 } 595 596 static void pch_request_dma(struct uart_port *port) 597 { 598 dma_cap_mask_t mask; 599 struct dma_chan *chan; 600 struct pci_dev *dma_dev; 601 struct pch_dma_slave *param; 602 struct eg20t_port *priv = 603 container_of(port, struct eg20t_port, port); 604 dma_cap_zero(mask); 605 dma_cap_set(DMA_SLAVE, mask); 606 607 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number, 608 PCI_DEVFN(0xa, 0)); /* Get DMA's dev 609 information */ 610 /* Set Tx DMA */ 611 param = &priv->param_tx; 612 param->dma_dev = &dma_dev->dev; 613 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ 614 615 param->tx_reg = port->mapbase + UART_TX; 616 chan = dma_request_channel(mask, filter, param); 617 if (!chan) { 618 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", 619 __func__); 620 return; 621 } 622 priv->chan_tx = chan; 623 624 /* Set Rx DMA */ 625 param = &priv->param_rx; 626 param->dma_dev = &dma_dev->dev; 627 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ 628 629 param->rx_reg = port->mapbase + UART_RX; 630 chan = dma_request_channel(mask, filter, param); 631 if (!chan) { 632 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", 633 __func__); 634 dma_release_channel(priv->chan_tx); 635 priv->chan_tx = NULL; 636 return; 637 } 638 639 /* Get Consistent memory for DMA */ 640 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, 641 &priv->rx_buf_dma, GFP_KERNEL); 642 priv->chan_rx = chan; 643 } 644 645 static void pch_dma_rx_complete(void *arg) 646 { 647 struct eg20t_port *priv = arg; 648 struct uart_port *port = &priv->port; 649 struct tty_struct *tty = tty_port_tty_get(&port->state->port); 650 int count; 651 652 if (!tty) { 653 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 654 return; 655 } 656 657 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); 658 count = dma_push_rx(priv, priv->trigger_level); 659 if (count) 660 tty_flip_buffer_push(tty); 661 tty_kref_put(tty); 662 async_tx_ack(priv->desc_rx); 663 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT); 664 } 665 666 static void pch_dma_tx_complete(void *arg) 667 { 668 struct eg20t_port *priv = arg; 669 struct uart_port *port = &priv->port; 670 struct circ_buf *xmit = &port->state->xmit; 671 struct scatterlist *sg = priv->sg_tx_p; 672 int i; 673 674 for (i = 0; i < priv->nent; i++, sg++) { 675 xmit->tail += sg_dma_len(sg); 676 port->icount.tx += sg_dma_len(sg); 677 } 678 xmit->tail &= UART_XMIT_SIZE - 1; 679 async_tx_ack(priv->desc_tx); 680 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE); 681 priv->tx_dma_use = 0; 682 priv->nent = 0; 683 kfree(priv->sg_tx_p); 684 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 685 } 686 687 static int pop_tx(struct eg20t_port *priv, int size) 688 { 689 int count = 0; 690 struct uart_port *port = &priv->port; 691 struct circ_buf *xmit = &port->state->xmit; 692 693 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size) 694 goto pop_tx_end; 695 696 do { 697 int cnt_to_end = 698 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 699 int sz = min(size - count, cnt_to_end); 700 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz); 701 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1); 702 count += sz; 703 } while (!uart_circ_empty(xmit) && count < size); 704 705 pop_tx_end: 706 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n", 707 count, size - count, jiffies); 708 709 return count; 710 } 711 712 static int handle_rx_to(struct eg20t_port *priv) 713 { 714 struct pch_uart_buffer *buf; 715 int rx_size; 716 int ret; 717 if (!priv->start_rx) { 718 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT); 719 return 0; 720 } 721 buf = &priv->rxbuf; 722 do { 723 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); 724 ret = push_rx(priv, buf->buf, rx_size); 725 if (ret) 726 return 0; 727 } while (rx_size == buf->size); 728 729 return PCH_UART_HANDLED_RX_INT; 730 } 731 732 static int handle_rx(struct eg20t_port *priv) 733 { 734 return handle_rx_to(priv); 735 } 736 737 static int dma_handle_rx(struct eg20t_port *priv) 738 { 739 struct uart_port *port = &priv->port; 740 struct dma_async_tx_descriptor *desc; 741 struct scatterlist *sg; 742 743 priv = container_of(port, struct eg20t_port, port); 744 sg = &priv->sg_rx; 745 746 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ 747 748 sg_dma_len(sg) = priv->trigger_level; 749 750 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), 751 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt & 752 ~PAGE_MASK); 753 754 sg_dma_address(sg) = priv->rx_buf_dma; 755 756 desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx, 757 sg, 1, DMA_FROM_DEVICE, 758 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 759 760 if (!desc) 761 return 0; 762 763 priv->desc_rx = desc; 764 desc->callback = pch_dma_rx_complete; 765 desc->callback_param = priv; 766 desc->tx_submit(desc); 767 dma_async_issue_pending(priv->chan_rx); 768 769 return PCH_UART_HANDLED_RX_INT; 770 } 771 772 static unsigned int handle_tx(struct eg20t_port *priv) 773 { 774 struct uart_port *port = &priv->port; 775 struct circ_buf *xmit = &port->state->xmit; 776 int fifo_size; 777 int tx_size; 778 int size; 779 int tx_empty; 780 781 if (!priv->start_tx) { 782 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 783 __func__, jiffies); 784 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 785 priv->tx_empty = 1; 786 return 0; 787 } 788 789 fifo_size = max(priv->fifo_size, 1); 790 tx_empty = 1; 791 if (pop_tx_x(priv, xmit->buf)) { 792 pch_uart_hal_write(priv, xmit->buf, 1); 793 port->icount.tx++; 794 tx_empty = 0; 795 fifo_size--; 796 } 797 size = min(xmit->head - xmit->tail, fifo_size); 798 if (size < 0) 799 size = fifo_size; 800 801 tx_size = pop_tx(priv, size); 802 if (tx_size > 0) { 803 port->icount.tx += tx_size; 804 tx_empty = 0; 805 } 806 807 priv->tx_empty = tx_empty; 808 809 if (tx_empty) { 810 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 811 uart_write_wakeup(port); 812 } 813 814 return PCH_UART_HANDLED_TX_INT; 815 } 816 817 static unsigned int dma_handle_tx(struct eg20t_port *priv) 818 { 819 struct uart_port *port = &priv->port; 820 struct circ_buf *xmit = &port->state->xmit; 821 struct scatterlist *sg; 822 int nent; 823 int fifo_size; 824 int tx_empty; 825 struct dma_async_tx_descriptor *desc; 826 int num; 827 int i; 828 int bytes; 829 int size; 830 int rem; 831 832 if (!priv->start_tx) { 833 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 834 __func__, jiffies); 835 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 836 priv->tx_empty = 1; 837 return 0; 838 } 839 840 if (priv->tx_dma_use) { 841 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", 842 __func__, jiffies); 843 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 844 priv->tx_empty = 1; 845 return 0; 846 } 847 848 fifo_size = max(priv->fifo_size, 1); 849 tx_empty = 1; 850 if (pop_tx_x(priv, xmit->buf)) { 851 pch_uart_hal_write(priv, xmit->buf, 1); 852 port->icount.tx++; 853 tx_empty = 0; 854 fifo_size--; 855 } 856 857 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail, 858 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head, 859 xmit->tail, UART_XMIT_SIZE)); 860 if (!bytes) { 861 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); 862 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 863 uart_write_wakeup(port); 864 return 0; 865 } 866 867 if (bytes > fifo_size) { 868 num = bytes / fifo_size + 1; 869 size = fifo_size; 870 rem = bytes % fifo_size; 871 } else { 872 num = 1; 873 size = bytes; 874 rem = bytes; 875 } 876 877 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", 878 __func__, num, size, rem); 879 880 priv->tx_dma_use = 1; 881 882 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); 883 884 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ 885 sg = priv->sg_tx_p; 886 887 for (i = 0; i < num; i++, sg++) { 888 if (i == (num - 1)) 889 sg_set_page(sg, virt_to_page(xmit->buf), 890 rem, fifo_size * i); 891 else 892 sg_set_page(sg, virt_to_page(xmit->buf), 893 size, fifo_size * i); 894 } 895 896 sg = priv->sg_tx_p; 897 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); 898 if (!nent) { 899 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); 900 return 0; 901 } 902 priv->nent = nent; 903 904 for (i = 0; i < nent; i++, sg++) { 905 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + 906 fifo_size * i; 907 sg_dma_address(sg) = (sg_dma_address(sg) & 908 ~(UART_XMIT_SIZE - 1)) + sg->offset; 909 if (i == (nent - 1)) 910 sg_dma_len(sg) = rem; 911 else 912 sg_dma_len(sg) = size; 913 } 914 915 desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx, 916 priv->sg_tx_p, nent, DMA_TO_DEVICE, 917 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 918 if (!desc) { 919 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n", 920 __func__); 921 return 0; 922 } 923 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); 924 priv->desc_tx = desc; 925 desc->callback = pch_dma_tx_complete; 926 desc->callback_param = priv; 927 928 desc->tx_submit(desc); 929 930 dma_async_issue_pending(priv->chan_tx); 931 932 return PCH_UART_HANDLED_TX_INT; 933 } 934 935 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) 936 { 937 u8 fcr = ioread8(priv->membase + UART_FCR); 938 939 /* Reset FIFO */ 940 fcr |= UART_FCR_CLEAR_RCVR; 941 iowrite8(fcr, priv->membase + UART_FCR); 942 943 if (lsr & PCH_UART_LSR_ERR) 944 dev_err(&priv->pdev->dev, "Error data in FIFO\n"); 945 946 if (lsr & UART_LSR_FE) 947 dev_err(&priv->pdev->dev, "Framing Error\n"); 948 949 if (lsr & UART_LSR_PE) 950 dev_err(&priv->pdev->dev, "Parity Error\n"); 951 952 if (lsr & UART_LSR_OE) 953 dev_err(&priv->pdev->dev, "Overrun Error\n"); 954 } 955 956 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) 957 { 958 struct eg20t_port *priv = dev_id; 959 unsigned int handled; 960 u8 lsr; 961 int ret = 0; 962 unsigned int iid; 963 unsigned long flags; 964 965 spin_lock_irqsave(&priv->port.lock, flags); 966 handled = 0; 967 while ((iid = pch_uart_hal_get_iid(priv)) > 1) { 968 switch (iid) { 969 case PCH_UART_IID_RLS: /* Receiver Line Status */ 970 lsr = pch_uart_hal_get_line_status(priv); 971 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | 972 UART_LSR_PE | UART_LSR_OE)) { 973 pch_uart_err_ir(priv, lsr); 974 ret = PCH_UART_HANDLED_RX_ERR_INT; 975 } 976 break; 977 case PCH_UART_IID_RDR: /* Received Data Ready */ 978 if (priv->use_dma) { 979 pch_uart_hal_disable_interrupt(priv, 980 PCH_UART_HAL_RX_INT); 981 ret = dma_handle_rx(priv); 982 if (!ret) 983 pch_uart_hal_enable_interrupt(priv, 984 PCH_UART_HAL_RX_INT); 985 } else { 986 ret = handle_rx(priv); 987 } 988 break; 989 case PCH_UART_IID_RDR_TO: /* Received Data Ready 990 (FIFO Timeout) */ 991 ret = handle_rx_to(priv); 992 break; 993 case PCH_UART_IID_THRE: /* Transmitter Holding Register 994 Empty */ 995 if (priv->use_dma) 996 ret = dma_handle_tx(priv); 997 else 998 ret = handle_tx(priv); 999 break; 1000 case PCH_UART_IID_MS: /* Modem Status */ 1001 ret = PCH_UART_HANDLED_MS_INT; 1002 break; 1003 default: /* Never junp to this label */ 1004 dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__, 1005 iid, jiffies); 1006 ret = -1; 1007 break; 1008 } 1009 handled |= (unsigned int)ret; 1010 } 1011 if (handled == 0 && iid <= 1) { 1012 if (priv->int_dis_flag) 1013 priv->int_dis_flag = 0; 1014 } 1015 1016 spin_unlock_irqrestore(&priv->port.lock, flags); 1017 return IRQ_RETVAL(handled); 1018 } 1019 1020 /* This function tests whether the transmitter fifo and shifter for the port 1021 described by 'port' is empty. */ 1022 static unsigned int pch_uart_tx_empty(struct uart_port *port) 1023 { 1024 struct eg20t_port *priv; 1025 int ret; 1026 priv = container_of(port, struct eg20t_port, port); 1027 if (priv->tx_empty) 1028 ret = TIOCSER_TEMT; 1029 else 1030 ret = 0; 1031 1032 return ret; 1033 } 1034 1035 /* Returns the current state of modem control inputs. */ 1036 static unsigned int pch_uart_get_mctrl(struct uart_port *port) 1037 { 1038 struct eg20t_port *priv; 1039 u8 modem; 1040 unsigned int ret = 0; 1041 1042 priv = container_of(port, struct eg20t_port, port); 1043 modem = pch_uart_hal_get_modem(priv); 1044 1045 if (modem & UART_MSR_DCD) 1046 ret |= TIOCM_CAR; 1047 1048 if (modem & UART_MSR_RI) 1049 ret |= TIOCM_RNG; 1050 1051 if (modem & UART_MSR_DSR) 1052 ret |= TIOCM_DSR; 1053 1054 if (modem & UART_MSR_CTS) 1055 ret |= TIOCM_CTS; 1056 1057 return ret; 1058 } 1059 1060 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1061 { 1062 u32 mcr = 0; 1063 struct eg20t_port *priv = container_of(port, struct eg20t_port, port); 1064 1065 if (mctrl & TIOCM_DTR) 1066 mcr |= UART_MCR_DTR; 1067 if (mctrl & TIOCM_RTS) 1068 mcr |= UART_MCR_RTS; 1069 if (mctrl & TIOCM_LOOP) 1070 mcr |= UART_MCR_LOOP; 1071 1072 if (priv->mcr & UART_MCR_AFE) 1073 mcr |= UART_MCR_AFE; 1074 1075 if (mctrl) 1076 iowrite8(mcr, priv->membase + UART_MCR); 1077 } 1078 1079 static void pch_uart_stop_tx(struct uart_port *port) 1080 { 1081 struct eg20t_port *priv; 1082 priv = container_of(port, struct eg20t_port, port); 1083 priv->start_tx = 0; 1084 priv->tx_dma_use = 0; 1085 } 1086 1087 static void pch_uart_start_tx(struct uart_port *port) 1088 { 1089 struct eg20t_port *priv; 1090 1091 priv = container_of(port, struct eg20t_port, port); 1092 1093 if (priv->use_dma) { 1094 if (priv->tx_dma_use) { 1095 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", 1096 __func__); 1097 return; 1098 } 1099 } 1100 1101 priv->start_tx = 1; 1102 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 1103 } 1104 1105 static void pch_uart_stop_rx(struct uart_port *port) 1106 { 1107 struct eg20t_port *priv; 1108 priv = container_of(port, struct eg20t_port, port); 1109 priv->start_rx = 0; 1110 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT); 1111 priv->int_dis_flag = 1; 1112 } 1113 1114 /* Enable the modem status interrupts. */ 1115 static void pch_uart_enable_ms(struct uart_port *port) 1116 { 1117 struct eg20t_port *priv; 1118 priv = container_of(port, struct eg20t_port, port); 1119 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); 1120 } 1121 1122 /* Control the transmission of a break signal. */ 1123 static void pch_uart_break_ctl(struct uart_port *port, int ctl) 1124 { 1125 struct eg20t_port *priv; 1126 unsigned long flags; 1127 1128 priv = container_of(port, struct eg20t_port, port); 1129 spin_lock_irqsave(&port->lock, flags); 1130 pch_uart_hal_set_break(priv, ctl); 1131 spin_unlock_irqrestore(&port->lock, flags); 1132 } 1133 1134 /* Grab any interrupt resources and initialise any low level driver state. */ 1135 static int pch_uart_startup(struct uart_port *port) 1136 { 1137 struct eg20t_port *priv; 1138 int ret; 1139 int fifo_size; 1140 int trigger_level; 1141 1142 priv = container_of(port, struct eg20t_port, port); 1143 priv->tx_empty = 1; 1144 1145 if (port->uartclk) 1146 priv->base_baud = port->uartclk; 1147 else 1148 port->uartclk = priv->base_baud; 1149 1150 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1151 ret = pch_uart_hal_set_line(priv, default_baud, 1152 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, 1153 PCH_UART_HAL_STB1); 1154 if (ret) 1155 return ret; 1156 1157 switch (priv->fifo_size) { 1158 case 256: 1159 fifo_size = PCH_UART_HAL_FIFO256; 1160 break; 1161 case 64: 1162 fifo_size = PCH_UART_HAL_FIFO64; 1163 break; 1164 case 16: 1165 fifo_size = PCH_UART_HAL_FIFO16; 1166 case 1: 1167 default: 1168 fifo_size = PCH_UART_HAL_FIFO_DIS; 1169 break; 1170 } 1171 1172 switch (priv->trigger) { 1173 case PCH_UART_HAL_TRIGGER1: 1174 trigger_level = 1; 1175 break; 1176 case PCH_UART_HAL_TRIGGER_L: 1177 trigger_level = priv->fifo_size / 4; 1178 break; 1179 case PCH_UART_HAL_TRIGGER_M: 1180 trigger_level = priv->fifo_size / 2; 1181 break; 1182 case PCH_UART_HAL_TRIGGER_H: 1183 default: 1184 trigger_level = priv->fifo_size - (priv->fifo_size / 8); 1185 break; 1186 } 1187 1188 priv->trigger_level = trigger_level; 1189 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1190 fifo_size, priv->trigger); 1191 if (ret < 0) 1192 return ret; 1193 1194 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, 1195 KBUILD_MODNAME, priv); 1196 if (ret < 0) 1197 return ret; 1198 1199 if (priv->use_dma) 1200 pch_request_dma(port); 1201 1202 priv->start_rx = 1; 1203 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT); 1204 uart_update_timeout(port, CS8, default_baud); 1205 1206 return 0; 1207 } 1208 1209 static void pch_uart_shutdown(struct uart_port *port) 1210 { 1211 struct eg20t_port *priv; 1212 int ret; 1213 1214 priv = container_of(port, struct eg20t_port, port); 1215 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1216 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); 1217 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1218 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); 1219 if (ret) 1220 dev_err(priv->port.dev, 1221 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); 1222 1223 pch_free_dma(port); 1224 1225 free_irq(priv->port.irq, priv); 1226 } 1227 1228 /* Change the port parameters, including word length, parity, stop 1229 *bits. Update read_status_mask and ignore_status_mask to indicate 1230 *the types of events we are interested in receiving. */ 1231 static void pch_uart_set_termios(struct uart_port *port, 1232 struct ktermios *termios, struct ktermios *old) 1233 { 1234 int baud; 1235 int rtn; 1236 unsigned int parity, bits, stb; 1237 struct eg20t_port *priv; 1238 unsigned long flags; 1239 1240 priv = container_of(port, struct eg20t_port, port); 1241 switch (termios->c_cflag & CSIZE) { 1242 case CS5: 1243 bits = PCH_UART_HAL_5BIT; 1244 break; 1245 case CS6: 1246 bits = PCH_UART_HAL_6BIT; 1247 break; 1248 case CS7: 1249 bits = PCH_UART_HAL_7BIT; 1250 break; 1251 default: /* CS8 */ 1252 bits = PCH_UART_HAL_8BIT; 1253 break; 1254 } 1255 if (termios->c_cflag & CSTOPB) 1256 stb = PCH_UART_HAL_STB2; 1257 else 1258 stb = PCH_UART_HAL_STB1; 1259 1260 if (termios->c_cflag & PARENB) { 1261 if (!(termios->c_cflag & PARODD)) 1262 parity = PCH_UART_HAL_PARITY_ODD; 1263 else 1264 parity = PCH_UART_HAL_PARITY_EVEN; 1265 1266 } else { 1267 parity = PCH_UART_HAL_PARITY_NONE; 1268 } 1269 1270 /* Only UART0 has auto hardware flow function */ 1271 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) 1272 priv->mcr |= UART_MCR_AFE; 1273 else 1274 priv->mcr &= ~UART_MCR_AFE; 1275 1276 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 1277 1278 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1279 1280 spin_lock_irqsave(&port->lock, flags); 1281 1282 uart_update_timeout(port, termios->c_cflag, baud); 1283 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); 1284 if (rtn) 1285 goto out; 1286 1287 pch_uart_set_mctrl(&priv->port, priv->port.mctrl); 1288 /* Don't rewrite B0 */ 1289 if (tty_termios_baud_rate(termios)) 1290 tty_termios_encode_baud_rate(termios, baud, baud); 1291 1292 out: 1293 spin_unlock_irqrestore(&port->lock, flags); 1294 } 1295 1296 static const char *pch_uart_type(struct uart_port *port) 1297 { 1298 return KBUILD_MODNAME; 1299 } 1300 1301 static void pch_uart_release_port(struct uart_port *port) 1302 { 1303 struct eg20t_port *priv; 1304 1305 priv = container_of(port, struct eg20t_port, port); 1306 pci_iounmap(priv->pdev, priv->membase); 1307 pci_release_regions(priv->pdev); 1308 } 1309 1310 static int pch_uart_request_port(struct uart_port *port) 1311 { 1312 struct eg20t_port *priv; 1313 int ret; 1314 void __iomem *membase; 1315 1316 priv = container_of(port, struct eg20t_port, port); 1317 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); 1318 if (ret < 0) 1319 return -EBUSY; 1320 1321 membase = pci_iomap(priv->pdev, 1, 0); 1322 if (!membase) { 1323 pci_release_regions(priv->pdev); 1324 return -EBUSY; 1325 } 1326 priv->membase = port->membase = membase; 1327 1328 return 0; 1329 } 1330 1331 static void pch_uart_config_port(struct uart_port *port, int type) 1332 { 1333 struct eg20t_port *priv; 1334 1335 priv = container_of(port, struct eg20t_port, port); 1336 if (type & UART_CONFIG_TYPE) { 1337 port->type = priv->port_type; 1338 pch_uart_request_port(port); 1339 } 1340 } 1341 1342 static int pch_uart_verify_port(struct uart_port *port, 1343 struct serial_struct *serinfo) 1344 { 1345 struct eg20t_port *priv; 1346 1347 priv = container_of(port, struct eg20t_port, port); 1348 if (serinfo->flags & UPF_LOW_LATENCY) { 1349 dev_info(priv->port.dev, 1350 "PCH UART : Use PIO Mode (without DMA)\n"); 1351 priv->use_dma = 0; 1352 serinfo->flags &= ~UPF_LOW_LATENCY; 1353 } else { 1354 #ifndef CONFIG_PCH_DMA 1355 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", 1356 __func__); 1357 return -EOPNOTSUPP; 1358 #endif 1359 priv->use_dma = 1; 1360 priv->use_dma_flag = 1; 1361 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n"); 1362 } 1363 1364 return 0; 1365 } 1366 1367 static struct uart_ops pch_uart_ops = { 1368 .tx_empty = pch_uart_tx_empty, 1369 .set_mctrl = pch_uart_set_mctrl, 1370 .get_mctrl = pch_uart_get_mctrl, 1371 .stop_tx = pch_uart_stop_tx, 1372 .start_tx = pch_uart_start_tx, 1373 .stop_rx = pch_uart_stop_rx, 1374 .enable_ms = pch_uart_enable_ms, 1375 .break_ctl = pch_uart_break_ctl, 1376 .startup = pch_uart_startup, 1377 .shutdown = pch_uart_shutdown, 1378 .set_termios = pch_uart_set_termios, 1379 /* .pm = pch_uart_pm, Not supported yet */ 1380 /* .set_wake = pch_uart_set_wake, Not supported yet */ 1381 .type = pch_uart_type, 1382 .release_port = pch_uart_release_port, 1383 .request_port = pch_uart_request_port, 1384 .config_port = pch_uart_config_port, 1385 .verify_port = pch_uart_verify_port 1386 }; 1387 1388 static struct uart_driver pch_uart_driver = { 1389 .owner = THIS_MODULE, 1390 .driver_name = KBUILD_MODNAME, 1391 .dev_name = PCH_UART_DRIVER_DEVICE, 1392 .major = 0, 1393 .minor = 0, 1394 .nr = PCH_UART_NR, 1395 }; 1396 1397 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, 1398 const struct pci_device_id *id) 1399 { 1400 struct eg20t_port *priv; 1401 int ret; 1402 unsigned int iobase; 1403 unsigned int mapbase; 1404 unsigned char *rxbuf; 1405 int fifosize, base_baud; 1406 int port_type; 1407 struct pch_uart_driver_data *board; 1408 const char *board_name; 1409 1410 board = &drv_dat[id->driver_data]; 1411 port_type = board->port_type; 1412 1413 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); 1414 if (priv == NULL) 1415 goto init_port_alloc_err; 1416 1417 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); 1418 if (!rxbuf) 1419 goto init_port_free_txbuf; 1420 1421 base_baud = 1843200; /* 1.8432MHz */ 1422 1423 /* quirk for CM-iTC board */ 1424 board_name = dmi_get_system_info(DMI_BOARD_NAME); 1425 if (board_name && strstr(board_name, "CM-iTC")) 1426 base_baud = 192000000; /* 192.0MHz */ 1427 1428 switch (port_type) { 1429 case PORT_UNKNOWN: 1430 fifosize = 256; /* EG20T/ML7213: UART0 */ 1431 break; 1432 case PORT_8250: 1433 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ 1434 break; 1435 default: 1436 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); 1437 goto init_port_hal_free; 1438 } 1439 1440 pci_enable_msi(pdev); 1441 1442 iobase = pci_resource_start(pdev, 0); 1443 mapbase = pci_resource_start(pdev, 1); 1444 priv->mapbase = mapbase; 1445 priv->iobase = iobase; 1446 priv->pdev = pdev; 1447 priv->tx_empty = 1; 1448 priv->rxbuf.buf = rxbuf; 1449 priv->rxbuf.size = PAGE_SIZE; 1450 1451 priv->fifo_size = fifosize; 1452 priv->base_baud = base_baud; 1453 priv->port_type = PORT_MAX_8250 + port_type + 1; 1454 priv->port.dev = &pdev->dev; 1455 priv->port.iobase = iobase; 1456 priv->port.membase = NULL; 1457 priv->port.mapbase = mapbase; 1458 priv->port.irq = pdev->irq; 1459 priv->port.iotype = UPIO_PORT; 1460 priv->port.ops = &pch_uart_ops; 1461 priv->port.flags = UPF_BOOT_AUTOCONF; 1462 priv->port.fifosize = fifosize; 1463 priv->port.line = board->line_no; 1464 priv->trigger = PCH_UART_HAL_TRIGGER_M; 1465 1466 spin_lock_init(&priv->port.lock); 1467 1468 pci_set_drvdata(pdev, priv); 1469 pch_uart_hal_request(pdev, fifosize, base_baud); 1470 1471 ret = uart_add_one_port(&pch_uart_driver, &priv->port); 1472 if (ret < 0) 1473 goto init_port_hal_free; 1474 1475 return priv; 1476 1477 init_port_hal_free: 1478 free_page((unsigned long)rxbuf); 1479 init_port_free_txbuf: 1480 kfree(priv); 1481 init_port_alloc_err: 1482 1483 return NULL; 1484 } 1485 1486 static void pch_uart_exit_port(struct eg20t_port *priv) 1487 { 1488 uart_remove_one_port(&pch_uart_driver, &priv->port); 1489 pci_set_drvdata(priv->pdev, NULL); 1490 free_page((unsigned long)priv->rxbuf.buf); 1491 } 1492 1493 static void pch_uart_pci_remove(struct pci_dev *pdev) 1494 { 1495 struct eg20t_port *priv; 1496 1497 priv = (struct eg20t_port *)pci_get_drvdata(pdev); 1498 1499 pci_disable_msi(pdev); 1500 pch_uart_exit_port(priv); 1501 pci_disable_device(pdev); 1502 kfree(priv); 1503 return; 1504 } 1505 #ifdef CONFIG_PM 1506 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1507 { 1508 struct eg20t_port *priv = pci_get_drvdata(pdev); 1509 1510 uart_suspend_port(&pch_uart_driver, &priv->port); 1511 1512 pci_save_state(pdev); 1513 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1514 return 0; 1515 } 1516 1517 static int pch_uart_pci_resume(struct pci_dev *pdev) 1518 { 1519 struct eg20t_port *priv = pci_get_drvdata(pdev); 1520 int ret; 1521 1522 pci_set_power_state(pdev, PCI_D0); 1523 pci_restore_state(pdev); 1524 1525 ret = pci_enable_device(pdev); 1526 if (ret) { 1527 dev_err(&pdev->dev, 1528 "%s-pci_enable_device failed(ret=%d) ", __func__, ret); 1529 return ret; 1530 } 1531 1532 uart_resume_port(&pch_uart_driver, &priv->port); 1533 1534 return 0; 1535 } 1536 #else 1537 #define pch_uart_pci_suspend NULL 1538 #define pch_uart_pci_resume NULL 1539 #endif 1540 1541 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = { 1542 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), 1543 .driver_data = pch_et20t_uart0}, 1544 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), 1545 .driver_data = pch_et20t_uart1}, 1546 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), 1547 .driver_data = pch_et20t_uart2}, 1548 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), 1549 .driver_data = pch_et20t_uart3}, 1550 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), 1551 .driver_data = pch_ml7213_uart0}, 1552 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), 1553 .driver_data = pch_ml7213_uart1}, 1554 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), 1555 .driver_data = pch_ml7213_uart2}, 1556 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C), 1557 .driver_data = pch_ml7223_uart0}, 1558 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D), 1559 .driver_data = pch_ml7223_uart1}, 1560 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811), 1561 .driver_data = pch_ml7831_uart0}, 1562 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812), 1563 .driver_data = pch_ml7831_uart1}, 1564 {0,}, 1565 }; 1566 1567 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev, 1568 const struct pci_device_id *id) 1569 { 1570 int ret; 1571 struct eg20t_port *priv; 1572 1573 ret = pci_enable_device(pdev); 1574 if (ret < 0) 1575 goto probe_error; 1576 1577 priv = pch_uart_init_port(pdev, id); 1578 if (!priv) { 1579 ret = -EBUSY; 1580 goto probe_disable_device; 1581 } 1582 pci_set_drvdata(pdev, priv); 1583 1584 return ret; 1585 1586 probe_disable_device: 1587 pci_disable_msi(pdev); 1588 pci_disable_device(pdev); 1589 probe_error: 1590 return ret; 1591 } 1592 1593 static struct pci_driver pch_uart_pci_driver = { 1594 .name = "pch_uart", 1595 .id_table = pch_uart_pci_id, 1596 .probe = pch_uart_pci_probe, 1597 .remove = __devexit_p(pch_uart_pci_remove), 1598 .suspend = pch_uart_pci_suspend, 1599 .resume = pch_uart_pci_resume, 1600 }; 1601 1602 static int __init pch_uart_module_init(void) 1603 { 1604 int ret; 1605 1606 /* register as UART driver */ 1607 ret = uart_register_driver(&pch_uart_driver); 1608 if (ret < 0) 1609 return ret; 1610 1611 /* register as PCI driver */ 1612 ret = pci_register_driver(&pch_uart_pci_driver); 1613 if (ret < 0) 1614 uart_unregister_driver(&pch_uart_driver); 1615 1616 return ret; 1617 } 1618 module_init(pch_uart_module_init); 1619 1620 static void __exit pch_uart_module_exit(void) 1621 { 1622 pci_unregister_driver(&pch_uart_pci_driver); 1623 uart_unregister_driver(&pch_uart_driver); 1624 } 1625 module_exit(pch_uart_module_exit); 1626 1627 MODULE_LICENSE("GPL v2"); 1628 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); 1629 module_param(default_baud, uint, S_IRUGO); 1630