1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for OMAP-UART controller. 4 * Based on drivers/serial/8250.c 5 * 6 * Copyright (C) 2010 Texas Instruments. 7 * 8 * Authors: 9 * Govindraj R <govindraj.raja@ti.com> 10 * Thara Gopinath <thara@ti.com> 11 * 12 * Note: This driver is made separate from 8250 driver as we cannot 13 * over load 8250 driver with omap platform specific configuration for 14 * features like DMA, it makes easier to implement features like DMA and 15 * hardware flow control and software flow control configuration with 16 * this driver as required for the omap-platform. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/console.h> 22 #include <linux/serial.h> 23 #include <linux/serial_reg.h> 24 #include <linux/delay.h> 25 #include <linux/slab.h> 26 #include <linux/tty.h> 27 #include <linux/tty_flip.h> 28 #include <linux/platform_device.h> 29 #include <linux/io.h> 30 #include <linux/clk.h> 31 #include <linux/serial_core.h> 32 #include <linux/irq.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/pm_wakeirq.h> 35 #include <linux/of.h> 36 #include <linux/of_irq.h> 37 #include <linux/gpio/consumer.h> 38 #include <linux/platform_data/serial-omap.h> 39 40 #define OMAP_MAX_HSUART_PORTS 10 41 42 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 43 44 #define OMAP_UART_REV_42 0x0402 45 #define OMAP_UART_REV_46 0x0406 46 #define OMAP_UART_REV_52 0x0502 47 #define OMAP_UART_REV_63 0x0603 48 49 #define OMAP_UART_TX_WAKEUP_EN BIT(7) 50 51 /* Feature flags */ 52 #define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0) 53 54 #define UART_ERRATA_i202_MDR1_ACCESS BIT(0) 55 #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1) 56 57 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */ 58 59 /* SCR register bitmasks */ 60 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 61 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 62 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 63 64 /* FCR register bitmasks */ 65 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6) 66 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4) 67 68 /* MVR register bitmasks */ 69 #define OMAP_UART_MVR_SCHEME_SHIFT 30 70 71 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 72 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 73 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 74 75 #define OMAP_UART_MVR_MAJ_MASK 0x700 76 #define OMAP_UART_MVR_MAJ_SHIFT 8 77 #define OMAP_UART_MVR_MIN_MASK 0x3f 78 79 #define OMAP_UART_DMA_CH_FREE -1 80 81 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA 82 #define OMAP_MODE13X_SPEED 230400 83 84 /* WER = 0x7F 85 * Enable module level wakeup in WER reg 86 */ 87 #define OMAP_UART_WER_MOD_WKUP 0x7F 88 89 /* Enable XON/XOFF flow control on output */ 90 #define OMAP_UART_SW_TX 0x08 91 92 /* Enable XON/XOFF flow control on input */ 93 #define OMAP_UART_SW_RX 0x02 94 95 #define OMAP_UART_SW_CLR 0xF0 96 97 #define OMAP_UART_TCR_TRIG 0x0F 98 99 struct uart_omap_dma { 100 u8 uart_dma_tx; 101 u8 uart_dma_rx; 102 int rx_dma_channel; 103 int tx_dma_channel; 104 dma_addr_t rx_buf_dma_phys; 105 dma_addr_t tx_buf_dma_phys; 106 unsigned int uart_base; 107 /* 108 * Buffer for rx dma. It is not required for tx because the buffer 109 * comes from port structure. 110 */ 111 unsigned char *rx_buf; 112 unsigned int prev_rx_dma_pos; 113 int tx_buf_size; 114 int tx_dma_used; 115 int rx_dma_used; 116 spinlock_t tx_lock; 117 spinlock_t rx_lock; 118 /* timer to poll activity on rx dma */ 119 struct timer_list rx_timer; 120 unsigned int rx_buf_size; 121 unsigned int rx_poll_rate; 122 unsigned int rx_timeout; 123 }; 124 125 struct uart_omap_port { 126 struct uart_port port; 127 struct uart_omap_dma uart_dma; 128 struct device *dev; 129 int wakeirq; 130 131 unsigned char ier; 132 unsigned char lcr; 133 unsigned char mcr; 134 unsigned char fcr; 135 unsigned char efr; 136 unsigned char dll; 137 unsigned char dlh; 138 unsigned char mdr1; 139 unsigned char scr; 140 unsigned char wer; 141 142 int use_dma; 143 /* 144 * Some bits in registers are cleared on a read, so they must 145 * be saved whenever the register is read, but the bits will not 146 * be immediately processed. 147 */ 148 unsigned int lsr_break_flag; 149 unsigned char msr_saved_flags; 150 char name[20]; 151 unsigned long port_activity; 152 int context_loss_cnt; 153 u32 errata; 154 u32 features; 155 156 struct gpio_desc *rts_gpiod; 157 158 struct pm_qos_request pm_qos_request; 159 u32 latency; 160 u32 calc_latency; 161 struct work_struct qos_work; 162 bool is_suspending; 163 164 unsigned int rs485_tx_filter_count; 165 }; 166 167 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port))) 168 169 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; 170 171 /* Forward declaration of functions */ 172 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1); 173 174 static inline unsigned int serial_in(struct uart_omap_port *up, int offset) 175 { 176 offset <<= up->port.regshift; 177 return readw(up->port.membase + offset); 178 } 179 180 static inline void serial_out(struct uart_omap_port *up, int offset, int value) 181 { 182 offset <<= up->port.regshift; 183 writew(value, up->port.membase + offset); 184 } 185 186 static inline void serial_omap_clear_fifos(struct uart_omap_port *up) 187 { 188 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 189 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 190 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 191 serial_out(up, UART_FCR, 0); 192 } 193 194 #ifdef CONFIG_PM 195 static int serial_omap_get_context_loss_count(struct uart_omap_port *up) 196 { 197 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev); 198 199 if (!pdata || !pdata->get_context_loss_count) 200 return -EINVAL; 201 202 return pdata->get_context_loss_count(up->dev); 203 } 204 205 /* REVISIT: Remove this when omap3 boots in device tree only mode */ 206 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable) 207 { 208 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev); 209 210 if (!pdata || !pdata->enable_wakeup) 211 return; 212 213 pdata->enable_wakeup(up->dev, enable); 214 } 215 #endif /* CONFIG_PM */ 216 217 /* 218 * Calculate the absolute difference between the desired and actual baud 219 * rate for the given mode. 220 */ 221 static inline int calculate_baud_abs_diff(struct uart_port *port, 222 unsigned int baud, unsigned int mode) 223 { 224 unsigned int n = port->uartclk / (mode * baud); 225 int abs_diff; 226 227 if (n == 0) 228 n = 1; 229 230 abs_diff = baud - (port->uartclk / (mode * n)); 231 if (abs_diff < 0) 232 abs_diff = -abs_diff; 233 234 return abs_diff; 235 } 236 237 /* 238 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X 239 * @port: uart port info 240 * @baud: baudrate for which mode needs to be determined 241 * 242 * Returns true if baud rate is MODE16X and false if MODE13X 243 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values, 244 * and Error Rates" determines modes not for all common baud rates. 245 * E.g. for 1000000 baud rate mode must be 16x, but according to that 246 * table it's determined as 13x. 247 */ 248 static bool 249 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud) 250 { 251 int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13); 252 int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16); 253 254 return (abs_diff_13 >= abs_diff_16); 255 } 256 257 /* 258 * serial_omap_get_divisor - calculate divisor value 259 * @port: uart port info 260 * @baud: baudrate for which divisor needs to be calculated. 261 */ 262 static unsigned int 263 serial_omap_get_divisor(struct uart_port *port, unsigned int baud) 264 { 265 unsigned int mode; 266 267 if (!serial_omap_baud_is_mode16(port, baud)) 268 mode = 13; 269 else 270 mode = 16; 271 return port->uartclk/(mode * baud); 272 } 273 274 static void serial_omap_enable_ms(struct uart_port *port) 275 { 276 struct uart_omap_port *up = to_uart_omap_port(port); 277 278 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line); 279 280 up->ier |= UART_IER_MSI; 281 serial_out(up, UART_IER, up->ier); 282 } 283 284 static void serial_omap_stop_tx(struct uart_port *port) 285 { 286 struct uart_omap_port *up = to_uart_omap_port(port); 287 int res; 288 289 /* Handle RS-485 */ 290 if (port->rs485.flags & SER_RS485_ENABLED) { 291 if (up->scr & OMAP_UART_SCR_TX_EMPTY) { 292 /* THR interrupt is fired when both TX FIFO and TX 293 * shift register are empty. This means there's nothing 294 * left to transmit now, so make sure the THR interrupt 295 * is fired when TX FIFO is below the trigger level, 296 * disable THR interrupts and toggle the RS-485 GPIO 297 * data direction pin if needed. 298 */ 299 up->scr &= ~OMAP_UART_SCR_TX_EMPTY; 300 serial_out(up, UART_OMAP_SCR, up->scr); 301 res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 302 1 : 0; 303 if (gpiod_get_value(up->rts_gpiod) != res) { 304 if (port->rs485.delay_rts_after_send > 0) 305 mdelay( 306 port->rs485.delay_rts_after_send); 307 gpiod_set_value(up->rts_gpiod, res); 308 } 309 } else { 310 /* We're asked to stop, but there's still stuff in the 311 * UART FIFO, so make sure the THR interrupt is fired 312 * when both TX FIFO and TX shift register are empty. 313 * The next THR interrupt (if no transmission is started 314 * in the meantime) will indicate the end of a 315 * transmission. Therefore we _don't_ disable THR 316 * interrupts in this situation. 317 */ 318 up->scr |= OMAP_UART_SCR_TX_EMPTY; 319 serial_out(up, UART_OMAP_SCR, up->scr); 320 return; 321 } 322 } 323 324 if (up->ier & UART_IER_THRI) { 325 up->ier &= ~UART_IER_THRI; 326 serial_out(up, UART_IER, up->ier); 327 } 328 } 329 330 static void serial_omap_stop_rx(struct uart_port *port) 331 { 332 struct uart_omap_port *up = to_uart_omap_port(port); 333 334 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 335 up->port.read_status_mask &= ~UART_LSR_DR; 336 serial_out(up, UART_IER, up->ier); 337 } 338 339 static void serial_omap_put_char(struct uart_omap_port *up, unsigned char ch) 340 { 341 serial_out(up, UART_TX, ch); 342 343 if ((up->port.rs485.flags & SER_RS485_ENABLED) && 344 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) 345 up->rs485_tx_filter_count++; 346 } 347 348 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr) 349 { 350 u8 ch; 351 352 uart_port_tx_limited(&up->port, ch, up->port.fifosize / 4, 353 true, 354 serial_omap_put_char(up, ch), 355 ({})); 356 } 357 358 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) 359 { 360 if (!(up->ier & UART_IER_THRI)) { 361 up->ier |= UART_IER_THRI; 362 serial_out(up, UART_IER, up->ier); 363 } 364 } 365 366 static void serial_omap_start_tx(struct uart_port *port) 367 { 368 struct uart_omap_port *up = to_uart_omap_port(port); 369 int res; 370 371 /* Handle RS-485 */ 372 if (port->rs485.flags & SER_RS485_ENABLED) { 373 /* Fire THR interrupts when FIFO is below trigger level */ 374 up->scr &= ~OMAP_UART_SCR_TX_EMPTY; 375 serial_out(up, UART_OMAP_SCR, up->scr); 376 377 /* if rts not already enabled */ 378 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0; 379 if (gpiod_get_value(up->rts_gpiod) != res) { 380 gpiod_set_value(up->rts_gpiod, res); 381 if (port->rs485.delay_rts_before_send > 0) 382 mdelay(port->rs485.delay_rts_before_send); 383 } 384 } 385 386 if ((port->rs485.flags & SER_RS485_ENABLED) && 387 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) 388 up->rs485_tx_filter_count = 0; 389 390 serial_omap_enable_ier_thri(up); 391 } 392 393 static void serial_omap_throttle(struct uart_port *port) 394 { 395 struct uart_omap_port *up = to_uart_omap_port(port); 396 unsigned long flags; 397 398 spin_lock_irqsave(&up->port.lock, flags); 399 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 400 serial_out(up, UART_IER, up->ier); 401 spin_unlock_irqrestore(&up->port.lock, flags); 402 } 403 404 static void serial_omap_unthrottle(struct uart_port *port) 405 { 406 struct uart_omap_port *up = to_uart_omap_port(port); 407 unsigned long flags; 408 409 spin_lock_irqsave(&up->port.lock, flags); 410 up->ier |= UART_IER_RLSI | UART_IER_RDI; 411 serial_out(up, UART_IER, up->ier); 412 spin_unlock_irqrestore(&up->port.lock, flags); 413 } 414 415 static unsigned int check_modem_status(struct uart_omap_port *up) 416 { 417 unsigned int status; 418 419 status = serial_in(up, UART_MSR); 420 status |= up->msr_saved_flags; 421 up->msr_saved_flags = 0; 422 if ((status & UART_MSR_ANY_DELTA) == 0) 423 return status; 424 425 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && 426 up->port.state != NULL) { 427 if (status & UART_MSR_TERI) 428 up->port.icount.rng++; 429 if (status & UART_MSR_DDSR) 430 up->port.icount.dsr++; 431 if (status & UART_MSR_DDCD) 432 uart_handle_dcd_change 433 (&up->port, status & UART_MSR_DCD); 434 if (status & UART_MSR_DCTS) 435 uart_handle_cts_change 436 (&up->port, status & UART_MSR_CTS); 437 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 438 } 439 440 return status; 441 } 442 443 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr) 444 { 445 u8 flag; 446 447 /* 448 * Read one data character out to avoid stalling the receiver according 449 * to the table 23-246 of the omap4 TRM. 450 */ 451 if (likely(lsr & UART_LSR_DR)) { 452 serial_in(up, UART_RX); 453 if ((up->port.rs485.flags & SER_RS485_ENABLED) && 454 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) && 455 up->rs485_tx_filter_count) 456 up->rs485_tx_filter_count--; 457 } 458 459 up->port.icount.rx++; 460 flag = TTY_NORMAL; 461 462 if (lsr & UART_LSR_BI) { 463 flag = TTY_BREAK; 464 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 465 up->port.icount.brk++; 466 /* 467 * We do the SysRQ and SAK checking 468 * here because otherwise the break 469 * may get masked by ignore_status_mask 470 * or read_status_mask. 471 */ 472 if (uart_handle_break(&up->port)) 473 return; 474 475 } 476 477 if (lsr & UART_LSR_PE) { 478 flag = TTY_PARITY; 479 up->port.icount.parity++; 480 } 481 482 if (lsr & UART_LSR_FE) { 483 flag = TTY_FRAME; 484 up->port.icount.frame++; 485 } 486 487 if (lsr & UART_LSR_OE) 488 up->port.icount.overrun++; 489 490 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 491 if (up->port.line == up->port.cons->index) { 492 /* Recover the break flag from console xmit */ 493 lsr |= up->lsr_break_flag; 494 } 495 #endif 496 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag); 497 } 498 499 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr) 500 { 501 u8 ch; 502 503 if (!(lsr & UART_LSR_DR)) 504 return; 505 506 ch = serial_in(up, UART_RX); 507 if ((up->port.rs485.flags & SER_RS485_ENABLED) && 508 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) && 509 up->rs485_tx_filter_count) { 510 up->rs485_tx_filter_count--; 511 return; 512 } 513 514 up->port.icount.rx++; 515 516 if (uart_handle_sysrq_char(&up->port, ch)) 517 return; 518 519 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, TTY_NORMAL); 520 } 521 522 /** 523 * serial_omap_irq() - This handles the interrupt from one port 524 * @irq: uart port irq number 525 * @dev_id: uart port info 526 */ 527 static irqreturn_t serial_omap_irq(int irq, void *dev_id) 528 { 529 struct uart_omap_port *up = dev_id; 530 unsigned int iir, lsr; 531 unsigned int type; 532 irqreturn_t ret = IRQ_NONE; 533 int max_count = 256; 534 535 spin_lock(&up->port.lock); 536 537 do { 538 iir = serial_in(up, UART_IIR); 539 if (iir & UART_IIR_NO_INT) 540 break; 541 542 ret = IRQ_HANDLED; 543 lsr = serial_in(up, UART_LSR); 544 545 /* extract IRQ type from IIR register */ 546 type = iir & 0x3e; 547 548 switch (type) { 549 case UART_IIR_MSI: 550 check_modem_status(up); 551 break; 552 case UART_IIR_THRI: 553 transmit_chars(up, lsr); 554 break; 555 case UART_IIR_RX_TIMEOUT: 556 case UART_IIR_RDI: 557 serial_omap_rdi(up, lsr); 558 break; 559 case UART_IIR_RLSI: 560 serial_omap_rlsi(up, lsr); 561 break; 562 case UART_IIR_CTS_RTS_DSR: 563 /* simply try again */ 564 break; 565 case UART_IIR_XOFF: 566 default: 567 break; 568 } 569 } while (max_count--); 570 571 spin_unlock(&up->port.lock); 572 573 tty_flip_buffer_push(&up->port.state->port); 574 575 up->port_activity = jiffies; 576 577 return ret; 578 } 579 580 static unsigned int serial_omap_tx_empty(struct uart_port *port) 581 { 582 struct uart_omap_port *up = to_uart_omap_port(port); 583 unsigned long flags; 584 unsigned int ret = 0; 585 586 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line); 587 spin_lock_irqsave(&up->port.lock, flags); 588 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 589 spin_unlock_irqrestore(&up->port.lock, flags); 590 591 return ret; 592 } 593 594 static unsigned int serial_omap_get_mctrl(struct uart_port *port) 595 { 596 struct uart_omap_port *up = to_uart_omap_port(port); 597 unsigned int status; 598 unsigned int ret = 0; 599 600 status = check_modem_status(up); 601 602 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line); 603 604 if (status & UART_MSR_DCD) 605 ret |= TIOCM_CAR; 606 if (status & UART_MSR_RI) 607 ret |= TIOCM_RNG; 608 if (status & UART_MSR_DSR) 609 ret |= TIOCM_DSR; 610 if (status & UART_MSR_CTS) 611 ret |= TIOCM_CTS; 612 return ret; 613 } 614 615 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) 616 { 617 struct uart_omap_port *up = to_uart_omap_port(port); 618 unsigned char mcr = 0, old_mcr, lcr; 619 620 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line); 621 if (mctrl & TIOCM_RTS) 622 mcr |= UART_MCR_RTS; 623 if (mctrl & TIOCM_DTR) 624 mcr |= UART_MCR_DTR; 625 if (mctrl & TIOCM_OUT1) 626 mcr |= UART_MCR_OUT1; 627 if (mctrl & TIOCM_OUT2) 628 mcr |= UART_MCR_OUT2; 629 if (mctrl & TIOCM_LOOP) 630 mcr |= UART_MCR_LOOP; 631 632 old_mcr = serial_in(up, UART_MCR); 633 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 | 634 UART_MCR_DTR | UART_MCR_RTS); 635 up->mcr = old_mcr | mcr; 636 serial_out(up, UART_MCR, up->mcr); 637 638 /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */ 639 lcr = serial_in(up, UART_LCR); 640 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 641 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 642 up->efr |= UART_EFR_RTS; 643 else 644 up->efr &= ~UART_EFR_RTS; 645 serial_out(up, UART_EFR, up->efr); 646 serial_out(up, UART_LCR, lcr); 647 } 648 649 static void serial_omap_break_ctl(struct uart_port *port, int break_state) 650 { 651 struct uart_omap_port *up = to_uart_omap_port(port); 652 unsigned long flags; 653 654 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line); 655 spin_lock_irqsave(&up->port.lock, flags); 656 if (break_state == -1) 657 up->lcr |= UART_LCR_SBC; 658 else 659 up->lcr &= ~UART_LCR_SBC; 660 serial_out(up, UART_LCR, up->lcr); 661 spin_unlock_irqrestore(&up->port.lock, flags); 662 } 663 664 static int serial_omap_startup(struct uart_port *port) 665 { 666 struct uart_omap_port *up = to_uart_omap_port(port); 667 unsigned long flags; 668 int retval; 669 670 /* 671 * Allocate the IRQ 672 */ 673 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, 674 up->name, up); 675 if (retval) 676 return retval; 677 678 /* Optional wake-up IRQ */ 679 if (up->wakeirq) { 680 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq); 681 if (retval) { 682 free_irq(up->port.irq, up); 683 return retval; 684 } 685 } 686 687 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line); 688 689 pm_runtime_get_sync(up->dev); 690 /* 691 * Clear the FIFO buffers and disable them. 692 * (they will be reenabled in set_termios()) 693 */ 694 serial_omap_clear_fifos(up); 695 696 /* 697 * Clear the interrupt registers. 698 */ 699 (void) serial_in(up, UART_LSR); 700 if (serial_in(up, UART_LSR) & UART_LSR_DR) 701 (void) serial_in(up, UART_RX); 702 (void) serial_in(up, UART_IIR); 703 (void) serial_in(up, UART_MSR); 704 705 /* 706 * Now, initialize the UART 707 */ 708 serial_out(up, UART_LCR, UART_LCR_WLEN8); 709 spin_lock_irqsave(&up->port.lock, flags); 710 /* 711 * Most PC uarts need OUT2 raised to enable interrupts. 712 */ 713 up->port.mctrl |= TIOCM_OUT2; 714 serial_omap_set_mctrl(&up->port, up->port.mctrl); 715 spin_unlock_irqrestore(&up->port.lock, flags); 716 717 up->msr_saved_flags = 0; 718 /* 719 * Finally, enable interrupts. Note: Modem status interrupts 720 * are set via set_termios(), which will be occurring imminently 721 * anyway, so we don't enable them here. 722 */ 723 up->ier = UART_IER_RLSI | UART_IER_RDI; 724 serial_out(up, UART_IER, up->ier); 725 726 /* Enable module level wake up */ 727 up->wer = OMAP_UART_WER_MOD_WKUP; 728 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP) 729 up->wer |= OMAP_UART_TX_WAKEUP_EN; 730 731 serial_out(up, UART_OMAP_WER, up->wer); 732 733 up->port_activity = jiffies; 734 return 0; 735 } 736 737 static void serial_omap_shutdown(struct uart_port *port) 738 { 739 struct uart_omap_port *up = to_uart_omap_port(port); 740 unsigned long flags; 741 742 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line); 743 744 /* 745 * Disable interrupts from this port 746 */ 747 up->ier = 0; 748 serial_out(up, UART_IER, 0); 749 750 spin_lock_irqsave(&up->port.lock, flags); 751 up->port.mctrl &= ~TIOCM_OUT2; 752 serial_omap_set_mctrl(&up->port, up->port.mctrl); 753 spin_unlock_irqrestore(&up->port.lock, flags); 754 755 /* 756 * Disable break condition and FIFOs 757 */ 758 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); 759 serial_omap_clear_fifos(up); 760 761 /* 762 * Read data port to reset things, and then free the irq 763 */ 764 if (serial_in(up, UART_LSR) & UART_LSR_DR) 765 (void) serial_in(up, UART_RX); 766 767 pm_runtime_put_sync(up->dev); 768 free_irq(up->port.irq, up); 769 dev_pm_clear_wake_irq(up->dev); 770 } 771 772 static void serial_omap_uart_qos_work(struct work_struct *work) 773 { 774 struct uart_omap_port *up = container_of(work, struct uart_omap_port, 775 qos_work); 776 777 cpu_latency_qos_update_request(&up->pm_qos_request, up->latency); 778 } 779 780 static void 781 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, 782 const struct ktermios *old) 783 { 784 struct uart_omap_port *up = to_uart_omap_port(port); 785 unsigned char cval = 0; 786 unsigned long flags; 787 unsigned int baud, quot; 788 789 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); 790 791 if (termios->c_cflag & CSTOPB) 792 cval |= UART_LCR_STOP; 793 if (termios->c_cflag & PARENB) 794 cval |= UART_LCR_PARITY; 795 if (!(termios->c_cflag & PARODD)) 796 cval |= UART_LCR_EPAR; 797 if (termios->c_cflag & CMSPAR) 798 cval |= UART_LCR_SPAR; 799 800 /* 801 * Ask the core to calculate the divisor for us. 802 */ 803 804 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); 805 quot = serial_omap_get_divisor(port, baud); 806 807 /* calculate wakeup latency constraint */ 808 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8); 809 up->latency = up->calc_latency; 810 schedule_work(&up->qos_work); 811 812 up->dll = quot & 0xff; 813 up->dlh = quot >> 8; 814 up->mdr1 = UART_OMAP_MDR1_DISABLE; 815 816 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | 817 UART_FCR_ENABLE_FIFO; 818 819 /* 820 * Ok, we're now changing the port state. Do it with 821 * interrupts disabled. 822 */ 823 spin_lock_irqsave(&up->port.lock, flags); 824 825 /* 826 * Update the per-port timeout. 827 */ 828 uart_update_timeout(port, termios->c_cflag, baud); 829 830 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 831 if (termios->c_iflag & INPCK) 832 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 833 if (termios->c_iflag & (BRKINT | PARMRK)) 834 up->port.read_status_mask |= UART_LSR_BI; 835 836 /* 837 * Characters to ignore 838 */ 839 up->port.ignore_status_mask = 0; 840 if (termios->c_iflag & IGNPAR) 841 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 842 if (termios->c_iflag & IGNBRK) { 843 up->port.ignore_status_mask |= UART_LSR_BI; 844 /* 845 * If we're ignoring parity and break indicators, 846 * ignore overruns too (for real raw support). 847 */ 848 if (termios->c_iflag & IGNPAR) 849 up->port.ignore_status_mask |= UART_LSR_OE; 850 } 851 852 /* 853 * ignore all characters if CREAD is not set 854 */ 855 if ((termios->c_cflag & CREAD) == 0) 856 up->port.ignore_status_mask |= UART_LSR_DR; 857 858 /* 859 * Modem status interrupts 860 */ 861 up->ier &= ~UART_IER_MSI; 862 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 863 up->ier |= UART_IER_MSI; 864 serial_out(up, UART_IER, up->ier); 865 serial_out(up, UART_LCR, cval); /* reset DLAB */ 866 up->lcr = cval; 867 up->scr = 0; 868 869 /* FIFOs and DMA Settings */ 870 871 /* FCR can be changed only when the 872 * baud clock is not running 873 * DLL_REG and DLH_REG set to 0. 874 */ 875 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 876 serial_out(up, UART_DLL, 0); 877 serial_out(up, UART_DLM, 0); 878 serial_out(up, UART_LCR, 0); 879 880 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 881 882 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB; 883 up->efr &= ~UART_EFR_SCD; 884 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 885 886 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 887 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR; 888 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 889 /* FIFO ENABLE, DMA MODE */ 890 891 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; 892 /* 893 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK 894 * sets Enables the granularity of 1 for TRIGGER RX 895 * level. Along with setting RX FIFO trigger level 896 * to 1 (as noted below, 16 characters) and TLR[3:0] 897 * to zero this will result RX FIFO threshold level 898 * to 1 character, instead of 16 as noted in comment 899 * below. 900 */ 901 902 /* Set receive FIFO threshold to 16 characters and 903 * transmit FIFO threshold to 32 spaces 904 */ 905 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; 906 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK; 907 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 | 908 UART_FCR_ENABLE_FIFO; 909 910 serial_out(up, UART_FCR, up->fcr); 911 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 912 913 serial_out(up, UART_OMAP_SCR, up->scr); 914 915 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */ 916 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 917 serial_out(up, UART_MCR, up->mcr); 918 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 919 serial_out(up, UART_EFR, up->efr); 920 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 921 922 /* Protocol, Baud Rate, and Interrupt Settings */ 923 924 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 925 serial_omap_mdr1_errataset(up, up->mdr1); 926 else 927 serial_out(up, UART_OMAP_MDR1, up->mdr1); 928 929 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 930 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 931 932 serial_out(up, UART_LCR, 0); 933 serial_out(up, UART_IER, 0); 934 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 935 936 serial_out(up, UART_DLL, up->dll); /* LS of divisor */ 937 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */ 938 939 serial_out(up, UART_LCR, 0); 940 serial_out(up, UART_IER, up->ier); 941 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 942 943 serial_out(up, UART_EFR, up->efr); 944 serial_out(up, UART_LCR, cval); 945 946 if (!serial_omap_baud_is_mode16(port, baud)) 947 up->mdr1 = UART_OMAP_MDR1_13X_MODE; 948 else 949 up->mdr1 = UART_OMAP_MDR1_16X_MODE; 950 951 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 952 serial_omap_mdr1_errataset(up, up->mdr1); 953 else 954 serial_out(up, UART_OMAP_MDR1, up->mdr1); 955 956 /* Configure flow control */ 957 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 958 959 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */ 960 serial_out(up, UART_XON1, termios->c_cc[VSTART]); 961 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); 962 963 /* Enable access to TCR/TLR */ 964 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 965 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 966 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 967 968 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); 969 970 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 971 972 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { 973 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 974 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 975 up->efr |= UART_EFR_CTS; 976 } else { 977 /* Disable AUTORTS and AUTOCTS */ 978 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS); 979 } 980 981 if (up->port.flags & UPF_SOFT_FLOW) { 982 /* clear SW control mode bits */ 983 up->efr &= OMAP_UART_SW_CLR; 984 985 /* 986 * IXON Flag: 987 * Enable XON/XOFF flow control on input. 988 * Receiver compares XON1, XOFF1. 989 */ 990 if (termios->c_iflag & IXON) 991 up->efr |= OMAP_UART_SW_RX; 992 993 /* 994 * IXOFF Flag: 995 * Enable XON/XOFF flow control on output. 996 * Transmit XON1, XOFF1 997 */ 998 if (termios->c_iflag & IXOFF) { 999 up->port.status |= UPSTAT_AUTOXOFF; 1000 up->efr |= OMAP_UART_SW_TX; 1001 } 1002 1003 /* 1004 * IXANY Flag: 1005 * Enable any character to restart output. 1006 * Operation resumes after receiving any 1007 * character after recognition of the XOFF character 1008 */ 1009 if (termios->c_iflag & IXANY) 1010 up->mcr |= UART_MCR_XONANY; 1011 else 1012 up->mcr &= ~UART_MCR_XONANY; 1013 } 1014 serial_out(up, UART_MCR, up->mcr); 1015 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1016 serial_out(up, UART_EFR, up->efr); 1017 serial_out(up, UART_LCR, up->lcr); 1018 1019 serial_omap_set_mctrl(&up->port, up->port.mctrl); 1020 1021 spin_unlock_irqrestore(&up->port.lock, flags); 1022 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line); 1023 } 1024 1025 static void 1026 serial_omap_pm(struct uart_port *port, unsigned int state, 1027 unsigned int oldstate) 1028 { 1029 struct uart_omap_port *up = to_uart_omap_port(port); 1030 unsigned char efr; 1031 1032 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line); 1033 1034 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1035 efr = serial_in(up, UART_EFR); 1036 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 1037 serial_out(up, UART_LCR, 0); 1038 1039 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 1040 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1041 serial_out(up, UART_EFR, efr); 1042 serial_out(up, UART_LCR, 0); 1043 } 1044 1045 static void serial_omap_release_port(struct uart_port *port) 1046 { 1047 dev_dbg(port->dev, "serial_omap_release_port+\n"); 1048 } 1049 1050 static int serial_omap_request_port(struct uart_port *port) 1051 { 1052 dev_dbg(port->dev, "serial_omap_request_port+\n"); 1053 return 0; 1054 } 1055 1056 static void serial_omap_config_port(struct uart_port *port, int flags) 1057 { 1058 struct uart_omap_port *up = to_uart_omap_port(port); 1059 1060 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", 1061 up->port.line); 1062 up->port.type = PORT_OMAP; 1063 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW; 1064 } 1065 1066 static int 1067 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) 1068 { 1069 /* we don't want the core code to modify any port params */ 1070 dev_dbg(port->dev, "serial_omap_verify_port+\n"); 1071 return -EINVAL; 1072 } 1073 1074 static const char * 1075 serial_omap_type(struct uart_port *port) 1076 { 1077 struct uart_omap_port *up = to_uart_omap_port(port); 1078 1079 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line); 1080 return up->name; 1081 } 1082 1083 static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up) 1084 { 1085 unsigned int status, tmout = 10000; 1086 1087 /* Wait up to 10ms for the character(s) to be sent. */ 1088 do { 1089 status = serial_in(up, UART_LSR); 1090 1091 if (status & UART_LSR_BI) 1092 up->lsr_break_flag = UART_LSR_BI; 1093 1094 if (--tmout == 0) 1095 break; 1096 udelay(1); 1097 } while (!uart_lsr_tx_empty(status)); 1098 1099 /* Wait up to 1s for flow control if necessary */ 1100 if (up->port.flags & UPF_CONS_FLOW) { 1101 tmout = 1000000; 1102 for (tmout = 1000000; tmout; tmout--) { 1103 unsigned int msr = serial_in(up, UART_MSR); 1104 1105 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; 1106 if (msr & UART_MSR_CTS) 1107 break; 1108 1109 udelay(1); 1110 } 1111 } 1112 } 1113 1114 #ifdef CONFIG_CONSOLE_POLL 1115 1116 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) 1117 { 1118 struct uart_omap_port *up = to_uart_omap_port(port); 1119 1120 wait_for_xmitr(up); 1121 serial_out(up, UART_TX, ch); 1122 } 1123 1124 static int serial_omap_poll_get_char(struct uart_port *port) 1125 { 1126 struct uart_omap_port *up = to_uart_omap_port(port); 1127 unsigned int status; 1128 1129 status = serial_in(up, UART_LSR); 1130 if (!(status & UART_LSR_DR)) { 1131 status = NO_POLL_CHAR; 1132 goto out; 1133 } 1134 1135 status = serial_in(up, UART_RX); 1136 1137 out: 1138 return status; 1139 } 1140 1141 #endif /* CONFIG_CONSOLE_POLL */ 1142 1143 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 1144 1145 #ifdef CONFIG_SERIAL_EARLYCON 1146 static unsigned int omap_serial_early_in(struct uart_port *port, int offset) 1147 { 1148 offset <<= port->regshift; 1149 return readw(port->membase + offset); 1150 } 1151 1152 static void omap_serial_early_out(struct uart_port *port, int offset, 1153 int value) 1154 { 1155 offset <<= port->regshift; 1156 writew(value, port->membase + offset); 1157 } 1158 1159 static void omap_serial_early_putc(struct uart_port *port, unsigned char c) 1160 { 1161 unsigned int status; 1162 1163 for (;;) { 1164 status = omap_serial_early_in(port, UART_LSR); 1165 if (uart_lsr_tx_empty(status)) 1166 break; 1167 cpu_relax(); 1168 } 1169 omap_serial_early_out(port, UART_TX, c); 1170 } 1171 1172 static void early_omap_serial_write(struct console *console, const char *s, 1173 unsigned int count) 1174 { 1175 struct earlycon_device *device = console->data; 1176 struct uart_port *port = &device->port; 1177 1178 uart_console_write(port, s, count, omap_serial_early_putc); 1179 } 1180 1181 static int __init early_omap_serial_setup(struct earlycon_device *device, 1182 const char *options) 1183 { 1184 struct uart_port *port = &device->port; 1185 1186 if (!(device->port.membase || device->port.iobase)) 1187 return -ENODEV; 1188 1189 port->regshift = 2; 1190 device->con->write = early_omap_serial_write; 1191 return 0; 1192 } 1193 1194 OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup); 1195 OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup); 1196 OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup); 1197 #endif /* CONFIG_SERIAL_EARLYCON */ 1198 1199 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS]; 1200 1201 static struct uart_driver serial_omap_reg; 1202 1203 static void serial_omap_console_putchar(struct uart_port *port, unsigned char ch) 1204 { 1205 struct uart_omap_port *up = to_uart_omap_port(port); 1206 1207 wait_for_xmitr(up); 1208 serial_out(up, UART_TX, ch); 1209 } 1210 1211 static void 1212 serial_omap_console_write(struct console *co, const char *s, 1213 unsigned int count) 1214 { 1215 struct uart_omap_port *up = serial_omap_console_ports[co->index]; 1216 unsigned long flags; 1217 unsigned int ier; 1218 int locked = 1; 1219 1220 local_irq_save(flags); 1221 if (up->port.sysrq) 1222 locked = 0; 1223 else if (oops_in_progress) 1224 locked = spin_trylock(&up->port.lock); 1225 else 1226 spin_lock(&up->port.lock); 1227 1228 /* 1229 * First save the IER then disable the interrupts 1230 */ 1231 ier = serial_in(up, UART_IER); 1232 serial_out(up, UART_IER, 0); 1233 1234 uart_console_write(&up->port, s, count, serial_omap_console_putchar); 1235 1236 /* 1237 * Finally, wait for transmitter to become empty 1238 * and restore the IER 1239 */ 1240 wait_for_xmitr(up); 1241 serial_out(up, UART_IER, ier); 1242 /* 1243 * The receive handling will happen properly because the 1244 * receive ready bit will still be set; it is not cleared 1245 * on read. However, modem control will not, we must 1246 * call it if we have saved something in the saved flags 1247 * while processing with interrupts off. 1248 */ 1249 if (up->msr_saved_flags) 1250 check_modem_status(up); 1251 1252 if (locked) 1253 spin_unlock(&up->port.lock); 1254 local_irq_restore(flags); 1255 } 1256 1257 static int __init 1258 serial_omap_console_setup(struct console *co, char *options) 1259 { 1260 struct uart_omap_port *up; 1261 int baud = 115200; 1262 int bits = 8; 1263 int parity = 'n'; 1264 int flow = 'n'; 1265 1266 if (serial_omap_console_ports[co->index] == NULL) 1267 return -ENODEV; 1268 up = serial_omap_console_ports[co->index]; 1269 1270 if (options) 1271 uart_parse_options(options, &baud, &parity, &bits, &flow); 1272 1273 return uart_set_options(&up->port, co, baud, parity, bits, flow); 1274 } 1275 1276 static struct console serial_omap_console = { 1277 .name = OMAP_SERIAL_NAME, 1278 .write = serial_omap_console_write, 1279 .device = uart_console_device, 1280 .setup = serial_omap_console_setup, 1281 .flags = CON_PRINTBUFFER, 1282 .index = -1, 1283 .data = &serial_omap_reg, 1284 }; 1285 1286 static void serial_omap_add_console_port(struct uart_omap_port *up) 1287 { 1288 serial_omap_console_ports[up->port.line] = up; 1289 } 1290 1291 #define OMAP_CONSOLE (&serial_omap_console) 1292 1293 #else 1294 1295 #define OMAP_CONSOLE NULL 1296 1297 static inline void serial_omap_add_console_port(struct uart_omap_port *up) 1298 {} 1299 1300 #endif 1301 1302 /* Enable or disable the rs485 support */ 1303 static int 1304 serial_omap_config_rs485(struct uart_port *port, struct ktermios *termios, 1305 struct serial_rs485 *rs485) 1306 { 1307 struct uart_omap_port *up = to_uart_omap_port(port); 1308 unsigned int mode; 1309 int val; 1310 1311 /* Disable interrupts from this port */ 1312 mode = up->ier; 1313 up->ier = 0; 1314 serial_out(up, UART_IER, 0); 1315 1316 /* enable / disable rts */ 1317 val = (rs485->flags & SER_RS485_ENABLED) ? 1318 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND; 1319 val = (rs485->flags & val) ? 1 : 0; 1320 gpiod_set_value(up->rts_gpiod, val); 1321 1322 /* Enable interrupts */ 1323 up->ier = mode; 1324 serial_out(up, UART_IER, up->ier); 1325 1326 /* If RS-485 is disabled, make sure the THR interrupt is fired when 1327 * TX FIFO is below the trigger level. 1328 */ 1329 if (!(rs485->flags & SER_RS485_ENABLED) && 1330 (up->scr & OMAP_UART_SCR_TX_EMPTY)) { 1331 up->scr &= ~OMAP_UART_SCR_TX_EMPTY; 1332 serial_out(up, UART_OMAP_SCR, up->scr); 1333 } 1334 1335 return 0; 1336 } 1337 1338 static const struct uart_ops serial_omap_pops = { 1339 .tx_empty = serial_omap_tx_empty, 1340 .set_mctrl = serial_omap_set_mctrl, 1341 .get_mctrl = serial_omap_get_mctrl, 1342 .stop_tx = serial_omap_stop_tx, 1343 .start_tx = serial_omap_start_tx, 1344 .throttle = serial_omap_throttle, 1345 .unthrottle = serial_omap_unthrottle, 1346 .stop_rx = serial_omap_stop_rx, 1347 .enable_ms = serial_omap_enable_ms, 1348 .break_ctl = serial_omap_break_ctl, 1349 .startup = serial_omap_startup, 1350 .shutdown = serial_omap_shutdown, 1351 .set_termios = serial_omap_set_termios, 1352 .pm = serial_omap_pm, 1353 .type = serial_omap_type, 1354 .release_port = serial_omap_release_port, 1355 .request_port = serial_omap_request_port, 1356 .config_port = serial_omap_config_port, 1357 .verify_port = serial_omap_verify_port, 1358 #ifdef CONFIG_CONSOLE_POLL 1359 .poll_put_char = serial_omap_poll_put_char, 1360 .poll_get_char = serial_omap_poll_get_char, 1361 #endif 1362 }; 1363 1364 static struct uart_driver serial_omap_reg = { 1365 .owner = THIS_MODULE, 1366 .driver_name = "OMAP-SERIAL", 1367 .dev_name = OMAP_SERIAL_NAME, 1368 .nr = OMAP_MAX_HSUART_PORTS, 1369 .cons = OMAP_CONSOLE, 1370 }; 1371 1372 #ifdef CONFIG_PM_SLEEP 1373 static int serial_omap_prepare(struct device *dev) 1374 { 1375 struct uart_omap_port *up = dev_get_drvdata(dev); 1376 1377 up->is_suspending = true; 1378 1379 return 0; 1380 } 1381 1382 static void serial_omap_complete(struct device *dev) 1383 { 1384 struct uart_omap_port *up = dev_get_drvdata(dev); 1385 1386 up->is_suspending = false; 1387 } 1388 1389 static int serial_omap_suspend(struct device *dev) 1390 { 1391 struct uart_omap_port *up = dev_get_drvdata(dev); 1392 1393 uart_suspend_port(&serial_omap_reg, &up->port); 1394 flush_work(&up->qos_work); 1395 1396 if (device_may_wakeup(dev)) 1397 serial_omap_enable_wakeup(up, true); 1398 else 1399 serial_omap_enable_wakeup(up, false); 1400 1401 return 0; 1402 } 1403 1404 static int serial_omap_resume(struct device *dev) 1405 { 1406 struct uart_omap_port *up = dev_get_drvdata(dev); 1407 1408 if (device_may_wakeup(dev)) 1409 serial_omap_enable_wakeup(up, false); 1410 1411 uart_resume_port(&serial_omap_reg, &up->port); 1412 1413 return 0; 1414 } 1415 #else 1416 #define serial_omap_prepare NULL 1417 #define serial_omap_complete NULL 1418 #endif /* CONFIG_PM_SLEEP */ 1419 1420 static void omap_serial_fill_features_erratas(struct uart_omap_port *up) 1421 { 1422 u32 mvr, scheme; 1423 u16 revision, major, minor; 1424 1425 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift)); 1426 1427 /* Check revision register scheme */ 1428 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 1429 1430 switch (scheme) { 1431 case 0: /* Legacy Scheme: OMAP2/3 */ 1432 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 1433 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 1434 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 1435 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 1436 break; 1437 case 1: 1438 /* New Scheme: OMAP4+ */ 1439 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 1440 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 1441 OMAP_UART_MVR_MAJ_SHIFT; 1442 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 1443 break; 1444 default: 1445 dev_warn(up->dev, 1446 "Unknown %s revision, defaulting to highest\n", 1447 up->name); 1448 /* highest possible revision */ 1449 major = 0xff; 1450 minor = 0xff; 1451 } 1452 1453 /* normalize revision for the driver */ 1454 revision = UART_BUILD_REVISION(major, minor); 1455 1456 switch (revision) { 1457 case OMAP_UART_REV_46: 1458 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1459 UART_ERRATA_i291_DMA_FORCEIDLE); 1460 break; 1461 case OMAP_UART_REV_52: 1462 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1463 UART_ERRATA_i291_DMA_FORCEIDLE); 1464 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP; 1465 break; 1466 case OMAP_UART_REV_63: 1467 up->errata |= UART_ERRATA_i202_MDR1_ACCESS; 1468 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP; 1469 break; 1470 default: 1471 break; 1472 } 1473 } 1474 1475 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev) 1476 { 1477 struct omap_uart_port_info *omap_up_info; 1478 1479 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL); 1480 if (!omap_up_info) 1481 return NULL; /* out of memory */ 1482 1483 of_property_read_u32(dev->of_node, "clock-frequency", 1484 &omap_up_info->uartclk); 1485 1486 omap_up_info->flags = UPF_BOOT_AUTOCONF; 1487 1488 return omap_up_info; 1489 } 1490 1491 static int serial_omap_probe_rs485(struct uart_omap_port *up, 1492 struct device *dev) 1493 { 1494 struct serial_rs485 *rs485conf = &up->port.rs485; 1495 struct device_node *np = dev->of_node; 1496 enum gpiod_flags gflags; 1497 int ret; 1498 1499 rs485conf->flags = 0; 1500 up->rts_gpiod = NULL; 1501 1502 if (!np) 1503 return 0; 1504 1505 ret = uart_get_rs485_mode(&up->port); 1506 if (ret) 1507 return ret; 1508 1509 if (of_property_read_bool(np, "rs485-rts-active-high")) { 1510 rs485conf->flags |= SER_RS485_RTS_ON_SEND; 1511 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 1512 } else { 1513 rs485conf->flags &= ~SER_RS485_RTS_ON_SEND; 1514 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 1515 } 1516 1517 /* check for tx enable gpio */ 1518 gflags = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ? 1519 GPIOD_OUT_HIGH : GPIOD_OUT_LOW; 1520 up->rts_gpiod = devm_gpiod_get_optional(dev, "rts", gflags); 1521 if (IS_ERR(up->rts_gpiod)) { 1522 ret = PTR_ERR(up->rts_gpiod); 1523 if (ret == -EPROBE_DEFER) 1524 return ret; 1525 1526 up->rts_gpiod = NULL; 1527 up->port.rs485_supported = (const struct serial_rs485) { }; 1528 if (rs485conf->flags & SER_RS485_ENABLED) { 1529 dev_err(dev, "disabling RS-485 (rts-gpio missing in device tree)\n"); 1530 memset(rs485conf, 0, sizeof(*rs485conf)); 1531 } 1532 } else { 1533 gpiod_set_consumer_name(up->rts_gpiod, "omap-serial"); 1534 } 1535 1536 return 0; 1537 } 1538 1539 static const struct serial_rs485 serial_omap_rs485_supported = { 1540 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND | 1541 SER_RS485_RX_DURING_TX, 1542 .delay_rts_before_send = 1, 1543 .delay_rts_after_send = 1, 1544 }; 1545 1546 static int serial_omap_probe(struct platform_device *pdev) 1547 { 1548 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev); 1549 struct uart_omap_port *up; 1550 struct resource *mem; 1551 void __iomem *base; 1552 int uartirq = 0; 1553 int wakeirq = 0; 1554 int ret; 1555 1556 /* The optional wakeirq may be specified in the board dts file */ 1557 if (pdev->dev.of_node) { 1558 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1559 if (!uartirq) 1560 return -EPROBE_DEFER; 1561 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1); 1562 omap_up_info = of_get_uart_port_info(&pdev->dev); 1563 pdev->dev.platform_data = omap_up_info; 1564 } else { 1565 uartirq = platform_get_irq(pdev, 0); 1566 if (uartirq < 0) 1567 return -EPROBE_DEFER; 1568 } 1569 1570 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL); 1571 if (!up) 1572 return -ENOMEM; 1573 1574 base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 1575 if (IS_ERR(base)) 1576 return PTR_ERR(base); 1577 1578 up->dev = &pdev->dev; 1579 up->port.dev = &pdev->dev; 1580 up->port.type = PORT_OMAP; 1581 up->port.iotype = UPIO_MEM; 1582 up->port.irq = uartirq; 1583 up->port.regshift = 2; 1584 up->port.fifosize = 64; 1585 up->port.ops = &serial_omap_pops; 1586 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_OMAP_CONSOLE); 1587 1588 if (pdev->dev.of_node) 1589 ret = of_alias_get_id(pdev->dev.of_node, "serial"); 1590 else 1591 ret = pdev->id; 1592 1593 if (ret < 0) { 1594 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", 1595 ret); 1596 goto err_port_line; 1597 } 1598 up->port.line = ret; 1599 1600 if (up->port.line >= OMAP_MAX_HSUART_PORTS) { 1601 dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line, 1602 OMAP_MAX_HSUART_PORTS); 1603 ret = -ENXIO; 1604 goto err_port_line; 1605 } 1606 1607 up->wakeirq = wakeirq; 1608 if (!up->wakeirq) 1609 dev_info(up->port.dev, "no wakeirq for uart%d\n", 1610 up->port.line); 1611 1612 ret = serial_omap_probe_rs485(up, &pdev->dev); 1613 if (ret < 0) 1614 goto err_rs485; 1615 1616 sprintf(up->name, "OMAP UART%d", up->port.line); 1617 up->port.mapbase = mem->start; 1618 up->port.membase = base; 1619 up->port.flags = omap_up_info->flags; 1620 up->port.uartclk = omap_up_info->uartclk; 1621 up->port.rs485_config = serial_omap_config_rs485; 1622 up->port.rs485_supported = serial_omap_rs485_supported; 1623 if (!up->port.uartclk) { 1624 up->port.uartclk = DEFAULT_CLK_SPEED; 1625 dev_warn(&pdev->dev, 1626 "No clock speed specified: using default: %d\n", 1627 DEFAULT_CLK_SPEED); 1628 } 1629 1630 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1631 up->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1632 cpu_latency_qos_add_request(&up->pm_qos_request, up->latency); 1633 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); 1634 1635 platform_set_drvdata(pdev, up); 1636 if (omap_up_info->autosuspend_timeout == 0) 1637 omap_up_info->autosuspend_timeout = -1; 1638 1639 device_init_wakeup(up->dev, true); 1640 1641 pm_runtime_enable(&pdev->dev); 1642 1643 pm_runtime_get_sync(&pdev->dev); 1644 1645 omap_serial_fill_features_erratas(up); 1646 1647 ui[up->port.line] = up; 1648 serial_omap_add_console_port(up); 1649 1650 ret = uart_add_one_port(&serial_omap_reg, &up->port); 1651 if (ret != 0) 1652 goto err_add_port; 1653 1654 return 0; 1655 1656 err_add_port: 1657 pm_runtime_put_sync(&pdev->dev); 1658 pm_runtime_disable(&pdev->dev); 1659 cpu_latency_qos_remove_request(&up->pm_qos_request); 1660 device_init_wakeup(up->dev, false); 1661 err_rs485: 1662 err_port_line: 1663 return ret; 1664 } 1665 1666 static int serial_omap_remove(struct platform_device *dev) 1667 { 1668 struct uart_omap_port *up = platform_get_drvdata(dev); 1669 1670 pm_runtime_get_sync(up->dev); 1671 1672 uart_remove_one_port(&serial_omap_reg, &up->port); 1673 1674 pm_runtime_put_sync(up->dev); 1675 pm_runtime_disable(up->dev); 1676 cpu_latency_qos_remove_request(&up->pm_qos_request); 1677 device_init_wakeup(&dev->dev, false); 1678 1679 return 0; 1680 } 1681 1682 /* 1683 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 1684 * The access to uart register after MDR1 Access 1685 * causes UART to corrupt data. 1686 * 1687 * Need a delay = 1688 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 1689 * give 10 times as much 1690 */ 1691 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1) 1692 { 1693 u8 timeout = 255; 1694 1695 serial_out(up, UART_OMAP_MDR1, mdr1); 1696 udelay(2); 1697 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 1698 UART_FCR_CLEAR_RCVR); 1699 /* 1700 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 1701 * TX_FIFO_E bit is 1. 1702 */ 1703 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 1704 (UART_LSR_THRE | UART_LSR_DR))) { 1705 timeout--; 1706 if (!timeout) { 1707 /* Should *never* happen. we warn and carry on */ 1708 dev_crit(up->dev, "Errata i202: timedout %x\n", 1709 serial_in(up, UART_LSR)); 1710 break; 1711 } 1712 udelay(1); 1713 } 1714 } 1715 1716 #ifdef CONFIG_PM 1717 static void serial_omap_restore_context(struct uart_omap_port *up) 1718 { 1719 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1720 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE); 1721 else 1722 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); 1723 1724 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1725 serial_out(up, UART_EFR, UART_EFR_ECB); 1726 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1727 serial_out(up, UART_IER, 0x0); 1728 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1729 serial_out(up, UART_DLL, up->dll); 1730 serial_out(up, UART_DLM, up->dlh); 1731 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1732 serial_out(up, UART_IER, up->ier); 1733 serial_out(up, UART_FCR, up->fcr); 1734 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1735 serial_out(up, UART_MCR, up->mcr); 1736 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1737 serial_out(up, UART_OMAP_SCR, up->scr); 1738 serial_out(up, UART_EFR, up->efr); 1739 serial_out(up, UART_LCR, up->lcr); 1740 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1741 serial_omap_mdr1_errataset(up, up->mdr1); 1742 else 1743 serial_out(up, UART_OMAP_MDR1, up->mdr1); 1744 serial_out(up, UART_OMAP_WER, up->wer); 1745 } 1746 1747 static int serial_omap_runtime_suspend(struct device *dev) 1748 { 1749 struct uart_omap_port *up = dev_get_drvdata(dev); 1750 1751 if (!up) 1752 return -EINVAL; 1753 1754 /* 1755 * When using 'no_console_suspend', the console UART must not be 1756 * suspended. Since driver suspend is managed by runtime suspend, 1757 * preventing runtime suspend (by returning error) will keep device 1758 * active during suspend. 1759 */ 1760 if (up->is_suspending && !console_suspend_enabled && 1761 uart_console(&up->port)) 1762 return -EBUSY; 1763 1764 up->context_loss_cnt = serial_omap_get_context_loss_count(up); 1765 1766 serial_omap_enable_wakeup(up, true); 1767 1768 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1769 schedule_work(&up->qos_work); 1770 1771 return 0; 1772 } 1773 1774 static int serial_omap_runtime_resume(struct device *dev) 1775 { 1776 struct uart_omap_port *up = dev_get_drvdata(dev); 1777 1778 int loss_cnt = serial_omap_get_context_loss_count(up); 1779 1780 serial_omap_enable_wakeup(up, false); 1781 1782 if (loss_cnt < 0) { 1783 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n", 1784 loss_cnt); 1785 serial_omap_restore_context(up); 1786 } else if (up->context_loss_cnt != loss_cnt) { 1787 serial_omap_restore_context(up); 1788 } 1789 up->latency = up->calc_latency; 1790 schedule_work(&up->qos_work); 1791 1792 return 0; 1793 } 1794 #endif 1795 1796 static const struct dev_pm_ops serial_omap_dev_pm_ops = { 1797 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume) 1798 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend, 1799 serial_omap_runtime_resume, NULL) 1800 .prepare = serial_omap_prepare, 1801 .complete = serial_omap_complete, 1802 }; 1803 1804 #if defined(CONFIG_OF) 1805 static const struct of_device_id omap_serial_of_match[] = { 1806 { .compatible = "ti,omap2-uart" }, 1807 { .compatible = "ti,omap3-uart" }, 1808 { .compatible = "ti,omap4-uart" }, 1809 {}, 1810 }; 1811 MODULE_DEVICE_TABLE(of, omap_serial_of_match); 1812 #endif 1813 1814 static struct platform_driver serial_omap_driver = { 1815 .probe = serial_omap_probe, 1816 .remove = serial_omap_remove, 1817 .driver = { 1818 .name = OMAP_SERIAL_DRIVER_NAME, 1819 .pm = &serial_omap_dev_pm_ops, 1820 .of_match_table = of_match_ptr(omap_serial_of_match), 1821 }, 1822 }; 1823 1824 static int __init serial_omap_init(void) 1825 { 1826 int ret; 1827 1828 ret = uart_register_driver(&serial_omap_reg); 1829 if (ret != 0) 1830 return ret; 1831 ret = platform_driver_register(&serial_omap_driver); 1832 if (ret != 0) 1833 uart_unregister_driver(&serial_omap_reg); 1834 return ret; 1835 } 1836 1837 static void __exit serial_omap_exit(void) 1838 { 1839 platform_driver_unregister(&serial_omap_driver); 1840 uart_unregister_driver(&serial_omap_reg); 1841 } 1842 1843 module_init(serial_omap_init); 1844 module_exit(serial_omap_exit); 1845 1846 MODULE_DESCRIPTION("OMAP High Speed UART driver"); 1847 MODULE_LICENSE("GPL"); 1848 MODULE_AUTHOR("Texas Instruments Inc"); 1849