1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for OMAP-UART controller. 4 * Based on drivers/serial/8250.c 5 * 6 * Copyright (C) 2010 Texas Instruments. 7 * 8 * Authors: 9 * Govindraj R <govindraj.raja@ti.com> 10 * Thara Gopinath <thara@ti.com> 11 * 12 * Note: This driver is made separate from 8250 driver as we cannot 13 * over load 8250 driver with omap platform specific configuration for 14 * features like DMA, it makes easier to implement features like DMA and 15 * hardware flow control and software flow control configuration with 16 * this driver as required for the omap-platform. 17 */ 18 19 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 20 #define SUPPORT_SYSRQ 21 #endif 22 23 #include <linux/module.h> 24 #include <linux/init.h> 25 #include <linux/console.h> 26 #include <linux/serial_reg.h> 27 #include <linux/delay.h> 28 #include <linux/slab.h> 29 #include <linux/tty.h> 30 #include <linux/tty_flip.h> 31 #include <linux/platform_device.h> 32 #include <linux/io.h> 33 #include <linux/clk.h> 34 #include <linux/serial_core.h> 35 #include <linux/irq.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/pm_wakeirq.h> 38 #include <linux/of.h> 39 #include <linux/of_irq.h> 40 #include <linux/gpio.h> 41 #include <linux/of_gpio.h> 42 #include <linux/platform_data/serial-omap.h> 43 44 #include <dt-bindings/gpio/gpio.h> 45 46 #define OMAP_MAX_HSUART_PORTS 10 47 48 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 49 50 #define OMAP_UART_REV_42 0x0402 51 #define OMAP_UART_REV_46 0x0406 52 #define OMAP_UART_REV_52 0x0502 53 #define OMAP_UART_REV_63 0x0603 54 55 #define OMAP_UART_TX_WAKEUP_EN BIT(7) 56 57 /* Feature flags */ 58 #define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0) 59 60 #define UART_ERRATA_i202_MDR1_ACCESS BIT(0) 61 #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1) 62 63 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */ 64 65 /* SCR register bitmasks */ 66 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 67 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 68 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 69 70 /* FCR register bitmasks */ 71 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6) 72 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4) 73 74 /* MVR register bitmasks */ 75 #define OMAP_UART_MVR_SCHEME_SHIFT 30 76 77 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 78 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 79 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 80 81 #define OMAP_UART_MVR_MAJ_MASK 0x700 82 #define OMAP_UART_MVR_MAJ_SHIFT 8 83 #define OMAP_UART_MVR_MIN_MASK 0x3f 84 85 #define OMAP_UART_DMA_CH_FREE -1 86 87 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA 88 #define OMAP_MODE13X_SPEED 230400 89 90 /* WER = 0x7F 91 * Enable module level wakeup in WER reg 92 */ 93 #define OMAP_UART_WER_MOD_WKUP 0x7F 94 95 /* Enable XON/XOFF flow control on output */ 96 #define OMAP_UART_SW_TX 0x08 97 98 /* Enable XON/XOFF flow control on input */ 99 #define OMAP_UART_SW_RX 0x02 100 101 #define OMAP_UART_SW_CLR 0xF0 102 103 #define OMAP_UART_TCR_TRIG 0x0F 104 105 struct uart_omap_dma { 106 u8 uart_dma_tx; 107 u8 uart_dma_rx; 108 int rx_dma_channel; 109 int tx_dma_channel; 110 dma_addr_t rx_buf_dma_phys; 111 dma_addr_t tx_buf_dma_phys; 112 unsigned int uart_base; 113 /* 114 * Buffer for rx dma. It is not required for tx because the buffer 115 * comes from port structure. 116 */ 117 unsigned char *rx_buf; 118 unsigned int prev_rx_dma_pos; 119 int tx_buf_size; 120 int tx_dma_used; 121 int rx_dma_used; 122 spinlock_t tx_lock; 123 spinlock_t rx_lock; 124 /* timer to poll activity on rx dma */ 125 struct timer_list rx_timer; 126 unsigned int rx_buf_size; 127 unsigned int rx_poll_rate; 128 unsigned int rx_timeout; 129 }; 130 131 struct uart_omap_port { 132 struct uart_port port; 133 struct uart_omap_dma uart_dma; 134 struct device *dev; 135 int wakeirq; 136 137 unsigned char ier; 138 unsigned char lcr; 139 unsigned char mcr; 140 unsigned char fcr; 141 unsigned char efr; 142 unsigned char dll; 143 unsigned char dlh; 144 unsigned char mdr1; 145 unsigned char scr; 146 unsigned char wer; 147 148 int use_dma; 149 /* 150 * Some bits in registers are cleared on a read, so they must 151 * be saved whenever the register is read, but the bits will not 152 * be immediately processed. 153 */ 154 unsigned int lsr_break_flag; 155 unsigned char msr_saved_flags; 156 char name[20]; 157 unsigned long port_activity; 158 int context_loss_cnt; 159 u32 errata; 160 u32 features; 161 162 int rts_gpio; 163 164 struct pm_qos_request pm_qos_request; 165 u32 latency; 166 u32 calc_latency; 167 struct work_struct qos_work; 168 bool is_suspending; 169 }; 170 171 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port))) 172 173 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; 174 175 /* Forward declaration of functions */ 176 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1); 177 178 static inline unsigned int serial_in(struct uart_omap_port *up, int offset) 179 { 180 offset <<= up->port.regshift; 181 return readw(up->port.membase + offset); 182 } 183 184 static inline void serial_out(struct uart_omap_port *up, int offset, int value) 185 { 186 offset <<= up->port.regshift; 187 writew(value, up->port.membase + offset); 188 } 189 190 static inline void serial_omap_clear_fifos(struct uart_omap_port *up) 191 { 192 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 193 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 194 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 195 serial_out(up, UART_FCR, 0); 196 } 197 198 #ifdef CONFIG_PM 199 static int serial_omap_get_context_loss_count(struct uart_omap_port *up) 200 { 201 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev); 202 203 if (!pdata || !pdata->get_context_loss_count) 204 return -EINVAL; 205 206 return pdata->get_context_loss_count(up->dev); 207 } 208 209 /* REVISIT: Remove this when omap3 boots in device tree only mode */ 210 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable) 211 { 212 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev); 213 214 if (!pdata || !pdata->enable_wakeup) 215 return; 216 217 pdata->enable_wakeup(up->dev, enable); 218 } 219 #endif /* CONFIG_PM */ 220 221 /* 222 * Calculate the absolute difference between the desired and actual baud 223 * rate for the given mode. 224 */ 225 static inline int calculate_baud_abs_diff(struct uart_port *port, 226 unsigned int baud, unsigned int mode) 227 { 228 unsigned int n = port->uartclk / (mode * baud); 229 int abs_diff; 230 231 if (n == 0) 232 n = 1; 233 234 abs_diff = baud - (port->uartclk / (mode * n)); 235 if (abs_diff < 0) 236 abs_diff = -abs_diff; 237 238 return abs_diff; 239 } 240 241 /* 242 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X 243 * @port: uart port info 244 * @baud: baudrate for which mode needs to be determined 245 * 246 * Returns true if baud rate is MODE16X and false if MODE13X 247 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values, 248 * and Error Rates" determines modes not for all common baud rates. 249 * E.g. for 1000000 baud rate mode must be 16x, but according to that 250 * table it's determined as 13x. 251 */ 252 static bool 253 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud) 254 { 255 int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13); 256 int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16); 257 258 return (abs_diff_13 >= abs_diff_16); 259 } 260 261 /* 262 * serial_omap_get_divisor - calculate divisor value 263 * @port: uart port info 264 * @baud: baudrate for which divisor needs to be calculated. 265 */ 266 static unsigned int 267 serial_omap_get_divisor(struct uart_port *port, unsigned int baud) 268 { 269 unsigned int mode; 270 271 if (!serial_omap_baud_is_mode16(port, baud)) 272 mode = 13; 273 else 274 mode = 16; 275 return port->uartclk/(mode * baud); 276 } 277 278 static void serial_omap_enable_ms(struct uart_port *port) 279 { 280 struct uart_omap_port *up = to_uart_omap_port(port); 281 282 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line); 283 284 pm_runtime_get_sync(up->dev); 285 up->ier |= UART_IER_MSI; 286 serial_out(up, UART_IER, up->ier); 287 pm_runtime_mark_last_busy(up->dev); 288 pm_runtime_put_autosuspend(up->dev); 289 } 290 291 static void serial_omap_stop_tx(struct uart_port *port) 292 { 293 struct uart_omap_port *up = to_uart_omap_port(port); 294 int res; 295 296 pm_runtime_get_sync(up->dev); 297 298 /* Handle RS-485 */ 299 if (port->rs485.flags & SER_RS485_ENABLED) { 300 if (up->scr & OMAP_UART_SCR_TX_EMPTY) { 301 /* THR interrupt is fired when both TX FIFO and TX 302 * shift register are empty. This means there's nothing 303 * left to transmit now, so make sure the THR interrupt 304 * is fired when TX FIFO is below the trigger level, 305 * disable THR interrupts and toggle the RS-485 GPIO 306 * data direction pin if needed. 307 */ 308 up->scr &= ~OMAP_UART_SCR_TX_EMPTY; 309 serial_out(up, UART_OMAP_SCR, up->scr); 310 res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 311 1 : 0; 312 if (gpio_get_value(up->rts_gpio) != res) { 313 if (port->rs485.delay_rts_after_send > 0) 314 mdelay( 315 port->rs485.delay_rts_after_send); 316 gpio_set_value(up->rts_gpio, res); 317 } 318 } else { 319 /* We're asked to stop, but there's still stuff in the 320 * UART FIFO, so make sure the THR interrupt is fired 321 * when both TX FIFO and TX shift register are empty. 322 * The next THR interrupt (if no transmission is started 323 * in the meantime) will indicate the end of a 324 * transmission. Therefore we _don't_ disable THR 325 * interrupts in this situation. 326 */ 327 up->scr |= OMAP_UART_SCR_TX_EMPTY; 328 serial_out(up, UART_OMAP_SCR, up->scr); 329 return; 330 } 331 } 332 333 if (up->ier & UART_IER_THRI) { 334 up->ier &= ~UART_IER_THRI; 335 serial_out(up, UART_IER, up->ier); 336 } 337 338 if ((port->rs485.flags & SER_RS485_ENABLED) && 339 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) { 340 /* 341 * Empty the RX FIFO, we are not interested in anything 342 * received during the half-duplex transmission. 343 */ 344 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR); 345 /* Re-enable RX interrupts */ 346 up->ier |= UART_IER_RLSI | UART_IER_RDI; 347 up->port.read_status_mask |= UART_LSR_DR; 348 serial_out(up, UART_IER, up->ier); 349 } 350 351 pm_runtime_mark_last_busy(up->dev); 352 pm_runtime_put_autosuspend(up->dev); 353 } 354 355 static void serial_omap_stop_rx(struct uart_port *port) 356 { 357 struct uart_omap_port *up = to_uart_omap_port(port); 358 359 pm_runtime_get_sync(up->dev); 360 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 361 up->port.read_status_mask &= ~UART_LSR_DR; 362 serial_out(up, UART_IER, up->ier); 363 pm_runtime_mark_last_busy(up->dev); 364 pm_runtime_put_autosuspend(up->dev); 365 } 366 367 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr) 368 { 369 struct circ_buf *xmit = &up->port.state->xmit; 370 int count; 371 372 if (up->port.x_char) { 373 serial_out(up, UART_TX, up->port.x_char); 374 up->port.icount.tx++; 375 up->port.x_char = 0; 376 return; 377 } 378 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 379 serial_omap_stop_tx(&up->port); 380 return; 381 } 382 count = up->port.fifosize / 4; 383 do { 384 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 385 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 386 up->port.icount.tx++; 387 if (uart_circ_empty(xmit)) 388 break; 389 } while (--count > 0); 390 391 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 392 uart_write_wakeup(&up->port); 393 394 if (uart_circ_empty(xmit)) 395 serial_omap_stop_tx(&up->port); 396 } 397 398 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) 399 { 400 if (!(up->ier & UART_IER_THRI)) { 401 up->ier |= UART_IER_THRI; 402 serial_out(up, UART_IER, up->ier); 403 } 404 } 405 406 static void serial_omap_start_tx(struct uart_port *port) 407 { 408 struct uart_omap_port *up = to_uart_omap_port(port); 409 int res; 410 411 pm_runtime_get_sync(up->dev); 412 413 /* Handle RS-485 */ 414 if (port->rs485.flags & SER_RS485_ENABLED) { 415 /* Fire THR interrupts when FIFO is below trigger level */ 416 up->scr &= ~OMAP_UART_SCR_TX_EMPTY; 417 serial_out(up, UART_OMAP_SCR, up->scr); 418 419 /* if rts not already enabled */ 420 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0; 421 if (gpio_get_value(up->rts_gpio) != res) { 422 gpio_set_value(up->rts_gpio, res); 423 if (port->rs485.delay_rts_before_send > 0) 424 mdelay(port->rs485.delay_rts_before_send); 425 } 426 } 427 428 if ((port->rs485.flags & SER_RS485_ENABLED) && 429 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) 430 serial_omap_stop_rx(port); 431 432 serial_omap_enable_ier_thri(up); 433 pm_runtime_mark_last_busy(up->dev); 434 pm_runtime_put_autosuspend(up->dev); 435 } 436 437 static void serial_omap_throttle(struct uart_port *port) 438 { 439 struct uart_omap_port *up = to_uart_omap_port(port); 440 unsigned long flags; 441 442 pm_runtime_get_sync(up->dev); 443 spin_lock_irqsave(&up->port.lock, flags); 444 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 445 serial_out(up, UART_IER, up->ier); 446 spin_unlock_irqrestore(&up->port.lock, flags); 447 pm_runtime_mark_last_busy(up->dev); 448 pm_runtime_put_autosuspend(up->dev); 449 } 450 451 static void serial_omap_unthrottle(struct uart_port *port) 452 { 453 struct uart_omap_port *up = to_uart_omap_port(port); 454 unsigned long flags; 455 456 pm_runtime_get_sync(up->dev); 457 spin_lock_irqsave(&up->port.lock, flags); 458 up->ier |= UART_IER_RLSI | UART_IER_RDI; 459 serial_out(up, UART_IER, up->ier); 460 spin_unlock_irqrestore(&up->port.lock, flags); 461 pm_runtime_mark_last_busy(up->dev); 462 pm_runtime_put_autosuspend(up->dev); 463 } 464 465 static unsigned int check_modem_status(struct uart_omap_port *up) 466 { 467 unsigned int status; 468 469 status = serial_in(up, UART_MSR); 470 status |= up->msr_saved_flags; 471 up->msr_saved_flags = 0; 472 if ((status & UART_MSR_ANY_DELTA) == 0) 473 return status; 474 475 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && 476 up->port.state != NULL) { 477 if (status & UART_MSR_TERI) 478 up->port.icount.rng++; 479 if (status & UART_MSR_DDSR) 480 up->port.icount.dsr++; 481 if (status & UART_MSR_DDCD) 482 uart_handle_dcd_change 483 (&up->port, status & UART_MSR_DCD); 484 if (status & UART_MSR_DCTS) 485 uart_handle_cts_change 486 (&up->port, status & UART_MSR_CTS); 487 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 488 } 489 490 return status; 491 } 492 493 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr) 494 { 495 unsigned int flag; 496 497 /* 498 * Read one data character out to avoid stalling the receiver according 499 * to the table 23-246 of the omap4 TRM. 500 */ 501 if (likely(lsr & UART_LSR_DR)) 502 serial_in(up, UART_RX); 503 504 up->port.icount.rx++; 505 flag = TTY_NORMAL; 506 507 if (lsr & UART_LSR_BI) { 508 flag = TTY_BREAK; 509 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 510 up->port.icount.brk++; 511 /* 512 * We do the SysRQ and SAK checking 513 * here because otherwise the break 514 * may get masked by ignore_status_mask 515 * or read_status_mask. 516 */ 517 if (uart_handle_break(&up->port)) 518 return; 519 520 } 521 522 if (lsr & UART_LSR_PE) { 523 flag = TTY_PARITY; 524 up->port.icount.parity++; 525 } 526 527 if (lsr & UART_LSR_FE) { 528 flag = TTY_FRAME; 529 up->port.icount.frame++; 530 } 531 532 if (lsr & UART_LSR_OE) 533 up->port.icount.overrun++; 534 535 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 536 if (up->port.line == up->port.cons->index) { 537 /* Recover the break flag from console xmit */ 538 lsr |= up->lsr_break_flag; 539 } 540 #endif 541 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag); 542 } 543 544 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr) 545 { 546 unsigned char ch = 0; 547 unsigned int flag; 548 549 if (!(lsr & UART_LSR_DR)) 550 return; 551 552 ch = serial_in(up, UART_RX); 553 flag = TTY_NORMAL; 554 up->port.icount.rx++; 555 556 if (uart_handle_sysrq_char(&up->port, ch)) 557 return; 558 559 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); 560 } 561 562 /** 563 * serial_omap_irq() - This handles the interrupt from one port 564 * @irq: uart port irq number 565 * @dev_id: uart port info 566 */ 567 static irqreturn_t serial_omap_irq(int irq, void *dev_id) 568 { 569 struct uart_omap_port *up = dev_id; 570 unsigned int iir, lsr; 571 unsigned int type; 572 irqreturn_t ret = IRQ_NONE; 573 int max_count = 256; 574 575 spin_lock(&up->port.lock); 576 pm_runtime_get_sync(up->dev); 577 578 do { 579 iir = serial_in(up, UART_IIR); 580 if (iir & UART_IIR_NO_INT) 581 break; 582 583 ret = IRQ_HANDLED; 584 lsr = serial_in(up, UART_LSR); 585 586 /* extract IRQ type from IIR register */ 587 type = iir & 0x3e; 588 589 switch (type) { 590 case UART_IIR_MSI: 591 check_modem_status(up); 592 break; 593 case UART_IIR_THRI: 594 transmit_chars(up, lsr); 595 break; 596 case UART_IIR_RX_TIMEOUT: 597 /* FALLTHROUGH */ 598 case UART_IIR_RDI: 599 serial_omap_rdi(up, lsr); 600 break; 601 case UART_IIR_RLSI: 602 serial_omap_rlsi(up, lsr); 603 break; 604 case UART_IIR_CTS_RTS_DSR: 605 /* simply try again */ 606 break; 607 case UART_IIR_XOFF: 608 /* FALLTHROUGH */ 609 default: 610 break; 611 } 612 } while (max_count--); 613 614 spin_unlock(&up->port.lock); 615 616 tty_flip_buffer_push(&up->port.state->port); 617 618 pm_runtime_mark_last_busy(up->dev); 619 pm_runtime_put_autosuspend(up->dev); 620 up->port_activity = jiffies; 621 622 return ret; 623 } 624 625 static unsigned int serial_omap_tx_empty(struct uart_port *port) 626 { 627 struct uart_omap_port *up = to_uart_omap_port(port); 628 unsigned long flags = 0; 629 unsigned int ret = 0; 630 631 pm_runtime_get_sync(up->dev); 632 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line); 633 spin_lock_irqsave(&up->port.lock, flags); 634 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 635 spin_unlock_irqrestore(&up->port.lock, flags); 636 pm_runtime_mark_last_busy(up->dev); 637 pm_runtime_put_autosuspend(up->dev); 638 return ret; 639 } 640 641 static unsigned int serial_omap_get_mctrl(struct uart_port *port) 642 { 643 struct uart_omap_port *up = to_uart_omap_port(port); 644 unsigned int status; 645 unsigned int ret = 0; 646 647 pm_runtime_get_sync(up->dev); 648 status = check_modem_status(up); 649 pm_runtime_mark_last_busy(up->dev); 650 pm_runtime_put_autosuspend(up->dev); 651 652 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line); 653 654 if (status & UART_MSR_DCD) 655 ret |= TIOCM_CAR; 656 if (status & UART_MSR_RI) 657 ret |= TIOCM_RNG; 658 if (status & UART_MSR_DSR) 659 ret |= TIOCM_DSR; 660 if (status & UART_MSR_CTS) 661 ret |= TIOCM_CTS; 662 return ret; 663 } 664 665 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) 666 { 667 struct uart_omap_port *up = to_uart_omap_port(port); 668 unsigned char mcr = 0, old_mcr, lcr; 669 670 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line); 671 if (mctrl & TIOCM_RTS) 672 mcr |= UART_MCR_RTS; 673 if (mctrl & TIOCM_DTR) 674 mcr |= UART_MCR_DTR; 675 if (mctrl & TIOCM_OUT1) 676 mcr |= UART_MCR_OUT1; 677 if (mctrl & TIOCM_OUT2) 678 mcr |= UART_MCR_OUT2; 679 if (mctrl & TIOCM_LOOP) 680 mcr |= UART_MCR_LOOP; 681 682 pm_runtime_get_sync(up->dev); 683 old_mcr = serial_in(up, UART_MCR); 684 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 | 685 UART_MCR_DTR | UART_MCR_RTS); 686 up->mcr = old_mcr | mcr; 687 serial_out(up, UART_MCR, up->mcr); 688 689 /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */ 690 lcr = serial_in(up, UART_LCR); 691 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 692 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 693 up->efr |= UART_EFR_RTS; 694 else 695 up->efr &= ~UART_EFR_RTS; 696 serial_out(up, UART_EFR, up->efr); 697 serial_out(up, UART_LCR, lcr); 698 699 pm_runtime_mark_last_busy(up->dev); 700 pm_runtime_put_autosuspend(up->dev); 701 } 702 703 static void serial_omap_break_ctl(struct uart_port *port, int break_state) 704 { 705 struct uart_omap_port *up = to_uart_omap_port(port); 706 unsigned long flags = 0; 707 708 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line); 709 pm_runtime_get_sync(up->dev); 710 spin_lock_irqsave(&up->port.lock, flags); 711 if (break_state == -1) 712 up->lcr |= UART_LCR_SBC; 713 else 714 up->lcr &= ~UART_LCR_SBC; 715 serial_out(up, UART_LCR, up->lcr); 716 spin_unlock_irqrestore(&up->port.lock, flags); 717 pm_runtime_mark_last_busy(up->dev); 718 pm_runtime_put_autosuspend(up->dev); 719 } 720 721 static int serial_omap_startup(struct uart_port *port) 722 { 723 struct uart_omap_port *up = to_uart_omap_port(port); 724 unsigned long flags = 0; 725 int retval; 726 727 /* 728 * Allocate the IRQ 729 */ 730 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, 731 up->name, up); 732 if (retval) 733 return retval; 734 735 /* Optional wake-up IRQ */ 736 if (up->wakeirq) { 737 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq); 738 if (retval) { 739 free_irq(up->port.irq, up); 740 return retval; 741 } 742 } 743 744 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line); 745 746 pm_runtime_get_sync(up->dev); 747 /* 748 * Clear the FIFO buffers and disable them. 749 * (they will be reenabled in set_termios()) 750 */ 751 serial_omap_clear_fifos(up); 752 753 /* 754 * Clear the interrupt registers. 755 */ 756 (void) serial_in(up, UART_LSR); 757 if (serial_in(up, UART_LSR) & UART_LSR_DR) 758 (void) serial_in(up, UART_RX); 759 (void) serial_in(up, UART_IIR); 760 (void) serial_in(up, UART_MSR); 761 762 /* 763 * Now, initialize the UART 764 */ 765 serial_out(up, UART_LCR, UART_LCR_WLEN8); 766 spin_lock_irqsave(&up->port.lock, flags); 767 /* 768 * Most PC uarts need OUT2 raised to enable interrupts. 769 */ 770 up->port.mctrl |= TIOCM_OUT2; 771 serial_omap_set_mctrl(&up->port, up->port.mctrl); 772 spin_unlock_irqrestore(&up->port.lock, flags); 773 774 up->msr_saved_flags = 0; 775 /* 776 * Finally, enable interrupts. Note: Modem status interrupts 777 * are set via set_termios(), which will be occurring imminently 778 * anyway, so we don't enable them here. 779 */ 780 up->ier = UART_IER_RLSI | UART_IER_RDI; 781 serial_out(up, UART_IER, up->ier); 782 783 /* Enable module level wake up */ 784 up->wer = OMAP_UART_WER_MOD_WKUP; 785 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP) 786 up->wer |= OMAP_UART_TX_WAKEUP_EN; 787 788 serial_out(up, UART_OMAP_WER, up->wer); 789 790 pm_runtime_mark_last_busy(up->dev); 791 pm_runtime_put_autosuspend(up->dev); 792 up->port_activity = jiffies; 793 return 0; 794 } 795 796 static void serial_omap_shutdown(struct uart_port *port) 797 { 798 struct uart_omap_port *up = to_uart_omap_port(port); 799 unsigned long flags = 0; 800 801 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line); 802 803 pm_runtime_get_sync(up->dev); 804 /* 805 * Disable interrupts from this port 806 */ 807 up->ier = 0; 808 serial_out(up, UART_IER, 0); 809 810 spin_lock_irqsave(&up->port.lock, flags); 811 up->port.mctrl &= ~TIOCM_OUT2; 812 serial_omap_set_mctrl(&up->port, up->port.mctrl); 813 spin_unlock_irqrestore(&up->port.lock, flags); 814 815 /* 816 * Disable break condition and FIFOs 817 */ 818 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); 819 serial_omap_clear_fifos(up); 820 821 /* 822 * Read data port to reset things, and then free the irq 823 */ 824 if (serial_in(up, UART_LSR) & UART_LSR_DR) 825 (void) serial_in(up, UART_RX); 826 827 pm_runtime_mark_last_busy(up->dev); 828 pm_runtime_put_autosuspend(up->dev); 829 free_irq(up->port.irq, up); 830 dev_pm_clear_wake_irq(up->dev); 831 } 832 833 static void serial_omap_uart_qos_work(struct work_struct *work) 834 { 835 struct uart_omap_port *up = container_of(work, struct uart_omap_port, 836 qos_work); 837 838 pm_qos_update_request(&up->pm_qos_request, up->latency); 839 } 840 841 static void 842 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, 843 struct ktermios *old) 844 { 845 struct uart_omap_port *up = to_uart_omap_port(port); 846 unsigned char cval = 0; 847 unsigned long flags = 0; 848 unsigned int baud, quot; 849 850 switch (termios->c_cflag & CSIZE) { 851 case CS5: 852 cval = UART_LCR_WLEN5; 853 break; 854 case CS6: 855 cval = UART_LCR_WLEN6; 856 break; 857 case CS7: 858 cval = UART_LCR_WLEN7; 859 break; 860 default: 861 case CS8: 862 cval = UART_LCR_WLEN8; 863 break; 864 } 865 866 if (termios->c_cflag & CSTOPB) 867 cval |= UART_LCR_STOP; 868 if (termios->c_cflag & PARENB) 869 cval |= UART_LCR_PARITY; 870 if (!(termios->c_cflag & PARODD)) 871 cval |= UART_LCR_EPAR; 872 if (termios->c_cflag & CMSPAR) 873 cval |= UART_LCR_SPAR; 874 875 /* 876 * Ask the core to calculate the divisor for us. 877 */ 878 879 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); 880 quot = serial_omap_get_divisor(port, baud); 881 882 /* calculate wakeup latency constraint */ 883 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8); 884 up->latency = up->calc_latency; 885 schedule_work(&up->qos_work); 886 887 up->dll = quot & 0xff; 888 up->dlh = quot >> 8; 889 up->mdr1 = UART_OMAP_MDR1_DISABLE; 890 891 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | 892 UART_FCR_ENABLE_FIFO; 893 894 /* 895 * Ok, we're now changing the port state. Do it with 896 * interrupts disabled. 897 */ 898 pm_runtime_get_sync(up->dev); 899 spin_lock_irqsave(&up->port.lock, flags); 900 901 /* 902 * Update the per-port timeout. 903 */ 904 uart_update_timeout(port, termios->c_cflag, baud); 905 906 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 907 if (termios->c_iflag & INPCK) 908 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 909 if (termios->c_iflag & (BRKINT | PARMRK)) 910 up->port.read_status_mask |= UART_LSR_BI; 911 912 /* 913 * Characters to ignore 914 */ 915 up->port.ignore_status_mask = 0; 916 if (termios->c_iflag & IGNPAR) 917 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 918 if (termios->c_iflag & IGNBRK) { 919 up->port.ignore_status_mask |= UART_LSR_BI; 920 /* 921 * If we're ignoring parity and break indicators, 922 * ignore overruns too (for real raw support). 923 */ 924 if (termios->c_iflag & IGNPAR) 925 up->port.ignore_status_mask |= UART_LSR_OE; 926 } 927 928 /* 929 * ignore all characters if CREAD is not set 930 */ 931 if ((termios->c_cflag & CREAD) == 0) 932 up->port.ignore_status_mask |= UART_LSR_DR; 933 934 /* 935 * Modem status interrupts 936 */ 937 up->ier &= ~UART_IER_MSI; 938 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 939 up->ier |= UART_IER_MSI; 940 serial_out(up, UART_IER, up->ier); 941 serial_out(up, UART_LCR, cval); /* reset DLAB */ 942 up->lcr = cval; 943 up->scr = 0; 944 945 /* FIFOs and DMA Settings */ 946 947 /* FCR can be changed only when the 948 * baud clock is not running 949 * DLL_REG and DLH_REG set to 0. 950 */ 951 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 952 serial_out(up, UART_DLL, 0); 953 serial_out(up, UART_DLM, 0); 954 serial_out(up, UART_LCR, 0); 955 956 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 957 958 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB; 959 up->efr &= ~UART_EFR_SCD; 960 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 961 962 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 963 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR; 964 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 965 /* FIFO ENABLE, DMA MODE */ 966 967 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; 968 /* 969 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK 970 * sets Enables the granularity of 1 for TRIGGER RX 971 * level. Along with setting RX FIFO trigger level 972 * to 1 (as noted below, 16 characters) and TLR[3:0] 973 * to zero this will result RX FIFO threshold level 974 * to 1 character, instead of 16 as noted in comment 975 * below. 976 */ 977 978 /* Set receive FIFO threshold to 16 characters and 979 * transmit FIFO threshold to 32 spaces 980 */ 981 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; 982 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK; 983 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 | 984 UART_FCR_ENABLE_FIFO; 985 986 serial_out(up, UART_FCR, up->fcr); 987 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 988 989 serial_out(up, UART_OMAP_SCR, up->scr); 990 991 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */ 992 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 993 serial_out(up, UART_MCR, up->mcr); 994 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 995 serial_out(up, UART_EFR, up->efr); 996 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 997 998 /* Protocol, Baud Rate, and Interrupt Settings */ 999 1000 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1001 serial_omap_mdr1_errataset(up, up->mdr1); 1002 else 1003 serial_out(up, UART_OMAP_MDR1, up->mdr1); 1004 1005 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1006 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 1007 1008 serial_out(up, UART_LCR, 0); 1009 serial_out(up, UART_IER, 0); 1010 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1011 1012 serial_out(up, UART_DLL, up->dll); /* LS of divisor */ 1013 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */ 1014 1015 serial_out(up, UART_LCR, 0); 1016 serial_out(up, UART_IER, up->ier); 1017 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1018 1019 serial_out(up, UART_EFR, up->efr); 1020 serial_out(up, UART_LCR, cval); 1021 1022 if (!serial_omap_baud_is_mode16(port, baud)) 1023 up->mdr1 = UART_OMAP_MDR1_13X_MODE; 1024 else 1025 up->mdr1 = UART_OMAP_MDR1_16X_MODE; 1026 1027 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1028 serial_omap_mdr1_errataset(up, up->mdr1); 1029 else 1030 serial_out(up, UART_OMAP_MDR1, up->mdr1); 1031 1032 /* Configure flow control */ 1033 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1034 1035 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */ 1036 serial_out(up, UART_XON1, termios->c_cc[VSTART]); 1037 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); 1038 1039 /* Enable access to TCR/TLR */ 1040 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 1041 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1042 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 1043 1044 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); 1045 1046 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 1047 1048 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { 1049 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 1050 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1051 up->efr |= UART_EFR_CTS; 1052 } else { 1053 /* Disable AUTORTS and AUTOCTS */ 1054 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS); 1055 } 1056 1057 if (up->port.flags & UPF_SOFT_FLOW) { 1058 /* clear SW control mode bits */ 1059 up->efr &= OMAP_UART_SW_CLR; 1060 1061 /* 1062 * IXON Flag: 1063 * Enable XON/XOFF flow control on input. 1064 * Receiver compares XON1, XOFF1. 1065 */ 1066 if (termios->c_iflag & IXON) 1067 up->efr |= OMAP_UART_SW_RX; 1068 1069 /* 1070 * IXOFF Flag: 1071 * Enable XON/XOFF flow control on output. 1072 * Transmit XON1, XOFF1 1073 */ 1074 if (termios->c_iflag & IXOFF) { 1075 up->port.status |= UPSTAT_AUTOXOFF; 1076 up->efr |= OMAP_UART_SW_TX; 1077 } 1078 1079 /* 1080 * IXANY Flag: 1081 * Enable any character to restart output. 1082 * Operation resumes after receiving any 1083 * character after recognition of the XOFF character 1084 */ 1085 if (termios->c_iflag & IXANY) 1086 up->mcr |= UART_MCR_XONANY; 1087 else 1088 up->mcr &= ~UART_MCR_XONANY; 1089 } 1090 serial_out(up, UART_MCR, up->mcr); 1091 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1092 serial_out(up, UART_EFR, up->efr); 1093 serial_out(up, UART_LCR, up->lcr); 1094 1095 serial_omap_set_mctrl(&up->port, up->port.mctrl); 1096 1097 spin_unlock_irqrestore(&up->port.lock, flags); 1098 pm_runtime_mark_last_busy(up->dev); 1099 pm_runtime_put_autosuspend(up->dev); 1100 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line); 1101 } 1102 1103 static void 1104 serial_omap_pm(struct uart_port *port, unsigned int state, 1105 unsigned int oldstate) 1106 { 1107 struct uart_omap_port *up = to_uart_omap_port(port); 1108 unsigned char efr; 1109 1110 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line); 1111 1112 pm_runtime_get_sync(up->dev); 1113 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1114 efr = serial_in(up, UART_EFR); 1115 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 1116 serial_out(up, UART_LCR, 0); 1117 1118 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 1119 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1120 serial_out(up, UART_EFR, efr); 1121 serial_out(up, UART_LCR, 0); 1122 1123 pm_runtime_mark_last_busy(up->dev); 1124 pm_runtime_put_autosuspend(up->dev); 1125 } 1126 1127 static void serial_omap_release_port(struct uart_port *port) 1128 { 1129 dev_dbg(port->dev, "serial_omap_release_port+\n"); 1130 } 1131 1132 static int serial_omap_request_port(struct uart_port *port) 1133 { 1134 dev_dbg(port->dev, "serial_omap_request_port+\n"); 1135 return 0; 1136 } 1137 1138 static void serial_omap_config_port(struct uart_port *port, int flags) 1139 { 1140 struct uart_omap_port *up = to_uart_omap_port(port); 1141 1142 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", 1143 up->port.line); 1144 up->port.type = PORT_OMAP; 1145 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW; 1146 } 1147 1148 static int 1149 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) 1150 { 1151 /* we don't want the core code to modify any port params */ 1152 dev_dbg(port->dev, "serial_omap_verify_port+\n"); 1153 return -EINVAL; 1154 } 1155 1156 static const char * 1157 serial_omap_type(struct uart_port *port) 1158 { 1159 struct uart_omap_port *up = to_uart_omap_port(port); 1160 1161 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line); 1162 return up->name; 1163 } 1164 1165 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 1166 1167 static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up) 1168 { 1169 unsigned int status, tmout = 10000; 1170 1171 /* Wait up to 10ms for the character(s) to be sent. */ 1172 do { 1173 status = serial_in(up, UART_LSR); 1174 1175 if (status & UART_LSR_BI) 1176 up->lsr_break_flag = UART_LSR_BI; 1177 1178 if (--tmout == 0) 1179 break; 1180 udelay(1); 1181 } while ((status & BOTH_EMPTY) != BOTH_EMPTY); 1182 1183 /* Wait up to 1s for flow control if necessary */ 1184 if (up->port.flags & UPF_CONS_FLOW) { 1185 tmout = 1000000; 1186 for (tmout = 1000000; tmout; tmout--) { 1187 unsigned int msr = serial_in(up, UART_MSR); 1188 1189 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; 1190 if (msr & UART_MSR_CTS) 1191 break; 1192 1193 udelay(1); 1194 } 1195 } 1196 } 1197 1198 #ifdef CONFIG_CONSOLE_POLL 1199 1200 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) 1201 { 1202 struct uart_omap_port *up = to_uart_omap_port(port); 1203 1204 pm_runtime_get_sync(up->dev); 1205 wait_for_xmitr(up); 1206 serial_out(up, UART_TX, ch); 1207 pm_runtime_mark_last_busy(up->dev); 1208 pm_runtime_put_autosuspend(up->dev); 1209 } 1210 1211 static int serial_omap_poll_get_char(struct uart_port *port) 1212 { 1213 struct uart_omap_port *up = to_uart_omap_port(port); 1214 unsigned int status; 1215 1216 pm_runtime_get_sync(up->dev); 1217 status = serial_in(up, UART_LSR); 1218 if (!(status & UART_LSR_DR)) { 1219 status = NO_POLL_CHAR; 1220 goto out; 1221 } 1222 1223 status = serial_in(up, UART_RX); 1224 1225 out: 1226 pm_runtime_mark_last_busy(up->dev); 1227 pm_runtime_put_autosuspend(up->dev); 1228 1229 return status; 1230 } 1231 1232 #endif /* CONFIG_CONSOLE_POLL */ 1233 1234 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 1235 1236 #ifdef CONFIG_SERIAL_EARLYCON 1237 static unsigned int omap_serial_early_in(struct uart_port *port, int offset) 1238 { 1239 offset <<= port->regshift; 1240 return readw(port->membase + offset); 1241 } 1242 1243 static void omap_serial_early_out(struct uart_port *port, int offset, 1244 int value) 1245 { 1246 offset <<= port->regshift; 1247 writew(value, port->membase + offset); 1248 } 1249 1250 static void omap_serial_early_putc(struct uart_port *port, int c) 1251 { 1252 unsigned int status; 1253 1254 for (;;) { 1255 status = omap_serial_early_in(port, UART_LSR); 1256 if ((status & BOTH_EMPTY) == BOTH_EMPTY) 1257 break; 1258 cpu_relax(); 1259 } 1260 omap_serial_early_out(port, UART_TX, c); 1261 } 1262 1263 static void early_omap_serial_write(struct console *console, const char *s, 1264 unsigned int count) 1265 { 1266 struct earlycon_device *device = console->data; 1267 struct uart_port *port = &device->port; 1268 1269 uart_console_write(port, s, count, omap_serial_early_putc); 1270 } 1271 1272 static int __init early_omap_serial_setup(struct earlycon_device *device, 1273 const char *options) 1274 { 1275 struct uart_port *port = &device->port; 1276 1277 if (!(device->port.membase || device->port.iobase)) 1278 return -ENODEV; 1279 1280 port->regshift = 2; 1281 device->con->write = early_omap_serial_write; 1282 return 0; 1283 } 1284 1285 OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup); 1286 OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup); 1287 OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup); 1288 #endif /* CONFIG_SERIAL_EARLYCON */ 1289 1290 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS]; 1291 1292 static struct uart_driver serial_omap_reg; 1293 1294 static void serial_omap_console_putchar(struct uart_port *port, int ch) 1295 { 1296 struct uart_omap_port *up = to_uart_omap_port(port); 1297 1298 wait_for_xmitr(up); 1299 serial_out(up, UART_TX, ch); 1300 } 1301 1302 static void 1303 serial_omap_console_write(struct console *co, const char *s, 1304 unsigned int count) 1305 { 1306 struct uart_omap_port *up = serial_omap_console_ports[co->index]; 1307 unsigned long flags; 1308 unsigned int ier; 1309 int locked = 1; 1310 1311 pm_runtime_get_sync(up->dev); 1312 1313 local_irq_save(flags); 1314 if (up->port.sysrq) 1315 locked = 0; 1316 else if (oops_in_progress) 1317 locked = spin_trylock(&up->port.lock); 1318 else 1319 spin_lock(&up->port.lock); 1320 1321 /* 1322 * First save the IER then disable the interrupts 1323 */ 1324 ier = serial_in(up, UART_IER); 1325 serial_out(up, UART_IER, 0); 1326 1327 uart_console_write(&up->port, s, count, serial_omap_console_putchar); 1328 1329 /* 1330 * Finally, wait for transmitter to become empty 1331 * and restore the IER 1332 */ 1333 wait_for_xmitr(up); 1334 serial_out(up, UART_IER, ier); 1335 /* 1336 * The receive handling will happen properly because the 1337 * receive ready bit will still be set; it is not cleared 1338 * on read. However, modem control will not, we must 1339 * call it if we have saved something in the saved flags 1340 * while processing with interrupts off. 1341 */ 1342 if (up->msr_saved_flags) 1343 check_modem_status(up); 1344 1345 pm_runtime_mark_last_busy(up->dev); 1346 pm_runtime_put_autosuspend(up->dev); 1347 if (locked) 1348 spin_unlock(&up->port.lock); 1349 local_irq_restore(flags); 1350 } 1351 1352 static int __init 1353 serial_omap_console_setup(struct console *co, char *options) 1354 { 1355 struct uart_omap_port *up; 1356 int baud = 115200; 1357 int bits = 8; 1358 int parity = 'n'; 1359 int flow = 'n'; 1360 1361 if (serial_omap_console_ports[co->index] == NULL) 1362 return -ENODEV; 1363 up = serial_omap_console_ports[co->index]; 1364 1365 if (options) 1366 uart_parse_options(options, &baud, &parity, &bits, &flow); 1367 1368 return uart_set_options(&up->port, co, baud, parity, bits, flow); 1369 } 1370 1371 static struct console serial_omap_console = { 1372 .name = OMAP_SERIAL_NAME, 1373 .write = serial_omap_console_write, 1374 .device = uart_console_device, 1375 .setup = serial_omap_console_setup, 1376 .flags = CON_PRINTBUFFER, 1377 .index = -1, 1378 .data = &serial_omap_reg, 1379 }; 1380 1381 static void serial_omap_add_console_port(struct uart_omap_port *up) 1382 { 1383 serial_omap_console_ports[up->port.line] = up; 1384 } 1385 1386 #define OMAP_CONSOLE (&serial_omap_console) 1387 1388 #else 1389 1390 #define OMAP_CONSOLE NULL 1391 1392 static inline void serial_omap_add_console_port(struct uart_omap_port *up) 1393 {} 1394 1395 #endif 1396 1397 /* Enable or disable the rs485 support */ 1398 static int 1399 serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485) 1400 { 1401 struct uart_omap_port *up = to_uart_omap_port(port); 1402 unsigned int mode; 1403 int val; 1404 1405 pm_runtime_get_sync(up->dev); 1406 1407 /* Disable interrupts from this port */ 1408 mode = up->ier; 1409 up->ier = 0; 1410 serial_out(up, UART_IER, 0); 1411 1412 /* Clamp the delays to [0, 100ms] */ 1413 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U); 1414 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U); 1415 1416 /* store new config */ 1417 port->rs485 = *rs485; 1418 1419 /* 1420 * Just as a precaution, only allow rs485 1421 * to be enabled if the gpio pin is valid 1422 */ 1423 if (gpio_is_valid(up->rts_gpio)) { 1424 /* enable / disable rts */ 1425 val = (port->rs485.flags & SER_RS485_ENABLED) ? 1426 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND; 1427 val = (port->rs485.flags & val) ? 1 : 0; 1428 gpio_set_value(up->rts_gpio, val); 1429 } else 1430 port->rs485.flags &= ~SER_RS485_ENABLED; 1431 1432 /* Enable interrupts */ 1433 up->ier = mode; 1434 serial_out(up, UART_IER, up->ier); 1435 1436 /* If RS-485 is disabled, make sure the THR interrupt is fired when 1437 * TX FIFO is below the trigger level. 1438 */ 1439 if (!(port->rs485.flags & SER_RS485_ENABLED) && 1440 (up->scr & OMAP_UART_SCR_TX_EMPTY)) { 1441 up->scr &= ~OMAP_UART_SCR_TX_EMPTY; 1442 serial_out(up, UART_OMAP_SCR, up->scr); 1443 } 1444 1445 pm_runtime_mark_last_busy(up->dev); 1446 pm_runtime_put_autosuspend(up->dev); 1447 1448 return 0; 1449 } 1450 1451 static const struct uart_ops serial_omap_pops = { 1452 .tx_empty = serial_omap_tx_empty, 1453 .set_mctrl = serial_omap_set_mctrl, 1454 .get_mctrl = serial_omap_get_mctrl, 1455 .stop_tx = serial_omap_stop_tx, 1456 .start_tx = serial_omap_start_tx, 1457 .throttle = serial_omap_throttle, 1458 .unthrottle = serial_omap_unthrottle, 1459 .stop_rx = serial_omap_stop_rx, 1460 .enable_ms = serial_omap_enable_ms, 1461 .break_ctl = serial_omap_break_ctl, 1462 .startup = serial_omap_startup, 1463 .shutdown = serial_omap_shutdown, 1464 .set_termios = serial_omap_set_termios, 1465 .pm = serial_omap_pm, 1466 .type = serial_omap_type, 1467 .release_port = serial_omap_release_port, 1468 .request_port = serial_omap_request_port, 1469 .config_port = serial_omap_config_port, 1470 .verify_port = serial_omap_verify_port, 1471 #ifdef CONFIG_CONSOLE_POLL 1472 .poll_put_char = serial_omap_poll_put_char, 1473 .poll_get_char = serial_omap_poll_get_char, 1474 #endif 1475 }; 1476 1477 static struct uart_driver serial_omap_reg = { 1478 .owner = THIS_MODULE, 1479 .driver_name = "OMAP-SERIAL", 1480 .dev_name = OMAP_SERIAL_NAME, 1481 .nr = OMAP_MAX_HSUART_PORTS, 1482 .cons = OMAP_CONSOLE, 1483 }; 1484 1485 #ifdef CONFIG_PM_SLEEP 1486 static int serial_omap_prepare(struct device *dev) 1487 { 1488 struct uart_omap_port *up = dev_get_drvdata(dev); 1489 1490 up->is_suspending = true; 1491 1492 return 0; 1493 } 1494 1495 static void serial_omap_complete(struct device *dev) 1496 { 1497 struct uart_omap_port *up = dev_get_drvdata(dev); 1498 1499 up->is_suspending = false; 1500 } 1501 1502 static int serial_omap_suspend(struct device *dev) 1503 { 1504 struct uart_omap_port *up = dev_get_drvdata(dev); 1505 1506 uart_suspend_port(&serial_omap_reg, &up->port); 1507 flush_work(&up->qos_work); 1508 1509 if (device_may_wakeup(dev)) 1510 serial_omap_enable_wakeup(up, true); 1511 else 1512 serial_omap_enable_wakeup(up, false); 1513 1514 return 0; 1515 } 1516 1517 static int serial_omap_resume(struct device *dev) 1518 { 1519 struct uart_omap_port *up = dev_get_drvdata(dev); 1520 1521 if (device_may_wakeup(dev)) 1522 serial_omap_enable_wakeup(up, false); 1523 1524 uart_resume_port(&serial_omap_reg, &up->port); 1525 1526 return 0; 1527 } 1528 #else 1529 #define serial_omap_prepare NULL 1530 #define serial_omap_complete NULL 1531 #endif /* CONFIG_PM_SLEEP */ 1532 1533 static void omap_serial_fill_features_erratas(struct uart_omap_port *up) 1534 { 1535 u32 mvr, scheme; 1536 u16 revision, major, minor; 1537 1538 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift)); 1539 1540 /* Check revision register scheme */ 1541 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 1542 1543 switch (scheme) { 1544 case 0: /* Legacy Scheme: OMAP2/3 */ 1545 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 1546 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 1547 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 1548 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 1549 break; 1550 case 1: 1551 /* New Scheme: OMAP4+ */ 1552 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 1553 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 1554 OMAP_UART_MVR_MAJ_SHIFT; 1555 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 1556 break; 1557 default: 1558 dev_warn(up->dev, 1559 "Unknown %s revision, defaulting to highest\n", 1560 up->name); 1561 /* highest possible revision */ 1562 major = 0xff; 1563 minor = 0xff; 1564 } 1565 1566 /* normalize revision for the driver */ 1567 revision = UART_BUILD_REVISION(major, minor); 1568 1569 switch (revision) { 1570 case OMAP_UART_REV_46: 1571 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1572 UART_ERRATA_i291_DMA_FORCEIDLE); 1573 break; 1574 case OMAP_UART_REV_52: 1575 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1576 UART_ERRATA_i291_DMA_FORCEIDLE); 1577 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP; 1578 break; 1579 case OMAP_UART_REV_63: 1580 up->errata |= UART_ERRATA_i202_MDR1_ACCESS; 1581 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP; 1582 break; 1583 default: 1584 break; 1585 } 1586 } 1587 1588 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev) 1589 { 1590 struct omap_uart_port_info *omap_up_info; 1591 1592 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL); 1593 if (!omap_up_info) 1594 return NULL; /* out of memory */ 1595 1596 of_property_read_u32(dev->of_node, "clock-frequency", 1597 &omap_up_info->uartclk); 1598 1599 omap_up_info->flags = UPF_BOOT_AUTOCONF; 1600 1601 return omap_up_info; 1602 } 1603 1604 static int serial_omap_probe_rs485(struct uart_omap_port *up, 1605 struct device_node *np) 1606 { 1607 struct serial_rs485 *rs485conf = &up->port.rs485; 1608 int ret; 1609 1610 rs485conf->flags = 0; 1611 up->rts_gpio = -EINVAL; 1612 1613 if (!np) 1614 return 0; 1615 1616 uart_get_rs485_mode(up->dev, rs485conf); 1617 1618 if (of_property_read_bool(np, "rs485-rts-active-high")) { 1619 rs485conf->flags |= SER_RS485_RTS_ON_SEND; 1620 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 1621 } else { 1622 rs485conf->flags &= ~SER_RS485_RTS_ON_SEND; 1623 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 1624 } 1625 1626 /* check for tx enable gpio */ 1627 up->rts_gpio = of_get_named_gpio(np, "rts-gpio", 0); 1628 if (gpio_is_valid(up->rts_gpio)) { 1629 ret = devm_gpio_request(up->dev, up->rts_gpio, "omap-serial"); 1630 if (ret < 0) 1631 return ret; 1632 ret = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ? 1 : 0; 1633 ret = gpio_direction_output(up->rts_gpio, ret); 1634 if (ret < 0) 1635 return ret; 1636 } else if (up->rts_gpio == -EPROBE_DEFER) { 1637 return -EPROBE_DEFER; 1638 } else { 1639 up->rts_gpio = -EINVAL; 1640 } 1641 1642 return 0; 1643 } 1644 1645 static int serial_omap_probe(struct platform_device *pdev) 1646 { 1647 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev); 1648 struct uart_omap_port *up; 1649 struct resource *mem; 1650 void __iomem *base; 1651 int uartirq = 0; 1652 int wakeirq = 0; 1653 int ret; 1654 1655 /* The optional wakeirq may be specified in the board dts file */ 1656 if (pdev->dev.of_node) { 1657 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1658 if (!uartirq) 1659 return -EPROBE_DEFER; 1660 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1); 1661 omap_up_info = of_get_uart_port_info(&pdev->dev); 1662 pdev->dev.platform_data = omap_up_info; 1663 } else { 1664 uartirq = platform_get_irq(pdev, 0); 1665 if (uartirq < 0) 1666 return -EPROBE_DEFER; 1667 } 1668 1669 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL); 1670 if (!up) 1671 return -ENOMEM; 1672 1673 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1674 base = devm_ioremap_resource(&pdev->dev, mem); 1675 if (IS_ERR(base)) 1676 return PTR_ERR(base); 1677 1678 up->dev = &pdev->dev; 1679 up->port.dev = &pdev->dev; 1680 up->port.type = PORT_OMAP; 1681 up->port.iotype = UPIO_MEM; 1682 up->port.irq = uartirq; 1683 up->port.regshift = 2; 1684 up->port.fifosize = 64; 1685 up->port.ops = &serial_omap_pops; 1686 1687 if (pdev->dev.of_node) 1688 ret = of_alias_get_id(pdev->dev.of_node, "serial"); 1689 else 1690 ret = pdev->id; 1691 1692 if (ret < 0) { 1693 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", 1694 ret); 1695 goto err_port_line; 1696 } 1697 up->port.line = ret; 1698 1699 if (up->port.line >= OMAP_MAX_HSUART_PORTS) { 1700 dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line, 1701 OMAP_MAX_HSUART_PORTS); 1702 ret = -ENXIO; 1703 goto err_port_line; 1704 } 1705 1706 up->wakeirq = wakeirq; 1707 if (!up->wakeirq) 1708 dev_info(up->port.dev, "no wakeirq for uart%d\n", 1709 up->port.line); 1710 1711 ret = serial_omap_probe_rs485(up, pdev->dev.of_node); 1712 if (ret < 0) 1713 goto err_rs485; 1714 1715 sprintf(up->name, "OMAP UART%d", up->port.line); 1716 up->port.mapbase = mem->start; 1717 up->port.membase = base; 1718 up->port.flags = omap_up_info->flags; 1719 up->port.uartclk = omap_up_info->uartclk; 1720 up->port.rs485_config = serial_omap_config_rs485; 1721 if (!up->port.uartclk) { 1722 up->port.uartclk = DEFAULT_CLK_SPEED; 1723 dev_warn(&pdev->dev, 1724 "No clock speed specified: using default: %d\n", 1725 DEFAULT_CLK_SPEED); 1726 } 1727 1728 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1729 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1730 pm_qos_add_request(&up->pm_qos_request, 1731 PM_QOS_CPU_DMA_LATENCY, up->latency); 1732 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); 1733 1734 platform_set_drvdata(pdev, up); 1735 if (omap_up_info->autosuspend_timeout == 0) 1736 omap_up_info->autosuspend_timeout = -1; 1737 1738 device_init_wakeup(up->dev, true); 1739 pm_runtime_use_autosuspend(&pdev->dev); 1740 pm_runtime_set_autosuspend_delay(&pdev->dev, 1741 omap_up_info->autosuspend_timeout); 1742 1743 pm_runtime_irq_safe(&pdev->dev); 1744 pm_runtime_enable(&pdev->dev); 1745 1746 pm_runtime_get_sync(&pdev->dev); 1747 1748 omap_serial_fill_features_erratas(up); 1749 1750 ui[up->port.line] = up; 1751 serial_omap_add_console_port(up); 1752 1753 ret = uart_add_one_port(&serial_omap_reg, &up->port); 1754 if (ret != 0) 1755 goto err_add_port; 1756 1757 pm_runtime_mark_last_busy(up->dev); 1758 pm_runtime_put_autosuspend(up->dev); 1759 return 0; 1760 1761 err_add_port: 1762 pm_runtime_dont_use_autosuspend(&pdev->dev); 1763 pm_runtime_put_sync(&pdev->dev); 1764 pm_runtime_disable(&pdev->dev); 1765 pm_qos_remove_request(&up->pm_qos_request); 1766 device_init_wakeup(up->dev, false); 1767 err_rs485: 1768 err_port_line: 1769 return ret; 1770 } 1771 1772 static int serial_omap_remove(struct platform_device *dev) 1773 { 1774 struct uart_omap_port *up = platform_get_drvdata(dev); 1775 1776 pm_runtime_get_sync(up->dev); 1777 1778 uart_remove_one_port(&serial_omap_reg, &up->port); 1779 1780 pm_runtime_dont_use_autosuspend(up->dev); 1781 pm_runtime_put_sync(up->dev); 1782 pm_runtime_disable(up->dev); 1783 pm_qos_remove_request(&up->pm_qos_request); 1784 device_init_wakeup(&dev->dev, false); 1785 1786 return 0; 1787 } 1788 1789 /* 1790 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 1791 * The access to uart register after MDR1 Access 1792 * causes UART to corrupt data. 1793 * 1794 * Need a delay = 1795 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 1796 * give 10 times as much 1797 */ 1798 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1) 1799 { 1800 u8 timeout = 255; 1801 1802 serial_out(up, UART_OMAP_MDR1, mdr1); 1803 udelay(2); 1804 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 1805 UART_FCR_CLEAR_RCVR); 1806 /* 1807 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 1808 * TX_FIFO_E bit is 1. 1809 */ 1810 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 1811 (UART_LSR_THRE | UART_LSR_DR))) { 1812 timeout--; 1813 if (!timeout) { 1814 /* Should *never* happen. we warn and carry on */ 1815 dev_crit(up->dev, "Errata i202: timedout %x\n", 1816 serial_in(up, UART_LSR)); 1817 break; 1818 } 1819 udelay(1); 1820 } 1821 } 1822 1823 #ifdef CONFIG_PM 1824 static void serial_omap_restore_context(struct uart_omap_port *up) 1825 { 1826 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1827 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE); 1828 else 1829 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); 1830 1831 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1832 serial_out(up, UART_EFR, UART_EFR_ECB); 1833 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1834 serial_out(up, UART_IER, 0x0); 1835 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1836 serial_out(up, UART_DLL, up->dll); 1837 serial_out(up, UART_DLM, up->dlh); 1838 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1839 serial_out(up, UART_IER, up->ier); 1840 serial_out(up, UART_FCR, up->fcr); 1841 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1842 serial_out(up, UART_MCR, up->mcr); 1843 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1844 serial_out(up, UART_OMAP_SCR, up->scr); 1845 serial_out(up, UART_EFR, up->efr); 1846 serial_out(up, UART_LCR, up->lcr); 1847 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1848 serial_omap_mdr1_errataset(up, up->mdr1); 1849 else 1850 serial_out(up, UART_OMAP_MDR1, up->mdr1); 1851 serial_out(up, UART_OMAP_WER, up->wer); 1852 } 1853 1854 static int serial_omap_runtime_suspend(struct device *dev) 1855 { 1856 struct uart_omap_port *up = dev_get_drvdata(dev); 1857 1858 if (!up) 1859 return -EINVAL; 1860 1861 /* 1862 * When using 'no_console_suspend', the console UART must not be 1863 * suspended. Since driver suspend is managed by runtime suspend, 1864 * preventing runtime suspend (by returning error) will keep device 1865 * active during suspend. 1866 */ 1867 if (up->is_suspending && !console_suspend_enabled && 1868 uart_console(&up->port)) 1869 return -EBUSY; 1870 1871 up->context_loss_cnt = serial_omap_get_context_loss_count(up); 1872 1873 serial_omap_enable_wakeup(up, true); 1874 1875 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1876 schedule_work(&up->qos_work); 1877 1878 return 0; 1879 } 1880 1881 static int serial_omap_runtime_resume(struct device *dev) 1882 { 1883 struct uart_omap_port *up = dev_get_drvdata(dev); 1884 1885 int loss_cnt = serial_omap_get_context_loss_count(up); 1886 1887 serial_omap_enable_wakeup(up, false); 1888 1889 if (loss_cnt < 0) { 1890 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n", 1891 loss_cnt); 1892 serial_omap_restore_context(up); 1893 } else if (up->context_loss_cnt != loss_cnt) { 1894 serial_omap_restore_context(up); 1895 } 1896 up->latency = up->calc_latency; 1897 schedule_work(&up->qos_work); 1898 1899 return 0; 1900 } 1901 #endif 1902 1903 static const struct dev_pm_ops serial_omap_dev_pm_ops = { 1904 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume) 1905 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend, 1906 serial_omap_runtime_resume, NULL) 1907 .prepare = serial_omap_prepare, 1908 .complete = serial_omap_complete, 1909 }; 1910 1911 #if defined(CONFIG_OF) 1912 static const struct of_device_id omap_serial_of_match[] = { 1913 { .compatible = "ti,omap2-uart" }, 1914 { .compatible = "ti,omap3-uart" }, 1915 { .compatible = "ti,omap4-uart" }, 1916 {}, 1917 }; 1918 MODULE_DEVICE_TABLE(of, omap_serial_of_match); 1919 #endif 1920 1921 static struct platform_driver serial_omap_driver = { 1922 .probe = serial_omap_probe, 1923 .remove = serial_omap_remove, 1924 .driver = { 1925 .name = OMAP_SERIAL_DRIVER_NAME, 1926 .pm = &serial_omap_dev_pm_ops, 1927 .of_match_table = of_match_ptr(omap_serial_of_match), 1928 }, 1929 }; 1930 1931 static int __init serial_omap_init(void) 1932 { 1933 int ret; 1934 1935 ret = uart_register_driver(&serial_omap_reg); 1936 if (ret != 0) 1937 return ret; 1938 ret = platform_driver_register(&serial_omap_driver); 1939 if (ret != 0) 1940 uart_unregister_driver(&serial_omap_reg); 1941 return ret; 1942 } 1943 1944 static void __exit serial_omap_exit(void) 1945 { 1946 platform_driver_unregister(&serial_omap_driver); 1947 uart_unregister_driver(&serial_omap_reg); 1948 } 1949 1950 module_init(serial_omap_init); 1951 module_exit(serial_omap_exit); 1952 1953 MODULE_DESCRIPTION("OMAP High Speed UART driver"); 1954 MODULE_LICENSE("GPL"); 1955 MODULE_AUTHOR("Texas Instruments Inc"); 1956