1 /* 2 * Driver for OMAP-UART controller. 3 * Based on drivers/serial/8250.c 4 * 5 * Copyright (C) 2010 Texas Instruments. 6 * 7 * Authors: 8 * Govindraj R <govindraj.raja@ti.com> 9 * Thara Gopinath <thara@ti.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * Note: This driver is made separate from 8250 driver as we cannot 17 * over load 8250 driver with omap platform specific configuration for 18 * features like DMA, it makes easier to implement features like DMA and 19 * hardware flow control and software flow control configuration with 20 * this driver as required for the omap-platform. 21 */ 22 23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 24 #define SUPPORT_SYSRQ 25 #endif 26 27 #include <linux/module.h> 28 #include <linux/init.h> 29 #include <linux/console.h> 30 #include <linux/serial_reg.h> 31 #include <linux/delay.h> 32 #include <linux/slab.h> 33 #include <linux/tty.h> 34 #include <linux/tty_flip.h> 35 #include <linux/io.h> 36 #include <linux/dma-mapping.h> 37 #include <linux/clk.h> 38 #include <linux/serial_core.h> 39 #include <linux/irq.h> 40 #include <linux/pm_runtime.h> 41 42 #include <plat/dma.h> 43 #include <plat/dmtimer.h> 44 #include <plat/omap-serial.h> 45 46 #define OMAP_UART_AUTOSUSPEND_DELAY -1 47 48 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; 49 50 /* Forward declaration of functions */ 51 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data); 52 static void serial_omap_rx_timeout(unsigned long uart_no); 53 static int serial_omap_start_rxdma(struct uart_omap_port *up); 54 55 static inline unsigned int serial_in(struct uart_omap_port *up, int offset) 56 { 57 offset <<= up->port.regshift; 58 return readw(up->port.membase + offset); 59 } 60 61 static inline void serial_out(struct uart_omap_port *up, int offset, int value) 62 { 63 offset <<= up->port.regshift; 64 writew(value, up->port.membase + offset); 65 } 66 67 static inline void serial_omap_clear_fifos(struct uart_omap_port *up) 68 { 69 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 70 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 71 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 72 serial_out(up, UART_FCR, 0); 73 } 74 75 /* 76 * serial_omap_get_divisor - calculate divisor value 77 * @port: uart port info 78 * @baud: baudrate for which divisor needs to be calculated. 79 * 80 * We have written our own function to get the divisor so as to support 81 * 13x mode. 3Mbps Baudrate as an different divisor. 82 * Reference OMAP TRM Chapter 17: 83 * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates 84 * referring to oversampling - divisor value 85 * baudrate 460,800 to 3,686,400 all have divisor 13 86 * except 3,000,000 which has divisor value 16 87 */ 88 static unsigned int 89 serial_omap_get_divisor(struct uart_port *port, unsigned int baud) 90 { 91 unsigned int divisor; 92 93 if (baud > OMAP_MODE13X_SPEED && baud != 3000000) 94 divisor = 13; 95 else 96 divisor = 16; 97 return port->uartclk/(baud * divisor); 98 } 99 100 static void serial_omap_stop_rxdma(struct uart_omap_port *up) 101 { 102 if (up->uart_dma.rx_dma_used) { 103 del_timer(&up->uart_dma.rx_timer); 104 omap_stop_dma(up->uart_dma.rx_dma_channel); 105 omap_free_dma(up->uart_dma.rx_dma_channel); 106 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE; 107 up->uart_dma.rx_dma_used = false; 108 pm_runtime_mark_last_busy(&up->pdev->dev); 109 pm_runtime_put_autosuspend(&up->pdev->dev); 110 } 111 } 112 113 static void serial_omap_enable_ms(struct uart_port *port) 114 { 115 struct uart_omap_port *up = (struct uart_omap_port *)port; 116 117 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->pdev->id); 118 119 pm_runtime_get_sync(&up->pdev->dev); 120 up->ier |= UART_IER_MSI; 121 serial_out(up, UART_IER, up->ier); 122 pm_runtime_put(&up->pdev->dev); 123 } 124 125 static void serial_omap_stop_tx(struct uart_port *port) 126 { 127 struct uart_omap_port *up = (struct uart_omap_port *)port; 128 129 if (up->use_dma && 130 up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) { 131 /* 132 * Check if dma is still active. If yes do nothing, 133 * return. Else stop dma 134 */ 135 if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel)) 136 return; 137 omap_stop_dma(up->uart_dma.tx_dma_channel); 138 omap_free_dma(up->uart_dma.tx_dma_channel); 139 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE; 140 pm_runtime_mark_last_busy(&up->pdev->dev); 141 pm_runtime_put_autosuspend(&up->pdev->dev); 142 } 143 144 pm_runtime_get_sync(&up->pdev->dev); 145 if (up->ier & UART_IER_THRI) { 146 up->ier &= ~UART_IER_THRI; 147 serial_out(up, UART_IER, up->ier); 148 } 149 150 pm_runtime_mark_last_busy(&up->pdev->dev); 151 pm_runtime_put_autosuspend(&up->pdev->dev); 152 } 153 154 static void serial_omap_stop_rx(struct uart_port *port) 155 { 156 struct uart_omap_port *up = (struct uart_omap_port *)port; 157 158 pm_runtime_get_sync(&up->pdev->dev); 159 if (up->use_dma) 160 serial_omap_stop_rxdma(up); 161 up->ier &= ~UART_IER_RLSI; 162 up->port.read_status_mask &= ~UART_LSR_DR; 163 serial_out(up, UART_IER, up->ier); 164 pm_runtime_mark_last_busy(&up->pdev->dev); 165 pm_runtime_put_autosuspend(&up->pdev->dev); 166 } 167 168 static inline void receive_chars(struct uart_omap_port *up, int *status) 169 { 170 struct tty_struct *tty = up->port.state->port.tty; 171 unsigned int flag; 172 unsigned char ch, lsr = *status; 173 int max_count = 256; 174 175 do { 176 if (likely(lsr & UART_LSR_DR)) 177 ch = serial_in(up, UART_RX); 178 flag = TTY_NORMAL; 179 up->port.icount.rx++; 180 181 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { 182 /* 183 * For statistics only 184 */ 185 if (lsr & UART_LSR_BI) { 186 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 187 up->port.icount.brk++; 188 /* 189 * We do the SysRQ and SAK checking 190 * here because otherwise the break 191 * may get masked by ignore_status_mask 192 * or read_status_mask. 193 */ 194 if (uart_handle_break(&up->port)) 195 goto ignore_char; 196 } else if (lsr & UART_LSR_PE) { 197 up->port.icount.parity++; 198 } else if (lsr & UART_LSR_FE) { 199 up->port.icount.frame++; 200 } 201 202 if (lsr & UART_LSR_OE) 203 up->port.icount.overrun++; 204 205 /* 206 * Mask off conditions which should be ignored. 207 */ 208 lsr &= up->port.read_status_mask; 209 210 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 211 if (up->port.line == up->port.cons->index) { 212 /* Recover the break flag from console xmit */ 213 lsr |= up->lsr_break_flag; 214 } 215 #endif 216 if (lsr & UART_LSR_BI) 217 flag = TTY_BREAK; 218 else if (lsr & UART_LSR_PE) 219 flag = TTY_PARITY; 220 else if (lsr & UART_LSR_FE) 221 flag = TTY_FRAME; 222 } 223 224 if (uart_handle_sysrq_char(&up->port, ch)) 225 goto ignore_char; 226 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); 227 ignore_char: 228 lsr = serial_in(up, UART_LSR); 229 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0)); 230 spin_unlock(&up->port.lock); 231 tty_flip_buffer_push(tty); 232 spin_lock(&up->port.lock); 233 } 234 235 static void transmit_chars(struct uart_omap_port *up) 236 { 237 struct circ_buf *xmit = &up->port.state->xmit; 238 int count; 239 240 if (up->port.x_char) { 241 serial_out(up, UART_TX, up->port.x_char); 242 up->port.icount.tx++; 243 up->port.x_char = 0; 244 return; 245 } 246 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 247 serial_omap_stop_tx(&up->port); 248 return; 249 } 250 count = up->port.fifosize / 4; 251 do { 252 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 253 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 254 up->port.icount.tx++; 255 if (uart_circ_empty(xmit)) 256 break; 257 } while (--count > 0); 258 259 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 260 uart_write_wakeup(&up->port); 261 262 if (uart_circ_empty(xmit)) 263 serial_omap_stop_tx(&up->port); 264 } 265 266 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) 267 { 268 if (!(up->ier & UART_IER_THRI)) { 269 up->ier |= UART_IER_THRI; 270 serial_out(up, UART_IER, up->ier); 271 } 272 } 273 274 static void serial_omap_start_tx(struct uart_port *port) 275 { 276 struct uart_omap_port *up = (struct uart_omap_port *)port; 277 struct circ_buf *xmit; 278 unsigned int start; 279 int ret = 0; 280 281 if (!up->use_dma) { 282 pm_runtime_get_sync(&up->pdev->dev); 283 serial_omap_enable_ier_thri(up); 284 pm_runtime_mark_last_busy(&up->pdev->dev); 285 pm_runtime_put_autosuspend(&up->pdev->dev); 286 return; 287 } 288 289 if (up->uart_dma.tx_dma_used) 290 return; 291 292 xmit = &up->port.state->xmit; 293 294 if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) { 295 pm_runtime_get_sync(&up->pdev->dev); 296 ret = omap_request_dma(up->uart_dma.uart_dma_tx, 297 "UART Tx DMA", 298 (void *)uart_tx_dma_callback, up, 299 &(up->uart_dma.tx_dma_channel)); 300 301 if (ret < 0) { 302 serial_omap_enable_ier_thri(up); 303 return; 304 } 305 } 306 spin_lock(&(up->uart_dma.tx_lock)); 307 up->uart_dma.tx_dma_used = true; 308 spin_unlock(&(up->uart_dma.tx_lock)); 309 310 start = up->uart_dma.tx_buf_dma_phys + 311 (xmit->tail & (UART_XMIT_SIZE - 1)); 312 313 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit); 314 /* 315 * It is a circular buffer. See if the buffer has wounded back. 316 * If yes it will have to be transferred in two separate dma 317 * transfers 318 */ 319 if (start + up->uart_dma.tx_buf_size >= 320 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) 321 up->uart_dma.tx_buf_size = 322 (up->uart_dma.tx_buf_dma_phys + 323 UART_XMIT_SIZE) - start; 324 325 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0, 326 OMAP_DMA_AMODE_CONSTANT, 327 up->uart_dma.uart_base, 0, 0); 328 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0, 329 OMAP_DMA_AMODE_POST_INC, start, 0, 0); 330 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel, 331 OMAP_DMA_DATA_TYPE_S8, 332 up->uart_dma.tx_buf_size, 1, 333 OMAP_DMA_SYNC_ELEMENT, 334 up->uart_dma.uart_dma_tx, 0); 335 /* FIXME: Cache maintenance needed here? */ 336 omap_start_dma(up->uart_dma.tx_dma_channel); 337 } 338 339 static unsigned int check_modem_status(struct uart_omap_port *up) 340 { 341 unsigned int status; 342 343 status = serial_in(up, UART_MSR); 344 status |= up->msr_saved_flags; 345 up->msr_saved_flags = 0; 346 if ((status & UART_MSR_ANY_DELTA) == 0) 347 return status; 348 349 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && 350 up->port.state != NULL) { 351 if (status & UART_MSR_TERI) 352 up->port.icount.rng++; 353 if (status & UART_MSR_DDSR) 354 up->port.icount.dsr++; 355 if (status & UART_MSR_DDCD) 356 uart_handle_dcd_change 357 (&up->port, status & UART_MSR_DCD); 358 if (status & UART_MSR_DCTS) 359 uart_handle_cts_change 360 (&up->port, status & UART_MSR_CTS); 361 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 362 } 363 364 return status; 365 } 366 367 /** 368 * serial_omap_irq() - This handles the interrupt from one port 369 * @irq: uart port irq number 370 * @dev_id: uart port info 371 */ 372 static inline irqreturn_t serial_omap_irq(int irq, void *dev_id) 373 { 374 struct uart_omap_port *up = dev_id; 375 unsigned int iir, lsr; 376 unsigned long flags; 377 378 pm_runtime_get_sync(&up->pdev->dev); 379 iir = serial_in(up, UART_IIR); 380 if (iir & UART_IIR_NO_INT) { 381 pm_runtime_mark_last_busy(&up->pdev->dev); 382 pm_runtime_put_autosuspend(&up->pdev->dev); 383 return IRQ_NONE; 384 } 385 386 spin_lock_irqsave(&up->port.lock, flags); 387 lsr = serial_in(up, UART_LSR); 388 if (iir & UART_IIR_RLSI) { 389 if (!up->use_dma) { 390 if (lsr & UART_LSR_DR) 391 receive_chars(up, &lsr); 392 } else { 393 up->ier &= ~(UART_IER_RDI | UART_IER_RLSI); 394 serial_out(up, UART_IER, up->ier); 395 if ((serial_omap_start_rxdma(up) != 0) && 396 (lsr & UART_LSR_DR)) 397 receive_chars(up, &lsr); 398 } 399 } 400 401 check_modem_status(up); 402 if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI)) 403 transmit_chars(up); 404 405 spin_unlock_irqrestore(&up->port.lock, flags); 406 pm_runtime_mark_last_busy(&up->pdev->dev); 407 pm_runtime_put_autosuspend(&up->pdev->dev); 408 409 up->port_activity = jiffies; 410 return IRQ_HANDLED; 411 } 412 413 static unsigned int serial_omap_tx_empty(struct uart_port *port) 414 { 415 struct uart_omap_port *up = (struct uart_omap_port *)port; 416 unsigned long flags = 0; 417 unsigned int ret = 0; 418 419 pm_runtime_get_sync(&up->pdev->dev); 420 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->pdev->id); 421 spin_lock_irqsave(&up->port.lock, flags); 422 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 423 spin_unlock_irqrestore(&up->port.lock, flags); 424 pm_runtime_put(&up->pdev->dev); 425 return ret; 426 } 427 428 static unsigned int serial_omap_get_mctrl(struct uart_port *port) 429 { 430 struct uart_omap_port *up = (struct uart_omap_port *)port; 431 unsigned char status; 432 unsigned int ret = 0; 433 434 pm_runtime_get_sync(&up->pdev->dev); 435 status = check_modem_status(up); 436 pm_runtime_put(&up->pdev->dev); 437 438 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->pdev->id); 439 440 if (status & UART_MSR_DCD) 441 ret |= TIOCM_CAR; 442 if (status & UART_MSR_RI) 443 ret |= TIOCM_RNG; 444 if (status & UART_MSR_DSR) 445 ret |= TIOCM_DSR; 446 if (status & UART_MSR_CTS) 447 ret |= TIOCM_CTS; 448 return ret; 449 } 450 451 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) 452 { 453 struct uart_omap_port *up = (struct uart_omap_port *)port; 454 unsigned char mcr = 0; 455 456 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->pdev->id); 457 if (mctrl & TIOCM_RTS) 458 mcr |= UART_MCR_RTS; 459 if (mctrl & TIOCM_DTR) 460 mcr |= UART_MCR_DTR; 461 if (mctrl & TIOCM_OUT1) 462 mcr |= UART_MCR_OUT1; 463 if (mctrl & TIOCM_OUT2) 464 mcr |= UART_MCR_OUT2; 465 if (mctrl & TIOCM_LOOP) 466 mcr |= UART_MCR_LOOP; 467 468 pm_runtime_get_sync(&up->pdev->dev); 469 up->mcr = serial_in(up, UART_MCR); 470 up->mcr |= mcr; 471 serial_out(up, UART_MCR, up->mcr); 472 pm_runtime_put(&up->pdev->dev); 473 } 474 475 static void serial_omap_break_ctl(struct uart_port *port, int break_state) 476 { 477 struct uart_omap_port *up = (struct uart_omap_port *)port; 478 unsigned long flags = 0; 479 480 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->pdev->id); 481 pm_runtime_get_sync(&up->pdev->dev); 482 spin_lock_irqsave(&up->port.lock, flags); 483 if (break_state == -1) 484 up->lcr |= UART_LCR_SBC; 485 else 486 up->lcr &= ~UART_LCR_SBC; 487 serial_out(up, UART_LCR, up->lcr); 488 spin_unlock_irqrestore(&up->port.lock, flags); 489 pm_runtime_put(&up->pdev->dev); 490 } 491 492 static int serial_omap_startup(struct uart_port *port) 493 { 494 struct uart_omap_port *up = (struct uart_omap_port *)port; 495 unsigned long flags = 0; 496 int retval; 497 498 /* 499 * Allocate the IRQ 500 */ 501 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, 502 up->name, up); 503 if (retval) 504 return retval; 505 506 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->pdev->id); 507 508 pm_runtime_get_sync(&up->pdev->dev); 509 /* 510 * Clear the FIFO buffers and disable them. 511 * (they will be reenabled in set_termios()) 512 */ 513 serial_omap_clear_fifos(up); 514 /* For Hardware flow control */ 515 serial_out(up, UART_MCR, UART_MCR_RTS); 516 517 /* 518 * Clear the interrupt registers. 519 */ 520 (void) serial_in(up, UART_LSR); 521 if (serial_in(up, UART_LSR) & UART_LSR_DR) 522 (void) serial_in(up, UART_RX); 523 (void) serial_in(up, UART_IIR); 524 (void) serial_in(up, UART_MSR); 525 526 /* 527 * Now, initialize the UART 528 */ 529 serial_out(up, UART_LCR, UART_LCR_WLEN8); 530 spin_lock_irqsave(&up->port.lock, flags); 531 /* 532 * Most PC uarts need OUT2 raised to enable interrupts. 533 */ 534 up->port.mctrl |= TIOCM_OUT2; 535 serial_omap_set_mctrl(&up->port, up->port.mctrl); 536 spin_unlock_irqrestore(&up->port.lock, flags); 537 538 up->msr_saved_flags = 0; 539 if (up->use_dma) { 540 free_page((unsigned long)up->port.state->xmit.buf); 541 up->port.state->xmit.buf = dma_alloc_coherent(NULL, 542 UART_XMIT_SIZE, 543 (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys), 544 0); 545 init_timer(&(up->uart_dma.rx_timer)); 546 up->uart_dma.rx_timer.function = serial_omap_rx_timeout; 547 up->uart_dma.rx_timer.data = up->pdev->id; 548 /* Currently the buffer size is 4KB. Can increase it */ 549 up->uart_dma.rx_buf = dma_alloc_coherent(NULL, 550 up->uart_dma.rx_buf_size, 551 (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0); 552 } 553 /* 554 * Finally, enable interrupts. Note: Modem status interrupts 555 * are set via set_termios(), which will be occurring imminently 556 * anyway, so we don't enable them here. 557 */ 558 up->ier = UART_IER_RLSI | UART_IER_RDI; 559 serial_out(up, UART_IER, up->ier); 560 561 /* Enable module level wake up */ 562 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP); 563 564 pm_runtime_mark_last_busy(&up->pdev->dev); 565 pm_runtime_put_autosuspend(&up->pdev->dev); 566 up->port_activity = jiffies; 567 return 0; 568 } 569 570 static void serial_omap_shutdown(struct uart_port *port) 571 { 572 struct uart_omap_port *up = (struct uart_omap_port *)port; 573 unsigned long flags = 0; 574 575 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->pdev->id); 576 577 pm_runtime_get_sync(&up->pdev->dev); 578 /* 579 * Disable interrupts from this port 580 */ 581 up->ier = 0; 582 serial_out(up, UART_IER, 0); 583 584 spin_lock_irqsave(&up->port.lock, flags); 585 up->port.mctrl &= ~TIOCM_OUT2; 586 serial_omap_set_mctrl(&up->port, up->port.mctrl); 587 spin_unlock_irqrestore(&up->port.lock, flags); 588 589 /* 590 * Disable break condition and FIFOs 591 */ 592 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); 593 serial_omap_clear_fifos(up); 594 595 /* 596 * Read data port to reset things, and then free the irq 597 */ 598 if (serial_in(up, UART_LSR) & UART_LSR_DR) 599 (void) serial_in(up, UART_RX); 600 if (up->use_dma) { 601 dma_free_coherent(up->port.dev, 602 UART_XMIT_SIZE, up->port.state->xmit.buf, 603 up->uart_dma.tx_buf_dma_phys); 604 up->port.state->xmit.buf = NULL; 605 serial_omap_stop_rx(port); 606 dma_free_coherent(up->port.dev, 607 up->uart_dma.rx_buf_size, up->uart_dma.rx_buf, 608 up->uart_dma.rx_buf_dma_phys); 609 up->uart_dma.rx_buf = NULL; 610 } 611 612 pm_runtime_put(&up->pdev->dev); 613 free_irq(up->port.irq, up); 614 } 615 616 static inline void 617 serial_omap_configure_xonxoff 618 (struct uart_omap_port *up, struct ktermios *termios) 619 { 620 up->lcr = serial_in(up, UART_LCR); 621 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 622 up->efr = serial_in(up, UART_EFR); 623 serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB); 624 625 serial_out(up, UART_XON1, termios->c_cc[VSTART]); 626 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); 627 628 /* clear SW control mode bits */ 629 up->efr &= OMAP_UART_SW_CLR; 630 631 /* 632 * IXON Flag: 633 * Enable XON/XOFF flow control on output. 634 * Transmit XON1, XOFF1 635 */ 636 if (termios->c_iflag & IXON) 637 up->efr |= OMAP_UART_SW_TX; 638 639 /* 640 * IXOFF Flag: 641 * Enable XON/XOFF flow control on input. 642 * Receiver compares XON1, XOFF1. 643 */ 644 if (termios->c_iflag & IXOFF) 645 up->efr |= OMAP_UART_SW_RX; 646 647 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 648 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 649 650 up->mcr = serial_in(up, UART_MCR); 651 652 /* 653 * IXANY Flag: 654 * Enable any character to restart output. 655 * Operation resumes after receiving any 656 * character after recognition of the XOFF character 657 */ 658 if (termios->c_iflag & IXANY) 659 up->mcr |= UART_MCR_XONANY; 660 661 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 662 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 663 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); 664 /* Enable special char function UARTi.EFR_REG[5] and 665 * load the new software flow control mode IXON or IXOFF 666 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value. 667 */ 668 serial_out(up, UART_EFR, up->efr | UART_EFR_SCD); 669 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 670 671 serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR); 672 serial_out(up, UART_LCR, up->lcr); 673 } 674 675 static void 676 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, 677 struct ktermios *old) 678 { 679 struct uart_omap_port *up = (struct uart_omap_port *)port; 680 unsigned char cval = 0; 681 unsigned char efr = 0; 682 unsigned long flags = 0; 683 unsigned int baud, quot; 684 685 switch (termios->c_cflag & CSIZE) { 686 case CS5: 687 cval = UART_LCR_WLEN5; 688 break; 689 case CS6: 690 cval = UART_LCR_WLEN6; 691 break; 692 case CS7: 693 cval = UART_LCR_WLEN7; 694 break; 695 default: 696 case CS8: 697 cval = UART_LCR_WLEN8; 698 break; 699 } 700 701 if (termios->c_cflag & CSTOPB) 702 cval |= UART_LCR_STOP; 703 if (termios->c_cflag & PARENB) 704 cval |= UART_LCR_PARITY; 705 if (!(termios->c_cflag & PARODD)) 706 cval |= UART_LCR_EPAR; 707 708 /* 709 * Ask the core to calculate the divisor for us. 710 */ 711 712 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); 713 quot = serial_omap_get_divisor(port, baud); 714 715 up->dll = quot & 0xff; 716 up->dlh = quot >> 8; 717 up->mdr1 = UART_OMAP_MDR1_DISABLE; 718 719 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | 720 UART_FCR_ENABLE_FIFO; 721 if (up->use_dma) 722 up->fcr |= UART_FCR_DMA_SELECT; 723 724 /* 725 * Ok, we're now changing the port state. Do it with 726 * interrupts disabled. 727 */ 728 pm_runtime_get_sync(&up->pdev->dev); 729 spin_lock_irqsave(&up->port.lock, flags); 730 731 /* 732 * Update the per-port timeout. 733 */ 734 uart_update_timeout(port, termios->c_cflag, baud); 735 736 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 737 if (termios->c_iflag & INPCK) 738 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 739 if (termios->c_iflag & (BRKINT | PARMRK)) 740 up->port.read_status_mask |= UART_LSR_BI; 741 742 /* 743 * Characters to ignore 744 */ 745 up->port.ignore_status_mask = 0; 746 if (termios->c_iflag & IGNPAR) 747 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 748 if (termios->c_iflag & IGNBRK) { 749 up->port.ignore_status_mask |= UART_LSR_BI; 750 /* 751 * If we're ignoring parity and break indicators, 752 * ignore overruns too (for real raw support). 753 */ 754 if (termios->c_iflag & IGNPAR) 755 up->port.ignore_status_mask |= UART_LSR_OE; 756 } 757 758 /* 759 * ignore all characters if CREAD is not set 760 */ 761 if ((termios->c_cflag & CREAD) == 0) 762 up->port.ignore_status_mask |= UART_LSR_DR; 763 764 /* 765 * Modem status interrupts 766 */ 767 up->ier &= ~UART_IER_MSI; 768 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 769 up->ier |= UART_IER_MSI; 770 serial_out(up, UART_IER, up->ier); 771 serial_out(up, UART_LCR, cval); /* reset DLAB */ 772 up->lcr = cval; 773 774 /* FIFOs and DMA Settings */ 775 776 /* FCR can be changed only when the 777 * baud clock is not running 778 * DLL_REG and DLH_REG set to 0. 779 */ 780 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 781 serial_out(up, UART_DLL, 0); 782 serial_out(up, UART_DLM, 0); 783 serial_out(up, UART_LCR, 0); 784 785 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 786 787 up->efr = serial_in(up, UART_EFR); 788 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 789 790 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 791 up->mcr = serial_in(up, UART_MCR); 792 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 793 /* FIFO ENABLE, DMA MODE */ 794 serial_out(up, UART_FCR, up->fcr); 795 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 796 797 if (up->use_dma) { 798 serial_out(up, UART_TI752_TLR, 0); 799 up->scr |= (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8); 800 } 801 802 serial_out(up, UART_OMAP_SCR, up->scr); 803 804 serial_out(up, UART_EFR, up->efr); 805 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 806 serial_out(up, UART_MCR, up->mcr); 807 808 /* Protocol, Baud Rate, and Interrupt Settings */ 809 810 serial_out(up, UART_OMAP_MDR1, up->mdr1); 811 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 812 813 up->efr = serial_in(up, UART_EFR); 814 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 815 816 serial_out(up, UART_LCR, 0); 817 serial_out(up, UART_IER, 0); 818 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 819 820 serial_out(up, UART_DLL, up->dll); /* LS of divisor */ 821 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */ 822 823 serial_out(up, UART_LCR, 0); 824 serial_out(up, UART_IER, up->ier); 825 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 826 827 serial_out(up, UART_EFR, up->efr); 828 serial_out(up, UART_LCR, cval); 829 830 if (baud > 230400 && baud != 3000000) 831 up->mdr1 = UART_OMAP_MDR1_13X_MODE; 832 else 833 up->mdr1 = UART_OMAP_MDR1_16X_MODE; 834 835 serial_out(up, UART_OMAP_MDR1, up->mdr1); 836 837 /* Hardware Flow Control Configuration */ 838 839 if (termios->c_cflag & CRTSCTS) { 840 efr |= (UART_EFR_CTS | UART_EFR_RTS); 841 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 842 843 up->mcr = serial_in(up, UART_MCR); 844 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 845 846 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 847 up->efr = serial_in(up, UART_EFR); 848 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 849 850 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); 851 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */ 852 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 853 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS); 854 serial_out(up, UART_LCR, cval); 855 } 856 857 serial_omap_set_mctrl(&up->port, up->port.mctrl); 858 /* Software Flow Control Configuration */ 859 serial_omap_configure_xonxoff(up, termios); 860 861 spin_unlock_irqrestore(&up->port.lock, flags); 862 pm_runtime_put(&up->pdev->dev); 863 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->pdev->id); 864 } 865 866 static void 867 serial_omap_pm(struct uart_port *port, unsigned int state, 868 unsigned int oldstate) 869 { 870 struct uart_omap_port *up = (struct uart_omap_port *)port; 871 unsigned char efr; 872 873 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->pdev->id); 874 875 pm_runtime_get_sync(&up->pdev->dev); 876 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 877 efr = serial_in(up, UART_EFR); 878 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 879 serial_out(up, UART_LCR, 0); 880 881 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 882 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 883 serial_out(up, UART_EFR, efr); 884 serial_out(up, UART_LCR, 0); 885 886 if (!device_may_wakeup(&up->pdev->dev)) { 887 if (!state) 888 pm_runtime_forbid(&up->pdev->dev); 889 else 890 pm_runtime_allow(&up->pdev->dev); 891 } 892 893 pm_runtime_put(&up->pdev->dev); 894 } 895 896 static void serial_omap_release_port(struct uart_port *port) 897 { 898 dev_dbg(port->dev, "serial_omap_release_port+\n"); 899 } 900 901 static int serial_omap_request_port(struct uart_port *port) 902 { 903 dev_dbg(port->dev, "serial_omap_request_port+\n"); 904 return 0; 905 } 906 907 static void serial_omap_config_port(struct uart_port *port, int flags) 908 { 909 struct uart_omap_port *up = (struct uart_omap_port *)port; 910 911 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", 912 up->pdev->id); 913 up->port.type = PORT_OMAP; 914 } 915 916 static int 917 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) 918 { 919 /* we don't want the core code to modify any port params */ 920 dev_dbg(port->dev, "serial_omap_verify_port+\n"); 921 return -EINVAL; 922 } 923 924 static const char * 925 serial_omap_type(struct uart_port *port) 926 { 927 struct uart_omap_port *up = (struct uart_omap_port *)port; 928 929 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->pdev->id); 930 return up->name; 931 } 932 933 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 934 935 static inline void wait_for_xmitr(struct uart_omap_port *up) 936 { 937 unsigned int status, tmout = 10000; 938 939 /* Wait up to 10ms for the character(s) to be sent. */ 940 do { 941 status = serial_in(up, UART_LSR); 942 943 if (status & UART_LSR_BI) 944 up->lsr_break_flag = UART_LSR_BI; 945 946 if (--tmout == 0) 947 break; 948 udelay(1); 949 } while ((status & BOTH_EMPTY) != BOTH_EMPTY); 950 951 /* Wait up to 1s for flow control if necessary */ 952 if (up->port.flags & UPF_CONS_FLOW) { 953 tmout = 1000000; 954 for (tmout = 1000000; tmout; tmout--) { 955 unsigned int msr = serial_in(up, UART_MSR); 956 957 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; 958 if (msr & UART_MSR_CTS) 959 break; 960 961 udelay(1); 962 } 963 } 964 } 965 966 #ifdef CONFIG_CONSOLE_POLL 967 968 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) 969 { 970 struct uart_omap_port *up = (struct uart_omap_port *)port; 971 972 pm_runtime_get_sync(&up->pdev->dev); 973 wait_for_xmitr(up); 974 serial_out(up, UART_TX, ch); 975 pm_runtime_put(&up->pdev->dev); 976 } 977 978 static int serial_omap_poll_get_char(struct uart_port *port) 979 { 980 struct uart_omap_port *up = (struct uart_omap_port *)port; 981 unsigned int status; 982 983 pm_runtime_get_sync(&up->pdev->dev); 984 status = serial_in(up, UART_LSR); 985 if (!(status & UART_LSR_DR)) 986 return NO_POLL_CHAR; 987 988 status = serial_in(up, UART_RX); 989 pm_runtime_put(&up->pdev->dev); 990 return status; 991 } 992 993 #endif /* CONFIG_CONSOLE_POLL */ 994 995 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 996 997 static struct uart_omap_port *serial_omap_console_ports[4]; 998 999 static struct uart_driver serial_omap_reg; 1000 1001 static void serial_omap_console_putchar(struct uart_port *port, int ch) 1002 { 1003 struct uart_omap_port *up = (struct uart_omap_port *)port; 1004 1005 wait_for_xmitr(up); 1006 serial_out(up, UART_TX, ch); 1007 } 1008 1009 static void 1010 serial_omap_console_write(struct console *co, const char *s, 1011 unsigned int count) 1012 { 1013 struct uart_omap_port *up = serial_omap_console_ports[co->index]; 1014 unsigned long flags; 1015 unsigned int ier; 1016 int locked = 1; 1017 1018 pm_runtime_get_sync(&up->pdev->dev); 1019 1020 local_irq_save(flags); 1021 if (up->port.sysrq) 1022 locked = 0; 1023 else if (oops_in_progress) 1024 locked = spin_trylock(&up->port.lock); 1025 else 1026 spin_lock(&up->port.lock); 1027 1028 /* 1029 * First save the IER then disable the interrupts 1030 */ 1031 ier = serial_in(up, UART_IER); 1032 serial_out(up, UART_IER, 0); 1033 1034 uart_console_write(&up->port, s, count, serial_omap_console_putchar); 1035 1036 /* 1037 * Finally, wait for transmitter to become empty 1038 * and restore the IER 1039 */ 1040 wait_for_xmitr(up); 1041 serial_out(up, UART_IER, ier); 1042 /* 1043 * The receive handling will happen properly because the 1044 * receive ready bit will still be set; it is not cleared 1045 * on read. However, modem control will not, we must 1046 * call it if we have saved something in the saved flags 1047 * while processing with interrupts off. 1048 */ 1049 if (up->msr_saved_flags) 1050 check_modem_status(up); 1051 1052 pm_runtime_mark_last_busy(&up->pdev->dev); 1053 pm_runtime_put_autosuspend(&up->pdev->dev); 1054 if (locked) 1055 spin_unlock(&up->port.lock); 1056 local_irq_restore(flags); 1057 } 1058 1059 static int __init 1060 serial_omap_console_setup(struct console *co, char *options) 1061 { 1062 struct uart_omap_port *up; 1063 int baud = 115200; 1064 int bits = 8; 1065 int parity = 'n'; 1066 int flow = 'n'; 1067 1068 if (serial_omap_console_ports[co->index] == NULL) 1069 return -ENODEV; 1070 up = serial_omap_console_ports[co->index]; 1071 1072 if (options) 1073 uart_parse_options(options, &baud, &parity, &bits, &flow); 1074 1075 return uart_set_options(&up->port, co, baud, parity, bits, flow); 1076 } 1077 1078 static struct console serial_omap_console = { 1079 .name = OMAP_SERIAL_NAME, 1080 .write = serial_omap_console_write, 1081 .device = uart_console_device, 1082 .setup = serial_omap_console_setup, 1083 .flags = CON_PRINTBUFFER, 1084 .index = -1, 1085 .data = &serial_omap_reg, 1086 }; 1087 1088 static void serial_omap_add_console_port(struct uart_omap_port *up) 1089 { 1090 serial_omap_console_ports[up->pdev->id] = up; 1091 } 1092 1093 #define OMAP_CONSOLE (&serial_omap_console) 1094 1095 #else 1096 1097 #define OMAP_CONSOLE NULL 1098 1099 static inline void serial_omap_add_console_port(struct uart_omap_port *up) 1100 {} 1101 1102 #endif 1103 1104 static struct uart_ops serial_omap_pops = { 1105 .tx_empty = serial_omap_tx_empty, 1106 .set_mctrl = serial_omap_set_mctrl, 1107 .get_mctrl = serial_omap_get_mctrl, 1108 .stop_tx = serial_omap_stop_tx, 1109 .start_tx = serial_omap_start_tx, 1110 .stop_rx = serial_omap_stop_rx, 1111 .enable_ms = serial_omap_enable_ms, 1112 .break_ctl = serial_omap_break_ctl, 1113 .startup = serial_omap_startup, 1114 .shutdown = serial_omap_shutdown, 1115 .set_termios = serial_omap_set_termios, 1116 .pm = serial_omap_pm, 1117 .type = serial_omap_type, 1118 .release_port = serial_omap_release_port, 1119 .request_port = serial_omap_request_port, 1120 .config_port = serial_omap_config_port, 1121 .verify_port = serial_omap_verify_port, 1122 #ifdef CONFIG_CONSOLE_POLL 1123 .poll_put_char = serial_omap_poll_put_char, 1124 .poll_get_char = serial_omap_poll_get_char, 1125 #endif 1126 }; 1127 1128 static struct uart_driver serial_omap_reg = { 1129 .owner = THIS_MODULE, 1130 .driver_name = "OMAP-SERIAL", 1131 .dev_name = OMAP_SERIAL_NAME, 1132 .nr = OMAP_MAX_HSUART_PORTS, 1133 .cons = OMAP_CONSOLE, 1134 }; 1135 1136 #ifdef CONFIG_SUSPEND 1137 static int serial_omap_suspend(struct device *dev) 1138 { 1139 struct uart_omap_port *up = dev_get_drvdata(dev); 1140 1141 if (up) 1142 uart_suspend_port(&serial_omap_reg, &up->port); 1143 return 0; 1144 } 1145 1146 static int serial_omap_resume(struct device *dev) 1147 { 1148 struct uart_omap_port *up = dev_get_drvdata(dev); 1149 1150 if (up) 1151 uart_resume_port(&serial_omap_reg, &up->port); 1152 return 0; 1153 } 1154 #endif 1155 1156 static void serial_omap_rx_timeout(unsigned long uart_no) 1157 { 1158 struct uart_omap_port *up = ui[uart_no]; 1159 unsigned int curr_dma_pos, curr_transmitted_size; 1160 int ret = 0; 1161 1162 curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel); 1163 if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) || 1164 (curr_dma_pos == 0)) { 1165 if (jiffies_to_msecs(jiffies - up->port_activity) < 1166 RX_TIMEOUT) { 1167 mod_timer(&up->uart_dma.rx_timer, jiffies + 1168 usecs_to_jiffies(up->uart_dma.rx_timeout)); 1169 } else { 1170 serial_omap_stop_rxdma(up); 1171 up->ier |= (UART_IER_RDI | UART_IER_RLSI); 1172 serial_out(up, UART_IER, up->ier); 1173 } 1174 return; 1175 } 1176 1177 curr_transmitted_size = curr_dma_pos - 1178 up->uart_dma.prev_rx_dma_pos; 1179 up->port.icount.rx += curr_transmitted_size; 1180 tty_insert_flip_string(up->port.state->port.tty, 1181 up->uart_dma.rx_buf + 1182 (up->uart_dma.prev_rx_dma_pos - 1183 up->uart_dma.rx_buf_dma_phys), 1184 curr_transmitted_size); 1185 tty_flip_buffer_push(up->port.state->port.tty); 1186 up->uart_dma.prev_rx_dma_pos = curr_dma_pos; 1187 if (up->uart_dma.rx_buf_size + 1188 up->uart_dma.rx_buf_dma_phys == curr_dma_pos) { 1189 ret = serial_omap_start_rxdma(up); 1190 if (ret < 0) { 1191 serial_omap_stop_rxdma(up); 1192 up->ier |= (UART_IER_RDI | UART_IER_RLSI); 1193 serial_out(up, UART_IER, up->ier); 1194 } 1195 } else { 1196 mod_timer(&up->uart_dma.rx_timer, jiffies + 1197 usecs_to_jiffies(up->uart_dma.rx_timeout)); 1198 } 1199 up->port_activity = jiffies; 1200 } 1201 1202 static void uart_rx_dma_callback(int lch, u16 ch_status, void *data) 1203 { 1204 return; 1205 } 1206 1207 static int serial_omap_start_rxdma(struct uart_omap_port *up) 1208 { 1209 int ret = 0; 1210 1211 if (up->uart_dma.rx_dma_channel == -1) { 1212 pm_runtime_get_sync(&up->pdev->dev); 1213 ret = omap_request_dma(up->uart_dma.uart_dma_rx, 1214 "UART Rx DMA", 1215 (void *)uart_rx_dma_callback, up, 1216 &(up->uart_dma.rx_dma_channel)); 1217 if (ret < 0) 1218 return ret; 1219 1220 omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0, 1221 OMAP_DMA_AMODE_CONSTANT, 1222 up->uart_dma.uart_base, 0, 0); 1223 omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0, 1224 OMAP_DMA_AMODE_POST_INC, 1225 up->uart_dma.rx_buf_dma_phys, 0, 0); 1226 omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel, 1227 OMAP_DMA_DATA_TYPE_S8, 1228 up->uart_dma.rx_buf_size, 1, 1229 OMAP_DMA_SYNC_ELEMENT, 1230 up->uart_dma.uart_dma_rx, 0); 1231 } 1232 up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys; 1233 /* FIXME: Cache maintenance needed here? */ 1234 omap_start_dma(up->uart_dma.rx_dma_channel); 1235 mod_timer(&up->uart_dma.rx_timer, jiffies + 1236 usecs_to_jiffies(up->uart_dma.rx_timeout)); 1237 up->uart_dma.rx_dma_used = true; 1238 return ret; 1239 } 1240 1241 static void serial_omap_continue_tx(struct uart_omap_port *up) 1242 { 1243 struct circ_buf *xmit = &up->port.state->xmit; 1244 unsigned int start = up->uart_dma.tx_buf_dma_phys 1245 + (xmit->tail & (UART_XMIT_SIZE - 1)); 1246 1247 if (uart_circ_empty(xmit)) 1248 return; 1249 1250 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit); 1251 /* 1252 * It is a circular buffer. See if the buffer has wounded back. 1253 * If yes it will have to be transferred in two separate dma 1254 * transfers 1255 */ 1256 if (start + up->uart_dma.tx_buf_size >= 1257 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) 1258 up->uart_dma.tx_buf_size = 1259 (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start; 1260 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0, 1261 OMAP_DMA_AMODE_CONSTANT, 1262 up->uart_dma.uart_base, 0, 0); 1263 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0, 1264 OMAP_DMA_AMODE_POST_INC, start, 0, 0); 1265 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel, 1266 OMAP_DMA_DATA_TYPE_S8, 1267 up->uart_dma.tx_buf_size, 1, 1268 OMAP_DMA_SYNC_ELEMENT, 1269 up->uart_dma.uart_dma_tx, 0); 1270 /* FIXME: Cache maintenance needed here? */ 1271 omap_start_dma(up->uart_dma.tx_dma_channel); 1272 } 1273 1274 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data) 1275 { 1276 struct uart_omap_port *up = (struct uart_omap_port *)data; 1277 struct circ_buf *xmit = &up->port.state->xmit; 1278 1279 xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \ 1280 (UART_XMIT_SIZE - 1); 1281 up->port.icount.tx += up->uart_dma.tx_buf_size; 1282 1283 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1284 uart_write_wakeup(&up->port); 1285 1286 if (uart_circ_empty(xmit)) { 1287 spin_lock(&(up->uart_dma.tx_lock)); 1288 serial_omap_stop_tx(&up->port); 1289 up->uart_dma.tx_dma_used = false; 1290 spin_unlock(&(up->uart_dma.tx_lock)); 1291 } else { 1292 omap_stop_dma(up->uart_dma.tx_dma_channel); 1293 serial_omap_continue_tx(up); 1294 } 1295 up->port_activity = jiffies; 1296 return; 1297 } 1298 1299 static int serial_omap_probe(struct platform_device *pdev) 1300 { 1301 struct uart_omap_port *up; 1302 struct resource *mem, *irq, *dma_tx, *dma_rx; 1303 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data; 1304 int ret = -ENOSPC; 1305 1306 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1307 if (!mem) { 1308 dev_err(&pdev->dev, "no mem resource?\n"); 1309 return -ENODEV; 1310 } 1311 1312 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1313 if (!irq) { 1314 dev_err(&pdev->dev, "no irq resource?\n"); 1315 return -ENODEV; 1316 } 1317 1318 if (!request_mem_region(mem->start, resource_size(mem), 1319 pdev->dev.driver->name)) { 1320 dev_err(&pdev->dev, "memory region already claimed\n"); 1321 return -EBUSY; 1322 } 1323 1324 dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 1325 if (!dma_rx) { 1326 ret = -EINVAL; 1327 goto err; 1328 } 1329 1330 dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 1331 if (!dma_tx) { 1332 ret = -EINVAL; 1333 goto err; 1334 } 1335 1336 up = kzalloc(sizeof(*up), GFP_KERNEL); 1337 if (up == NULL) { 1338 ret = -ENOMEM; 1339 goto do_release_region; 1340 } 1341 sprintf(up->name, "OMAP UART%d", pdev->id); 1342 up->pdev = pdev; 1343 up->port.dev = &pdev->dev; 1344 up->port.type = PORT_OMAP; 1345 up->port.iotype = UPIO_MEM; 1346 up->port.irq = irq->start; 1347 1348 up->port.regshift = 2; 1349 up->port.fifosize = 64; 1350 up->port.ops = &serial_omap_pops; 1351 up->port.line = pdev->id; 1352 1353 up->port.mapbase = mem->start; 1354 up->port.membase = ioremap(mem->start, resource_size(mem)); 1355 if (!up->port.membase) { 1356 dev_err(&pdev->dev, "can't ioremap UART\n"); 1357 ret = -ENOMEM; 1358 goto err; 1359 } 1360 1361 up->port.flags = omap_up_info->flags; 1362 up->port.uartclk = omap_up_info->uartclk; 1363 up->uart_dma.uart_base = mem->start; 1364 1365 if (omap_up_info->dma_enabled) { 1366 up->uart_dma.uart_dma_tx = dma_tx->start; 1367 up->uart_dma.uart_dma_rx = dma_rx->start; 1368 up->use_dma = 1; 1369 up->uart_dma.rx_buf_size = 4096; 1370 up->uart_dma.rx_timeout = 2; 1371 spin_lock_init(&(up->uart_dma.tx_lock)); 1372 spin_lock_init(&(up->uart_dma.rx_lock)); 1373 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE; 1374 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE; 1375 } 1376 1377 pm_runtime_use_autosuspend(&pdev->dev); 1378 pm_runtime_set_autosuspend_delay(&pdev->dev, 1379 OMAP_UART_AUTOSUSPEND_DELAY); 1380 1381 pm_runtime_irq_safe(&pdev->dev); 1382 pm_runtime_enable(&pdev->dev); 1383 pm_runtime_get_sync(&pdev->dev); 1384 1385 ui[pdev->id] = up; 1386 serial_omap_add_console_port(up); 1387 1388 ret = uart_add_one_port(&serial_omap_reg, &up->port); 1389 if (ret != 0) 1390 goto do_release_region; 1391 1392 pm_runtime_put(&pdev->dev); 1393 platform_set_drvdata(pdev, up); 1394 return 0; 1395 err: 1396 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n", 1397 pdev->id, __func__, ret); 1398 do_release_region: 1399 release_mem_region(mem->start, resource_size(mem)); 1400 return ret; 1401 } 1402 1403 static int serial_omap_remove(struct platform_device *dev) 1404 { 1405 struct uart_omap_port *up = platform_get_drvdata(dev); 1406 1407 if (up) { 1408 pm_runtime_disable(&up->pdev->dev); 1409 uart_remove_one_port(&serial_omap_reg, &up->port); 1410 kfree(up); 1411 } 1412 1413 platform_set_drvdata(dev, NULL); 1414 return 0; 1415 } 1416 1417 static void serial_omap_restore_context(struct uart_omap_port *up) 1418 { 1419 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); 1420 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1421 serial_out(up, UART_EFR, UART_EFR_ECB); 1422 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1423 serial_out(up, UART_IER, 0x0); 1424 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1425 serial_out(up, UART_DLL, up->dll); 1426 serial_out(up, UART_DLM, up->dlh); 1427 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1428 serial_out(up, UART_IER, up->ier); 1429 serial_out(up, UART_FCR, up->fcr); 1430 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1431 serial_out(up, UART_MCR, up->mcr); 1432 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1433 serial_out(up, UART_OMAP_SCR, up->scr); 1434 serial_out(up, UART_EFR, up->efr); 1435 serial_out(up, UART_LCR, up->lcr); 1436 serial_out(up, UART_OMAP_MDR1, up->mdr1); 1437 } 1438 1439 #ifdef CONFIG_PM_RUNTIME 1440 static int serial_omap_runtime_suspend(struct device *dev) 1441 { 1442 return 0; 1443 } 1444 1445 static int serial_omap_runtime_resume(struct device *dev) 1446 { 1447 struct uart_omap_port *up = dev_get_drvdata(dev); 1448 1449 if (up) 1450 serial_omap_restore_context(up); 1451 1452 return 0; 1453 } 1454 #endif 1455 1456 static const struct dev_pm_ops serial_omap_dev_pm_ops = { 1457 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume) 1458 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend, 1459 serial_omap_runtime_resume, NULL) 1460 }; 1461 1462 static struct platform_driver serial_omap_driver = { 1463 .probe = serial_omap_probe, 1464 .remove = serial_omap_remove, 1465 .driver = { 1466 .name = DRIVER_NAME, 1467 .pm = &serial_omap_dev_pm_ops, 1468 }, 1469 }; 1470 1471 static int __init serial_omap_init(void) 1472 { 1473 int ret; 1474 1475 ret = uart_register_driver(&serial_omap_reg); 1476 if (ret != 0) 1477 return ret; 1478 ret = platform_driver_register(&serial_omap_driver); 1479 if (ret != 0) 1480 uart_unregister_driver(&serial_omap_reg); 1481 return ret; 1482 } 1483 1484 static void __exit serial_omap_exit(void) 1485 { 1486 platform_driver_unregister(&serial_omap_driver); 1487 uart_unregister_driver(&serial_omap_reg); 1488 } 1489 1490 module_init(serial_omap_init); 1491 module_exit(serial_omap_exit); 1492 1493 MODULE_DESCRIPTION("OMAP High Speed UART driver"); 1494 MODULE_LICENSE("GPL"); 1495 MODULE_AUTHOR("Texas Instruments Inc"); 1496