1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for OMAP-UART controller. 4 * Based on drivers/serial/8250.c 5 * 6 * Copyright (C) 2010 Texas Instruments. 7 * 8 * Authors: 9 * Govindraj R <govindraj.raja@ti.com> 10 * Thara Gopinath <thara@ti.com> 11 * 12 * Note: This driver is made separate from 8250 driver as we cannot 13 * over load 8250 driver with omap platform specific configuration for 14 * features like DMA, it makes easier to implement features like DMA and 15 * hardware flow control and software flow control configuration with 16 * this driver as required for the omap-platform. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/console.h> 22 #include <linux/serial.h> 23 #include <linux/serial_reg.h> 24 #include <linux/delay.h> 25 #include <linux/slab.h> 26 #include <linux/tty.h> 27 #include <linux/tty_flip.h> 28 #include <linux/platform_device.h> 29 #include <linux/io.h> 30 #include <linux/clk.h> 31 #include <linux/serial_core.h> 32 #include <linux/irq.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/pm_wakeirq.h> 35 #include <linux/of.h> 36 #include <linux/of_irq.h> 37 #include <linux/gpio/consumer.h> 38 #include <linux/platform_data/serial-omap.h> 39 40 #define OMAP_MAX_HSUART_PORTS 10 41 42 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 43 44 #define OMAP_UART_REV_42 0x0402 45 #define OMAP_UART_REV_46 0x0406 46 #define OMAP_UART_REV_52 0x0502 47 #define OMAP_UART_REV_63 0x0603 48 49 #define OMAP_UART_TX_WAKEUP_EN BIT(7) 50 51 /* Feature flags */ 52 #define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0) 53 54 #define UART_ERRATA_i202_MDR1_ACCESS BIT(0) 55 #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1) 56 57 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */ 58 59 /* SCR register bitmasks */ 60 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 61 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 62 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 63 64 /* FCR register bitmasks */ 65 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6) 66 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4) 67 68 /* MVR register bitmasks */ 69 #define OMAP_UART_MVR_SCHEME_SHIFT 30 70 71 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 72 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 73 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 74 75 #define OMAP_UART_MVR_MAJ_MASK 0x700 76 #define OMAP_UART_MVR_MAJ_SHIFT 8 77 #define OMAP_UART_MVR_MIN_MASK 0x3f 78 79 #define OMAP_UART_DMA_CH_FREE -1 80 81 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA 82 #define OMAP_MODE13X_SPEED 230400 83 84 /* WER = 0x7F 85 * Enable module level wakeup in WER reg 86 */ 87 #define OMAP_UART_WER_MOD_WKUP 0x7F 88 89 /* Enable XON/XOFF flow control on output */ 90 #define OMAP_UART_SW_TX 0x08 91 92 /* Enable XON/XOFF flow control on input */ 93 #define OMAP_UART_SW_RX 0x02 94 95 #define OMAP_UART_SW_CLR 0xF0 96 97 #define OMAP_UART_TCR_TRIG 0x0F 98 99 struct uart_omap_dma { 100 u8 uart_dma_tx; 101 u8 uart_dma_rx; 102 int rx_dma_channel; 103 int tx_dma_channel; 104 dma_addr_t rx_buf_dma_phys; 105 dma_addr_t tx_buf_dma_phys; 106 unsigned int uart_base; 107 /* 108 * Buffer for rx dma. It is not required for tx because the buffer 109 * comes from port structure. 110 */ 111 unsigned char *rx_buf; 112 unsigned int prev_rx_dma_pos; 113 int tx_buf_size; 114 int tx_dma_used; 115 int rx_dma_used; 116 spinlock_t tx_lock; 117 spinlock_t rx_lock; 118 /* timer to poll activity on rx dma */ 119 struct timer_list rx_timer; 120 unsigned int rx_buf_size; 121 unsigned int rx_poll_rate; 122 unsigned int rx_timeout; 123 }; 124 125 struct uart_omap_port { 126 struct uart_port port; 127 struct uart_omap_dma uart_dma; 128 struct device *dev; 129 int wakeirq; 130 131 unsigned char ier; 132 unsigned char lcr; 133 unsigned char mcr; 134 unsigned char fcr; 135 unsigned char efr; 136 unsigned char dll; 137 unsigned char dlh; 138 unsigned char mdr1; 139 unsigned char scr; 140 unsigned char wer; 141 142 int use_dma; 143 /* 144 * Some bits in registers are cleared on a read, so they must 145 * be saved whenever the register is read, but the bits will not 146 * be immediately processed. 147 */ 148 unsigned int lsr_break_flag; 149 unsigned char msr_saved_flags; 150 char name[20]; 151 unsigned long port_activity; 152 int context_loss_cnt; 153 u32 errata; 154 u32 features; 155 156 struct gpio_desc *rts_gpiod; 157 158 struct pm_qos_request pm_qos_request; 159 u32 latency; 160 u32 calc_latency; 161 struct work_struct qos_work; 162 bool is_suspending; 163 164 unsigned int rs485_tx_filter_count; 165 }; 166 167 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port))) 168 169 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; 170 171 /* Forward declaration of functions */ 172 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1); 173 174 static inline unsigned int serial_in(struct uart_omap_port *up, int offset) 175 { 176 offset <<= up->port.regshift; 177 return readw(up->port.membase + offset); 178 } 179 180 static inline void serial_out(struct uart_omap_port *up, int offset, int value) 181 { 182 offset <<= up->port.regshift; 183 writew(value, up->port.membase + offset); 184 } 185 186 static inline void serial_omap_clear_fifos(struct uart_omap_port *up) 187 { 188 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 189 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 190 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 191 serial_out(up, UART_FCR, 0); 192 } 193 194 #ifdef CONFIG_PM 195 static int serial_omap_get_context_loss_count(struct uart_omap_port *up) 196 { 197 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev); 198 199 if (!pdata || !pdata->get_context_loss_count) 200 return -EINVAL; 201 202 return pdata->get_context_loss_count(up->dev); 203 } 204 205 /* REVISIT: Remove this when omap3 boots in device tree only mode */ 206 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable) 207 { 208 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev); 209 210 if (!pdata || !pdata->enable_wakeup) 211 return; 212 213 pdata->enable_wakeup(up->dev, enable); 214 } 215 #endif /* CONFIG_PM */ 216 217 /* 218 * Calculate the absolute difference between the desired and actual baud 219 * rate for the given mode. 220 */ 221 static inline int calculate_baud_abs_diff(struct uart_port *port, 222 unsigned int baud, unsigned int mode) 223 { 224 unsigned int n = port->uartclk / (mode * baud); 225 int abs_diff; 226 227 if (n == 0) 228 n = 1; 229 230 abs_diff = baud - (port->uartclk / (mode * n)); 231 if (abs_diff < 0) 232 abs_diff = -abs_diff; 233 234 return abs_diff; 235 } 236 237 /* 238 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X 239 * @port: uart port info 240 * @baud: baudrate for which mode needs to be determined 241 * 242 * Returns true if baud rate is MODE16X and false if MODE13X 243 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values, 244 * and Error Rates" determines modes not for all common baud rates. 245 * E.g. for 1000000 baud rate mode must be 16x, but according to that 246 * table it's determined as 13x. 247 */ 248 static bool 249 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud) 250 { 251 int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13); 252 int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16); 253 254 return (abs_diff_13 >= abs_diff_16); 255 } 256 257 /* 258 * serial_omap_get_divisor - calculate divisor value 259 * @port: uart port info 260 * @baud: baudrate for which divisor needs to be calculated. 261 */ 262 static unsigned int 263 serial_omap_get_divisor(struct uart_port *port, unsigned int baud) 264 { 265 unsigned int mode; 266 267 if (!serial_omap_baud_is_mode16(port, baud)) 268 mode = 13; 269 else 270 mode = 16; 271 return port->uartclk/(mode * baud); 272 } 273 274 static void serial_omap_enable_ms(struct uart_port *port) 275 { 276 struct uart_omap_port *up = to_uart_omap_port(port); 277 278 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line); 279 280 up->ier |= UART_IER_MSI; 281 serial_out(up, UART_IER, up->ier); 282 } 283 284 static void serial_omap_stop_tx(struct uart_port *port) 285 { 286 struct uart_omap_port *up = to_uart_omap_port(port); 287 int res; 288 289 /* Handle RS-485 */ 290 if (port->rs485.flags & SER_RS485_ENABLED) { 291 if (up->scr & OMAP_UART_SCR_TX_EMPTY) { 292 /* THR interrupt is fired when both TX FIFO and TX 293 * shift register are empty. This means there's nothing 294 * left to transmit now, so make sure the THR interrupt 295 * is fired when TX FIFO is below the trigger level, 296 * disable THR interrupts and toggle the RS-485 GPIO 297 * data direction pin if needed. 298 */ 299 up->scr &= ~OMAP_UART_SCR_TX_EMPTY; 300 serial_out(up, UART_OMAP_SCR, up->scr); 301 res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 302 1 : 0; 303 if (gpiod_get_value(up->rts_gpiod) != res) { 304 if (port->rs485.delay_rts_after_send > 0) 305 mdelay( 306 port->rs485.delay_rts_after_send); 307 gpiod_set_value(up->rts_gpiod, res); 308 } 309 } else { 310 /* We're asked to stop, but there's still stuff in the 311 * UART FIFO, so make sure the THR interrupt is fired 312 * when both TX FIFO and TX shift register are empty. 313 * The next THR interrupt (if no transmission is started 314 * in the meantime) will indicate the end of a 315 * transmission. Therefore we _don't_ disable THR 316 * interrupts in this situation. 317 */ 318 up->scr |= OMAP_UART_SCR_TX_EMPTY; 319 serial_out(up, UART_OMAP_SCR, up->scr); 320 return; 321 } 322 } 323 324 if (up->ier & UART_IER_THRI) { 325 up->ier &= ~UART_IER_THRI; 326 serial_out(up, UART_IER, up->ier); 327 } 328 } 329 330 static void serial_omap_stop_rx(struct uart_port *port) 331 { 332 struct uart_omap_port *up = to_uart_omap_port(port); 333 334 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 335 up->port.read_status_mask &= ~UART_LSR_DR; 336 serial_out(up, UART_IER, up->ier); 337 } 338 339 static void serial_omap_put_char(struct uart_omap_port *up, unsigned char ch) 340 { 341 serial_out(up, UART_TX, ch); 342 343 if ((up->port.rs485.flags & SER_RS485_ENABLED) && 344 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) 345 up->rs485_tx_filter_count++; 346 } 347 348 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr) 349 { 350 u8 ch; 351 352 uart_port_tx_limited(&up->port, ch, up->port.fifosize / 4, 353 true, 354 serial_omap_put_char(up, ch), 355 ({})); 356 } 357 358 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) 359 { 360 if (!(up->ier & UART_IER_THRI)) { 361 up->ier |= UART_IER_THRI; 362 serial_out(up, UART_IER, up->ier); 363 } 364 } 365 366 static void serial_omap_start_tx(struct uart_port *port) 367 { 368 struct uart_omap_port *up = to_uart_omap_port(port); 369 int res; 370 371 /* Handle RS-485 */ 372 if (port->rs485.flags & SER_RS485_ENABLED) { 373 /* Fire THR interrupts when FIFO is below trigger level */ 374 up->scr &= ~OMAP_UART_SCR_TX_EMPTY; 375 serial_out(up, UART_OMAP_SCR, up->scr); 376 377 /* if rts not already enabled */ 378 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0; 379 if (gpiod_get_value(up->rts_gpiod) != res) { 380 gpiod_set_value(up->rts_gpiod, res); 381 if (port->rs485.delay_rts_before_send > 0) 382 mdelay(port->rs485.delay_rts_before_send); 383 } 384 } 385 386 if ((port->rs485.flags & SER_RS485_ENABLED) && 387 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) 388 up->rs485_tx_filter_count = 0; 389 390 serial_omap_enable_ier_thri(up); 391 } 392 393 static void serial_omap_throttle(struct uart_port *port) 394 { 395 struct uart_omap_port *up = to_uart_omap_port(port); 396 unsigned long flags; 397 398 spin_lock_irqsave(&up->port.lock, flags); 399 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 400 serial_out(up, UART_IER, up->ier); 401 spin_unlock_irqrestore(&up->port.lock, flags); 402 } 403 404 static void serial_omap_unthrottle(struct uart_port *port) 405 { 406 struct uart_omap_port *up = to_uart_omap_port(port); 407 unsigned long flags; 408 409 spin_lock_irqsave(&up->port.lock, flags); 410 up->ier |= UART_IER_RLSI | UART_IER_RDI; 411 serial_out(up, UART_IER, up->ier); 412 spin_unlock_irqrestore(&up->port.lock, flags); 413 } 414 415 static unsigned int check_modem_status(struct uart_omap_port *up) 416 { 417 unsigned int status; 418 419 status = serial_in(up, UART_MSR); 420 status |= up->msr_saved_flags; 421 up->msr_saved_flags = 0; 422 if ((status & UART_MSR_ANY_DELTA) == 0) 423 return status; 424 425 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && 426 up->port.state != NULL) { 427 if (status & UART_MSR_TERI) 428 up->port.icount.rng++; 429 if (status & UART_MSR_DDSR) 430 up->port.icount.dsr++; 431 if (status & UART_MSR_DDCD) 432 uart_handle_dcd_change 433 (&up->port, status & UART_MSR_DCD); 434 if (status & UART_MSR_DCTS) 435 uart_handle_cts_change 436 (&up->port, status & UART_MSR_CTS); 437 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 438 } 439 440 return status; 441 } 442 443 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr) 444 { 445 unsigned int flag; 446 447 /* 448 * Read one data character out to avoid stalling the receiver according 449 * to the table 23-246 of the omap4 TRM. 450 */ 451 if (likely(lsr & UART_LSR_DR)) { 452 serial_in(up, UART_RX); 453 if ((up->port.rs485.flags & SER_RS485_ENABLED) && 454 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) && 455 up->rs485_tx_filter_count) 456 up->rs485_tx_filter_count--; 457 } 458 459 up->port.icount.rx++; 460 flag = TTY_NORMAL; 461 462 if (lsr & UART_LSR_BI) { 463 flag = TTY_BREAK; 464 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 465 up->port.icount.brk++; 466 /* 467 * We do the SysRQ and SAK checking 468 * here because otherwise the break 469 * may get masked by ignore_status_mask 470 * or read_status_mask. 471 */ 472 if (uart_handle_break(&up->port)) 473 return; 474 475 } 476 477 if (lsr & UART_LSR_PE) { 478 flag = TTY_PARITY; 479 up->port.icount.parity++; 480 } 481 482 if (lsr & UART_LSR_FE) { 483 flag = TTY_FRAME; 484 up->port.icount.frame++; 485 } 486 487 if (lsr & UART_LSR_OE) 488 up->port.icount.overrun++; 489 490 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 491 if (up->port.line == up->port.cons->index) { 492 /* Recover the break flag from console xmit */ 493 lsr |= up->lsr_break_flag; 494 } 495 #endif 496 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag); 497 } 498 499 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr) 500 { 501 unsigned char ch = 0; 502 unsigned int flag; 503 504 if (!(lsr & UART_LSR_DR)) 505 return; 506 507 ch = serial_in(up, UART_RX); 508 if ((up->port.rs485.flags & SER_RS485_ENABLED) && 509 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) && 510 up->rs485_tx_filter_count) { 511 up->rs485_tx_filter_count--; 512 return; 513 } 514 515 flag = TTY_NORMAL; 516 up->port.icount.rx++; 517 518 if (uart_handle_sysrq_char(&up->port, ch)) 519 return; 520 521 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); 522 } 523 524 /** 525 * serial_omap_irq() - This handles the interrupt from one port 526 * @irq: uart port irq number 527 * @dev_id: uart port info 528 */ 529 static irqreturn_t serial_omap_irq(int irq, void *dev_id) 530 { 531 struct uart_omap_port *up = dev_id; 532 unsigned int iir, lsr; 533 unsigned int type; 534 irqreturn_t ret = IRQ_NONE; 535 int max_count = 256; 536 537 spin_lock(&up->port.lock); 538 539 do { 540 iir = serial_in(up, UART_IIR); 541 if (iir & UART_IIR_NO_INT) 542 break; 543 544 ret = IRQ_HANDLED; 545 lsr = serial_in(up, UART_LSR); 546 547 /* extract IRQ type from IIR register */ 548 type = iir & 0x3e; 549 550 switch (type) { 551 case UART_IIR_MSI: 552 check_modem_status(up); 553 break; 554 case UART_IIR_THRI: 555 transmit_chars(up, lsr); 556 break; 557 case UART_IIR_RX_TIMEOUT: 558 case UART_IIR_RDI: 559 serial_omap_rdi(up, lsr); 560 break; 561 case UART_IIR_RLSI: 562 serial_omap_rlsi(up, lsr); 563 break; 564 case UART_IIR_CTS_RTS_DSR: 565 /* simply try again */ 566 break; 567 case UART_IIR_XOFF: 568 default: 569 break; 570 } 571 } while (max_count--); 572 573 spin_unlock(&up->port.lock); 574 575 tty_flip_buffer_push(&up->port.state->port); 576 577 up->port_activity = jiffies; 578 579 return ret; 580 } 581 582 static unsigned int serial_omap_tx_empty(struct uart_port *port) 583 { 584 struct uart_omap_port *up = to_uart_omap_port(port); 585 unsigned long flags; 586 unsigned int ret = 0; 587 588 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line); 589 spin_lock_irqsave(&up->port.lock, flags); 590 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 591 spin_unlock_irqrestore(&up->port.lock, flags); 592 593 return ret; 594 } 595 596 static unsigned int serial_omap_get_mctrl(struct uart_port *port) 597 { 598 struct uart_omap_port *up = to_uart_omap_port(port); 599 unsigned int status; 600 unsigned int ret = 0; 601 602 status = check_modem_status(up); 603 604 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line); 605 606 if (status & UART_MSR_DCD) 607 ret |= TIOCM_CAR; 608 if (status & UART_MSR_RI) 609 ret |= TIOCM_RNG; 610 if (status & UART_MSR_DSR) 611 ret |= TIOCM_DSR; 612 if (status & UART_MSR_CTS) 613 ret |= TIOCM_CTS; 614 return ret; 615 } 616 617 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) 618 { 619 struct uart_omap_port *up = to_uart_omap_port(port); 620 unsigned char mcr = 0, old_mcr, lcr; 621 622 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line); 623 if (mctrl & TIOCM_RTS) 624 mcr |= UART_MCR_RTS; 625 if (mctrl & TIOCM_DTR) 626 mcr |= UART_MCR_DTR; 627 if (mctrl & TIOCM_OUT1) 628 mcr |= UART_MCR_OUT1; 629 if (mctrl & TIOCM_OUT2) 630 mcr |= UART_MCR_OUT2; 631 if (mctrl & TIOCM_LOOP) 632 mcr |= UART_MCR_LOOP; 633 634 old_mcr = serial_in(up, UART_MCR); 635 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 | 636 UART_MCR_DTR | UART_MCR_RTS); 637 up->mcr = old_mcr | mcr; 638 serial_out(up, UART_MCR, up->mcr); 639 640 /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */ 641 lcr = serial_in(up, UART_LCR); 642 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 643 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 644 up->efr |= UART_EFR_RTS; 645 else 646 up->efr &= ~UART_EFR_RTS; 647 serial_out(up, UART_EFR, up->efr); 648 serial_out(up, UART_LCR, lcr); 649 } 650 651 static void serial_omap_break_ctl(struct uart_port *port, int break_state) 652 { 653 struct uart_omap_port *up = to_uart_omap_port(port); 654 unsigned long flags; 655 656 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line); 657 spin_lock_irqsave(&up->port.lock, flags); 658 if (break_state == -1) 659 up->lcr |= UART_LCR_SBC; 660 else 661 up->lcr &= ~UART_LCR_SBC; 662 serial_out(up, UART_LCR, up->lcr); 663 spin_unlock_irqrestore(&up->port.lock, flags); 664 } 665 666 static int serial_omap_startup(struct uart_port *port) 667 { 668 struct uart_omap_port *up = to_uart_omap_port(port); 669 unsigned long flags; 670 int retval; 671 672 /* 673 * Allocate the IRQ 674 */ 675 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, 676 up->name, up); 677 if (retval) 678 return retval; 679 680 /* Optional wake-up IRQ */ 681 if (up->wakeirq) { 682 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq); 683 if (retval) { 684 free_irq(up->port.irq, up); 685 return retval; 686 } 687 } 688 689 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line); 690 691 pm_runtime_get_sync(up->dev); 692 /* 693 * Clear the FIFO buffers and disable them. 694 * (they will be reenabled in set_termios()) 695 */ 696 serial_omap_clear_fifos(up); 697 698 /* 699 * Clear the interrupt registers. 700 */ 701 (void) serial_in(up, UART_LSR); 702 if (serial_in(up, UART_LSR) & UART_LSR_DR) 703 (void) serial_in(up, UART_RX); 704 (void) serial_in(up, UART_IIR); 705 (void) serial_in(up, UART_MSR); 706 707 /* 708 * Now, initialize the UART 709 */ 710 serial_out(up, UART_LCR, UART_LCR_WLEN8); 711 spin_lock_irqsave(&up->port.lock, flags); 712 /* 713 * Most PC uarts need OUT2 raised to enable interrupts. 714 */ 715 up->port.mctrl |= TIOCM_OUT2; 716 serial_omap_set_mctrl(&up->port, up->port.mctrl); 717 spin_unlock_irqrestore(&up->port.lock, flags); 718 719 up->msr_saved_flags = 0; 720 /* 721 * Finally, enable interrupts. Note: Modem status interrupts 722 * are set via set_termios(), which will be occurring imminently 723 * anyway, so we don't enable them here. 724 */ 725 up->ier = UART_IER_RLSI | UART_IER_RDI; 726 serial_out(up, UART_IER, up->ier); 727 728 /* Enable module level wake up */ 729 up->wer = OMAP_UART_WER_MOD_WKUP; 730 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP) 731 up->wer |= OMAP_UART_TX_WAKEUP_EN; 732 733 serial_out(up, UART_OMAP_WER, up->wer); 734 735 up->port_activity = jiffies; 736 return 0; 737 } 738 739 static void serial_omap_shutdown(struct uart_port *port) 740 { 741 struct uart_omap_port *up = to_uart_omap_port(port); 742 unsigned long flags; 743 744 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line); 745 746 /* 747 * Disable interrupts from this port 748 */ 749 up->ier = 0; 750 serial_out(up, UART_IER, 0); 751 752 spin_lock_irqsave(&up->port.lock, flags); 753 up->port.mctrl &= ~TIOCM_OUT2; 754 serial_omap_set_mctrl(&up->port, up->port.mctrl); 755 spin_unlock_irqrestore(&up->port.lock, flags); 756 757 /* 758 * Disable break condition and FIFOs 759 */ 760 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); 761 serial_omap_clear_fifos(up); 762 763 /* 764 * Read data port to reset things, and then free the irq 765 */ 766 if (serial_in(up, UART_LSR) & UART_LSR_DR) 767 (void) serial_in(up, UART_RX); 768 769 pm_runtime_put_sync(up->dev); 770 free_irq(up->port.irq, up); 771 dev_pm_clear_wake_irq(up->dev); 772 } 773 774 static void serial_omap_uart_qos_work(struct work_struct *work) 775 { 776 struct uart_omap_port *up = container_of(work, struct uart_omap_port, 777 qos_work); 778 779 cpu_latency_qos_update_request(&up->pm_qos_request, up->latency); 780 } 781 782 static void 783 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, 784 const struct ktermios *old) 785 { 786 struct uart_omap_port *up = to_uart_omap_port(port); 787 unsigned char cval = 0; 788 unsigned long flags; 789 unsigned int baud, quot; 790 791 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); 792 793 if (termios->c_cflag & CSTOPB) 794 cval |= UART_LCR_STOP; 795 if (termios->c_cflag & PARENB) 796 cval |= UART_LCR_PARITY; 797 if (!(termios->c_cflag & PARODD)) 798 cval |= UART_LCR_EPAR; 799 if (termios->c_cflag & CMSPAR) 800 cval |= UART_LCR_SPAR; 801 802 /* 803 * Ask the core to calculate the divisor for us. 804 */ 805 806 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); 807 quot = serial_omap_get_divisor(port, baud); 808 809 /* calculate wakeup latency constraint */ 810 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8); 811 up->latency = up->calc_latency; 812 schedule_work(&up->qos_work); 813 814 up->dll = quot & 0xff; 815 up->dlh = quot >> 8; 816 up->mdr1 = UART_OMAP_MDR1_DISABLE; 817 818 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | 819 UART_FCR_ENABLE_FIFO; 820 821 /* 822 * Ok, we're now changing the port state. Do it with 823 * interrupts disabled. 824 */ 825 spin_lock_irqsave(&up->port.lock, flags); 826 827 /* 828 * Update the per-port timeout. 829 */ 830 uart_update_timeout(port, termios->c_cflag, baud); 831 832 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 833 if (termios->c_iflag & INPCK) 834 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 835 if (termios->c_iflag & (BRKINT | PARMRK)) 836 up->port.read_status_mask |= UART_LSR_BI; 837 838 /* 839 * Characters to ignore 840 */ 841 up->port.ignore_status_mask = 0; 842 if (termios->c_iflag & IGNPAR) 843 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 844 if (termios->c_iflag & IGNBRK) { 845 up->port.ignore_status_mask |= UART_LSR_BI; 846 /* 847 * If we're ignoring parity and break indicators, 848 * ignore overruns too (for real raw support). 849 */ 850 if (termios->c_iflag & IGNPAR) 851 up->port.ignore_status_mask |= UART_LSR_OE; 852 } 853 854 /* 855 * ignore all characters if CREAD is not set 856 */ 857 if ((termios->c_cflag & CREAD) == 0) 858 up->port.ignore_status_mask |= UART_LSR_DR; 859 860 /* 861 * Modem status interrupts 862 */ 863 up->ier &= ~UART_IER_MSI; 864 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 865 up->ier |= UART_IER_MSI; 866 serial_out(up, UART_IER, up->ier); 867 serial_out(up, UART_LCR, cval); /* reset DLAB */ 868 up->lcr = cval; 869 up->scr = 0; 870 871 /* FIFOs and DMA Settings */ 872 873 /* FCR can be changed only when the 874 * baud clock is not running 875 * DLL_REG and DLH_REG set to 0. 876 */ 877 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 878 serial_out(up, UART_DLL, 0); 879 serial_out(up, UART_DLM, 0); 880 serial_out(up, UART_LCR, 0); 881 882 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 883 884 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB; 885 up->efr &= ~UART_EFR_SCD; 886 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 887 888 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 889 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR; 890 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 891 /* FIFO ENABLE, DMA MODE */ 892 893 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; 894 /* 895 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK 896 * sets Enables the granularity of 1 for TRIGGER RX 897 * level. Along with setting RX FIFO trigger level 898 * to 1 (as noted below, 16 characters) and TLR[3:0] 899 * to zero this will result RX FIFO threshold level 900 * to 1 character, instead of 16 as noted in comment 901 * below. 902 */ 903 904 /* Set receive FIFO threshold to 16 characters and 905 * transmit FIFO threshold to 32 spaces 906 */ 907 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; 908 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK; 909 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 | 910 UART_FCR_ENABLE_FIFO; 911 912 serial_out(up, UART_FCR, up->fcr); 913 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 914 915 serial_out(up, UART_OMAP_SCR, up->scr); 916 917 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */ 918 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 919 serial_out(up, UART_MCR, up->mcr); 920 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 921 serial_out(up, UART_EFR, up->efr); 922 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 923 924 /* Protocol, Baud Rate, and Interrupt Settings */ 925 926 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 927 serial_omap_mdr1_errataset(up, up->mdr1); 928 else 929 serial_out(up, UART_OMAP_MDR1, up->mdr1); 930 931 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 932 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 933 934 serial_out(up, UART_LCR, 0); 935 serial_out(up, UART_IER, 0); 936 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 937 938 serial_out(up, UART_DLL, up->dll); /* LS of divisor */ 939 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */ 940 941 serial_out(up, UART_LCR, 0); 942 serial_out(up, UART_IER, up->ier); 943 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 944 945 serial_out(up, UART_EFR, up->efr); 946 serial_out(up, UART_LCR, cval); 947 948 if (!serial_omap_baud_is_mode16(port, baud)) 949 up->mdr1 = UART_OMAP_MDR1_13X_MODE; 950 else 951 up->mdr1 = UART_OMAP_MDR1_16X_MODE; 952 953 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 954 serial_omap_mdr1_errataset(up, up->mdr1); 955 else 956 serial_out(up, UART_OMAP_MDR1, up->mdr1); 957 958 /* Configure flow control */ 959 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 960 961 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */ 962 serial_out(up, UART_XON1, termios->c_cc[VSTART]); 963 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); 964 965 /* Enable access to TCR/TLR */ 966 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 967 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 968 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 969 970 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); 971 972 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 973 974 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { 975 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 976 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 977 up->efr |= UART_EFR_CTS; 978 } else { 979 /* Disable AUTORTS and AUTOCTS */ 980 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS); 981 } 982 983 if (up->port.flags & UPF_SOFT_FLOW) { 984 /* clear SW control mode bits */ 985 up->efr &= OMAP_UART_SW_CLR; 986 987 /* 988 * IXON Flag: 989 * Enable XON/XOFF flow control on input. 990 * Receiver compares XON1, XOFF1. 991 */ 992 if (termios->c_iflag & IXON) 993 up->efr |= OMAP_UART_SW_RX; 994 995 /* 996 * IXOFF Flag: 997 * Enable XON/XOFF flow control on output. 998 * Transmit XON1, XOFF1 999 */ 1000 if (termios->c_iflag & IXOFF) { 1001 up->port.status |= UPSTAT_AUTOXOFF; 1002 up->efr |= OMAP_UART_SW_TX; 1003 } 1004 1005 /* 1006 * IXANY Flag: 1007 * Enable any character to restart output. 1008 * Operation resumes after receiving any 1009 * character after recognition of the XOFF character 1010 */ 1011 if (termios->c_iflag & IXANY) 1012 up->mcr |= UART_MCR_XONANY; 1013 else 1014 up->mcr &= ~UART_MCR_XONANY; 1015 } 1016 serial_out(up, UART_MCR, up->mcr); 1017 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1018 serial_out(up, UART_EFR, up->efr); 1019 serial_out(up, UART_LCR, up->lcr); 1020 1021 serial_omap_set_mctrl(&up->port, up->port.mctrl); 1022 1023 spin_unlock_irqrestore(&up->port.lock, flags); 1024 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line); 1025 } 1026 1027 static void 1028 serial_omap_pm(struct uart_port *port, unsigned int state, 1029 unsigned int oldstate) 1030 { 1031 struct uart_omap_port *up = to_uart_omap_port(port); 1032 unsigned char efr; 1033 1034 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line); 1035 1036 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1037 efr = serial_in(up, UART_EFR); 1038 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 1039 serial_out(up, UART_LCR, 0); 1040 1041 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 1042 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1043 serial_out(up, UART_EFR, efr); 1044 serial_out(up, UART_LCR, 0); 1045 } 1046 1047 static void serial_omap_release_port(struct uart_port *port) 1048 { 1049 dev_dbg(port->dev, "serial_omap_release_port+\n"); 1050 } 1051 1052 static int serial_omap_request_port(struct uart_port *port) 1053 { 1054 dev_dbg(port->dev, "serial_omap_request_port+\n"); 1055 return 0; 1056 } 1057 1058 static void serial_omap_config_port(struct uart_port *port, int flags) 1059 { 1060 struct uart_omap_port *up = to_uart_omap_port(port); 1061 1062 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", 1063 up->port.line); 1064 up->port.type = PORT_OMAP; 1065 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW; 1066 } 1067 1068 static int 1069 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) 1070 { 1071 /* we don't want the core code to modify any port params */ 1072 dev_dbg(port->dev, "serial_omap_verify_port+\n"); 1073 return -EINVAL; 1074 } 1075 1076 static const char * 1077 serial_omap_type(struct uart_port *port) 1078 { 1079 struct uart_omap_port *up = to_uart_omap_port(port); 1080 1081 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line); 1082 return up->name; 1083 } 1084 1085 static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up) 1086 { 1087 unsigned int status, tmout = 10000; 1088 1089 /* Wait up to 10ms for the character(s) to be sent. */ 1090 do { 1091 status = serial_in(up, UART_LSR); 1092 1093 if (status & UART_LSR_BI) 1094 up->lsr_break_flag = UART_LSR_BI; 1095 1096 if (--tmout == 0) 1097 break; 1098 udelay(1); 1099 } while (!uart_lsr_tx_empty(status)); 1100 1101 /* Wait up to 1s for flow control if necessary */ 1102 if (up->port.flags & UPF_CONS_FLOW) { 1103 tmout = 1000000; 1104 for (tmout = 1000000; tmout; tmout--) { 1105 unsigned int msr = serial_in(up, UART_MSR); 1106 1107 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; 1108 if (msr & UART_MSR_CTS) 1109 break; 1110 1111 udelay(1); 1112 } 1113 } 1114 } 1115 1116 #ifdef CONFIG_CONSOLE_POLL 1117 1118 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) 1119 { 1120 struct uart_omap_port *up = to_uart_omap_port(port); 1121 1122 wait_for_xmitr(up); 1123 serial_out(up, UART_TX, ch); 1124 } 1125 1126 static int serial_omap_poll_get_char(struct uart_port *port) 1127 { 1128 struct uart_omap_port *up = to_uart_omap_port(port); 1129 unsigned int status; 1130 1131 status = serial_in(up, UART_LSR); 1132 if (!(status & UART_LSR_DR)) { 1133 status = NO_POLL_CHAR; 1134 goto out; 1135 } 1136 1137 status = serial_in(up, UART_RX); 1138 1139 out: 1140 return status; 1141 } 1142 1143 #endif /* CONFIG_CONSOLE_POLL */ 1144 1145 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 1146 1147 #ifdef CONFIG_SERIAL_EARLYCON 1148 static unsigned int omap_serial_early_in(struct uart_port *port, int offset) 1149 { 1150 offset <<= port->regshift; 1151 return readw(port->membase + offset); 1152 } 1153 1154 static void omap_serial_early_out(struct uart_port *port, int offset, 1155 int value) 1156 { 1157 offset <<= port->regshift; 1158 writew(value, port->membase + offset); 1159 } 1160 1161 static void omap_serial_early_putc(struct uart_port *port, unsigned char c) 1162 { 1163 unsigned int status; 1164 1165 for (;;) { 1166 status = omap_serial_early_in(port, UART_LSR); 1167 if (uart_lsr_tx_empty(status)) 1168 break; 1169 cpu_relax(); 1170 } 1171 omap_serial_early_out(port, UART_TX, c); 1172 } 1173 1174 static void early_omap_serial_write(struct console *console, const char *s, 1175 unsigned int count) 1176 { 1177 struct earlycon_device *device = console->data; 1178 struct uart_port *port = &device->port; 1179 1180 uart_console_write(port, s, count, omap_serial_early_putc); 1181 } 1182 1183 static int __init early_omap_serial_setup(struct earlycon_device *device, 1184 const char *options) 1185 { 1186 struct uart_port *port = &device->port; 1187 1188 if (!(device->port.membase || device->port.iobase)) 1189 return -ENODEV; 1190 1191 port->regshift = 2; 1192 device->con->write = early_omap_serial_write; 1193 return 0; 1194 } 1195 1196 OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup); 1197 OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup); 1198 OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup); 1199 #endif /* CONFIG_SERIAL_EARLYCON */ 1200 1201 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS]; 1202 1203 static struct uart_driver serial_omap_reg; 1204 1205 static void serial_omap_console_putchar(struct uart_port *port, unsigned char ch) 1206 { 1207 struct uart_omap_port *up = to_uart_omap_port(port); 1208 1209 wait_for_xmitr(up); 1210 serial_out(up, UART_TX, ch); 1211 } 1212 1213 static void 1214 serial_omap_console_write(struct console *co, const char *s, 1215 unsigned int count) 1216 { 1217 struct uart_omap_port *up = serial_omap_console_ports[co->index]; 1218 unsigned long flags; 1219 unsigned int ier; 1220 int locked = 1; 1221 1222 local_irq_save(flags); 1223 if (up->port.sysrq) 1224 locked = 0; 1225 else if (oops_in_progress) 1226 locked = spin_trylock(&up->port.lock); 1227 else 1228 spin_lock(&up->port.lock); 1229 1230 /* 1231 * First save the IER then disable the interrupts 1232 */ 1233 ier = serial_in(up, UART_IER); 1234 serial_out(up, UART_IER, 0); 1235 1236 uart_console_write(&up->port, s, count, serial_omap_console_putchar); 1237 1238 /* 1239 * Finally, wait for transmitter to become empty 1240 * and restore the IER 1241 */ 1242 wait_for_xmitr(up); 1243 serial_out(up, UART_IER, ier); 1244 /* 1245 * The receive handling will happen properly because the 1246 * receive ready bit will still be set; it is not cleared 1247 * on read. However, modem control will not, we must 1248 * call it if we have saved something in the saved flags 1249 * while processing with interrupts off. 1250 */ 1251 if (up->msr_saved_flags) 1252 check_modem_status(up); 1253 1254 if (locked) 1255 spin_unlock(&up->port.lock); 1256 local_irq_restore(flags); 1257 } 1258 1259 static int __init 1260 serial_omap_console_setup(struct console *co, char *options) 1261 { 1262 struct uart_omap_port *up; 1263 int baud = 115200; 1264 int bits = 8; 1265 int parity = 'n'; 1266 int flow = 'n'; 1267 1268 if (serial_omap_console_ports[co->index] == NULL) 1269 return -ENODEV; 1270 up = serial_omap_console_ports[co->index]; 1271 1272 if (options) 1273 uart_parse_options(options, &baud, &parity, &bits, &flow); 1274 1275 return uart_set_options(&up->port, co, baud, parity, bits, flow); 1276 } 1277 1278 static struct console serial_omap_console = { 1279 .name = OMAP_SERIAL_NAME, 1280 .write = serial_omap_console_write, 1281 .device = uart_console_device, 1282 .setup = serial_omap_console_setup, 1283 .flags = CON_PRINTBUFFER, 1284 .index = -1, 1285 .data = &serial_omap_reg, 1286 }; 1287 1288 static void serial_omap_add_console_port(struct uart_omap_port *up) 1289 { 1290 serial_omap_console_ports[up->port.line] = up; 1291 } 1292 1293 #define OMAP_CONSOLE (&serial_omap_console) 1294 1295 #else 1296 1297 #define OMAP_CONSOLE NULL 1298 1299 static inline void serial_omap_add_console_port(struct uart_omap_port *up) 1300 {} 1301 1302 #endif 1303 1304 /* Enable or disable the rs485 support */ 1305 static int 1306 serial_omap_config_rs485(struct uart_port *port, struct ktermios *termios, 1307 struct serial_rs485 *rs485) 1308 { 1309 struct uart_omap_port *up = to_uart_omap_port(port); 1310 unsigned int mode; 1311 int val; 1312 1313 /* Disable interrupts from this port */ 1314 mode = up->ier; 1315 up->ier = 0; 1316 serial_out(up, UART_IER, 0); 1317 1318 /* enable / disable rts */ 1319 val = (rs485->flags & SER_RS485_ENABLED) ? 1320 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND; 1321 val = (rs485->flags & val) ? 1 : 0; 1322 gpiod_set_value(up->rts_gpiod, val); 1323 1324 /* Enable interrupts */ 1325 up->ier = mode; 1326 serial_out(up, UART_IER, up->ier); 1327 1328 /* If RS-485 is disabled, make sure the THR interrupt is fired when 1329 * TX FIFO is below the trigger level. 1330 */ 1331 if (!(rs485->flags & SER_RS485_ENABLED) && 1332 (up->scr & OMAP_UART_SCR_TX_EMPTY)) { 1333 up->scr &= ~OMAP_UART_SCR_TX_EMPTY; 1334 serial_out(up, UART_OMAP_SCR, up->scr); 1335 } 1336 1337 return 0; 1338 } 1339 1340 static const struct uart_ops serial_omap_pops = { 1341 .tx_empty = serial_omap_tx_empty, 1342 .set_mctrl = serial_omap_set_mctrl, 1343 .get_mctrl = serial_omap_get_mctrl, 1344 .stop_tx = serial_omap_stop_tx, 1345 .start_tx = serial_omap_start_tx, 1346 .throttle = serial_omap_throttle, 1347 .unthrottle = serial_omap_unthrottle, 1348 .stop_rx = serial_omap_stop_rx, 1349 .enable_ms = serial_omap_enable_ms, 1350 .break_ctl = serial_omap_break_ctl, 1351 .startup = serial_omap_startup, 1352 .shutdown = serial_omap_shutdown, 1353 .set_termios = serial_omap_set_termios, 1354 .pm = serial_omap_pm, 1355 .type = serial_omap_type, 1356 .release_port = serial_omap_release_port, 1357 .request_port = serial_omap_request_port, 1358 .config_port = serial_omap_config_port, 1359 .verify_port = serial_omap_verify_port, 1360 #ifdef CONFIG_CONSOLE_POLL 1361 .poll_put_char = serial_omap_poll_put_char, 1362 .poll_get_char = serial_omap_poll_get_char, 1363 #endif 1364 }; 1365 1366 static struct uart_driver serial_omap_reg = { 1367 .owner = THIS_MODULE, 1368 .driver_name = "OMAP-SERIAL", 1369 .dev_name = OMAP_SERIAL_NAME, 1370 .nr = OMAP_MAX_HSUART_PORTS, 1371 .cons = OMAP_CONSOLE, 1372 }; 1373 1374 #ifdef CONFIG_PM_SLEEP 1375 static int serial_omap_prepare(struct device *dev) 1376 { 1377 struct uart_omap_port *up = dev_get_drvdata(dev); 1378 1379 up->is_suspending = true; 1380 1381 return 0; 1382 } 1383 1384 static void serial_omap_complete(struct device *dev) 1385 { 1386 struct uart_omap_port *up = dev_get_drvdata(dev); 1387 1388 up->is_suspending = false; 1389 } 1390 1391 static int serial_omap_suspend(struct device *dev) 1392 { 1393 struct uart_omap_port *up = dev_get_drvdata(dev); 1394 1395 uart_suspend_port(&serial_omap_reg, &up->port); 1396 flush_work(&up->qos_work); 1397 1398 if (device_may_wakeup(dev)) 1399 serial_omap_enable_wakeup(up, true); 1400 else 1401 serial_omap_enable_wakeup(up, false); 1402 1403 return 0; 1404 } 1405 1406 static int serial_omap_resume(struct device *dev) 1407 { 1408 struct uart_omap_port *up = dev_get_drvdata(dev); 1409 1410 if (device_may_wakeup(dev)) 1411 serial_omap_enable_wakeup(up, false); 1412 1413 uart_resume_port(&serial_omap_reg, &up->port); 1414 1415 return 0; 1416 } 1417 #else 1418 #define serial_omap_prepare NULL 1419 #define serial_omap_complete NULL 1420 #endif /* CONFIG_PM_SLEEP */ 1421 1422 static void omap_serial_fill_features_erratas(struct uart_omap_port *up) 1423 { 1424 u32 mvr, scheme; 1425 u16 revision, major, minor; 1426 1427 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift)); 1428 1429 /* Check revision register scheme */ 1430 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 1431 1432 switch (scheme) { 1433 case 0: /* Legacy Scheme: OMAP2/3 */ 1434 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 1435 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 1436 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 1437 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 1438 break; 1439 case 1: 1440 /* New Scheme: OMAP4+ */ 1441 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 1442 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 1443 OMAP_UART_MVR_MAJ_SHIFT; 1444 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 1445 break; 1446 default: 1447 dev_warn(up->dev, 1448 "Unknown %s revision, defaulting to highest\n", 1449 up->name); 1450 /* highest possible revision */ 1451 major = 0xff; 1452 minor = 0xff; 1453 } 1454 1455 /* normalize revision for the driver */ 1456 revision = UART_BUILD_REVISION(major, minor); 1457 1458 switch (revision) { 1459 case OMAP_UART_REV_46: 1460 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1461 UART_ERRATA_i291_DMA_FORCEIDLE); 1462 break; 1463 case OMAP_UART_REV_52: 1464 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1465 UART_ERRATA_i291_DMA_FORCEIDLE); 1466 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP; 1467 break; 1468 case OMAP_UART_REV_63: 1469 up->errata |= UART_ERRATA_i202_MDR1_ACCESS; 1470 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP; 1471 break; 1472 default: 1473 break; 1474 } 1475 } 1476 1477 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev) 1478 { 1479 struct omap_uart_port_info *omap_up_info; 1480 1481 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL); 1482 if (!omap_up_info) 1483 return NULL; /* out of memory */ 1484 1485 of_property_read_u32(dev->of_node, "clock-frequency", 1486 &omap_up_info->uartclk); 1487 1488 omap_up_info->flags = UPF_BOOT_AUTOCONF; 1489 1490 return omap_up_info; 1491 } 1492 1493 static int serial_omap_probe_rs485(struct uart_omap_port *up, 1494 struct device *dev) 1495 { 1496 struct serial_rs485 *rs485conf = &up->port.rs485; 1497 struct device_node *np = dev->of_node; 1498 enum gpiod_flags gflags; 1499 int ret; 1500 1501 rs485conf->flags = 0; 1502 up->rts_gpiod = NULL; 1503 1504 if (!np) 1505 return 0; 1506 1507 ret = uart_get_rs485_mode(&up->port); 1508 if (ret) 1509 return ret; 1510 1511 if (of_property_read_bool(np, "rs485-rts-active-high")) { 1512 rs485conf->flags |= SER_RS485_RTS_ON_SEND; 1513 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 1514 } else { 1515 rs485conf->flags &= ~SER_RS485_RTS_ON_SEND; 1516 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 1517 } 1518 1519 /* check for tx enable gpio */ 1520 gflags = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ? 1521 GPIOD_OUT_HIGH : GPIOD_OUT_LOW; 1522 up->rts_gpiod = devm_gpiod_get_optional(dev, "rts", gflags); 1523 if (IS_ERR(up->rts_gpiod)) { 1524 ret = PTR_ERR(up->rts_gpiod); 1525 if (ret == -EPROBE_DEFER) 1526 return ret; 1527 1528 up->rts_gpiod = NULL; 1529 up->port.rs485_supported = (const struct serial_rs485) { }; 1530 if (rs485conf->flags & SER_RS485_ENABLED) { 1531 dev_err(dev, "disabling RS-485 (rts-gpio missing in device tree)\n"); 1532 memset(rs485conf, 0, sizeof(*rs485conf)); 1533 } 1534 } else { 1535 gpiod_set_consumer_name(up->rts_gpiod, "omap-serial"); 1536 } 1537 1538 return 0; 1539 } 1540 1541 static const struct serial_rs485 serial_omap_rs485_supported = { 1542 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND | 1543 SER_RS485_RX_DURING_TX, 1544 .delay_rts_before_send = 1, 1545 .delay_rts_after_send = 1, 1546 }; 1547 1548 static int serial_omap_probe(struct platform_device *pdev) 1549 { 1550 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev); 1551 struct uart_omap_port *up; 1552 struct resource *mem; 1553 void __iomem *base; 1554 int uartirq = 0; 1555 int wakeirq = 0; 1556 int ret; 1557 1558 /* The optional wakeirq may be specified in the board dts file */ 1559 if (pdev->dev.of_node) { 1560 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1561 if (!uartirq) 1562 return -EPROBE_DEFER; 1563 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1); 1564 omap_up_info = of_get_uart_port_info(&pdev->dev); 1565 pdev->dev.platform_data = omap_up_info; 1566 } else { 1567 uartirq = platform_get_irq(pdev, 0); 1568 if (uartirq < 0) 1569 return -EPROBE_DEFER; 1570 } 1571 1572 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL); 1573 if (!up) 1574 return -ENOMEM; 1575 1576 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1577 base = devm_ioremap_resource(&pdev->dev, mem); 1578 if (IS_ERR(base)) 1579 return PTR_ERR(base); 1580 1581 up->dev = &pdev->dev; 1582 up->port.dev = &pdev->dev; 1583 up->port.type = PORT_OMAP; 1584 up->port.iotype = UPIO_MEM; 1585 up->port.irq = uartirq; 1586 up->port.regshift = 2; 1587 up->port.fifosize = 64; 1588 up->port.ops = &serial_omap_pops; 1589 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_OMAP_CONSOLE); 1590 1591 if (pdev->dev.of_node) 1592 ret = of_alias_get_id(pdev->dev.of_node, "serial"); 1593 else 1594 ret = pdev->id; 1595 1596 if (ret < 0) { 1597 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", 1598 ret); 1599 goto err_port_line; 1600 } 1601 up->port.line = ret; 1602 1603 if (up->port.line >= OMAP_MAX_HSUART_PORTS) { 1604 dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line, 1605 OMAP_MAX_HSUART_PORTS); 1606 ret = -ENXIO; 1607 goto err_port_line; 1608 } 1609 1610 up->wakeirq = wakeirq; 1611 if (!up->wakeirq) 1612 dev_info(up->port.dev, "no wakeirq for uart%d\n", 1613 up->port.line); 1614 1615 ret = serial_omap_probe_rs485(up, &pdev->dev); 1616 if (ret < 0) 1617 goto err_rs485; 1618 1619 sprintf(up->name, "OMAP UART%d", up->port.line); 1620 up->port.mapbase = mem->start; 1621 up->port.membase = base; 1622 up->port.flags = omap_up_info->flags; 1623 up->port.uartclk = omap_up_info->uartclk; 1624 up->port.rs485_config = serial_omap_config_rs485; 1625 up->port.rs485_supported = serial_omap_rs485_supported; 1626 if (!up->port.uartclk) { 1627 up->port.uartclk = DEFAULT_CLK_SPEED; 1628 dev_warn(&pdev->dev, 1629 "No clock speed specified: using default: %d\n", 1630 DEFAULT_CLK_SPEED); 1631 } 1632 1633 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1634 up->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1635 cpu_latency_qos_add_request(&up->pm_qos_request, up->latency); 1636 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); 1637 1638 platform_set_drvdata(pdev, up); 1639 if (omap_up_info->autosuspend_timeout == 0) 1640 omap_up_info->autosuspend_timeout = -1; 1641 1642 device_init_wakeup(up->dev, true); 1643 1644 pm_runtime_enable(&pdev->dev); 1645 1646 pm_runtime_get_sync(&pdev->dev); 1647 1648 omap_serial_fill_features_erratas(up); 1649 1650 ui[up->port.line] = up; 1651 serial_omap_add_console_port(up); 1652 1653 ret = uart_add_one_port(&serial_omap_reg, &up->port); 1654 if (ret != 0) 1655 goto err_add_port; 1656 1657 return 0; 1658 1659 err_add_port: 1660 pm_runtime_put_sync(&pdev->dev); 1661 pm_runtime_disable(&pdev->dev); 1662 cpu_latency_qos_remove_request(&up->pm_qos_request); 1663 device_init_wakeup(up->dev, false); 1664 err_rs485: 1665 err_port_line: 1666 return ret; 1667 } 1668 1669 static int serial_omap_remove(struct platform_device *dev) 1670 { 1671 struct uart_omap_port *up = platform_get_drvdata(dev); 1672 1673 pm_runtime_get_sync(up->dev); 1674 1675 uart_remove_one_port(&serial_omap_reg, &up->port); 1676 1677 pm_runtime_put_sync(up->dev); 1678 pm_runtime_disable(up->dev); 1679 cpu_latency_qos_remove_request(&up->pm_qos_request); 1680 device_init_wakeup(&dev->dev, false); 1681 1682 return 0; 1683 } 1684 1685 /* 1686 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 1687 * The access to uart register after MDR1 Access 1688 * causes UART to corrupt data. 1689 * 1690 * Need a delay = 1691 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 1692 * give 10 times as much 1693 */ 1694 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1) 1695 { 1696 u8 timeout = 255; 1697 1698 serial_out(up, UART_OMAP_MDR1, mdr1); 1699 udelay(2); 1700 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 1701 UART_FCR_CLEAR_RCVR); 1702 /* 1703 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 1704 * TX_FIFO_E bit is 1. 1705 */ 1706 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 1707 (UART_LSR_THRE | UART_LSR_DR))) { 1708 timeout--; 1709 if (!timeout) { 1710 /* Should *never* happen. we warn and carry on */ 1711 dev_crit(up->dev, "Errata i202: timedout %x\n", 1712 serial_in(up, UART_LSR)); 1713 break; 1714 } 1715 udelay(1); 1716 } 1717 } 1718 1719 #ifdef CONFIG_PM 1720 static void serial_omap_restore_context(struct uart_omap_port *up) 1721 { 1722 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1723 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE); 1724 else 1725 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); 1726 1727 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1728 serial_out(up, UART_EFR, UART_EFR_ECB); 1729 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1730 serial_out(up, UART_IER, 0x0); 1731 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1732 serial_out(up, UART_DLL, up->dll); 1733 serial_out(up, UART_DLM, up->dlh); 1734 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1735 serial_out(up, UART_IER, up->ier); 1736 serial_out(up, UART_FCR, up->fcr); 1737 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1738 serial_out(up, UART_MCR, up->mcr); 1739 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1740 serial_out(up, UART_OMAP_SCR, up->scr); 1741 serial_out(up, UART_EFR, up->efr); 1742 serial_out(up, UART_LCR, up->lcr); 1743 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1744 serial_omap_mdr1_errataset(up, up->mdr1); 1745 else 1746 serial_out(up, UART_OMAP_MDR1, up->mdr1); 1747 serial_out(up, UART_OMAP_WER, up->wer); 1748 } 1749 1750 static int serial_omap_runtime_suspend(struct device *dev) 1751 { 1752 struct uart_omap_port *up = dev_get_drvdata(dev); 1753 1754 if (!up) 1755 return -EINVAL; 1756 1757 /* 1758 * When using 'no_console_suspend', the console UART must not be 1759 * suspended. Since driver suspend is managed by runtime suspend, 1760 * preventing runtime suspend (by returning error) will keep device 1761 * active during suspend. 1762 */ 1763 if (up->is_suspending && !console_suspend_enabled && 1764 uart_console(&up->port)) 1765 return -EBUSY; 1766 1767 up->context_loss_cnt = serial_omap_get_context_loss_count(up); 1768 1769 serial_omap_enable_wakeup(up, true); 1770 1771 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1772 schedule_work(&up->qos_work); 1773 1774 return 0; 1775 } 1776 1777 static int serial_omap_runtime_resume(struct device *dev) 1778 { 1779 struct uart_omap_port *up = dev_get_drvdata(dev); 1780 1781 int loss_cnt = serial_omap_get_context_loss_count(up); 1782 1783 serial_omap_enable_wakeup(up, false); 1784 1785 if (loss_cnt < 0) { 1786 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n", 1787 loss_cnt); 1788 serial_omap_restore_context(up); 1789 } else if (up->context_loss_cnt != loss_cnt) { 1790 serial_omap_restore_context(up); 1791 } 1792 up->latency = up->calc_latency; 1793 schedule_work(&up->qos_work); 1794 1795 return 0; 1796 } 1797 #endif 1798 1799 static const struct dev_pm_ops serial_omap_dev_pm_ops = { 1800 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume) 1801 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend, 1802 serial_omap_runtime_resume, NULL) 1803 .prepare = serial_omap_prepare, 1804 .complete = serial_omap_complete, 1805 }; 1806 1807 #if defined(CONFIG_OF) 1808 static const struct of_device_id omap_serial_of_match[] = { 1809 { .compatible = "ti,omap2-uart" }, 1810 { .compatible = "ti,omap3-uart" }, 1811 { .compatible = "ti,omap4-uart" }, 1812 {}, 1813 }; 1814 MODULE_DEVICE_TABLE(of, omap_serial_of_match); 1815 #endif 1816 1817 static struct platform_driver serial_omap_driver = { 1818 .probe = serial_omap_probe, 1819 .remove = serial_omap_remove, 1820 .driver = { 1821 .name = OMAP_SERIAL_DRIVER_NAME, 1822 .pm = &serial_omap_dev_pm_ops, 1823 .of_match_table = of_match_ptr(omap_serial_of_match), 1824 }, 1825 }; 1826 1827 static int __init serial_omap_init(void) 1828 { 1829 int ret; 1830 1831 ret = uart_register_driver(&serial_omap_reg); 1832 if (ret != 0) 1833 return ret; 1834 ret = platform_driver_register(&serial_omap_driver); 1835 if (ret != 0) 1836 uart_unregister_driver(&serial_omap_reg); 1837 return ret; 1838 } 1839 1840 static void __exit serial_omap_exit(void) 1841 { 1842 platform_driver_unregister(&serial_omap_driver); 1843 uart_unregister_driver(&serial_omap_reg); 1844 } 1845 1846 module_init(serial_omap_init); 1847 module_exit(serial_omap_exit); 1848 1849 MODULE_DESCRIPTION("OMAP High Speed UART driver"); 1850 MODULE_LICENSE("GPL"); 1851 MODULE_AUTHOR("Texas Instruments Inc"); 1852