1 /* 2 * Driver for OMAP-UART controller. 3 * Based on drivers/serial/8250.c 4 * 5 * Copyright (C) 2010 Texas Instruments. 6 * 7 * Authors: 8 * Govindraj R <govindraj.raja@ti.com> 9 * Thara Gopinath <thara@ti.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * Note: This driver is made separate from 8250 driver as we cannot 17 * over load 8250 driver with omap platform specific configuration for 18 * features like DMA, it makes easier to implement features like DMA and 19 * hardware flow control and software flow control configuration with 20 * this driver as required for the omap-platform. 21 */ 22 23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 24 #define SUPPORT_SYSRQ 25 #endif 26 27 #include <linux/module.h> 28 #include <linux/init.h> 29 #include <linux/console.h> 30 #include <linux/serial_reg.h> 31 #include <linux/delay.h> 32 #include <linux/slab.h> 33 #include <linux/tty.h> 34 #include <linux/tty_flip.h> 35 #include <linux/platform_device.h> 36 #include <linux/io.h> 37 #include <linux/clk.h> 38 #include <linux/serial_core.h> 39 #include <linux/irq.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/of.h> 42 #include <linux/gpio.h> 43 #include <linux/pinctrl/consumer.h> 44 #include <linux/platform_data/serial-omap.h> 45 46 #define OMAP_MAX_HSUART_PORTS 6 47 48 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 49 50 #define OMAP_UART_REV_42 0x0402 51 #define OMAP_UART_REV_46 0x0406 52 #define OMAP_UART_REV_52 0x0502 53 #define OMAP_UART_REV_63 0x0603 54 55 #define UART_ERRATA_i202_MDR1_ACCESS BIT(0) 56 #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1) 57 58 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/ 59 60 /* SCR register bitmasks */ 61 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 62 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 63 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 64 65 /* FCR register bitmasks */ 66 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6) 67 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4) 68 69 /* MVR register bitmasks */ 70 #define OMAP_UART_MVR_SCHEME_SHIFT 30 71 72 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 73 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 74 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 75 76 #define OMAP_UART_MVR_MAJ_MASK 0x700 77 #define OMAP_UART_MVR_MAJ_SHIFT 8 78 #define OMAP_UART_MVR_MIN_MASK 0x3f 79 80 #define OMAP_UART_DMA_CH_FREE -1 81 82 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA 83 #define OMAP_MODE13X_SPEED 230400 84 85 /* WER = 0x7F 86 * Enable module level wakeup in WER reg 87 */ 88 #define OMAP_UART_WER_MOD_WKUP 0X7F 89 90 /* Enable XON/XOFF flow control on output */ 91 #define OMAP_UART_SW_TX 0x08 92 93 /* Enable XON/XOFF flow control on input */ 94 #define OMAP_UART_SW_RX 0x02 95 96 #define OMAP_UART_SW_CLR 0xF0 97 98 #define OMAP_UART_TCR_TRIG 0x0F 99 100 struct uart_omap_dma { 101 u8 uart_dma_tx; 102 u8 uart_dma_rx; 103 int rx_dma_channel; 104 int tx_dma_channel; 105 dma_addr_t rx_buf_dma_phys; 106 dma_addr_t tx_buf_dma_phys; 107 unsigned int uart_base; 108 /* 109 * Buffer for rx dma.It is not required for tx because the buffer 110 * comes from port structure. 111 */ 112 unsigned char *rx_buf; 113 unsigned int prev_rx_dma_pos; 114 int tx_buf_size; 115 int tx_dma_used; 116 int rx_dma_used; 117 spinlock_t tx_lock; 118 spinlock_t rx_lock; 119 /* timer to poll activity on rx dma */ 120 struct timer_list rx_timer; 121 unsigned int rx_buf_size; 122 unsigned int rx_poll_rate; 123 unsigned int rx_timeout; 124 }; 125 126 struct uart_omap_port { 127 struct uart_port port; 128 struct uart_omap_dma uart_dma; 129 struct device *dev; 130 131 unsigned char ier; 132 unsigned char lcr; 133 unsigned char mcr; 134 unsigned char fcr; 135 unsigned char efr; 136 unsigned char dll; 137 unsigned char dlh; 138 unsigned char mdr1; 139 unsigned char scr; 140 141 int use_dma; 142 /* 143 * Some bits in registers are cleared on a read, so they must 144 * be saved whenever the register is read but the bits will not 145 * be immediately processed. 146 */ 147 unsigned int lsr_break_flag; 148 unsigned char msr_saved_flags; 149 char name[20]; 150 unsigned long port_activity; 151 int context_loss_cnt; 152 u32 errata; 153 u8 wakeups_enabled; 154 155 int DTR_gpio; 156 int DTR_inverted; 157 int DTR_active; 158 159 struct pm_qos_request pm_qos_request; 160 u32 latency; 161 u32 calc_latency; 162 struct work_struct qos_work; 163 struct pinctrl *pins; 164 }; 165 166 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port))) 167 168 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; 169 170 /* Forward declaration of functions */ 171 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1); 172 173 static struct workqueue_struct *serial_omap_uart_wq; 174 175 static inline unsigned int serial_in(struct uart_omap_port *up, int offset) 176 { 177 offset <<= up->port.regshift; 178 return readw(up->port.membase + offset); 179 } 180 181 static inline void serial_out(struct uart_omap_port *up, int offset, int value) 182 { 183 offset <<= up->port.regshift; 184 writew(value, up->port.membase + offset); 185 } 186 187 static inline void serial_omap_clear_fifos(struct uart_omap_port *up) 188 { 189 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 190 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 191 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 192 serial_out(up, UART_FCR, 0); 193 } 194 195 static int serial_omap_get_context_loss_count(struct uart_omap_port *up) 196 { 197 struct omap_uart_port_info *pdata = up->dev->platform_data; 198 199 if (!pdata || !pdata->get_context_loss_count) 200 return 0; 201 202 return pdata->get_context_loss_count(up->dev); 203 } 204 205 static void serial_omap_set_forceidle(struct uart_omap_port *up) 206 { 207 struct omap_uart_port_info *pdata = up->dev->platform_data; 208 209 if (!pdata || !pdata->set_forceidle) 210 return; 211 212 pdata->set_forceidle(up->dev); 213 } 214 215 static void serial_omap_set_noidle(struct uart_omap_port *up) 216 { 217 struct omap_uart_port_info *pdata = up->dev->platform_data; 218 219 if (!pdata || !pdata->set_noidle) 220 return; 221 222 pdata->set_noidle(up->dev); 223 } 224 225 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable) 226 { 227 struct omap_uart_port_info *pdata = up->dev->platform_data; 228 229 if (!pdata || !pdata->enable_wakeup) 230 return; 231 232 pdata->enable_wakeup(up->dev, enable); 233 } 234 235 /* 236 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X 237 * @port: uart port info 238 * @baud: baudrate for which mode needs to be determined 239 * 240 * Returns true if baud rate is MODE16X and false if MODE13X 241 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values, 242 * and Error Rates" determines modes not for all common baud rates. 243 * E.g. for 1000000 baud rate mode must be 16x, but according to that 244 * table it's determined as 13x. 245 */ 246 static bool 247 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud) 248 { 249 unsigned int n13 = port->uartclk / (13 * baud); 250 unsigned int n16 = port->uartclk / (16 * baud); 251 int baudAbsDiff13 = baud - (port->uartclk / (13 * n13)); 252 int baudAbsDiff16 = baud - (port->uartclk / (16 * n16)); 253 if(baudAbsDiff13 < 0) 254 baudAbsDiff13 = -baudAbsDiff13; 255 if(baudAbsDiff16 < 0) 256 baudAbsDiff16 = -baudAbsDiff16; 257 258 return (baudAbsDiff13 > baudAbsDiff16); 259 } 260 261 /* 262 * serial_omap_get_divisor - calculate divisor value 263 * @port: uart port info 264 * @baud: baudrate for which divisor needs to be calculated. 265 */ 266 static unsigned int 267 serial_omap_get_divisor(struct uart_port *port, unsigned int baud) 268 { 269 unsigned int divisor; 270 271 if (!serial_omap_baud_is_mode16(port, baud)) 272 divisor = 13; 273 else 274 divisor = 16; 275 return port->uartclk/(baud * divisor); 276 } 277 278 static void serial_omap_enable_ms(struct uart_port *port) 279 { 280 struct uart_omap_port *up = to_uart_omap_port(port); 281 282 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line); 283 284 pm_runtime_get_sync(up->dev); 285 up->ier |= UART_IER_MSI; 286 serial_out(up, UART_IER, up->ier); 287 pm_runtime_mark_last_busy(up->dev); 288 pm_runtime_put_autosuspend(up->dev); 289 } 290 291 static void serial_omap_stop_tx(struct uart_port *port) 292 { 293 struct uart_omap_port *up = to_uart_omap_port(port); 294 295 pm_runtime_get_sync(up->dev); 296 if (up->ier & UART_IER_THRI) { 297 up->ier &= ~UART_IER_THRI; 298 serial_out(up, UART_IER, up->ier); 299 } 300 301 serial_omap_set_forceidle(up); 302 303 pm_runtime_mark_last_busy(up->dev); 304 pm_runtime_put_autosuspend(up->dev); 305 } 306 307 static void serial_omap_stop_rx(struct uart_port *port) 308 { 309 struct uart_omap_port *up = to_uart_omap_port(port); 310 311 pm_runtime_get_sync(up->dev); 312 up->ier &= ~UART_IER_RLSI; 313 up->port.read_status_mask &= ~UART_LSR_DR; 314 serial_out(up, UART_IER, up->ier); 315 pm_runtime_mark_last_busy(up->dev); 316 pm_runtime_put_autosuspend(up->dev); 317 } 318 319 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr) 320 { 321 struct circ_buf *xmit = &up->port.state->xmit; 322 int count; 323 324 if (up->port.x_char) { 325 serial_out(up, UART_TX, up->port.x_char); 326 up->port.icount.tx++; 327 up->port.x_char = 0; 328 return; 329 } 330 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 331 serial_omap_stop_tx(&up->port); 332 return; 333 } 334 count = up->port.fifosize / 4; 335 do { 336 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 337 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 338 up->port.icount.tx++; 339 if (uart_circ_empty(xmit)) 340 break; 341 } while (--count > 0); 342 343 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) { 344 spin_unlock(&up->port.lock); 345 uart_write_wakeup(&up->port); 346 spin_lock(&up->port.lock); 347 } 348 349 if (uart_circ_empty(xmit)) 350 serial_omap_stop_tx(&up->port); 351 } 352 353 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) 354 { 355 if (!(up->ier & UART_IER_THRI)) { 356 up->ier |= UART_IER_THRI; 357 serial_out(up, UART_IER, up->ier); 358 } 359 } 360 361 static void serial_omap_start_tx(struct uart_port *port) 362 { 363 struct uart_omap_port *up = to_uart_omap_port(port); 364 365 pm_runtime_get_sync(up->dev); 366 serial_omap_enable_ier_thri(up); 367 serial_omap_set_noidle(up); 368 pm_runtime_mark_last_busy(up->dev); 369 pm_runtime_put_autosuspend(up->dev); 370 } 371 372 static void serial_omap_throttle(struct uart_port *port) 373 { 374 struct uart_omap_port *up = to_uart_omap_port(port); 375 unsigned long flags; 376 377 pm_runtime_get_sync(up->dev); 378 spin_lock_irqsave(&up->port.lock, flags); 379 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 380 serial_out(up, UART_IER, up->ier); 381 spin_unlock_irqrestore(&up->port.lock, flags); 382 pm_runtime_mark_last_busy(up->dev); 383 pm_runtime_put_autosuspend(up->dev); 384 } 385 386 static void serial_omap_unthrottle(struct uart_port *port) 387 { 388 struct uart_omap_port *up = to_uart_omap_port(port); 389 unsigned long flags; 390 391 pm_runtime_get_sync(up->dev); 392 spin_lock_irqsave(&up->port.lock, flags); 393 up->ier |= UART_IER_RLSI | UART_IER_RDI; 394 serial_out(up, UART_IER, up->ier); 395 spin_unlock_irqrestore(&up->port.lock, flags); 396 pm_runtime_mark_last_busy(up->dev); 397 pm_runtime_put_autosuspend(up->dev); 398 } 399 400 static unsigned int check_modem_status(struct uart_omap_port *up) 401 { 402 unsigned int status; 403 404 status = serial_in(up, UART_MSR); 405 status |= up->msr_saved_flags; 406 up->msr_saved_flags = 0; 407 if ((status & UART_MSR_ANY_DELTA) == 0) 408 return status; 409 410 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && 411 up->port.state != NULL) { 412 if (status & UART_MSR_TERI) 413 up->port.icount.rng++; 414 if (status & UART_MSR_DDSR) 415 up->port.icount.dsr++; 416 if (status & UART_MSR_DDCD) 417 uart_handle_dcd_change 418 (&up->port, status & UART_MSR_DCD); 419 if (status & UART_MSR_DCTS) 420 uart_handle_cts_change 421 (&up->port, status & UART_MSR_CTS); 422 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 423 } 424 425 return status; 426 } 427 428 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr) 429 { 430 unsigned int flag; 431 unsigned char ch = 0; 432 433 if (likely(lsr & UART_LSR_DR)) 434 ch = serial_in(up, UART_RX); 435 436 up->port.icount.rx++; 437 flag = TTY_NORMAL; 438 439 if (lsr & UART_LSR_BI) { 440 flag = TTY_BREAK; 441 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 442 up->port.icount.brk++; 443 /* 444 * We do the SysRQ and SAK checking 445 * here because otherwise the break 446 * may get masked by ignore_status_mask 447 * or read_status_mask. 448 */ 449 if (uart_handle_break(&up->port)) 450 return; 451 452 } 453 454 if (lsr & UART_LSR_PE) { 455 flag = TTY_PARITY; 456 up->port.icount.parity++; 457 } 458 459 if (lsr & UART_LSR_FE) { 460 flag = TTY_FRAME; 461 up->port.icount.frame++; 462 } 463 464 if (lsr & UART_LSR_OE) 465 up->port.icount.overrun++; 466 467 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 468 if (up->port.line == up->port.cons->index) { 469 /* Recover the break flag from console xmit */ 470 lsr |= up->lsr_break_flag; 471 } 472 #endif 473 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag); 474 } 475 476 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr) 477 { 478 unsigned char ch = 0; 479 unsigned int flag; 480 481 if (!(lsr & UART_LSR_DR)) 482 return; 483 484 ch = serial_in(up, UART_RX); 485 flag = TTY_NORMAL; 486 up->port.icount.rx++; 487 488 if (uart_handle_sysrq_char(&up->port, ch)) 489 return; 490 491 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); 492 } 493 494 /** 495 * serial_omap_irq() - This handles the interrupt from one port 496 * @irq: uart port irq number 497 * @dev_id: uart port info 498 */ 499 static irqreturn_t serial_omap_irq(int irq, void *dev_id) 500 { 501 struct uart_omap_port *up = dev_id; 502 unsigned int iir, lsr; 503 unsigned int type; 504 irqreturn_t ret = IRQ_NONE; 505 int max_count = 256; 506 507 spin_lock(&up->port.lock); 508 pm_runtime_get_sync(up->dev); 509 510 do { 511 iir = serial_in(up, UART_IIR); 512 if (iir & UART_IIR_NO_INT) 513 break; 514 515 ret = IRQ_HANDLED; 516 lsr = serial_in(up, UART_LSR); 517 518 /* extract IRQ type from IIR register */ 519 type = iir & 0x3e; 520 521 switch (type) { 522 case UART_IIR_MSI: 523 check_modem_status(up); 524 break; 525 case UART_IIR_THRI: 526 transmit_chars(up, lsr); 527 break; 528 case UART_IIR_RX_TIMEOUT: 529 /* FALLTHROUGH */ 530 case UART_IIR_RDI: 531 serial_omap_rdi(up, lsr); 532 break; 533 case UART_IIR_RLSI: 534 serial_omap_rlsi(up, lsr); 535 break; 536 case UART_IIR_CTS_RTS_DSR: 537 /* simply try again */ 538 break; 539 case UART_IIR_XOFF: 540 /* FALLTHROUGH */ 541 default: 542 break; 543 } 544 } while (!(iir & UART_IIR_NO_INT) && max_count--); 545 546 spin_unlock(&up->port.lock); 547 548 tty_flip_buffer_push(&up->port.state->port); 549 550 pm_runtime_mark_last_busy(up->dev); 551 pm_runtime_put_autosuspend(up->dev); 552 up->port_activity = jiffies; 553 554 return ret; 555 } 556 557 static unsigned int serial_omap_tx_empty(struct uart_port *port) 558 { 559 struct uart_omap_port *up = to_uart_omap_port(port); 560 unsigned long flags = 0; 561 unsigned int ret = 0; 562 563 pm_runtime_get_sync(up->dev); 564 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line); 565 spin_lock_irqsave(&up->port.lock, flags); 566 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 567 spin_unlock_irqrestore(&up->port.lock, flags); 568 pm_runtime_mark_last_busy(up->dev); 569 pm_runtime_put_autosuspend(up->dev); 570 return ret; 571 } 572 573 static unsigned int serial_omap_get_mctrl(struct uart_port *port) 574 { 575 struct uart_omap_port *up = to_uart_omap_port(port); 576 unsigned int status; 577 unsigned int ret = 0; 578 579 pm_runtime_get_sync(up->dev); 580 status = check_modem_status(up); 581 pm_runtime_mark_last_busy(up->dev); 582 pm_runtime_put_autosuspend(up->dev); 583 584 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line); 585 586 if (status & UART_MSR_DCD) 587 ret |= TIOCM_CAR; 588 if (status & UART_MSR_RI) 589 ret |= TIOCM_RNG; 590 if (status & UART_MSR_DSR) 591 ret |= TIOCM_DSR; 592 if (status & UART_MSR_CTS) 593 ret |= TIOCM_CTS; 594 return ret; 595 } 596 597 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) 598 { 599 struct uart_omap_port *up = to_uart_omap_port(port); 600 unsigned char mcr = 0, old_mcr; 601 602 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line); 603 if (mctrl & TIOCM_RTS) 604 mcr |= UART_MCR_RTS; 605 if (mctrl & TIOCM_DTR) 606 mcr |= UART_MCR_DTR; 607 if (mctrl & TIOCM_OUT1) 608 mcr |= UART_MCR_OUT1; 609 if (mctrl & TIOCM_OUT2) 610 mcr |= UART_MCR_OUT2; 611 if (mctrl & TIOCM_LOOP) 612 mcr |= UART_MCR_LOOP; 613 614 pm_runtime_get_sync(up->dev); 615 old_mcr = serial_in(up, UART_MCR); 616 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 | 617 UART_MCR_DTR | UART_MCR_RTS); 618 up->mcr = old_mcr | mcr; 619 serial_out(up, UART_MCR, up->mcr); 620 pm_runtime_mark_last_busy(up->dev); 621 pm_runtime_put_autosuspend(up->dev); 622 623 if (gpio_is_valid(up->DTR_gpio) && 624 !!(mctrl & TIOCM_DTR) != up->DTR_active) { 625 up->DTR_active = !up->DTR_active; 626 if (gpio_cansleep(up->DTR_gpio)) 627 schedule_work(&up->qos_work); 628 else 629 gpio_set_value(up->DTR_gpio, 630 up->DTR_active != up->DTR_inverted); 631 } 632 } 633 634 static void serial_omap_break_ctl(struct uart_port *port, int break_state) 635 { 636 struct uart_omap_port *up = to_uart_omap_port(port); 637 unsigned long flags = 0; 638 639 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line); 640 pm_runtime_get_sync(up->dev); 641 spin_lock_irqsave(&up->port.lock, flags); 642 if (break_state == -1) 643 up->lcr |= UART_LCR_SBC; 644 else 645 up->lcr &= ~UART_LCR_SBC; 646 serial_out(up, UART_LCR, up->lcr); 647 spin_unlock_irqrestore(&up->port.lock, flags); 648 pm_runtime_mark_last_busy(up->dev); 649 pm_runtime_put_autosuspend(up->dev); 650 } 651 652 static int serial_omap_startup(struct uart_port *port) 653 { 654 struct uart_omap_port *up = to_uart_omap_port(port); 655 unsigned long flags = 0; 656 int retval; 657 658 /* 659 * Allocate the IRQ 660 */ 661 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, 662 up->name, up); 663 if (retval) 664 return retval; 665 666 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line); 667 668 pm_runtime_get_sync(up->dev); 669 /* 670 * Clear the FIFO buffers and disable them. 671 * (they will be reenabled in set_termios()) 672 */ 673 serial_omap_clear_fifos(up); 674 /* For Hardware flow control */ 675 serial_out(up, UART_MCR, UART_MCR_RTS); 676 677 /* 678 * Clear the interrupt registers. 679 */ 680 (void) serial_in(up, UART_LSR); 681 if (serial_in(up, UART_LSR) & UART_LSR_DR) 682 (void) serial_in(up, UART_RX); 683 (void) serial_in(up, UART_IIR); 684 (void) serial_in(up, UART_MSR); 685 686 /* 687 * Now, initialize the UART 688 */ 689 serial_out(up, UART_LCR, UART_LCR_WLEN8); 690 spin_lock_irqsave(&up->port.lock, flags); 691 /* 692 * Most PC uarts need OUT2 raised to enable interrupts. 693 */ 694 up->port.mctrl |= TIOCM_OUT2; 695 serial_omap_set_mctrl(&up->port, up->port.mctrl); 696 spin_unlock_irqrestore(&up->port.lock, flags); 697 698 up->msr_saved_flags = 0; 699 /* 700 * Finally, enable interrupts. Note: Modem status interrupts 701 * are set via set_termios(), which will be occurring imminently 702 * anyway, so we don't enable them here. 703 */ 704 up->ier = UART_IER_RLSI | UART_IER_RDI; 705 serial_out(up, UART_IER, up->ier); 706 707 /* Enable module level wake up */ 708 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP); 709 710 pm_runtime_mark_last_busy(up->dev); 711 pm_runtime_put_autosuspend(up->dev); 712 up->port_activity = jiffies; 713 return 0; 714 } 715 716 static void serial_omap_shutdown(struct uart_port *port) 717 { 718 struct uart_omap_port *up = to_uart_omap_port(port); 719 unsigned long flags = 0; 720 721 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line); 722 723 pm_runtime_get_sync(up->dev); 724 /* 725 * Disable interrupts from this port 726 */ 727 up->ier = 0; 728 serial_out(up, UART_IER, 0); 729 730 spin_lock_irqsave(&up->port.lock, flags); 731 up->port.mctrl &= ~TIOCM_OUT2; 732 serial_omap_set_mctrl(&up->port, up->port.mctrl); 733 spin_unlock_irqrestore(&up->port.lock, flags); 734 735 /* 736 * Disable break condition and FIFOs 737 */ 738 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); 739 serial_omap_clear_fifos(up); 740 741 /* 742 * Read data port to reset things, and then free the irq 743 */ 744 if (serial_in(up, UART_LSR) & UART_LSR_DR) 745 (void) serial_in(up, UART_RX); 746 747 pm_runtime_mark_last_busy(up->dev); 748 pm_runtime_put_autosuspend(up->dev); 749 free_irq(up->port.irq, up); 750 } 751 752 static void serial_omap_uart_qos_work(struct work_struct *work) 753 { 754 struct uart_omap_port *up = container_of(work, struct uart_omap_port, 755 qos_work); 756 757 pm_qos_update_request(&up->pm_qos_request, up->latency); 758 if (gpio_is_valid(up->DTR_gpio)) 759 gpio_set_value_cansleep(up->DTR_gpio, 760 up->DTR_active != up->DTR_inverted); 761 } 762 763 static void 764 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, 765 struct ktermios *old) 766 { 767 struct uart_omap_port *up = to_uart_omap_port(port); 768 unsigned char cval = 0; 769 unsigned long flags = 0; 770 unsigned int baud, quot; 771 772 switch (termios->c_cflag & CSIZE) { 773 case CS5: 774 cval = UART_LCR_WLEN5; 775 break; 776 case CS6: 777 cval = UART_LCR_WLEN6; 778 break; 779 case CS7: 780 cval = UART_LCR_WLEN7; 781 break; 782 default: 783 case CS8: 784 cval = UART_LCR_WLEN8; 785 break; 786 } 787 788 if (termios->c_cflag & CSTOPB) 789 cval |= UART_LCR_STOP; 790 if (termios->c_cflag & PARENB) 791 cval |= UART_LCR_PARITY; 792 if (!(termios->c_cflag & PARODD)) 793 cval |= UART_LCR_EPAR; 794 if (termios->c_cflag & CMSPAR) 795 cval |= UART_LCR_SPAR; 796 797 /* 798 * Ask the core to calculate the divisor for us. 799 */ 800 801 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); 802 quot = serial_omap_get_divisor(port, baud); 803 804 /* calculate wakeup latency constraint */ 805 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8); 806 up->latency = up->calc_latency; 807 schedule_work(&up->qos_work); 808 809 up->dll = quot & 0xff; 810 up->dlh = quot >> 8; 811 up->mdr1 = UART_OMAP_MDR1_DISABLE; 812 813 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | 814 UART_FCR_ENABLE_FIFO; 815 816 /* 817 * Ok, we're now changing the port state. Do it with 818 * interrupts disabled. 819 */ 820 pm_runtime_get_sync(up->dev); 821 spin_lock_irqsave(&up->port.lock, flags); 822 823 /* 824 * Update the per-port timeout. 825 */ 826 uart_update_timeout(port, termios->c_cflag, baud); 827 828 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 829 if (termios->c_iflag & INPCK) 830 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 831 if (termios->c_iflag & (BRKINT | PARMRK)) 832 up->port.read_status_mask |= UART_LSR_BI; 833 834 /* 835 * Characters to ignore 836 */ 837 up->port.ignore_status_mask = 0; 838 if (termios->c_iflag & IGNPAR) 839 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 840 if (termios->c_iflag & IGNBRK) { 841 up->port.ignore_status_mask |= UART_LSR_BI; 842 /* 843 * If we're ignoring parity and break indicators, 844 * ignore overruns too (for real raw support). 845 */ 846 if (termios->c_iflag & IGNPAR) 847 up->port.ignore_status_mask |= UART_LSR_OE; 848 } 849 850 /* 851 * ignore all characters if CREAD is not set 852 */ 853 if ((termios->c_cflag & CREAD) == 0) 854 up->port.ignore_status_mask |= UART_LSR_DR; 855 856 /* 857 * Modem status interrupts 858 */ 859 up->ier &= ~UART_IER_MSI; 860 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 861 up->ier |= UART_IER_MSI; 862 serial_out(up, UART_IER, up->ier); 863 serial_out(up, UART_LCR, cval); /* reset DLAB */ 864 up->lcr = cval; 865 up->scr = 0; 866 867 /* FIFOs and DMA Settings */ 868 869 /* FCR can be changed only when the 870 * baud clock is not running 871 * DLL_REG and DLH_REG set to 0. 872 */ 873 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 874 serial_out(up, UART_DLL, 0); 875 serial_out(up, UART_DLM, 0); 876 serial_out(up, UART_LCR, 0); 877 878 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 879 880 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB; 881 up->efr &= ~UART_EFR_SCD; 882 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 883 884 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 885 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR; 886 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 887 /* FIFO ENABLE, DMA MODE */ 888 889 /* Set receive FIFO threshold to 16 characters and 890 * transmit FIFO threshold to 16 spaces 891 */ 892 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; 893 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK; 894 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 | 895 UART_FCR_ENABLE_FIFO; 896 897 serial_out(up, UART_FCR, up->fcr); 898 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 899 900 serial_out(up, UART_OMAP_SCR, up->scr); 901 902 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */ 903 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 904 serial_out(up, UART_MCR, up->mcr); 905 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 906 serial_out(up, UART_EFR, up->efr); 907 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 908 909 /* Protocol, Baud Rate, and Interrupt Settings */ 910 911 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 912 serial_omap_mdr1_errataset(up, up->mdr1); 913 else 914 serial_out(up, UART_OMAP_MDR1, up->mdr1); 915 916 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 917 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 918 919 serial_out(up, UART_LCR, 0); 920 serial_out(up, UART_IER, 0); 921 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 922 923 serial_out(up, UART_DLL, up->dll); /* LS of divisor */ 924 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */ 925 926 serial_out(up, UART_LCR, 0); 927 serial_out(up, UART_IER, up->ier); 928 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 929 930 serial_out(up, UART_EFR, up->efr); 931 serial_out(up, UART_LCR, cval); 932 933 if (!serial_omap_baud_is_mode16(port, baud)) 934 up->mdr1 = UART_OMAP_MDR1_13X_MODE; 935 else 936 up->mdr1 = UART_OMAP_MDR1_16X_MODE; 937 938 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 939 serial_omap_mdr1_errataset(up, up->mdr1); 940 else 941 serial_out(up, UART_OMAP_MDR1, up->mdr1); 942 943 /* Configure flow control */ 944 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 945 946 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */ 947 serial_out(up, UART_XON1, termios->c_cc[VSTART]); 948 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); 949 950 /* Enable access to TCR/TLR */ 951 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 952 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 953 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 954 955 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); 956 957 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { 958 /* Enable AUTORTS and AUTOCTS */ 959 up->efr |= UART_EFR_CTS | UART_EFR_RTS; 960 961 /* Ensure MCR RTS is asserted */ 962 up->mcr |= UART_MCR_RTS; 963 } else { 964 /* Disable AUTORTS and AUTOCTS */ 965 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS); 966 } 967 968 if (up->port.flags & UPF_SOFT_FLOW) { 969 /* clear SW control mode bits */ 970 up->efr &= OMAP_UART_SW_CLR; 971 972 /* 973 * IXON Flag: 974 * Enable XON/XOFF flow control on input. 975 * Receiver compares XON1, XOFF1. 976 */ 977 if (termios->c_iflag & IXON) 978 up->efr |= OMAP_UART_SW_RX; 979 980 /* 981 * IXOFF Flag: 982 * Enable XON/XOFF flow control on output. 983 * Transmit XON1, XOFF1 984 */ 985 if (termios->c_iflag & IXOFF) 986 up->efr |= OMAP_UART_SW_TX; 987 988 /* 989 * IXANY Flag: 990 * Enable any character to restart output. 991 * Operation resumes after receiving any 992 * character after recognition of the XOFF character 993 */ 994 if (termios->c_iflag & IXANY) 995 up->mcr |= UART_MCR_XONANY; 996 else 997 up->mcr &= ~UART_MCR_XONANY; 998 } 999 serial_out(up, UART_MCR, up->mcr); 1000 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1001 serial_out(up, UART_EFR, up->efr); 1002 serial_out(up, UART_LCR, up->lcr); 1003 1004 serial_omap_set_mctrl(&up->port, up->port.mctrl); 1005 1006 spin_unlock_irqrestore(&up->port.lock, flags); 1007 pm_runtime_mark_last_busy(up->dev); 1008 pm_runtime_put_autosuspend(up->dev); 1009 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line); 1010 } 1011 1012 static int serial_omap_set_wake(struct uart_port *port, unsigned int state) 1013 { 1014 struct uart_omap_port *up = to_uart_omap_port(port); 1015 1016 serial_omap_enable_wakeup(up, state); 1017 1018 return 0; 1019 } 1020 1021 static void 1022 serial_omap_pm(struct uart_port *port, unsigned int state, 1023 unsigned int oldstate) 1024 { 1025 struct uart_omap_port *up = to_uart_omap_port(port); 1026 unsigned char efr; 1027 1028 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line); 1029 1030 pm_runtime_get_sync(up->dev); 1031 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1032 efr = serial_in(up, UART_EFR); 1033 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 1034 serial_out(up, UART_LCR, 0); 1035 1036 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 1037 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1038 serial_out(up, UART_EFR, efr); 1039 serial_out(up, UART_LCR, 0); 1040 1041 if (!device_may_wakeup(up->dev)) { 1042 if (!state) 1043 pm_runtime_forbid(up->dev); 1044 else 1045 pm_runtime_allow(up->dev); 1046 } 1047 1048 pm_runtime_mark_last_busy(up->dev); 1049 pm_runtime_put_autosuspend(up->dev); 1050 } 1051 1052 static void serial_omap_release_port(struct uart_port *port) 1053 { 1054 dev_dbg(port->dev, "serial_omap_release_port+\n"); 1055 } 1056 1057 static int serial_omap_request_port(struct uart_port *port) 1058 { 1059 dev_dbg(port->dev, "serial_omap_request_port+\n"); 1060 return 0; 1061 } 1062 1063 static void serial_omap_config_port(struct uart_port *port, int flags) 1064 { 1065 struct uart_omap_port *up = to_uart_omap_port(port); 1066 1067 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", 1068 up->port.line); 1069 up->port.type = PORT_OMAP; 1070 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW; 1071 } 1072 1073 static int 1074 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) 1075 { 1076 /* we don't want the core code to modify any port params */ 1077 dev_dbg(port->dev, "serial_omap_verify_port+\n"); 1078 return -EINVAL; 1079 } 1080 1081 static const char * 1082 serial_omap_type(struct uart_port *port) 1083 { 1084 struct uart_omap_port *up = to_uart_omap_port(port); 1085 1086 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line); 1087 return up->name; 1088 } 1089 1090 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 1091 1092 static inline void wait_for_xmitr(struct uart_omap_port *up) 1093 { 1094 unsigned int status, tmout = 10000; 1095 1096 /* Wait up to 10ms for the character(s) to be sent. */ 1097 do { 1098 status = serial_in(up, UART_LSR); 1099 1100 if (status & UART_LSR_BI) 1101 up->lsr_break_flag = UART_LSR_BI; 1102 1103 if (--tmout == 0) 1104 break; 1105 udelay(1); 1106 } while ((status & BOTH_EMPTY) != BOTH_EMPTY); 1107 1108 /* Wait up to 1s for flow control if necessary */ 1109 if (up->port.flags & UPF_CONS_FLOW) { 1110 tmout = 1000000; 1111 for (tmout = 1000000; tmout; tmout--) { 1112 unsigned int msr = serial_in(up, UART_MSR); 1113 1114 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; 1115 if (msr & UART_MSR_CTS) 1116 break; 1117 1118 udelay(1); 1119 } 1120 } 1121 } 1122 1123 #ifdef CONFIG_CONSOLE_POLL 1124 1125 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) 1126 { 1127 struct uart_omap_port *up = to_uart_omap_port(port); 1128 1129 pm_runtime_get_sync(up->dev); 1130 wait_for_xmitr(up); 1131 serial_out(up, UART_TX, ch); 1132 pm_runtime_mark_last_busy(up->dev); 1133 pm_runtime_put_autosuspend(up->dev); 1134 } 1135 1136 static int serial_omap_poll_get_char(struct uart_port *port) 1137 { 1138 struct uart_omap_port *up = to_uart_omap_port(port); 1139 unsigned int status; 1140 1141 pm_runtime_get_sync(up->dev); 1142 status = serial_in(up, UART_LSR); 1143 if (!(status & UART_LSR_DR)) { 1144 status = NO_POLL_CHAR; 1145 goto out; 1146 } 1147 1148 status = serial_in(up, UART_RX); 1149 1150 out: 1151 pm_runtime_mark_last_busy(up->dev); 1152 pm_runtime_put_autosuspend(up->dev); 1153 1154 return status; 1155 } 1156 1157 #endif /* CONFIG_CONSOLE_POLL */ 1158 1159 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 1160 1161 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS]; 1162 1163 static struct uart_driver serial_omap_reg; 1164 1165 static void serial_omap_console_putchar(struct uart_port *port, int ch) 1166 { 1167 struct uart_omap_port *up = to_uart_omap_port(port); 1168 1169 wait_for_xmitr(up); 1170 serial_out(up, UART_TX, ch); 1171 } 1172 1173 static void 1174 serial_omap_console_write(struct console *co, const char *s, 1175 unsigned int count) 1176 { 1177 struct uart_omap_port *up = serial_omap_console_ports[co->index]; 1178 unsigned long flags; 1179 unsigned int ier; 1180 int locked = 1; 1181 1182 pm_runtime_get_sync(up->dev); 1183 1184 local_irq_save(flags); 1185 if (up->port.sysrq) 1186 locked = 0; 1187 else if (oops_in_progress) 1188 locked = spin_trylock(&up->port.lock); 1189 else 1190 spin_lock(&up->port.lock); 1191 1192 /* 1193 * First save the IER then disable the interrupts 1194 */ 1195 ier = serial_in(up, UART_IER); 1196 serial_out(up, UART_IER, 0); 1197 1198 uart_console_write(&up->port, s, count, serial_omap_console_putchar); 1199 1200 /* 1201 * Finally, wait for transmitter to become empty 1202 * and restore the IER 1203 */ 1204 wait_for_xmitr(up); 1205 serial_out(up, UART_IER, ier); 1206 /* 1207 * The receive handling will happen properly because the 1208 * receive ready bit will still be set; it is not cleared 1209 * on read. However, modem control will not, we must 1210 * call it if we have saved something in the saved flags 1211 * while processing with interrupts off. 1212 */ 1213 if (up->msr_saved_flags) 1214 check_modem_status(up); 1215 1216 pm_runtime_mark_last_busy(up->dev); 1217 pm_runtime_put_autosuspend(up->dev); 1218 if (locked) 1219 spin_unlock(&up->port.lock); 1220 local_irq_restore(flags); 1221 } 1222 1223 static int __init 1224 serial_omap_console_setup(struct console *co, char *options) 1225 { 1226 struct uart_omap_port *up; 1227 int baud = 115200; 1228 int bits = 8; 1229 int parity = 'n'; 1230 int flow = 'n'; 1231 1232 if (serial_omap_console_ports[co->index] == NULL) 1233 return -ENODEV; 1234 up = serial_omap_console_ports[co->index]; 1235 1236 if (options) 1237 uart_parse_options(options, &baud, &parity, &bits, &flow); 1238 1239 return uart_set_options(&up->port, co, baud, parity, bits, flow); 1240 } 1241 1242 static struct console serial_omap_console = { 1243 .name = OMAP_SERIAL_NAME, 1244 .write = serial_omap_console_write, 1245 .device = uart_console_device, 1246 .setup = serial_omap_console_setup, 1247 .flags = CON_PRINTBUFFER, 1248 .index = -1, 1249 .data = &serial_omap_reg, 1250 }; 1251 1252 static void serial_omap_add_console_port(struct uart_omap_port *up) 1253 { 1254 serial_omap_console_ports[up->port.line] = up; 1255 } 1256 1257 #define OMAP_CONSOLE (&serial_omap_console) 1258 1259 #else 1260 1261 #define OMAP_CONSOLE NULL 1262 1263 static inline void serial_omap_add_console_port(struct uart_omap_port *up) 1264 {} 1265 1266 #endif 1267 1268 static struct uart_ops serial_omap_pops = { 1269 .tx_empty = serial_omap_tx_empty, 1270 .set_mctrl = serial_omap_set_mctrl, 1271 .get_mctrl = serial_omap_get_mctrl, 1272 .stop_tx = serial_omap_stop_tx, 1273 .start_tx = serial_omap_start_tx, 1274 .throttle = serial_omap_throttle, 1275 .unthrottle = serial_omap_unthrottle, 1276 .stop_rx = serial_omap_stop_rx, 1277 .enable_ms = serial_omap_enable_ms, 1278 .break_ctl = serial_omap_break_ctl, 1279 .startup = serial_omap_startup, 1280 .shutdown = serial_omap_shutdown, 1281 .set_termios = serial_omap_set_termios, 1282 .pm = serial_omap_pm, 1283 .set_wake = serial_omap_set_wake, 1284 .type = serial_omap_type, 1285 .release_port = serial_omap_release_port, 1286 .request_port = serial_omap_request_port, 1287 .config_port = serial_omap_config_port, 1288 .verify_port = serial_omap_verify_port, 1289 #ifdef CONFIG_CONSOLE_POLL 1290 .poll_put_char = serial_omap_poll_put_char, 1291 .poll_get_char = serial_omap_poll_get_char, 1292 #endif 1293 }; 1294 1295 static struct uart_driver serial_omap_reg = { 1296 .owner = THIS_MODULE, 1297 .driver_name = "OMAP-SERIAL", 1298 .dev_name = OMAP_SERIAL_NAME, 1299 .nr = OMAP_MAX_HSUART_PORTS, 1300 .cons = OMAP_CONSOLE, 1301 }; 1302 1303 #ifdef CONFIG_PM_SLEEP 1304 static int serial_omap_suspend(struct device *dev) 1305 { 1306 struct uart_omap_port *up = dev_get_drvdata(dev); 1307 1308 uart_suspend_port(&serial_omap_reg, &up->port); 1309 flush_work(&up->qos_work); 1310 1311 return 0; 1312 } 1313 1314 static int serial_omap_resume(struct device *dev) 1315 { 1316 struct uart_omap_port *up = dev_get_drvdata(dev); 1317 1318 uart_resume_port(&serial_omap_reg, &up->port); 1319 1320 return 0; 1321 } 1322 #endif 1323 1324 static void omap_serial_fill_features_erratas(struct uart_omap_port *up) 1325 { 1326 u32 mvr, scheme; 1327 u16 revision, major, minor; 1328 1329 mvr = serial_in(up, UART_OMAP_MVER); 1330 1331 /* Check revision register scheme */ 1332 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 1333 1334 switch (scheme) { 1335 case 0: /* Legacy Scheme: OMAP2/3 */ 1336 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 1337 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 1338 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 1339 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 1340 break; 1341 case 1: 1342 /* New Scheme: OMAP4+ */ 1343 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 1344 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 1345 OMAP_UART_MVR_MAJ_SHIFT; 1346 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 1347 break; 1348 default: 1349 dev_warn(up->dev, 1350 "Unknown %s revision, defaulting to highest\n", 1351 up->name); 1352 /* highest possible revision */ 1353 major = 0xff; 1354 minor = 0xff; 1355 } 1356 1357 /* normalize revision for the driver */ 1358 revision = UART_BUILD_REVISION(major, minor); 1359 1360 switch (revision) { 1361 case OMAP_UART_REV_46: 1362 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1363 UART_ERRATA_i291_DMA_FORCEIDLE); 1364 break; 1365 case OMAP_UART_REV_52: 1366 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1367 UART_ERRATA_i291_DMA_FORCEIDLE); 1368 break; 1369 case OMAP_UART_REV_63: 1370 up->errata |= UART_ERRATA_i202_MDR1_ACCESS; 1371 break; 1372 default: 1373 break; 1374 } 1375 } 1376 1377 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev) 1378 { 1379 struct omap_uart_port_info *omap_up_info; 1380 1381 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL); 1382 if (!omap_up_info) 1383 return NULL; /* out of memory */ 1384 1385 of_property_read_u32(dev->of_node, "clock-frequency", 1386 &omap_up_info->uartclk); 1387 return omap_up_info; 1388 } 1389 1390 static int serial_omap_probe(struct platform_device *pdev) 1391 { 1392 struct uart_omap_port *up; 1393 struct resource *mem, *irq; 1394 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data; 1395 int ret; 1396 1397 if (pdev->dev.of_node) 1398 omap_up_info = of_get_uart_port_info(&pdev->dev); 1399 1400 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1401 if (!mem) { 1402 dev_err(&pdev->dev, "no mem resource?\n"); 1403 return -ENODEV; 1404 } 1405 1406 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1407 if (!irq) { 1408 dev_err(&pdev->dev, "no irq resource?\n"); 1409 return -ENODEV; 1410 } 1411 1412 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem), 1413 pdev->dev.driver->name)) { 1414 dev_err(&pdev->dev, "memory region already claimed\n"); 1415 return -EBUSY; 1416 } 1417 1418 if (gpio_is_valid(omap_up_info->DTR_gpio) && 1419 omap_up_info->DTR_present) { 1420 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial"); 1421 if (ret < 0) 1422 return ret; 1423 ret = gpio_direction_output(omap_up_info->DTR_gpio, 1424 omap_up_info->DTR_inverted); 1425 if (ret < 0) 1426 return ret; 1427 } 1428 1429 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL); 1430 if (!up) 1431 return -ENOMEM; 1432 1433 if (gpio_is_valid(omap_up_info->DTR_gpio) && 1434 omap_up_info->DTR_present) { 1435 up->DTR_gpio = omap_up_info->DTR_gpio; 1436 up->DTR_inverted = omap_up_info->DTR_inverted; 1437 } else 1438 up->DTR_gpio = -EINVAL; 1439 up->DTR_active = 0; 1440 1441 up->dev = &pdev->dev; 1442 up->port.dev = &pdev->dev; 1443 up->port.type = PORT_OMAP; 1444 up->port.iotype = UPIO_MEM; 1445 up->port.irq = irq->start; 1446 1447 up->port.regshift = 2; 1448 up->port.fifosize = 64; 1449 up->port.ops = &serial_omap_pops; 1450 1451 if (pdev->dev.of_node) 1452 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial"); 1453 else 1454 up->port.line = pdev->id; 1455 1456 if (up->port.line < 0) { 1457 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", 1458 up->port.line); 1459 ret = -ENODEV; 1460 goto err_port_line; 1461 } 1462 1463 up->pins = devm_pinctrl_get_select_default(&pdev->dev); 1464 if (IS_ERR(up->pins)) { 1465 dev_warn(&pdev->dev, "did not get pins for uart%i error: %li\n", 1466 up->port.line, PTR_ERR(up->pins)); 1467 up->pins = NULL; 1468 } 1469 1470 sprintf(up->name, "OMAP UART%d", up->port.line); 1471 up->port.mapbase = mem->start; 1472 up->port.membase = devm_ioremap(&pdev->dev, mem->start, 1473 resource_size(mem)); 1474 if (!up->port.membase) { 1475 dev_err(&pdev->dev, "can't ioremap UART\n"); 1476 ret = -ENOMEM; 1477 goto err_ioremap; 1478 } 1479 1480 up->port.flags = omap_up_info->flags; 1481 up->port.uartclk = omap_up_info->uartclk; 1482 if (!up->port.uartclk) { 1483 up->port.uartclk = DEFAULT_CLK_SPEED; 1484 dev_warn(&pdev->dev, "No clock speed specified: using default:" 1485 "%d\n", DEFAULT_CLK_SPEED); 1486 } 1487 1488 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1489 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1490 pm_qos_add_request(&up->pm_qos_request, 1491 PM_QOS_CPU_DMA_LATENCY, up->latency); 1492 serial_omap_uart_wq = create_singlethread_workqueue(up->name); 1493 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); 1494 1495 platform_set_drvdata(pdev, up); 1496 pm_runtime_enable(&pdev->dev); 1497 pm_runtime_use_autosuspend(&pdev->dev); 1498 pm_runtime_set_autosuspend_delay(&pdev->dev, 1499 omap_up_info->autosuspend_timeout); 1500 1501 pm_runtime_irq_safe(&pdev->dev); 1502 pm_runtime_get_sync(&pdev->dev); 1503 1504 omap_serial_fill_features_erratas(up); 1505 1506 ui[up->port.line] = up; 1507 serial_omap_add_console_port(up); 1508 1509 ret = uart_add_one_port(&serial_omap_reg, &up->port); 1510 if (ret != 0) 1511 goto err_add_port; 1512 1513 pm_runtime_mark_last_busy(up->dev); 1514 pm_runtime_put_autosuspend(up->dev); 1515 return 0; 1516 1517 err_add_port: 1518 pm_runtime_put(&pdev->dev); 1519 pm_runtime_disable(&pdev->dev); 1520 err_ioremap: 1521 err_port_line: 1522 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n", 1523 pdev->id, __func__, ret); 1524 return ret; 1525 } 1526 1527 static int serial_omap_remove(struct platform_device *dev) 1528 { 1529 struct uart_omap_port *up = platform_get_drvdata(dev); 1530 1531 pm_runtime_put_sync(up->dev); 1532 pm_runtime_disable(up->dev); 1533 uart_remove_one_port(&serial_omap_reg, &up->port); 1534 pm_qos_remove_request(&up->pm_qos_request); 1535 1536 return 0; 1537 } 1538 1539 /* 1540 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 1541 * The access to uart register after MDR1 Access 1542 * causes UART to corrupt data. 1543 * 1544 * Need a delay = 1545 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 1546 * give 10 times as much 1547 */ 1548 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1) 1549 { 1550 u8 timeout = 255; 1551 1552 serial_out(up, UART_OMAP_MDR1, mdr1); 1553 udelay(2); 1554 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 1555 UART_FCR_CLEAR_RCVR); 1556 /* 1557 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 1558 * TX_FIFO_E bit is 1. 1559 */ 1560 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 1561 (UART_LSR_THRE | UART_LSR_DR))) { 1562 timeout--; 1563 if (!timeout) { 1564 /* Should *never* happen. we warn and carry on */ 1565 dev_crit(up->dev, "Errata i202: timedout %x\n", 1566 serial_in(up, UART_LSR)); 1567 break; 1568 } 1569 udelay(1); 1570 } 1571 } 1572 1573 #ifdef CONFIG_PM_RUNTIME 1574 static void serial_omap_restore_context(struct uart_omap_port *up) 1575 { 1576 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1577 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE); 1578 else 1579 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); 1580 1581 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1582 serial_out(up, UART_EFR, UART_EFR_ECB); 1583 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1584 serial_out(up, UART_IER, 0x0); 1585 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1586 serial_out(up, UART_DLL, up->dll); 1587 serial_out(up, UART_DLM, up->dlh); 1588 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1589 serial_out(up, UART_IER, up->ier); 1590 serial_out(up, UART_FCR, up->fcr); 1591 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1592 serial_out(up, UART_MCR, up->mcr); 1593 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1594 serial_out(up, UART_OMAP_SCR, up->scr); 1595 serial_out(up, UART_EFR, up->efr); 1596 serial_out(up, UART_LCR, up->lcr); 1597 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1598 serial_omap_mdr1_errataset(up, up->mdr1); 1599 else 1600 serial_out(up, UART_OMAP_MDR1, up->mdr1); 1601 } 1602 1603 static int serial_omap_runtime_suspend(struct device *dev) 1604 { 1605 struct uart_omap_port *up = dev_get_drvdata(dev); 1606 struct omap_uart_port_info *pdata = dev->platform_data; 1607 1608 if (!up) 1609 return -EINVAL; 1610 1611 if (!pdata) 1612 return 0; 1613 1614 up->context_loss_cnt = serial_omap_get_context_loss_count(up); 1615 1616 if (device_may_wakeup(dev)) { 1617 if (!up->wakeups_enabled) { 1618 serial_omap_enable_wakeup(up, true); 1619 up->wakeups_enabled = true; 1620 } 1621 } else { 1622 if (up->wakeups_enabled) { 1623 serial_omap_enable_wakeup(up, false); 1624 up->wakeups_enabled = false; 1625 } 1626 } 1627 1628 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1629 schedule_work(&up->qos_work); 1630 1631 return 0; 1632 } 1633 1634 static int serial_omap_runtime_resume(struct device *dev) 1635 { 1636 struct uart_omap_port *up = dev_get_drvdata(dev); 1637 1638 int loss_cnt = serial_omap_get_context_loss_count(up); 1639 1640 if (loss_cnt < 0) { 1641 dev_err(dev, "serial_omap_get_context_loss_count failed : %d\n", 1642 loss_cnt); 1643 serial_omap_restore_context(up); 1644 } else if (up->context_loss_cnt != loss_cnt) { 1645 serial_omap_restore_context(up); 1646 } 1647 up->latency = up->calc_latency; 1648 schedule_work(&up->qos_work); 1649 1650 return 0; 1651 } 1652 #endif 1653 1654 static const struct dev_pm_ops serial_omap_dev_pm_ops = { 1655 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume) 1656 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend, 1657 serial_omap_runtime_resume, NULL) 1658 }; 1659 1660 #if defined(CONFIG_OF) 1661 static const struct of_device_id omap_serial_of_match[] = { 1662 { .compatible = "ti,omap2-uart" }, 1663 { .compatible = "ti,omap3-uart" }, 1664 { .compatible = "ti,omap4-uart" }, 1665 {}, 1666 }; 1667 MODULE_DEVICE_TABLE(of, omap_serial_of_match); 1668 #endif 1669 1670 static struct platform_driver serial_omap_driver = { 1671 .probe = serial_omap_probe, 1672 .remove = serial_omap_remove, 1673 .driver = { 1674 .name = DRIVER_NAME, 1675 .pm = &serial_omap_dev_pm_ops, 1676 .of_match_table = of_match_ptr(omap_serial_of_match), 1677 }, 1678 }; 1679 1680 static int __init serial_omap_init(void) 1681 { 1682 int ret; 1683 1684 ret = uart_register_driver(&serial_omap_reg); 1685 if (ret != 0) 1686 return ret; 1687 ret = platform_driver_register(&serial_omap_driver); 1688 if (ret != 0) 1689 uart_unregister_driver(&serial_omap_reg); 1690 return ret; 1691 } 1692 1693 static void __exit serial_omap_exit(void) 1694 { 1695 platform_driver_unregister(&serial_omap_driver); 1696 uart_unregister_driver(&serial_omap_reg); 1697 } 1698 1699 module_init(serial_omap_init); 1700 module_exit(serial_omap_exit); 1701 1702 MODULE_DESCRIPTION("OMAP High Speed UART driver"); 1703 MODULE_LICENSE("GPL"); 1704 MODULE_AUTHOR("Texas Instruments Inc"); 1705