1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for OMAP-UART controller. 4 * Based on drivers/serial/8250.c 5 * 6 * Copyright (C) 2010 Texas Instruments. 7 * 8 * Authors: 9 * Govindraj R <govindraj.raja@ti.com> 10 * Thara Gopinath <thara@ti.com> 11 * 12 * Note: This driver is made separate from 8250 driver as we cannot 13 * over load 8250 driver with omap platform specific configuration for 14 * features like DMA, it makes easier to implement features like DMA and 15 * hardware flow control and software flow control configuration with 16 * this driver as required for the omap-platform. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/console.h> 22 #include <linux/serial_reg.h> 23 #include <linux/delay.h> 24 #include <linux/slab.h> 25 #include <linux/tty.h> 26 #include <linux/tty_flip.h> 27 #include <linux/platform_device.h> 28 #include <linux/io.h> 29 #include <linux/clk.h> 30 #include <linux/serial_core.h> 31 #include <linux/irq.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/pm_wakeirq.h> 34 #include <linux/of.h> 35 #include <linux/of_irq.h> 36 #include <linux/gpio/consumer.h> 37 #include <linux/platform_data/serial-omap.h> 38 39 #define OMAP_MAX_HSUART_PORTS 10 40 41 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 42 43 #define OMAP_UART_REV_42 0x0402 44 #define OMAP_UART_REV_46 0x0406 45 #define OMAP_UART_REV_52 0x0502 46 #define OMAP_UART_REV_63 0x0603 47 48 #define OMAP_UART_TX_WAKEUP_EN BIT(7) 49 50 /* Feature flags */ 51 #define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0) 52 53 #define UART_ERRATA_i202_MDR1_ACCESS BIT(0) 54 #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1) 55 56 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */ 57 58 /* SCR register bitmasks */ 59 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 60 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 61 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 62 63 /* FCR register bitmasks */ 64 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6) 65 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4) 66 67 /* MVR register bitmasks */ 68 #define OMAP_UART_MVR_SCHEME_SHIFT 30 69 70 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 71 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 72 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 73 74 #define OMAP_UART_MVR_MAJ_MASK 0x700 75 #define OMAP_UART_MVR_MAJ_SHIFT 8 76 #define OMAP_UART_MVR_MIN_MASK 0x3f 77 78 #define OMAP_UART_DMA_CH_FREE -1 79 80 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA 81 #define OMAP_MODE13X_SPEED 230400 82 83 /* WER = 0x7F 84 * Enable module level wakeup in WER reg 85 */ 86 #define OMAP_UART_WER_MOD_WKUP 0x7F 87 88 /* Enable XON/XOFF flow control on output */ 89 #define OMAP_UART_SW_TX 0x08 90 91 /* Enable XON/XOFF flow control on input */ 92 #define OMAP_UART_SW_RX 0x02 93 94 #define OMAP_UART_SW_CLR 0xF0 95 96 #define OMAP_UART_TCR_TRIG 0x0F 97 98 struct uart_omap_dma { 99 u8 uart_dma_tx; 100 u8 uart_dma_rx; 101 int rx_dma_channel; 102 int tx_dma_channel; 103 dma_addr_t rx_buf_dma_phys; 104 dma_addr_t tx_buf_dma_phys; 105 unsigned int uart_base; 106 /* 107 * Buffer for rx dma. It is not required for tx because the buffer 108 * comes from port structure. 109 */ 110 unsigned char *rx_buf; 111 unsigned int prev_rx_dma_pos; 112 int tx_buf_size; 113 int tx_dma_used; 114 int rx_dma_used; 115 spinlock_t tx_lock; 116 spinlock_t rx_lock; 117 /* timer to poll activity on rx dma */ 118 struct timer_list rx_timer; 119 unsigned int rx_buf_size; 120 unsigned int rx_poll_rate; 121 unsigned int rx_timeout; 122 }; 123 124 struct uart_omap_port { 125 struct uart_port port; 126 struct uart_omap_dma uart_dma; 127 struct device *dev; 128 int wakeirq; 129 130 unsigned char ier; 131 unsigned char lcr; 132 unsigned char mcr; 133 unsigned char fcr; 134 unsigned char efr; 135 unsigned char dll; 136 unsigned char dlh; 137 unsigned char mdr1; 138 unsigned char scr; 139 unsigned char wer; 140 141 int use_dma; 142 /* 143 * Some bits in registers are cleared on a read, so they must 144 * be saved whenever the register is read, but the bits will not 145 * be immediately processed. 146 */ 147 unsigned int lsr_break_flag; 148 unsigned char msr_saved_flags; 149 char name[20]; 150 unsigned long port_activity; 151 int context_loss_cnt; 152 u32 errata; 153 u32 features; 154 155 struct gpio_desc *rts_gpiod; 156 157 struct pm_qos_request pm_qos_request; 158 u32 latency; 159 u32 calc_latency; 160 struct work_struct qos_work; 161 bool is_suspending; 162 }; 163 164 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port))) 165 166 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; 167 168 /* Forward declaration of functions */ 169 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1); 170 171 static inline unsigned int serial_in(struct uart_omap_port *up, int offset) 172 { 173 offset <<= up->port.regshift; 174 return readw(up->port.membase + offset); 175 } 176 177 static inline void serial_out(struct uart_omap_port *up, int offset, int value) 178 { 179 offset <<= up->port.regshift; 180 writew(value, up->port.membase + offset); 181 } 182 183 static inline void serial_omap_clear_fifos(struct uart_omap_port *up) 184 { 185 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 186 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 187 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 188 serial_out(up, UART_FCR, 0); 189 } 190 191 #ifdef CONFIG_PM 192 static int serial_omap_get_context_loss_count(struct uart_omap_port *up) 193 { 194 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev); 195 196 if (!pdata || !pdata->get_context_loss_count) 197 return -EINVAL; 198 199 return pdata->get_context_loss_count(up->dev); 200 } 201 202 /* REVISIT: Remove this when omap3 boots in device tree only mode */ 203 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable) 204 { 205 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev); 206 207 if (!pdata || !pdata->enable_wakeup) 208 return; 209 210 pdata->enable_wakeup(up->dev, enable); 211 } 212 #endif /* CONFIG_PM */ 213 214 /* 215 * Calculate the absolute difference between the desired and actual baud 216 * rate for the given mode. 217 */ 218 static inline int calculate_baud_abs_diff(struct uart_port *port, 219 unsigned int baud, unsigned int mode) 220 { 221 unsigned int n = port->uartclk / (mode * baud); 222 int abs_diff; 223 224 if (n == 0) 225 n = 1; 226 227 abs_diff = baud - (port->uartclk / (mode * n)); 228 if (abs_diff < 0) 229 abs_diff = -abs_diff; 230 231 return abs_diff; 232 } 233 234 /* 235 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X 236 * @port: uart port info 237 * @baud: baudrate for which mode needs to be determined 238 * 239 * Returns true if baud rate is MODE16X and false if MODE13X 240 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values, 241 * and Error Rates" determines modes not for all common baud rates. 242 * E.g. for 1000000 baud rate mode must be 16x, but according to that 243 * table it's determined as 13x. 244 */ 245 static bool 246 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud) 247 { 248 int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13); 249 int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16); 250 251 return (abs_diff_13 >= abs_diff_16); 252 } 253 254 /* 255 * serial_omap_get_divisor - calculate divisor value 256 * @port: uart port info 257 * @baud: baudrate for which divisor needs to be calculated. 258 */ 259 static unsigned int 260 serial_omap_get_divisor(struct uart_port *port, unsigned int baud) 261 { 262 unsigned int mode; 263 264 if (!serial_omap_baud_is_mode16(port, baud)) 265 mode = 13; 266 else 267 mode = 16; 268 return port->uartclk/(mode * baud); 269 } 270 271 static void serial_omap_enable_ms(struct uart_port *port) 272 { 273 struct uart_omap_port *up = to_uart_omap_port(port); 274 275 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line); 276 277 pm_runtime_get_sync(up->dev); 278 up->ier |= UART_IER_MSI; 279 serial_out(up, UART_IER, up->ier); 280 pm_runtime_mark_last_busy(up->dev); 281 pm_runtime_put_autosuspend(up->dev); 282 } 283 284 static void serial_omap_stop_tx(struct uart_port *port) 285 { 286 struct uart_omap_port *up = to_uart_omap_port(port); 287 int res; 288 289 pm_runtime_get_sync(up->dev); 290 291 /* Handle RS-485 */ 292 if (port->rs485.flags & SER_RS485_ENABLED) { 293 if (up->scr & OMAP_UART_SCR_TX_EMPTY) { 294 /* THR interrupt is fired when both TX FIFO and TX 295 * shift register are empty. This means there's nothing 296 * left to transmit now, so make sure the THR interrupt 297 * is fired when TX FIFO is below the trigger level, 298 * disable THR interrupts and toggle the RS-485 GPIO 299 * data direction pin if needed. 300 */ 301 up->scr &= ~OMAP_UART_SCR_TX_EMPTY; 302 serial_out(up, UART_OMAP_SCR, up->scr); 303 res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 304 1 : 0; 305 if (up->rts_gpiod && 306 gpiod_get_value(up->rts_gpiod) != res) { 307 if (port->rs485.delay_rts_after_send > 0) 308 mdelay( 309 port->rs485.delay_rts_after_send); 310 gpiod_set_value(up->rts_gpiod, res); 311 } 312 } else { 313 /* We're asked to stop, but there's still stuff in the 314 * UART FIFO, so make sure the THR interrupt is fired 315 * when both TX FIFO and TX shift register are empty. 316 * The next THR interrupt (if no transmission is started 317 * in the meantime) will indicate the end of a 318 * transmission. Therefore we _don't_ disable THR 319 * interrupts in this situation. 320 */ 321 up->scr |= OMAP_UART_SCR_TX_EMPTY; 322 serial_out(up, UART_OMAP_SCR, up->scr); 323 return; 324 } 325 } 326 327 if (up->ier & UART_IER_THRI) { 328 up->ier &= ~UART_IER_THRI; 329 serial_out(up, UART_IER, up->ier); 330 } 331 332 if ((port->rs485.flags & SER_RS485_ENABLED) && 333 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) { 334 /* 335 * Empty the RX FIFO, we are not interested in anything 336 * received during the half-duplex transmission. 337 */ 338 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR); 339 /* Re-enable RX interrupts */ 340 up->ier |= UART_IER_RLSI | UART_IER_RDI; 341 up->port.read_status_mask |= UART_LSR_DR; 342 serial_out(up, UART_IER, up->ier); 343 } 344 345 pm_runtime_mark_last_busy(up->dev); 346 pm_runtime_put_autosuspend(up->dev); 347 } 348 349 static void serial_omap_stop_rx(struct uart_port *port) 350 { 351 struct uart_omap_port *up = to_uart_omap_port(port); 352 353 pm_runtime_get_sync(up->dev); 354 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 355 up->port.read_status_mask &= ~UART_LSR_DR; 356 serial_out(up, UART_IER, up->ier); 357 pm_runtime_mark_last_busy(up->dev); 358 pm_runtime_put_autosuspend(up->dev); 359 } 360 361 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr) 362 { 363 struct circ_buf *xmit = &up->port.state->xmit; 364 int count; 365 366 if (up->port.x_char) { 367 serial_out(up, UART_TX, up->port.x_char); 368 up->port.icount.tx++; 369 up->port.x_char = 0; 370 return; 371 } 372 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 373 serial_omap_stop_tx(&up->port); 374 return; 375 } 376 count = up->port.fifosize / 4; 377 do { 378 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 379 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 380 up->port.icount.tx++; 381 if (uart_circ_empty(xmit)) 382 break; 383 } while (--count > 0); 384 385 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 386 uart_write_wakeup(&up->port); 387 388 if (uart_circ_empty(xmit)) 389 serial_omap_stop_tx(&up->port); 390 } 391 392 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) 393 { 394 if (!(up->ier & UART_IER_THRI)) { 395 up->ier |= UART_IER_THRI; 396 serial_out(up, UART_IER, up->ier); 397 } 398 } 399 400 static void serial_omap_start_tx(struct uart_port *port) 401 { 402 struct uart_omap_port *up = to_uart_omap_port(port); 403 int res; 404 405 pm_runtime_get_sync(up->dev); 406 407 /* Handle RS-485 */ 408 if (port->rs485.flags & SER_RS485_ENABLED) { 409 /* Fire THR interrupts when FIFO is below trigger level */ 410 up->scr &= ~OMAP_UART_SCR_TX_EMPTY; 411 serial_out(up, UART_OMAP_SCR, up->scr); 412 413 /* if rts not already enabled */ 414 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0; 415 if (up->rts_gpiod && gpiod_get_value(up->rts_gpiod) != res) { 416 gpiod_set_value(up->rts_gpiod, res); 417 if (port->rs485.delay_rts_before_send > 0) 418 mdelay(port->rs485.delay_rts_before_send); 419 } 420 } 421 422 if ((port->rs485.flags & SER_RS485_ENABLED) && 423 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) 424 serial_omap_stop_rx(port); 425 426 serial_omap_enable_ier_thri(up); 427 pm_runtime_mark_last_busy(up->dev); 428 pm_runtime_put_autosuspend(up->dev); 429 } 430 431 static void serial_omap_throttle(struct uart_port *port) 432 { 433 struct uart_omap_port *up = to_uart_omap_port(port); 434 unsigned long flags; 435 436 pm_runtime_get_sync(up->dev); 437 spin_lock_irqsave(&up->port.lock, flags); 438 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 439 serial_out(up, UART_IER, up->ier); 440 spin_unlock_irqrestore(&up->port.lock, flags); 441 pm_runtime_mark_last_busy(up->dev); 442 pm_runtime_put_autosuspend(up->dev); 443 } 444 445 static void serial_omap_unthrottle(struct uart_port *port) 446 { 447 struct uart_omap_port *up = to_uart_omap_port(port); 448 unsigned long flags; 449 450 pm_runtime_get_sync(up->dev); 451 spin_lock_irqsave(&up->port.lock, flags); 452 up->ier |= UART_IER_RLSI | UART_IER_RDI; 453 serial_out(up, UART_IER, up->ier); 454 spin_unlock_irqrestore(&up->port.lock, flags); 455 pm_runtime_mark_last_busy(up->dev); 456 pm_runtime_put_autosuspend(up->dev); 457 } 458 459 static unsigned int check_modem_status(struct uart_omap_port *up) 460 { 461 unsigned int status; 462 463 status = serial_in(up, UART_MSR); 464 status |= up->msr_saved_flags; 465 up->msr_saved_flags = 0; 466 if ((status & UART_MSR_ANY_DELTA) == 0) 467 return status; 468 469 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && 470 up->port.state != NULL) { 471 if (status & UART_MSR_TERI) 472 up->port.icount.rng++; 473 if (status & UART_MSR_DDSR) 474 up->port.icount.dsr++; 475 if (status & UART_MSR_DDCD) 476 uart_handle_dcd_change 477 (&up->port, status & UART_MSR_DCD); 478 if (status & UART_MSR_DCTS) 479 uart_handle_cts_change 480 (&up->port, status & UART_MSR_CTS); 481 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 482 } 483 484 return status; 485 } 486 487 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr) 488 { 489 unsigned int flag; 490 491 /* 492 * Read one data character out to avoid stalling the receiver according 493 * to the table 23-246 of the omap4 TRM. 494 */ 495 if (likely(lsr & UART_LSR_DR)) 496 serial_in(up, UART_RX); 497 498 up->port.icount.rx++; 499 flag = TTY_NORMAL; 500 501 if (lsr & UART_LSR_BI) { 502 flag = TTY_BREAK; 503 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 504 up->port.icount.brk++; 505 /* 506 * We do the SysRQ and SAK checking 507 * here because otherwise the break 508 * may get masked by ignore_status_mask 509 * or read_status_mask. 510 */ 511 if (uart_handle_break(&up->port)) 512 return; 513 514 } 515 516 if (lsr & UART_LSR_PE) { 517 flag = TTY_PARITY; 518 up->port.icount.parity++; 519 } 520 521 if (lsr & UART_LSR_FE) { 522 flag = TTY_FRAME; 523 up->port.icount.frame++; 524 } 525 526 if (lsr & UART_LSR_OE) 527 up->port.icount.overrun++; 528 529 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 530 if (up->port.line == up->port.cons->index) { 531 /* Recover the break flag from console xmit */ 532 lsr |= up->lsr_break_flag; 533 } 534 #endif 535 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag); 536 } 537 538 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr) 539 { 540 unsigned char ch = 0; 541 unsigned int flag; 542 543 if (!(lsr & UART_LSR_DR)) 544 return; 545 546 ch = serial_in(up, UART_RX); 547 flag = TTY_NORMAL; 548 up->port.icount.rx++; 549 550 if (uart_handle_sysrq_char(&up->port, ch)) 551 return; 552 553 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); 554 } 555 556 /** 557 * serial_omap_irq() - This handles the interrupt from one port 558 * @irq: uart port irq number 559 * @dev_id: uart port info 560 */ 561 static irqreturn_t serial_omap_irq(int irq, void *dev_id) 562 { 563 struct uart_omap_port *up = dev_id; 564 unsigned int iir, lsr; 565 unsigned int type; 566 irqreturn_t ret = IRQ_NONE; 567 int max_count = 256; 568 569 spin_lock(&up->port.lock); 570 pm_runtime_get_sync(up->dev); 571 572 do { 573 iir = serial_in(up, UART_IIR); 574 if (iir & UART_IIR_NO_INT) 575 break; 576 577 ret = IRQ_HANDLED; 578 lsr = serial_in(up, UART_LSR); 579 580 /* extract IRQ type from IIR register */ 581 type = iir & 0x3e; 582 583 switch (type) { 584 case UART_IIR_MSI: 585 check_modem_status(up); 586 break; 587 case UART_IIR_THRI: 588 transmit_chars(up, lsr); 589 break; 590 case UART_IIR_RX_TIMEOUT: 591 case UART_IIR_RDI: 592 serial_omap_rdi(up, lsr); 593 break; 594 case UART_IIR_RLSI: 595 serial_omap_rlsi(up, lsr); 596 break; 597 case UART_IIR_CTS_RTS_DSR: 598 /* simply try again */ 599 break; 600 case UART_IIR_XOFF: 601 default: 602 break; 603 } 604 } while (max_count--); 605 606 spin_unlock(&up->port.lock); 607 608 tty_flip_buffer_push(&up->port.state->port); 609 610 pm_runtime_mark_last_busy(up->dev); 611 pm_runtime_put_autosuspend(up->dev); 612 up->port_activity = jiffies; 613 614 return ret; 615 } 616 617 static unsigned int serial_omap_tx_empty(struct uart_port *port) 618 { 619 struct uart_omap_port *up = to_uart_omap_port(port); 620 unsigned long flags = 0; 621 unsigned int ret = 0; 622 623 pm_runtime_get_sync(up->dev); 624 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line); 625 spin_lock_irqsave(&up->port.lock, flags); 626 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 627 spin_unlock_irqrestore(&up->port.lock, flags); 628 pm_runtime_mark_last_busy(up->dev); 629 pm_runtime_put_autosuspend(up->dev); 630 return ret; 631 } 632 633 static unsigned int serial_omap_get_mctrl(struct uart_port *port) 634 { 635 struct uart_omap_port *up = to_uart_omap_port(port); 636 unsigned int status; 637 unsigned int ret = 0; 638 639 pm_runtime_get_sync(up->dev); 640 status = check_modem_status(up); 641 pm_runtime_mark_last_busy(up->dev); 642 pm_runtime_put_autosuspend(up->dev); 643 644 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line); 645 646 if (status & UART_MSR_DCD) 647 ret |= TIOCM_CAR; 648 if (status & UART_MSR_RI) 649 ret |= TIOCM_RNG; 650 if (status & UART_MSR_DSR) 651 ret |= TIOCM_DSR; 652 if (status & UART_MSR_CTS) 653 ret |= TIOCM_CTS; 654 return ret; 655 } 656 657 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) 658 { 659 struct uart_omap_port *up = to_uart_omap_port(port); 660 unsigned char mcr = 0, old_mcr, lcr; 661 662 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line); 663 if (mctrl & TIOCM_RTS) 664 mcr |= UART_MCR_RTS; 665 if (mctrl & TIOCM_DTR) 666 mcr |= UART_MCR_DTR; 667 if (mctrl & TIOCM_OUT1) 668 mcr |= UART_MCR_OUT1; 669 if (mctrl & TIOCM_OUT2) 670 mcr |= UART_MCR_OUT2; 671 if (mctrl & TIOCM_LOOP) 672 mcr |= UART_MCR_LOOP; 673 674 pm_runtime_get_sync(up->dev); 675 old_mcr = serial_in(up, UART_MCR); 676 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 | 677 UART_MCR_DTR | UART_MCR_RTS); 678 up->mcr = old_mcr | mcr; 679 serial_out(up, UART_MCR, up->mcr); 680 681 /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */ 682 lcr = serial_in(up, UART_LCR); 683 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 684 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 685 up->efr |= UART_EFR_RTS; 686 else 687 up->efr &= ~UART_EFR_RTS; 688 serial_out(up, UART_EFR, up->efr); 689 serial_out(up, UART_LCR, lcr); 690 691 pm_runtime_mark_last_busy(up->dev); 692 pm_runtime_put_autosuspend(up->dev); 693 } 694 695 static void serial_omap_break_ctl(struct uart_port *port, int break_state) 696 { 697 struct uart_omap_port *up = to_uart_omap_port(port); 698 unsigned long flags = 0; 699 700 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line); 701 pm_runtime_get_sync(up->dev); 702 spin_lock_irqsave(&up->port.lock, flags); 703 if (break_state == -1) 704 up->lcr |= UART_LCR_SBC; 705 else 706 up->lcr &= ~UART_LCR_SBC; 707 serial_out(up, UART_LCR, up->lcr); 708 spin_unlock_irqrestore(&up->port.lock, flags); 709 pm_runtime_mark_last_busy(up->dev); 710 pm_runtime_put_autosuspend(up->dev); 711 } 712 713 static int serial_omap_startup(struct uart_port *port) 714 { 715 struct uart_omap_port *up = to_uart_omap_port(port); 716 unsigned long flags = 0; 717 int retval; 718 719 /* 720 * Allocate the IRQ 721 */ 722 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, 723 up->name, up); 724 if (retval) 725 return retval; 726 727 /* Optional wake-up IRQ */ 728 if (up->wakeirq) { 729 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq); 730 if (retval) { 731 free_irq(up->port.irq, up); 732 return retval; 733 } 734 } 735 736 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line); 737 738 pm_runtime_get_sync(up->dev); 739 /* 740 * Clear the FIFO buffers and disable them. 741 * (they will be reenabled in set_termios()) 742 */ 743 serial_omap_clear_fifos(up); 744 745 /* 746 * Clear the interrupt registers. 747 */ 748 (void) serial_in(up, UART_LSR); 749 if (serial_in(up, UART_LSR) & UART_LSR_DR) 750 (void) serial_in(up, UART_RX); 751 (void) serial_in(up, UART_IIR); 752 (void) serial_in(up, UART_MSR); 753 754 /* 755 * Now, initialize the UART 756 */ 757 serial_out(up, UART_LCR, UART_LCR_WLEN8); 758 spin_lock_irqsave(&up->port.lock, flags); 759 /* 760 * Most PC uarts need OUT2 raised to enable interrupts. 761 */ 762 up->port.mctrl |= TIOCM_OUT2; 763 serial_omap_set_mctrl(&up->port, up->port.mctrl); 764 spin_unlock_irqrestore(&up->port.lock, flags); 765 766 up->msr_saved_flags = 0; 767 /* 768 * Finally, enable interrupts. Note: Modem status interrupts 769 * are set via set_termios(), which will be occurring imminently 770 * anyway, so we don't enable them here. 771 */ 772 up->ier = UART_IER_RLSI | UART_IER_RDI; 773 serial_out(up, UART_IER, up->ier); 774 775 /* Enable module level wake up */ 776 up->wer = OMAP_UART_WER_MOD_WKUP; 777 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP) 778 up->wer |= OMAP_UART_TX_WAKEUP_EN; 779 780 serial_out(up, UART_OMAP_WER, up->wer); 781 782 pm_runtime_mark_last_busy(up->dev); 783 pm_runtime_put_autosuspend(up->dev); 784 up->port_activity = jiffies; 785 return 0; 786 } 787 788 static void serial_omap_shutdown(struct uart_port *port) 789 { 790 struct uart_omap_port *up = to_uart_omap_port(port); 791 unsigned long flags = 0; 792 793 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line); 794 795 pm_runtime_get_sync(up->dev); 796 /* 797 * Disable interrupts from this port 798 */ 799 up->ier = 0; 800 serial_out(up, UART_IER, 0); 801 802 spin_lock_irqsave(&up->port.lock, flags); 803 up->port.mctrl &= ~TIOCM_OUT2; 804 serial_omap_set_mctrl(&up->port, up->port.mctrl); 805 spin_unlock_irqrestore(&up->port.lock, flags); 806 807 /* 808 * Disable break condition and FIFOs 809 */ 810 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); 811 serial_omap_clear_fifos(up); 812 813 /* 814 * Read data port to reset things, and then free the irq 815 */ 816 if (serial_in(up, UART_LSR) & UART_LSR_DR) 817 (void) serial_in(up, UART_RX); 818 819 pm_runtime_mark_last_busy(up->dev); 820 pm_runtime_put_autosuspend(up->dev); 821 free_irq(up->port.irq, up); 822 dev_pm_clear_wake_irq(up->dev); 823 } 824 825 static void serial_omap_uart_qos_work(struct work_struct *work) 826 { 827 struct uart_omap_port *up = container_of(work, struct uart_omap_port, 828 qos_work); 829 830 cpu_latency_qos_update_request(&up->pm_qos_request, up->latency); 831 } 832 833 static void 834 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, 835 struct ktermios *old) 836 { 837 struct uart_omap_port *up = to_uart_omap_port(port); 838 unsigned char cval = 0; 839 unsigned long flags = 0; 840 unsigned int baud, quot; 841 842 switch (termios->c_cflag & CSIZE) { 843 case CS5: 844 cval = UART_LCR_WLEN5; 845 break; 846 case CS6: 847 cval = UART_LCR_WLEN6; 848 break; 849 case CS7: 850 cval = UART_LCR_WLEN7; 851 break; 852 default: 853 case CS8: 854 cval = UART_LCR_WLEN8; 855 break; 856 } 857 858 if (termios->c_cflag & CSTOPB) 859 cval |= UART_LCR_STOP; 860 if (termios->c_cflag & PARENB) 861 cval |= UART_LCR_PARITY; 862 if (!(termios->c_cflag & PARODD)) 863 cval |= UART_LCR_EPAR; 864 if (termios->c_cflag & CMSPAR) 865 cval |= UART_LCR_SPAR; 866 867 /* 868 * Ask the core to calculate the divisor for us. 869 */ 870 871 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); 872 quot = serial_omap_get_divisor(port, baud); 873 874 /* calculate wakeup latency constraint */ 875 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8); 876 up->latency = up->calc_latency; 877 schedule_work(&up->qos_work); 878 879 up->dll = quot & 0xff; 880 up->dlh = quot >> 8; 881 up->mdr1 = UART_OMAP_MDR1_DISABLE; 882 883 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | 884 UART_FCR_ENABLE_FIFO; 885 886 /* 887 * Ok, we're now changing the port state. Do it with 888 * interrupts disabled. 889 */ 890 pm_runtime_get_sync(up->dev); 891 spin_lock_irqsave(&up->port.lock, flags); 892 893 /* 894 * Update the per-port timeout. 895 */ 896 uart_update_timeout(port, termios->c_cflag, baud); 897 898 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 899 if (termios->c_iflag & INPCK) 900 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 901 if (termios->c_iflag & (BRKINT | PARMRK)) 902 up->port.read_status_mask |= UART_LSR_BI; 903 904 /* 905 * Characters to ignore 906 */ 907 up->port.ignore_status_mask = 0; 908 if (termios->c_iflag & IGNPAR) 909 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 910 if (termios->c_iflag & IGNBRK) { 911 up->port.ignore_status_mask |= UART_LSR_BI; 912 /* 913 * If we're ignoring parity and break indicators, 914 * ignore overruns too (for real raw support). 915 */ 916 if (termios->c_iflag & IGNPAR) 917 up->port.ignore_status_mask |= UART_LSR_OE; 918 } 919 920 /* 921 * ignore all characters if CREAD is not set 922 */ 923 if ((termios->c_cflag & CREAD) == 0) 924 up->port.ignore_status_mask |= UART_LSR_DR; 925 926 /* 927 * Modem status interrupts 928 */ 929 up->ier &= ~UART_IER_MSI; 930 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 931 up->ier |= UART_IER_MSI; 932 serial_out(up, UART_IER, up->ier); 933 serial_out(up, UART_LCR, cval); /* reset DLAB */ 934 up->lcr = cval; 935 up->scr = 0; 936 937 /* FIFOs and DMA Settings */ 938 939 /* FCR can be changed only when the 940 * baud clock is not running 941 * DLL_REG and DLH_REG set to 0. 942 */ 943 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 944 serial_out(up, UART_DLL, 0); 945 serial_out(up, UART_DLM, 0); 946 serial_out(up, UART_LCR, 0); 947 948 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 949 950 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB; 951 up->efr &= ~UART_EFR_SCD; 952 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 953 954 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 955 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR; 956 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 957 /* FIFO ENABLE, DMA MODE */ 958 959 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; 960 /* 961 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK 962 * sets Enables the granularity of 1 for TRIGGER RX 963 * level. Along with setting RX FIFO trigger level 964 * to 1 (as noted below, 16 characters) and TLR[3:0] 965 * to zero this will result RX FIFO threshold level 966 * to 1 character, instead of 16 as noted in comment 967 * below. 968 */ 969 970 /* Set receive FIFO threshold to 16 characters and 971 * transmit FIFO threshold to 32 spaces 972 */ 973 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; 974 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK; 975 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 | 976 UART_FCR_ENABLE_FIFO; 977 978 serial_out(up, UART_FCR, up->fcr); 979 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 980 981 serial_out(up, UART_OMAP_SCR, up->scr); 982 983 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */ 984 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 985 serial_out(up, UART_MCR, up->mcr); 986 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 987 serial_out(up, UART_EFR, up->efr); 988 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 989 990 /* Protocol, Baud Rate, and Interrupt Settings */ 991 992 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 993 serial_omap_mdr1_errataset(up, up->mdr1); 994 else 995 serial_out(up, UART_OMAP_MDR1, up->mdr1); 996 997 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 998 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 999 1000 serial_out(up, UART_LCR, 0); 1001 serial_out(up, UART_IER, 0); 1002 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1003 1004 serial_out(up, UART_DLL, up->dll); /* LS of divisor */ 1005 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */ 1006 1007 serial_out(up, UART_LCR, 0); 1008 serial_out(up, UART_IER, up->ier); 1009 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1010 1011 serial_out(up, UART_EFR, up->efr); 1012 serial_out(up, UART_LCR, cval); 1013 1014 if (!serial_omap_baud_is_mode16(port, baud)) 1015 up->mdr1 = UART_OMAP_MDR1_13X_MODE; 1016 else 1017 up->mdr1 = UART_OMAP_MDR1_16X_MODE; 1018 1019 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1020 serial_omap_mdr1_errataset(up, up->mdr1); 1021 else 1022 serial_out(up, UART_OMAP_MDR1, up->mdr1); 1023 1024 /* Configure flow control */ 1025 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1026 1027 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */ 1028 serial_out(up, UART_XON1, termios->c_cc[VSTART]); 1029 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); 1030 1031 /* Enable access to TCR/TLR */ 1032 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 1033 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1034 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 1035 1036 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); 1037 1038 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 1039 1040 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { 1041 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 1042 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1043 up->efr |= UART_EFR_CTS; 1044 } else { 1045 /* Disable AUTORTS and AUTOCTS */ 1046 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS); 1047 } 1048 1049 if (up->port.flags & UPF_SOFT_FLOW) { 1050 /* clear SW control mode bits */ 1051 up->efr &= OMAP_UART_SW_CLR; 1052 1053 /* 1054 * IXON Flag: 1055 * Enable XON/XOFF flow control on input. 1056 * Receiver compares XON1, XOFF1. 1057 */ 1058 if (termios->c_iflag & IXON) 1059 up->efr |= OMAP_UART_SW_RX; 1060 1061 /* 1062 * IXOFF Flag: 1063 * Enable XON/XOFF flow control on output. 1064 * Transmit XON1, XOFF1 1065 */ 1066 if (termios->c_iflag & IXOFF) { 1067 up->port.status |= UPSTAT_AUTOXOFF; 1068 up->efr |= OMAP_UART_SW_TX; 1069 } 1070 1071 /* 1072 * IXANY Flag: 1073 * Enable any character to restart output. 1074 * Operation resumes after receiving any 1075 * character after recognition of the XOFF character 1076 */ 1077 if (termios->c_iflag & IXANY) 1078 up->mcr |= UART_MCR_XONANY; 1079 else 1080 up->mcr &= ~UART_MCR_XONANY; 1081 } 1082 serial_out(up, UART_MCR, up->mcr); 1083 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1084 serial_out(up, UART_EFR, up->efr); 1085 serial_out(up, UART_LCR, up->lcr); 1086 1087 serial_omap_set_mctrl(&up->port, up->port.mctrl); 1088 1089 spin_unlock_irqrestore(&up->port.lock, flags); 1090 pm_runtime_mark_last_busy(up->dev); 1091 pm_runtime_put_autosuspend(up->dev); 1092 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line); 1093 } 1094 1095 static void 1096 serial_omap_pm(struct uart_port *port, unsigned int state, 1097 unsigned int oldstate) 1098 { 1099 struct uart_omap_port *up = to_uart_omap_port(port); 1100 unsigned char efr; 1101 1102 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line); 1103 1104 pm_runtime_get_sync(up->dev); 1105 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1106 efr = serial_in(up, UART_EFR); 1107 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 1108 serial_out(up, UART_LCR, 0); 1109 1110 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 1111 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1112 serial_out(up, UART_EFR, efr); 1113 serial_out(up, UART_LCR, 0); 1114 1115 pm_runtime_mark_last_busy(up->dev); 1116 pm_runtime_put_autosuspend(up->dev); 1117 } 1118 1119 static void serial_omap_release_port(struct uart_port *port) 1120 { 1121 dev_dbg(port->dev, "serial_omap_release_port+\n"); 1122 } 1123 1124 static int serial_omap_request_port(struct uart_port *port) 1125 { 1126 dev_dbg(port->dev, "serial_omap_request_port+\n"); 1127 return 0; 1128 } 1129 1130 static void serial_omap_config_port(struct uart_port *port, int flags) 1131 { 1132 struct uart_omap_port *up = to_uart_omap_port(port); 1133 1134 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", 1135 up->port.line); 1136 up->port.type = PORT_OMAP; 1137 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW; 1138 } 1139 1140 static int 1141 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) 1142 { 1143 /* we don't want the core code to modify any port params */ 1144 dev_dbg(port->dev, "serial_omap_verify_port+\n"); 1145 return -EINVAL; 1146 } 1147 1148 static const char * 1149 serial_omap_type(struct uart_port *port) 1150 { 1151 struct uart_omap_port *up = to_uart_omap_port(port); 1152 1153 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line); 1154 return up->name; 1155 } 1156 1157 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 1158 1159 static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up) 1160 { 1161 unsigned int status, tmout = 10000; 1162 1163 /* Wait up to 10ms for the character(s) to be sent. */ 1164 do { 1165 status = serial_in(up, UART_LSR); 1166 1167 if (status & UART_LSR_BI) 1168 up->lsr_break_flag = UART_LSR_BI; 1169 1170 if (--tmout == 0) 1171 break; 1172 udelay(1); 1173 } while ((status & BOTH_EMPTY) != BOTH_EMPTY); 1174 1175 /* Wait up to 1s for flow control if necessary */ 1176 if (up->port.flags & UPF_CONS_FLOW) { 1177 tmout = 1000000; 1178 for (tmout = 1000000; tmout; tmout--) { 1179 unsigned int msr = serial_in(up, UART_MSR); 1180 1181 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; 1182 if (msr & UART_MSR_CTS) 1183 break; 1184 1185 udelay(1); 1186 } 1187 } 1188 } 1189 1190 #ifdef CONFIG_CONSOLE_POLL 1191 1192 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) 1193 { 1194 struct uart_omap_port *up = to_uart_omap_port(port); 1195 1196 pm_runtime_get_sync(up->dev); 1197 wait_for_xmitr(up); 1198 serial_out(up, UART_TX, ch); 1199 pm_runtime_mark_last_busy(up->dev); 1200 pm_runtime_put_autosuspend(up->dev); 1201 } 1202 1203 static int serial_omap_poll_get_char(struct uart_port *port) 1204 { 1205 struct uart_omap_port *up = to_uart_omap_port(port); 1206 unsigned int status; 1207 1208 pm_runtime_get_sync(up->dev); 1209 status = serial_in(up, UART_LSR); 1210 if (!(status & UART_LSR_DR)) { 1211 status = NO_POLL_CHAR; 1212 goto out; 1213 } 1214 1215 status = serial_in(up, UART_RX); 1216 1217 out: 1218 pm_runtime_mark_last_busy(up->dev); 1219 pm_runtime_put_autosuspend(up->dev); 1220 1221 return status; 1222 } 1223 1224 #endif /* CONFIG_CONSOLE_POLL */ 1225 1226 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 1227 1228 #ifdef CONFIG_SERIAL_EARLYCON 1229 static unsigned int omap_serial_early_in(struct uart_port *port, int offset) 1230 { 1231 offset <<= port->regshift; 1232 return readw(port->membase + offset); 1233 } 1234 1235 static void omap_serial_early_out(struct uart_port *port, int offset, 1236 int value) 1237 { 1238 offset <<= port->regshift; 1239 writew(value, port->membase + offset); 1240 } 1241 1242 static void omap_serial_early_putc(struct uart_port *port, int c) 1243 { 1244 unsigned int status; 1245 1246 for (;;) { 1247 status = omap_serial_early_in(port, UART_LSR); 1248 if ((status & BOTH_EMPTY) == BOTH_EMPTY) 1249 break; 1250 cpu_relax(); 1251 } 1252 omap_serial_early_out(port, UART_TX, c); 1253 } 1254 1255 static void early_omap_serial_write(struct console *console, const char *s, 1256 unsigned int count) 1257 { 1258 struct earlycon_device *device = console->data; 1259 struct uart_port *port = &device->port; 1260 1261 uart_console_write(port, s, count, omap_serial_early_putc); 1262 } 1263 1264 static int __init early_omap_serial_setup(struct earlycon_device *device, 1265 const char *options) 1266 { 1267 struct uart_port *port = &device->port; 1268 1269 if (!(device->port.membase || device->port.iobase)) 1270 return -ENODEV; 1271 1272 port->regshift = 2; 1273 device->con->write = early_omap_serial_write; 1274 return 0; 1275 } 1276 1277 OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup); 1278 OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup); 1279 OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup); 1280 #endif /* CONFIG_SERIAL_EARLYCON */ 1281 1282 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS]; 1283 1284 static struct uart_driver serial_omap_reg; 1285 1286 static void serial_omap_console_putchar(struct uart_port *port, int ch) 1287 { 1288 struct uart_omap_port *up = to_uart_omap_port(port); 1289 1290 wait_for_xmitr(up); 1291 serial_out(up, UART_TX, ch); 1292 } 1293 1294 static void 1295 serial_omap_console_write(struct console *co, const char *s, 1296 unsigned int count) 1297 { 1298 struct uart_omap_port *up = serial_omap_console_ports[co->index]; 1299 unsigned long flags; 1300 unsigned int ier; 1301 int locked = 1; 1302 1303 pm_runtime_get_sync(up->dev); 1304 1305 local_irq_save(flags); 1306 if (up->port.sysrq) 1307 locked = 0; 1308 else if (oops_in_progress) 1309 locked = spin_trylock(&up->port.lock); 1310 else 1311 spin_lock(&up->port.lock); 1312 1313 /* 1314 * First save the IER then disable the interrupts 1315 */ 1316 ier = serial_in(up, UART_IER); 1317 serial_out(up, UART_IER, 0); 1318 1319 uart_console_write(&up->port, s, count, serial_omap_console_putchar); 1320 1321 /* 1322 * Finally, wait for transmitter to become empty 1323 * and restore the IER 1324 */ 1325 wait_for_xmitr(up); 1326 serial_out(up, UART_IER, ier); 1327 /* 1328 * The receive handling will happen properly because the 1329 * receive ready bit will still be set; it is not cleared 1330 * on read. However, modem control will not, we must 1331 * call it if we have saved something in the saved flags 1332 * while processing with interrupts off. 1333 */ 1334 if (up->msr_saved_flags) 1335 check_modem_status(up); 1336 1337 pm_runtime_mark_last_busy(up->dev); 1338 pm_runtime_put_autosuspend(up->dev); 1339 if (locked) 1340 spin_unlock(&up->port.lock); 1341 local_irq_restore(flags); 1342 } 1343 1344 static int __init 1345 serial_omap_console_setup(struct console *co, char *options) 1346 { 1347 struct uart_omap_port *up; 1348 int baud = 115200; 1349 int bits = 8; 1350 int parity = 'n'; 1351 int flow = 'n'; 1352 1353 if (serial_omap_console_ports[co->index] == NULL) 1354 return -ENODEV; 1355 up = serial_omap_console_ports[co->index]; 1356 1357 if (options) 1358 uart_parse_options(options, &baud, &parity, &bits, &flow); 1359 1360 return uart_set_options(&up->port, co, baud, parity, bits, flow); 1361 } 1362 1363 static struct console serial_omap_console = { 1364 .name = OMAP_SERIAL_NAME, 1365 .write = serial_omap_console_write, 1366 .device = uart_console_device, 1367 .setup = serial_omap_console_setup, 1368 .flags = CON_PRINTBUFFER, 1369 .index = -1, 1370 .data = &serial_omap_reg, 1371 }; 1372 1373 static void serial_omap_add_console_port(struct uart_omap_port *up) 1374 { 1375 serial_omap_console_ports[up->port.line] = up; 1376 } 1377 1378 #define OMAP_CONSOLE (&serial_omap_console) 1379 1380 #else 1381 1382 #define OMAP_CONSOLE NULL 1383 1384 static inline void serial_omap_add_console_port(struct uart_omap_port *up) 1385 {} 1386 1387 #endif 1388 1389 /* Enable or disable the rs485 support */ 1390 static int 1391 serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485) 1392 { 1393 struct uart_omap_port *up = to_uart_omap_port(port); 1394 unsigned int mode; 1395 int val; 1396 1397 pm_runtime_get_sync(up->dev); 1398 1399 /* Disable interrupts from this port */ 1400 mode = up->ier; 1401 up->ier = 0; 1402 serial_out(up, UART_IER, 0); 1403 1404 /* Clamp the delays to [0, 100ms] */ 1405 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U); 1406 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U); 1407 1408 /* store new config */ 1409 port->rs485 = *rs485; 1410 1411 if (up->rts_gpiod) { 1412 /* enable / disable rts */ 1413 val = (port->rs485.flags & SER_RS485_ENABLED) ? 1414 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND; 1415 val = (port->rs485.flags & val) ? 1 : 0; 1416 gpiod_set_value(up->rts_gpiod, val); 1417 } 1418 1419 /* Enable interrupts */ 1420 up->ier = mode; 1421 serial_out(up, UART_IER, up->ier); 1422 1423 /* If RS-485 is disabled, make sure the THR interrupt is fired when 1424 * TX FIFO is below the trigger level. 1425 */ 1426 if (!(port->rs485.flags & SER_RS485_ENABLED) && 1427 (up->scr & OMAP_UART_SCR_TX_EMPTY)) { 1428 up->scr &= ~OMAP_UART_SCR_TX_EMPTY; 1429 serial_out(up, UART_OMAP_SCR, up->scr); 1430 } 1431 1432 pm_runtime_mark_last_busy(up->dev); 1433 pm_runtime_put_autosuspend(up->dev); 1434 1435 return 0; 1436 } 1437 1438 static const struct uart_ops serial_omap_pops = { 1439 .tx_empty = serial_omap_tx_empty, 1440 .set_mctrl = serial_omap_set_mctrl, 1441 .get_mctrl = serial_omap_get_mctrl, 1442 .stop_tx = serial_omap_stop_tx, 1443 .start_tx = serial_omap_start_tx, 1444 .throttle = serial_omap_throttle, 1445 .unthrottle = serial_omap_unthrottle, 1446 .stop_rx = serial_omap_stop_rx, 1447 .enable_ms = serial_omap_enable_ms, 1448 .break_ctl = serial_omap_break_ctl, 1449 .startup = serial_omap_startup, 1450 .shutdown = serial_omap_shutdown, 1451 .set_termios = serial_omap_set_termios, 1452 .pm = serial_omap_pm, 1453 .type = serial_omap_type, 1454 .release_port = serial_omap_release_port, 1455 .request_port = serial_omap_request_port, 1456 .config_port = serial_omap_config_port, 1457 .verify_port = serial_omap_verify_port, 1458 #ifdef CONFIG_CONSOLE_POLL 1459 .poll_put_char = serial_omap_poll_put_char, 1460 .poll_get_char = serial_omap_poll_get_char, 1461 #endif 1462 }; 1463 1464 static struct uart_driver serial_omap_reg = { 1465 .owner = THIS_MODULE, 1466 .driver_name = "OMAP-SERIAL", 1467 .dev_name = OMAP_SERIAL_NAME, 1468 .nr = OMAP_MAX_HSUART_PORTS, 1469 .cons = OMAP_CONSOLE, 1470 }; 1471 1472 #ifdef CONFIG_PM_SLEEP 1473 static int serial_omap_prepare(struct device *dev) 1474 { 1475 struct uart_omap_port *up = dev_get_drvdata(dev); 1476 1477 up->is_suspending = true; 1478 1479 return 0; 1480 } 1481 1482 static void serial_omap_complete(struct device *dev) 1483 { 1484 struct uart_omap_port *up = dev_get_drvdata(dev); 1485 1486 up->is_suspending = false; 1487 } 1488 1489 static int serial_omap_suspend(struct device *dev) 1490 { 1491 struct uart_omap_port *up = dev_get_drvdata(dev); 1492 1493 uart_suspend_port(&serial_omap_reg, &up->port); 1494 flush_work(&up->qos_work); 1495 1496 if (device_may_wakeup(dev)) 1497 serial_omap_enable_wakeup(up, true); 1498 else 1499 serial_omap_enable_wakeup(up, false); 1500 1501 return 0; 1502 } 1503 1504 static int serial_omap_resume(struct device *dev) 1505 { 1506 struct uart_omap_port *up = dev_get_drvdata(dev); 1507 1508 if (device_may_wakeup(dev)) 1509 serial_omap_enable_wakeup(up, false); 1510 1511 uart_resume_port(&serial_omap_reg, &up->port); 1512 1513 return 0; 1514 } 1515 #else 1516 #define serial_omap_prepare NULL 1517 #define serial_omap_complete NULL 1518 #endif /* CONFIG_PM_SLEEP */ 1519 1520 static void omap_serial_fill_features_erratas(struct uart_omap_port *up) 1521 { 1522 u32 mvr, scheme; 1523 u16 revision, major, minor; 1524 1525 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift)); 1526 1527 /* Check revision register scheme */ 1528 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 1529 1530 switch (scheme) { 1531 case 0: /* Legacy Scheme: OMAP2/3 */ 1532 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 1533 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 1534 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 1535 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 1536 break; 1537 case 1: 1538 /* New Scheme: OMAP4+ */ 1539 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 1540 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 1541 OMAP_UART_MVR_MAJ_SHIFT; 1542 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 1543 break; 1544 default: 1545 dev_warn(up->dev, 1546 "Unknown %s revision, defaulting to highest\n", 1547 up->name); 1548 /* highest possible revision */ 1549 major = 0xff; 1550 minor = 0xff; 1551 } 1552 1553 /* normalize revision for the driver */ 1554 revision = UART_BUILD_REVISION(major, minor); 1555 1556 switch (revision) { 1557 case OMAP_UART_REV_46: 1558 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1559 UART_ERRATA_i291_DMA_FORCEIDLE); 1560 break; 1561 case OMAP_UART_REV_52: 1562 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1563 UART_ERRATA_i291_DMA_FORCEIDLE); 1564 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP; 1565 break; 1566 case OMAP_UART_REV_63: 1567 up->errata |= UART_ERRATA_i202_MDR1_ACCESS; 1568 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP; 1569 break; 1570 default: 1571 break; 1572 } 1573 } 1574 1575 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev) 1576 { 1577 struct omap_uart_port_info *omap_up_info; 1578 1579 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL); 1580 if (!omap_up_info) 1581 return NULL; /* out of memory */ 1582 1583 of_property_read_u32(dev->of_node, "clock-frequency", 1584 &omap_up_info->uartclk); 1585 1586 omap_up_info->flags = UPF_BOOT_AUTOCONF; 1587 1588 return omap_up_info; 1589 } 1590 1591 static int serial_omap_probe_rs485(struct uart_omap_port *up, 1592 struct device *dev) 1593 { 1594 struct serial_rs485 *rs485conf = &up->port.rs485; 1595 struct device_node *np = dev->of_node; 1596 enum gpiod_flags gflags; 1597 int ret; 1598 1599 rs485conf->flags = 0; 1600 up->rts_gpiod = NULL; 1601 1602 if (!np) 1603 return 0; 1604 1605 ret = uart_get_rs485_mode(&up->port); 1606 if (ret) 1607 return ret; 1608 1609 if (of_property_read_bool(np, "rs485-rts-active-high")) { 1610 rs485conf->flags |= SER_RS485_RTS_ON_SEND; 1611 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 1612 } else { 1613 rs485conf->flags &= ~SER_RS485_RTS_ON_SEND; 1614 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 1615 } 1616 1617 /* check for tx enable gpio */ 1618 gflags = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ? 1619 GPIOD_OUT_HIGH : GPIOD_OUT_LOW; 1620 up->rts_gpiod = devm_gpiod_get_optional(dev, "rts", gflags); 1621 if (IS_ERR(up->rts_gpiod)) { 1622 ret = PTR_ERR(up->rts_gpiod); 1623 if (ret == -EPROBE_DEFER) 1624 return ret; 1625 /* 1626 * FIXME: the code historically ignored any other error than 1627 * -EPROBE_DEFER and just went on without GPIO. 1628 */ 1629 up->rts_gpiod = NULL; 1630 } else { 1631 gpiod_set_consumer_name(up->rts_gpiod, "omap-serial"); 1632 } 1633 1634 return 0; 1635 } 1636 1637 static int serial_omap_probe(struct platform_device *pdev) 1638 { 1639 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev); 1640 struct uart_omap_port *up; 1641 struct resource *mem; 1642 void __iomem *base; 1643 int uartirq = 0; 1644 int wakeirq = 0; 1645 int ret; 1646 1647 /* The optional wakeirq may be specified in the board dts file */ 1648 if (pdev->dev.of_node) { 1649 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1650 if (!uartirq) 1651 return -EPROBE_DEFER; 1652 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1); 1653 omap_up_info = of_get_uart_port_info(&pdev->dev); 1654 pdev->dev.platform_data = omap_up_info; 1655 } else { 1656 uartirq = platform_get_irq(pdev, 0); 1657 if (uartirq < 0) 1658 return -EPROBE_DEFER; 1659 } 1660 1661 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL); 1662 if (!up) 1663 return -ENOMEM; 1664 1665 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1666 base = devm_ioremap_resource(&pdev->dev, mem); 1667 if (IS_ERR(base)) 1668 return PTR_ERR(base); 1669 1670 up->dev = &pdev->dev; 1671 up->port.dev = &pdev->dev; 1672 up->port.type = PORT_OMAP; 1673 up->port.iotype = UPIO_MEM; 1674 up->port.irq = uartirq; 1675 up->port.regshift = 2; 1676 up->port.fifosize = 64; 1677 up->port.ops = &serial_omap_pops; 1678 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_OMAP_CONSOLE); 1679 1680 if (pdev->dev.of_node) 1681 ret = of_alias_get_id(pdev->dev.of_node, "serial"); 1682 else 1683 ret = pdev->id; 1684 1685 if (ret < 0) { 1686 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", 1687 ret); 1688 goto err_port_line; 1689 } 1690 up->port.line = ret; 1691 1692 if (up->port.line >= OMAP_MAX_HSUART_PORTS) { 1693 dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line, 1694 OMAP_MAX_HSUART_PORTS); 1695 ret = -ENXIO; 1696 goto err_port_line; 1697 } 1698 1699 up->wakeirq = wakeirq; 1700 if (!up->wakeirq) 1701 dev_info(up->port.dev, "no wakeirq for uart%d\n", 1702 up->port.line); 1703 1704 ret = serial_omap_probe_rs485(up, &pdev->dev); 1705 if (ret < 0) 1706 goto err_rs485; 1707 1708 sprintf(up->name, "OMAP UART%d", up->port.line); 1709 up->port.mapbase = mem->start; 1710 up->port.membase = base; 1711 up->port.flags = omap_up_info->flags; 1712 up->port.uartclk = omap_up_info->uartclk; 1713 up->port.rs485_config = serial_omap_config_rs485; 1714 if (!up->port.uartclk) { 1715 up->port.uartclk = DEFAULT_CLK_SPEED; 1716 dev_warn(&pdev->dev, 1717 "No clock speed specified: using default: %d\n", 1718 DEFAULT_CLK_SPEED); 1719 } 1720 1721 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1722 up->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1723 cpu_latency_qos_add_request(&up->pm_qos_request, up->latency); 1724 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); 1725 1726 platform_set_drvdata(pdev, up); 1727 if (omap_up_info->autosuspend_timeout == 0) 1728 omap_up_info->autosuspend_timeout = -1; 1729 1730 device_init_wakeup(up->dev, true); 1731 pm_runtime_use_autosuspend(&pdev->dev); 1732 pm_runtime_set_autosuspend_delay(&pdev->dev, 1733 omap_up_info->autosuspend_timeout); 1734 1735 pm_runtime_irq_safe(&pdev->dev); 1736 pm_runtime_enable(&pdev->dev); 1737 1738 pm_runtime_get_sync(&pdev->dev); 1739 1740 omap_serial_fill_features_erratas(up); 1741 1742 ui[up->port.line] = up; 1743 serial_omap_add_console_port(up); 1744 1745 ret = uart_add_one_port(&serial_omap_reg, &up->port); 1746 if (ret != 0) 1747 goto err_add_port; 1748 1749 pm_runtime_mark_last_busy(up->dev); 1750 pm_runtime_put_autosuspend(up->dev); 1751 return 0; 1752 1753 err_add_port: 1754 pm_runtime_dont_use_autosuspend(&pdev->dev); 1755 pm_runtime_put_sync(&pdev->dev); 1756 pm_runtime_disable(&pdev->dev); 1757 cpu_latency_qos_remove_request(&up->pm_qos_request); 1758 device_init_wakeup(up->dev, false); 1759 err_rs485: 1760 err_port_line: 1761 return ret; 1762 } 1763 1764 static int serial_omap_remove(struct platform_device *dev) 1765 { 1766 struct uart_omap_port *up = platform_get_drvdata(dev); 1767 1768 pm_runtime_get_sync(up->dev); 1769 1770 uart_remove_one_port(&serial_omap_reg, &up->port); 1771 1772 pm_runtime_dont_use_autosuspend(up->dev); 1773 pm_runtime_put_sync(up->dev); 1774 pm_runtime_disable(up->dev); 1775 cpu_latency_qos_remove_request(&up->pm_qos_request); 1776 device_init_wakeup(&dev->dev, false); 1777 1778 return 0; 1779 } 1780 1781 /* 1782 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 1783 * The access to uart register after MDR1 Access 1784 * causes UART to corrupt data. 1785 * 1786 * Need a delay = 1787 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 1788 * give 10 times as much 1789 */ 1790 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1) 1791 { 1792 u8 timeout = 255; 1793 1794 serial_out(up, UART_OMAP_MDR1, mdr1); 1795 udelay(2); 1796 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 1797 UART_FCR_CLEAR_RCVR); 1798 /* 1799 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 1800 * TX_FIFO_E bit is 1. 1801 */ 1802 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 1803 (UART_LSR_THRE | UART_LSR_DR))) { 1804 timeout--; 1805 if (!timeout) { 1806 /* Should *never* happen. we warn and carry on */ 1807 dev_crit(up->dev, "Errata i202: timedout %x\n", 1808 serial_in(up, UART_LSR)); 1809 break; 1810 } 1811 udelay(1); 1812 } 1813 } 1814 1815 #ifdef CONFIG_PM 1816 static void serial_omap_restore_context(struct uart_omap_port *up) 1817 { 1818 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1819 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE); 1820 else 1821 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); 1822 1823 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1824 serial_out(up, UART_EFR, UART_EFR_ECB); 1825 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1826 serial_out(up, UART_IER, 0x0); 1827 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1828 serial_out(up, UART_DLL, up->dll); 1829 serial_out(up, UART_DLM, up->dlh); 1830 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1831 serial_out(up, UART_IER, up->ier); 1832 serial_out(up, UART_FCR, up->fcr); 1833 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1834 serial_out(up, UART_MCR, up->mcr); 1835 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1836 serial_out(up, UART_OMAP_SCR, up->scr); 1837 serial_out(up, UART_EFR, up->efr); 1838 serial_out(up, UART_LCR, up->lcr); 1839 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1840 serial_omap_mdr1_errataset(up, up->mdr1); 1841 else 1842 serial_out(up, UART_OMAP_MDR1, up->mdr1); 1843 serial_out(up, UART_OMAP_WER, up->wer); 1844 } 1845 1846 static int serial_omap_runtime_suspend(struct device *dev) 1847 { 1848 struct uart_omap_port *up = dev_get_drvdata(dev); 1849 1850 if (!up) 1851 return -EINVAL; 1852 1853 /* 1854 * When using 'no_console_suspend', the console UART must not be 1855 * suspended. Since driver suspend is managed by runtime suspend, 1856 * preventing runtime suspend (by returning error) will keep device 1857 * active during suspend. 1858 */ 1859 if (up->is_suspending && !console_suspend_enabled && 1860 uart_console(&up->port)) 1861 return -EBUSY; 1862 1863 up->context_loss_cnt = serial_omap_get_context_loss_count(up); 1864 1865 serial_omap_enable_wakeup(up, true); 1866 1867 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1868 schedule_work(&up->qos_work); 1869 1870 return 0; 1871 } 1872 1873 static int serial_omap_runtime_resume(struct device *dev) 1874 { 1875 struct uart_omap_port *up = dev_get_drvdata(dev); 1876 1877 int loss_cnt = serial_omap_get_context_loss_count(up); 1878 1879 serial_omap_enable_wakeup(up, false); 1880 1881 if (loss_cnt < 0) { 1882 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n", 1883 loss_cnt); 1884 serial_omap_restore_context(up); 1885 } else if (up->context_loss_cnt != loss_cnt) { 1886 serial_omap_restore_context(up); 1887 } 1888 up->latency = up->calc_latency; 1889 schedule_work(&up->qos_work); 1890 1891 return 0; 1892 } 1893 #endif 1894 1895 static const struct dev_pm_ops serial_omap_dev_pm_ops = { 1896 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume) 1897 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend, 1898 serial_omap_runtime_resume, NULL) 1899 .prepare = serial_omap_prepare, 1900 .complete = serial_omap_complete, 1901 }; 1902 1903 #if defined(CONFIG_OF) 1904 static const struct of_device_id omap_serial_of_match[] = { 1905 { .compatible = "ti,omap2-uart" }, 1906 { .compatible = "ti,omap3-uart" }, 1907 { .compatible = "ti,omap4-uart" }, 1908 {}, 1909 }; 1910 MODULE_DEVICE_TABLE(of, omap_serial_of_match); 1911 #endif 1912 1913 static struct platform_driver serial_omap_driver = { 1914 .probe = serial_omap_probe, 1915 .remove = serial_omap_remove, 1916 .driver = { 1917 .name = OMAP_SERIAL_DRIVER_NAME, 1918 .pm = &serial_omap_dev_pm_ops, 1919 .of_match_table = of_match_ptr(omap_serial_of_match), 1920 }, 1921 }; 1922 1923 static int __init serial_omap_init(void) 1924 { 1925 int ret; 1926 1927 ret = uart_register_driver(&serial_omap_reg); 1928 if (ret != 0) 1929 return ret; 1930 ret = platform_driver_register(&serial_omap_driver); 1931 if (ret != 0) 1932 uart_unregister_driver(&serial_omap_reg); 1933 return ret; 1934 } 1935 1936 static void __exit serial_omap_exit(void) 1937 { 1938 platform_driver_unregister(&serial_omap_driver); 1939 uart_unregister_driver(&serial_omap_reg); 1940 } 1941 1942 module_init(serial_omap_init); 1943 module_exit(serial_omap_exit); 1944 1945 MODULE_DESCRIPTION("OMAP High Speed UART driver"); 1946 MODULE_LICENSE("GPL"); 1947 MODULE_AUTHOR("Texas Instruments Inc"); 1948