1 /* 2 * Driver for OMAP-UART controller. 3 * Based on drivers/serial/8250.c 4 * 5 * Copyright (C) 2010 Texas Instruments. 6 * 7 * Authors: 8 * Govindraj R <govindraj.raja@ti.com> 9 * Thara Gopinath <thara@ti.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * Note: This driver is made separate from 8250 driver as we cannot 17 * over load 8250 driver with omap platform specific configuration for 18 * features like DMA, it makes easier to implement features like DMA and 19 * hardware flow control and software flow control configuration with 20 * this driver as required for the omap-platform. 21 */ 22 23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 24 #define SUPPORT_SYSRQ 25 #endif 26 27 #include <linux/module.h> 28 #include <linux/init.h> 29 #include <linux/console.h> 30 #include <linux/serial_reg.h> 31 #include <linux/delay.h> 32 #include <linux/slab.h> 33 #include <linux/tty.h> 34 #include <linux/tty_flip.h> 35 #include <linux/io.h> 36 #include <linux/dma-mapping.h> 37 #include <linux/clk.h> 38 #include <linux/serial_core.h> 39 #include <linux/irq.h> 40 #include <linux/pm_runtime.h> 41 42 #include <plat/dma.h> 43 #include <plat/dmtimer.h> 44 #include <plat/omap-serial.h> 45 46 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; 47 48 /* Forward declaration of functions */ 49 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data); 50 static void serial_omap_rxdma_poll(unsigned long uart_no); 51 static int serial_omap_start_rxdma(struct uart_omap_port *up); 52 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1); 53 54 static struct workqueue_struct *serial_omap_uart_wq; 55 56 static inline unsigned int serial_in(struct uart_omap_port *up, int offset) 57 { 58 offset <<= up->port.regshift; 59 return readw(up->port.membase + offset); 60 } 61 62 static inline void serial_out(struct uart_omap_port *up, int offset, int value) 63 { 64 offset <<= up->port.regshift; 65 writew(value, up->port.membase + offset); 66 } 67 68 static inline void serial_omap_clear_fifos(struct uart_omap_port *up) 69 { 70 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 71 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 72 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 73 serial_out(up, UART_FCR, 0); 74 } 75 76 /* 77 * serial_omap_get_divisor - calculate divisor value 78 * @port: uart port info 79 * @baud: baudrate for which divisor needs to be calculated. 80 * 81 * We have written our own function to get the divisor so as to support 82 * 13x mode. 3Mbps Baudrate as an different divisor. 83 * Reference OMAP TRM Chapter 17: 84 * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates 85 * referring to oversampling - divisor value 86 * baudrate 460,800 to 3,686,400 all have divisor 13 87 * except 3,000,000 which has divisor value 16 88 */ 89 static unsigned int 90 serial_omap_get_divisor(struct uart_port *port, unsigned int baud) 91 { 92 unsigned int divisor; 93 94 if (baud > OMAP_MODE13X_SPEED && baud != 3000000) 95 divisor = 13; 96 else 97 divisor = 16; 98 return port->uartclk/(baud * divisor); 99 } 100 101 static void serial_omap_stop_rxdma(struct uart_omap_port *up) 102 { 103 if (up->uart_dma.rx_dma_used) { 104 del_timer(&up->uart_dma.rx_timer); 105 omap_stop_dma(up->uart_dma.rx_dma_channel); 106 omap_free_dma(up->uart_dma.rx_dma_channel); 107 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE; 108 up->uart_dma.rx_dma_used = false; 109 pm_runtime_mark_last_busy(&up->pdev->dev); 110 pm_runtime_put_autosuspend(&up->pdev->dev); 111 } 112 } 113 114 static void serial_omap_enable_ms(struct uart_port *port) 115 { 116 struct uart_omap_port *up = (struct uart_omap_port *)port; 117 118 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->pdev->id); 119 120 pm_runtime_get_sync(&up->pdev->dev); 121 up->ier |= UART_IER_MSI; 122 serial_out(up, UART_IER, up->ier); 123 pm_runtime_put(&up->pdev->dev); 124 } 125 126 static void serial_omap_stop_tx(struct uart_port *port) 127 { 128 struct uart_omap_port *up = (struct uart_omap_port *)port; 129 130 if (up->use_dma && 131 up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) { 132 /* 133 * Check if dma is still active. If yes do nothing, 134 * return. Else stop dma 135 */ 136 if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel)) 137 return; 138 omap_stop_dma(up->uart_dma.tx_dma_channel); 139 omap_free_dma(up->uart_dma.tx_dma_channel); 140 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE; 141 pm_runtime_mark_last_busy(&up->pdev->dev); 142 pm_runtime_put_autosuspend(&up->pdev->dev); 143 } 144 145 pm_runtime_get_sync(&up->pdev->dev); 146 if (up->ier & UART_IER_THRI) { 147 up->ier &= ~UART_IER_THRI; 148 serial_out(up, UART_IER, up->ier); 149 } 150 151 pm_runtime_mark_last_busy(&up->pdev->dev); 152 pm_runtime_put_autosuspend(&up->pdev->dev); 153 } 154 155 static void serial_omap_stop_rx(struct uart_port *port) 156 { 157 struct uart_omap_port *up = (struct uart_omap_port *)port; 158 159 pm_runtime_get_sync(&up->pdev->dev); 160 if (up->use_dma) 161 serial_omap_stop_rxdma(up); 162 up->ier &= ~UART_IER_RLSI; 163 up->port.read_status_mask &= ~UART_LSR_DR; 164 serial_out(up, UART_IER, up->ier); 165 pm_runtime_mark_last_busy(&up->pdev->dev); 166 pm_runtime_put_autosuspend(&up->pdev->dev); 167 } 168 169 static inline void receive_chars(struct uart_omap_port *up, int *status) 170 { 171 struct tty_struct *tty = up->port.state->port.tty; 172 unsigned int flag; 173 unsigned char ch, lsr = *status; 174 int max_count = 256; 175 176 do { 177 if (likely(lsr & UART_LSR_DR)) 178 ch = serial_in(up, UART_RX); 179 flag = TTY_NORMAL; 180 up->port.icount.rx++; 181 182 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { 183 /* 184 * For statistics only 185 */ 186 if (lsr & UART_LSR_BI) { 187 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 188 up->port.icount.brk++; 189 /* 190 * We do the SysRQ and SAK checking 191 * here because otherwise the break 192 * may get masked by ignore_status_mask 193 * or read_status_mask. 194 */ 195 if (uart_handle_break(&up->port)) 196 goto ignore_char; 197 } else if (lsr & UART_LSR_PE) { 198 up->port.icount.parity++; 199 } else if (lsr & UART_LSR_FE) { 200 up->port.icount.frame++; 201 } 202 203 if (lsr & UART_LSR_OE) 204 up->port.icount.overrun++; 205 206 /* 207 * Mask off conditions which should be ignored. 208 */ 209 lsr &= up->port.read_status_mask; 210 211 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 212 if (up->port.line == up->port.cons->index) { 213 /* Recover the break flag from console xmit */ 214 lsr |= up->lsr_break_flag; 215 } 216 #endif 217 if (lsr & UART_LSR_BI) 218 flag = TTY_BREAK; 219 else if (lsr & UART_LSR_PE) 220 flag = TTY_PARITY; 221 else if (lsr & UART_LSR_FE) 222 flag = TTY_FRAME; 223 } 224 225 if (uart_handle_sysrq_char(&up->port, ch)) 226 goto ignore_char; 227 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); 228 ignore_char: 229 lsr = serial_in(up, UART_LSR); 230 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0)); 231 spin_unlock(&up->port.lock); 232 tty_flip_buffer_push(tty); 233 spin_lock(&up->port.lock); 234 } 235 236 static void transmit_chars(struct uart_omap_port *up) 237 { 238 struct circ_buf *xmit = &up->port.state->xmit; 239 int count; 240 241 if (up->port.x_char) { 242 serial_out(up, UART_TX, up->port.x_char); 243 up->port.icount.tx++; 244 up->port.x_char = 0; 245 return; 246 } 247 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 248 serial_omap_stop_tx(&up->port); 249 return; 250 } 251 count = up->port.fifosize / 4; 252 do { 253 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 254 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 255 up->port.icount.tx++; 256 if (uart_circ_empty(xmit)) 257 break; 258 } while (--count > 0); 259 260 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 261 uart_write_wakeup(&up->port); 262 263 if (uart_circ_empty(xmit)) 264 serial_omap_stop_tx(&up->port); 265 } 266 267 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) 268 { 269 if (!(up->ier & UART_IER_THRI)) { 270 up->ier |= UART_IER_THRI; 271 serial_out(up, UART_IER, up->ier); 272 } 273 } 274 275 static void serial_omap_start_tx(struct uart_port *port) 276 { 277 struct uart_omap_port *up = (struct uart_omap_port *)port; 278 struct circ_buf *xmit; 279 unsigned int start; 280 int ret = 0; 281 282 if (!up->use_dma) { 283 pm_runtime_get_sync(&up->pdev->dev); 284 serial_omap_enable_ier_thri(up); 285 pm_runtime_mark_last_busy(&up->pdev->dev); 286 pm_runtime_put_autosuspend(&up->pdev->dev); 287 return; 288 } 289 290 if (up->uart_dma.tx_dma_used) 291 return; 292 293 xmit = &up->port.state->xmit; 294 295 if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) { 296 pm_runtime_get_sync(&up->pdev->dev); 297 ret = omap_request_dma(up->uart_dma.uart_dma_tx, 298 "UART Tx DMA", 299 (void *)uart_tx_dma_callback, up, 300 &(up->uart_dma.tx_dma_channel)); 301 302 if (ret < 0) { 303 serial_omap_enable_ier_thri(up); 304 return; 305 } 306 } 307 spin_lock(&(up->uart_dma.tx_lock)); 308 up->uart_dma.tx_dma_used = true; 309 spin_unlock(&(up->uart_dma.tx_lock)); 310 311 start = up->uart_dma.tx_buf_dma_phys + 312 (xmit->tail & (UART_XMIT_SIZE - 1)); 313 314 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit); 315 /* 316 * It is a circular buffer. See if the buffer has wounded back. 317 * If yes it will have to be transferred in two separate dma 318 * transfers 319 */ 320 if (start + up->uart_dma.tx_buf_size >= 321 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) 322 up->uart_dma.tx_buf_size = 323 (up->uart_dma.tx_buf_dma_phys + 324 UART_XMIT_SIZE) - start; 325 326 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0, 327 OMAP_DMA_AMODE_CONSTANT, 328 up->uart_dma.uart_base, 0, 0); 329 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0, 330 OMAP_DMA_AMODE_POST_INC, start, 0, 0); 331 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel, 332 OMAP_DMA_DATA_TYPE_S8, 333 up->uart_dma.tx_buf_size, 1, 334 OMAP_DMA_SYNC_ELEMENT, 335 up->uart_dma.uart_dma_tx, 0); 336 /* FIXME: Cache maintenance needed here? */ 337 omap_start_dma(up->uart_dma.tx_dma_channel); 338 } 339 340 static unsigned int check_modem_status(struct uart_omap_port *up) 341 { 342 unsigned int status; 343 344 status = serial_in(up, UART_MSR); 345 status |= up->msr_saved_flags; 346 up->msr_saved_flags = 0; 347 if ((status & UART_MSR_ANY_DELTA) == 0) 348 return status; 349 350 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && 351 up->port.state != NULL) { 352 if (status & UART_MSR_TERI) 353 up->port.icount.rng++; 354 if (status & UART_MSR_DDSR) 355 up->port.icount.dsr++; 356 if (status & UART_MSR_DDCD) 357 uart_handle_dcd_change 358 (&up->port, status & UART_MSR_DCD); 359 if (status & UART_MSR_DCTS) 360 uart_handle_cts_change 361 (&up->port, status & UART_MSR_CTS); 362 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 363 } 364 365 return status; 366 } 367 368 /** 369 * serial_omap_irq() - This handles the interrupt from one port 370 * @irq: uart port irq number 371 * @dev_id: uart port info 372 */ 373 static inline irqreturn_t serial_omap_irq(int irq, void *dev_id) 374 { 375 struct uart_omap_port *up = dev_id; 376 unsigned int iir, lsr; 377 unsigned long flags; 378 379 pm_runtime_get_sync(&up->pdev->dev); 380 iir = serial_in(up, UART_IIR); 381 if (iir & UART_IIR_NO_INT) { 382 pm_runtime_mark_last_busy(&up->pdev->dev); 383 pm_runtime_put_autosuspend(&up->pdev->dev); 384 return IRQ_NONE; 385 } 386 387 spin_lock_irqsave(&up->port.lock, flags); 388 lsr = serial_in(up, UART_LSR); 389 if (iir & UART_IIR_RLSI) { 390 if (!up->use_dma) { 391 if (lsr & UART_LSR_DR) 392 receive_chars(up, &lsr); 393 } else { 394 up->ier &= ~(UART_IER_RDI | UART_IER_RLSI); 395 serial_out(up, UART_IER, up->ier); 396 if ((serial_omap_start_rxdma(up) != 0) && 397 (lsr & UART_LSR_DR)) 398 receive_chars(up, &lsr); 399 } 400 } 401 402 check_modem_status(up); 403 if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI)) 404 transmit_chars(up); 405 406 spin_unlock_irqrestore(&up->port.lock, flags); 407 pm_runtime_mark_last_busy(&up->pdev->dev); 408 pm_runtime_put_autosuspend(&up->pdev->dev); 409 410 up->port_activity = jiffies; 411 return IRQ_HANDLED; 412 } 413 414 static unsigned int serial_omap_tx_empty(struct uart_port *port) 415 { 416 struct uart_omap_port *up = (struct uart_omap_port *)port; 417 unsigned long flags = 0; 418 unsigned int ret = 0; 419 420 pm_runtime_get_sync(&up->pdev->dev); 421 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->pdev->id); 422 spin_lock_irqsave(&up->port.lock, flags); 423 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 424 spin_unlock_irqrestore(&up->port.lock, flags); 425 pm_runtime_put(&up->pdev->dev); 426 return ret; 427 } 428 429 static unsigned int serial_omap_get_mctrl(struct uart_port *port) 430 { 431 struct uart_omap_port *up = (struct uart_omap_port *)port; 432 unsigned char status; 433 unsigned int ret = 0; 434 435 pm_runtime_get_sync(&up->pdev->dev); 436 status = check_modem_status(up); 437 pm_runtime_put(&up->pdev->dev); 438 439 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->pdev->id); 440 441 if (status & UART_MSR_DCD) 442 ret |= TIOCM_CAR; 443 if (status & UART_MSR_RI) 444 ret |= TIOCM_RNG; 445 if (status & UART_MSR_DSR) 446 ret |= TIOCM_DSR; 447 if (status & UART_MSR_CTS) 448 ret |= TIOCM_CTS; 449 return ret; 450 } 451 452 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) 453 { 454 struct uart_omap_port *up = (struct uart_omap_port *)port; 455 unsigned char mcr = 0; 456 457 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->pdev->id); 458 if (mctrl & TIOCM_RTS) 459 mcr |= UART_MCR_RTS; 460 if (mctrl & TIOCM_DTR) 461 mcr |= UART_MCR_DTR; 462 if (mctrl & TIOCM_OUT1) 463 mcr |= UART_MCR_OUT1; 464 if (mctrl & TIOCM_OUT2) 465 mcr |= UART_MCR_OUT2; 466 if (mctrl & TIOCM_LOOP) 467 mcr |= UART_MCR_LOOP; 468 469 pm_runtime_get_sync(&up->pdev->dev); 470 up->mcr = serial_in(up, UART_MCR); 471 up->mcr |= mcr; 472 serial_out(up, UART_MCR, up->mcr); 473 pm_runtime_put(&up->pdev->dev); 474 } 475 476 static void serial_omap_break_ctl(struct uart_port *port, int break_state) 477 { 478 struct uart_omap_port *up = (struct uart_omap_port *)port; 479 unsigned long flags = 0; 480 481 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->pdev->id); 482 pm_runtime_get_sync(&up->pdev->dev); 483 spin_lock_irqsave(&up->port.lock, flags); 484 if (break_state == -1) 485 up->lcr |= UART_LCR_SBC; 486 else 487 up->lcr &= ~UART_LCR_SBC; 488 serial_out(up, UART_LCR, up->lcr); 489 spin_unlock_irqrestore(&up->port.lock, flags); 490 pm_runtime_put(&up->pdev->dev); 491 } 492 493 static int serial_omap_startup(struct uart_port *port) 494 { 495 struct uart_omap_port *up = (struct uart_omap_port *)port; 496 unsigned long flags = 0; 497 int retval; 498 499 /* 500 * Allocate the IRQ 501 */ 502 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, 503 up->name, up); 504 if (retval) 505 return retval; 506 507 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->pdev->id); 508 509 pm_runtime_get_sync(&up->pdev->dev); 510 /* 511 * Clear the FIFO buffers and disable them. 512 * (they will be reenabled in set_termios()) 513 */ 514 serial_omap_clear_fifos(up); 515 /* For Hardware flow control */ 516 serial_out(up, UART_MCR, UART_MCR_RTS); 517 518 /* 519 * Clear the interrupt registers. 520 */ 521 (void) serial_in(up, UART_LSR); 522 if (serial_in(up, UART_LSR) & UART_LSR_DR) 523 (void) serial_in(up, UART_RX); 524 (void) serial_in(up, UART_IIR); 525 (void) serial_in(up, UART_MSR); 526 527 /* 528 * Now, initialize the UART 529 */ 530 serial_out(up, UART_LCR, UART_LCR_WLEN8); 531 spin_lock_irqsave(&up->port.lock, flags); 532 /* 533 * Most PC uarts need OUT2 raised to enable interrupts. 534 */ 535 up->port.mctrl |= TIOCM_OUT2; 536 serial_omap_set_mctrl(&up->port, up->port.mctrl); 537 spin_unlock_irqrestore(&up->port.lock, flags); 538 539 up->msr_saved_flags = 0; 540 if (up->use_dma) { 541 free_page((unsigned long)up->port.state->xmit.buf); 542 up->port.state->xmit.buf = dma_alloc_coherent(NULL, 543 UART_XMIT_SIZE, 544 (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys), 545 0); 546 init_timer(&(up->uart_dma.rx_timer)); 547 up->uart_dma.rx_timer.function = serial_omap_rxdma_poll; 548 up->uart_dma.rx_timer.data = up->pdev->id; 549 /* Currently the buffer size is 4KB. Can increase it */ 550 up->uart_dma.rx_buf = dma_alloc_coherent(NULL, 551 up->uart_dma.rx_buf_size, 552 (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0); 553 } 554 /* 555 * Finally, enable interrupts. Note: Modem status interrupts 556 * are set via set_termios(), which will be occurring imminently 557 * anyway, so we don't enable them here. 558 */ 559 up->ier = UART_IER_RLSI | UART_IER_RDI; 560 serial_out(up, UART_IER, up->ier); 561 562 /* Enable module level wake up */ 563 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP); 564 565 pm_runtime_mark_last_busy(&up->pdev->dev); 566 pm_runtime_put_autosuspend(&up->pdev->dev); 567 up->port_activity = jiffies; 568 return 0; 569 } 570 571 static void serial_omap_shutdown(struct uart_port *port) 572 { 573 struct uart_omap_port *up = (struct uart_omap_port *)port; 574 unsigned long flags = 0; 575 576 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->pdev->id); 577 578 pm_runtime_get_sync(&up->pdev->dev); 579 /* 580 * Disable interrupts from this port 581 */ 582 up->ier = 0; 583 serial_out(up, UART_IER, 0); 584 585 spin_lock_irqsave(&up->port.lock, flags); 586 up->port.mctrl &= ~TIOCM_OUT2; 587 serial_omap_set_mctrl(&up->port, up->port.mctrl); 588 spin_unlock_irqrestore(&up->port.lock, flags); 589 590 /* 591 * Disable break condition and FIFOs 592 */ 593 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); 594 serial_omap_clear_fifos(up); 595 596 /* 597 * Read data port to reset things, and then free the irq 598 */ 599 if (serial_in(up, UART_LSR) & UART_LSR_DR) 600 (void) serial_in(up, UART_RX); 601 if (up->use_dma) { 602 dma_free_coherent(up->port.dev, 603 UART_XMIT_SIZE, up->port.state->xmit.buf, 604 up->uart_dma.tx_buf_dma_phys); 605 up->port.state->xmit.buf = NULL; 606 serial_omap_stop_rx(port); 607 dma_free_coherent(up->port.dev, 608 up->uart_dma.rx_buf_size, up->uart_dma.rx_buf, 609 up->uart_dma.rx_buf_dma_phys); 610 up->uart_dma.rx_buf = NULL; 611 } 612 613 pm_runtime_put(&up->pdev->dev); 614 free_irq(up->port.irq, up); 615 } 616 617 static inline void 618 serial_omap_configure_xonxoff 619 (struct uart_omap_port *up, struct ktermios *termios) 620 { 621 up->lcr = serial_in(up, UART_LCR); 622 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 623 up->efr = serial_in(up, UART_EFR); 624 serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB); 625 626 serial_out(up, UART_XON1, termios->c_cc[VSTART]); 627 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); 628 629 /* clear SW control mode bits */ 630 up->efr &= OMAP_UART_SW_CLR; 631 632 /* 633 * IXON Flag: 634 * Enable XON/XOFF flow control on output. 635 * Transmit XON1, XOFF1 636 */ 637 if (termios->c_iflag & IXON) 638 up->efr |= OMAP_UART_SW_TX; 639 640 /* 641 * IXOFF Flag: 642 * Enable XON/XOFF flow control on input. 643 * Receiver compares XON1, XOFF1. 644 */ 645 if (termios->c_iflag & IXOFF) 646 up->efr |= OMAP_UART_SW_RX; 647 648 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 649 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 650 651 up->mcr = serial_in(up, UART_MCR); 652 653 /* 654 * IXANY Flag: 655 * Enable any character to restart output. 656 * Operation resumes after receiving any 657 * character after recognition of the XOFF character 658 */ 659 if (termios->c_iflag & IXANY) 660 up->mcr |= UART_MCR_XONANY; 661 662 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 663 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 664 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); 665 /* Enable special char function UARTi.EFR_REG[5] and 666 * load the new software flow control mode IXON or IXOFF 667 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value. 668 */ 669 serial_out(up, UART_EFR, up->efr | UART_EFR_SCD); 670 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 671 672 serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR); 673 serial_out(up, UART_LCR, up->lcr); 674 } 675 676 static void serial_omap_uart_qos_work(struct work_struct *work) 677 { 678 struct uart_omap_port *up = container_of(work, struct uart_omap_port, 679 qos_work); 680 681 pm_qos_update_request(&up->pm_qos_request, up->latency); 682 } 683 684 static void 685 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, 686 struct ktermios *old) 687 { 688 struct uart_omap_port *up = (struct uart_omap_port *)port; 689 unsigned char cval = 0; 690 unsigned char efr = 0; 691 unsigned long flags = 0; 692 unsigned int baud, quot; 693 694 switch (termios->c_cflag & CSIZE) { 695 case CS5: 696 cval = UART_LCR_WLEN5; 697 break; 698 case CS6: 699 cval = UART_LCR_WLEN6; 700 break; 701 case CS7: 702 cval = UART_LCR_WLEN7; 703 break; 704 default: 705 case CS8: 706 cval = UART_LCR_WLEN8; 707 break; 708 } 709 710 if (termios->c_cflag & CSTOPB) 711 cval |= UART_LCR_STOP; 712 if (termios->c_cflag & PARENB) 713 cval |= UART_LCR_PARITY; 714 if (!(termios->c_cflag & PARODD)) 715 cval |= UART_LCR_EPAR; 716 717 /* 718 * Ask the core to calculate the divisor for us. 719 */ 720 721 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); 722 quot = serial_omap_get_divisor(port, baud); 723 724 /* calculate wakeup latency constraint */ 725 up->calc_latency = (1000000 * up->port.fifosize) / 726 (1000 * baud / 8); 727 up->latency = up->calc_latency; 728 schedule_work(&up->qos_work); 729 730 up->dll = quot & 0xff; 731 up->dlh = quot >> 8; 732 up->mdr1 = UART_OMAP_MDR1_DISABLE; 733 734 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | 735 UART_FCR_ENABLE_FIFO; 736 if (up->use_dma) 737 up->fcr |= UART_FCR_DMA_SELECT; 738 739 /* 740 * Ok, we're now changing the port state. Do it with 741 * interrupts disabled. 742 */ 743 pm_runtime_get_sync(&up->pdev->dev); 744 spin_lock_irqsave(&up->port.lock, flags); 745 746 /* 747 * Update the per-port timeout. 748 */ 749 uart_update_timeout(port, termios->c_cflag, baud); 750 751 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 752 if (termios->c_iflag & INPCK) 753 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 754 if (termios->c_iflag & (BRKINT | PARMRK)) 755 up->port.read_status_mask |= UART_LSR_BI; 756 757 /* 758 * Characters to ignore 759 */ 760 up->port.ignore_status_mask = 0; 761 if (termios->c_iflag & IGNPAR) 762 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 763 if (termios->c_iflag & IGNBRK) { 764 up->port.ignore_status_mask |= UART_LSR_BI; 765 /* 766 * If we're ignoring parity and break indicators, 767 * ignore overruns too (for real raw support). 768 */ 769 if (termios->c_iflag & IGNPAR) 770 up->port.ignore_status_mask |= UART_LSR_OE; 771 } 772 773 /* 774 * ignore all characters if CREAD is not set 775 */ 776 if ((termios->c_cflag & CREAD) == 0) 777 up->port.ignore_status_mask |= UART_LSR_DR; 778 779 /* 780 * Modem status interrupts 781 */ 782 up->ier &= ~UART_IER_MSI; 783 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 784 up->ier |= UART_IER_MSI; 785 serial_out(up, UART_IER, up->ier); 786 serial_out(up, UART_LCR, cval); /* reset DLAB */ 787 up->lcr = cval; 788 up->scr = OMAP_UART_SCR_TX_EMPTY; 789 790 /* FIFOs and DMA Settings */ 791 792 /* FCR can be changed only when the 793 * baud clock is not running 794 * DLL_REG and DLH_REG set to 0. 795 */ 796 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 797 serial_out(up, UART_DLL, 0); 798 serial_out(up, UART_DLM, 0); 799 serial_out(up, UART_LCR, 0); 800 801 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 802 803 up->efr = serial_in(up, UART_EFR); 804 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 805 806 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 807 up->mcr = serial_in(up, UART_MCR); 808 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 809 /* FIFO ENABLE, DMA MODE */ 810 serial_out(up, UART_FCR, up->fcr); 811 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 812 813 if (up->use_dma) { 814 serial_out(up, UART_TI752_TLR, 0); 815 up->scr |= (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8); 816 } 817 818 serial_out(up, UART_OMAP_SCR, up->scr); 819 820 serial_out(up, UART_EFR, up->efr); 821 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 822 serial_out(up, UART_MCR, up->mcr); 823 824 /* Protocol, Baud Rate, and Interrupt Settings */ 825 826 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 827 serial_omap_mdr1_errataset(up, up->mdr1); 828 else 829 serial_out(up, UART_OMAP_MDR1, up->mdr1); 830 831 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 832 833 up->efr = serial_in(up, UART_EFR); 834 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 835 836 serial_out(up, UART_LCR, 0); 837 serial_out(up, UART_IER, 0); 838 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 839 840 serial_out(up, UART_DLL, up->dll); /* LS of divisor */ 841 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */ 842 843 serial_out(up, UART_LCR, 0); 844 serial_out(up, UART_IER, up->ier); 845 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 846 847 serial_out(up, UART_EFR, up->efr); 848 serial_out(up, UART_LCR, cval); 849 850 if (baud > 230400 && baud != 3000000) 851 up->mdr1 = UART_OMAP_MDR1_13X_MODE; 852 else 853 up->mdr1 = UART_OMAP_MDR1_16X_MODE; 854 855 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 856 serial_omap_mdr1_errataset(up, up->mdr1); 857 else 858 serial_out(up, UART_OMAP_MDR1, up->mdr1); 859 860 /* Hardware Flow Control Configuration */ 861 862 if (termios->c_cflag & CRTSCTS) { 863 efr |= (UART_EFR_CTS | UART_EFR_RTS); 864 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 865 866 up->mcr = serial_in(up, UART_MCR); 867 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 868 869 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 870 up->efr = serial_in(up, UART_EFR); 871 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 872 873 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); 874 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */ 875 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 876 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS); 877 serial_out(up, UART_LCR, cval); 878 } 879 880 serial_omap_set_mctrl(&up->port, up->port.mctrl); 881 /* Software Flow Control Configuration */ 882 serial_omap_configure_xonxoff(up, termios); 883 884 spin_unlock_irqrestore(&up->port.lock, flags); 885 pm_runtime_put(&up->pdev->dev); 886 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->pdev->id); 887 } 888 889 static void 890 serial_omap_pm(struct uart_port *port, unsigned int state, 891 unsigned int oldstate) 892 { 893 struct uart_omap_port *up = (struct uart_omap_port *)port; 894 unsigned char efr; 895 896 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->pdev->id); 897 898 pm_runtime_get_sync(&up->pdev->dev); 899 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 900 efr = serial_in(up, UART_EFR); 901 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 902 serial_out(up, UART_LCR, 0); 903 904 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 905 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 906 serial_out(up, UART_EFR, efr); 907 serial_out(up, UART_LCR, 0); 908 909 if (!device_may_wakeup(&up->pdev->dev)) { 910 if (!state) 911 pm_runtime_forbid(&up->pdev->dev); 912 else 913 pm_runtime_allow(&up->pdev->dev); 914 } 915 916 pm_runtime_put(&up->pdev->dev); 917 } 918 919 static void serial_omap_release_port(struct uart_port *port) 920 { 921 dev_dbg(port->dev, "serial_omap_release_port+\n"); 922 } 923 924 static int serial_omap_request_port(struct uart_port *port) 925 { 926 dev_dbg(port->dev, "serial_omap_request_port+\n"); 927 return 0; 928 } 929 930 static void serial_omap_config_port(struct uart_port *port, int flags) 931 { 932 struct uart_omap_port *up = (struct uart_omap_port *)port; 933 934 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", 935 up->pdev->id); 936 up->port.type = PORT_OMAP; 937 } 938 939 static int 940 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) 941 { 942 /* we don't want the core code to modify any port params */ 943 dev_dbg(port->dev, "serial_omap_verify_port+\n"); 944 return -EINVAL; 945 } 946 947 static const char * 948 serial_omap_type(struct uart_port *port) 949 { 950 struct uart_omap_port *up = (struct uart_omap_port *)port; 951 952 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->pdev->id); 953 return up->name; 954 } 955 956 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 957 958 static inline void wait_for_xmitr(struct uart_omap_port *up) 959 { 960 unsigned int status, tmout = 10000; 961 962 /* Wait up to 10ms for the character(s) to be sent. */ 963 do { 964 status = serial_in(up, UART_LSR); 965 966 if (status & UART_LSR_BI) 967 up->lsr_break_flag = UART_LSR_BI; 968 969 if (--tmout == 0) 970 break; 971 udelay(1); 972 } while ((status & BOTH_EMPTY) != BOTH_EMPTY); 973 974 /* Wait up to 1s for flow control if necessary */ 975 if (up->port.flags & UPF_CONS_FLOW) { 976 tmout = 1000000; 977 for (tmout = 1000000; tmout; tmout--) { 978 unsigned int msr = serial_in(up, UART_MSR); 979 980 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; 981 if (msr & UART_MSR_CTS) 982 break; 983 984 udelay(1); 985 } 986 } 987 } 988 989 #ifdef CONFIG_CONSOLE_POLL 990 991 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) 992 { 993 struct uart_omap_port *up = (struct uart_omap_port *)port; 994 995 pm_runtime_get_sync(&up->pdev->dev); 996 wait_for_xmitr(up); 997 serial_out(up, UART_TX, ch); 998 pm_runtime_put(&up->pdev->dev); 999 } 1000 1001 static int serial_omap_poll_get_char(struct uart_port *port) 1002 { 1003 struct uart_omap_port *up = (struct uart_omap_port *)port; 1004 unsigned int status; 1005 1006 pm_runtime_get_sync(&up->pdev->dev); 1007 status = serial_in(up, UART_LSR); 1008 if (!(status & UART_LSR_DR)) 1009 return NO_POLL_CHAR; 1010 1011 status = serial_in(up, UART_RX); 1012 pm_runtime_put(&up->pdev->dev); 1013 return status; 1014 } 1015 1016 #endif /* CONFIG_CONSOLE_POLL */ 1017 1018 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 1019 1020 static struct uart_omap_port *serial_omap_console_ports[4]; 1021 1022 static struct uart_driver serial_omap_reg; 1023 1024 static void serial_omap_console_putchar(struct uart_port *port, int ch) 1025 { 1026 struct uart_omap_port *up = (struct uart_omap_port *)port; 1027 1028 wait_for_xmitr(up); 1029 serial_out(up, UART_TX, ch); 1030 } 1031 1032 static void 1033 serial_omap_console_write(struct console *co, const char *s, 1034 unsigned int count) 1035 { 1036 struct uart_omap_port *up = serial_omap_console_ports[co->index]; 1037 unsigned long flags; 1038 unsigned int ier; 1039 int locked = 1; 1040 1041 pm_runtime_get_sync(&up->pdev->dev); 1042 1043 local_irq_save(flags); 1044 if (up->port.sysrq) 1045 locked = 0; 1046 else if (oops_in_progress) 1047 locked = spin_trylock(&up->port.lock); 1048 else 1049 spin_lock(&up->port.lock); 1050 1051 /* 1052 * First save the IER then disable the interrupts 1053 */ 1054 ier = serial_in(up, UART_IER); 1055 serial_out(up, UART_IER, 0); 1056 1057 uart_console_write(&up->port, s, count, serial_omap_console_putchar); 1058 1059 /* 1060 * Finally, wait for transmitter to become empty 1061 * and restore the IER 1062 */ 1063 wait_for_xmitr(up); 1064 serial_out(up, UART_IER, ier); 1065 /* 1066 * The receive handling will happen properly because the 1067 * receive ready bit will still be set; it is not cleared 1068 * on read. However, modem control will not, we must 1069 * call it if we have saved something in the saved flags 1070 * while processing with interrupts off. 1071 */ 1072 if (up->msr_saved_flags) 1073 check_modem_status(up); 1074 1075 pm_runtime_mark_last_busy(&up->pdev->dev); 1076 pm_runtime_put_autosuspend(&up->pdev->dev); 1077 if (locked) 1078 spin_unlock(&up->port.lock); 1079 local_irq_restore(flags); 1080 } 1081 1082 static int __init 1083 serial_omap_console_setup(struct console *co, char *options) 1084 { 1085 struct uart_omap_port *up; 1086 int baud = 115200; 1087 int bits = 8; 1088 int parity = 'n'; 1089 int flow = 'n'; 1090 1091 if (serial_omap_console_ports[co->index] == NULL) 1092 return -ENODEV; 1093 up = serial_omap_console_ports[co->index]; 1094 1095 if (options) 1096 uart_parse_options(options, &baud, &parity, &bits, &flow); 1097 1098 return uart_set_options(&up->port, co, baud, parity, bits, flow); 1099 } 1100 1101 static struct console serial_omap_console = { 1102 .name = OMAP_SERIAL_NAME, 1103 .write = serial_omap_console_write, 1104 .device = uart_console_device, 1105 .setup = serial_omap_console_setup, 1106 .flags = CON_PRINTBUFFER, 1107 .index = -1, 1108 .data = &serial_omap_reg, 1109 }; 1110 1111 static void serial_omap_add_console_port(struct uart_omap_port *up) 1112 { 1113 serial_omap_console_ports[up->pdev->id] = up; 1114 } 1115 1116 #define OMAP_CONSOLE (&serial_omap_console) 1117 1118 #else 1119 1120 #define OMAP_CONSOLE NULL 1121 1122 static inline void serial_omap_add_console_port(struct uart_omap_port *up) 1123 {} 1124 1125 #endif 1126 1127 static struct uart_ops serial_omap_pops = { 1128 .tx_empty = serial_omap_tx_empty, 1129 .set_mctrl = serial_omap_set_mctrl, 1130 .get_mctrl = serial_omap_get_mctrl, 1131 .stop_tx = serial_omap_stop_tx, 1132 .start_tx = serial_omap_start_tx, 1133 .stop_rx = serial_omap_stop_rx, 1134 .enable_ms = serial_omap_enable_ms, 1135 .break_ctl = serial_omap_break_ctl, 1136 .startup = serial_omap_startup, 1137 .shutdown = serial_omap_shutdown, 1138 .set_termios = serial_omap_set_termios, 1139 .pm = serial_omap_pm, 1140 .type = serial_omap_type, 1141 .release_port = serial_omap_release_port, 1142 .request_port = serial_omap_request_port, 1143 .config_port = serial_omap_config_port, 1144 .verify_port = serial_omap_verify_port, 1145 #ifdef CONFIG_CONSOLE_POLL 1146 .poll_put_char = serial_omap_poll_put_char, 1147 .poll_get_char = serial_omap_poll_get_char, 1148 #endif 1149 }; 1150 1151 static struct uart_driver serial_omap_reg = { 1152 .owner = THIS_MODULE, 1153 .driver_name = "OMAP-SERIAL", 1154 .dev_name = OMAP_SERIAL_NAME, 1155 .nr = OMAP_MAX_HSUART_PORTS, 1156 .cons = OMAP_CONSOLE, 1157 }; 1158 1159 #ifdef CONFIG_SUSPEND 1160 static int serial_omap_suspend(struct device *dev) 1161 { 1162 struct uart_omap_port *up = dev_get_drvdata(dev); 1163 1164 if (up) { 1165 uart_suspend_port(&serial_omap_reg, &up->port); 1166 flush_work_sync(&up->qos_work); 1167 } 1168 1169 return 0; 1170 } 1171 1172 static int serial_omap_resume(struct device *dev) 1173 { 1174 struct uart_omap_port *up = dev_get_drvdata(dev); 1175 1176 if (up) 1177 uart_resume_port(&serial_omap_reg, &up->port); 1178 return 0; 1179 } 1180 #endif 1181 1182 static void serial_omap_rxdma_poll(unsigned long uart_no) 1183 { 1184 struct uart_omap_port *up = ui[uart_no]; 1185 unsigned int curr_dma_pos, curr_transmitted_size; 1186 int ret = 0; 1187 1188 curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel); 1189 if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) || 1190 (curr_dma_pos == 0)) { 1191 if (jiffies_to_msecs(jiffies - up->port_activity) < 1192 up->uart_dma.rx_timeout) { 1193 mod_timer(&up->uart_dma.rx_timer, jiffies + 1194 usecs_to_jiffies(up->uart_dma.rx_poll_rate)); 1195 } else { 1196 serial_omap_stop_rxdma(up); 1197 up->ier |= (UART_IER_RDI | UART_IER_RLSI); 1198 serial_out(up, UART_IER, up->ier); 1199 } 1200 return; 1201 } 1202 1203 curr_transmitted_size = curr_dma_pos - 1204 up->uart_dma.prev_rx_dma_pos; 1205 up->port.icount.rx += curr_transmitted_size; 1206 tty_insert_flip_string(up->port.state->port.tty, 1207 up->uart_dma.rx_buf + 1208 (up->uart_dma.prev_rx_dma_pos - 1209 up->uart_dma.rx_buf_dma_phys), 1210 curr_transmitted_size); 1211 tty_flip_buffer_push(up->port.state->port.tty); 1212 up->uart_dma.prev_rx_dma_pos = curr_dma_pos; 1213 if (up->uart_dma.rx_buf_size + 1214 up->uart_dma.rx_buf_dma_phys == curr_dma_pos) { 1215 ret = serial_omap_start_rxdma(up); 1216 if (ret < 0) { 1217 serial_omap_stop_rxdma(up); 1218 up->ier |= (UART_IER_RDI | UART_IER_RLSI); 1219 serial_out(up, UART_IER, up->ier); 1220 } 1221 } else { 1222 mod_timer(&up->uart_dma.rx_timer, jiffies + 1223 usecs_to_jiffies(up->uart_dma.rx_poll_rate)); 1224 } 1225 up->port_activity = jiffies; 1226 } 1227 1228 static void uart_rx_dma_callback(int lch, u16 ch_status, void *data) 1229 { 1230 return; 1231 } 1232 1233 static int serial_omap_start_rxdma(struct uart_omap_port *up) 1234 { 1235 int ret = 0; 1236 1237 if (up->uart_dma.rx_dma_channel == -1) { 1238 pm_runtime_get_sync(&up->pdev->dev); 1239 ret = omap_request_dma(up->uart_dma.uart_dma_rx, 1240 "UART Rx DMA", 1241 (void *)uart_rx_dma_callback, up, 1242 &(up->uart_dma.rx_dma_channel)); 1243 if (ret < 0) 1244 return ret; 1245 1246 omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0, 1247 OMAP_DMA_AMODE_CONSTANT, 1248 up->uart_dma.uart_base, 0, 0); 1249 omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0, 1250 OMAP_DMA_AMODE_POST_INC, 1251 up->uart_dma.rx_buf_dma_phys, 0, 0); 1252 omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel, 1253 OMAP_DMA_DATA_TYPE_S8, 1254 up->uart_dma.rx_buf_size, 1, 1255 OMAP_DMA_SYNC_ELEMENT, 1256 up->uart_dma.uart_dma_rx, 0); 1257 } 1258 up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys; 1259 /* FIXME: Cache maintenance needed here? */ 1260 omap_start_dma(up->uart_dma.rx_dma_channel); 1261 mod_timer(&up->uart_dma.rx_timer, jiffies + 1262 usecs_to_jiffies(up->uart_dma.rx_poll_rate)); 1263 up->uart_dma.rx_dma_used = true; 1264 return ret; 1265 } 1266 1267 static void serial_omap_continue_tx(struct uart_omap_port *up) 1268 { 1269 struct circ_buf *xmit = &up->port.state->xmit; 1270 unsigned int start = up->uart_dma.tx_buf_dma_phys 1271 + (xmit->tail & (UART_XMIT_SIZE - 1)); 1272 1273 if (uart_circ_empty(xmit)) 1274 return; 1275 1276 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit); 1277 /* 1278 * It is a circular buffer. See if the buffer has wounded back. 1279 * If yes it will have to be transferred in two separate dma 1280 * transfers 1281 */ 1282 if (start + up->uart_dma.tx_buf_size >= 1283 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) 1284 up->uart_dma.tx_buf_size = 1285 (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start; 1286 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0, 1287 OMAP_DMA_AMODE_CONSTANT, 1288 up->uart_dma.uart_base, 0, 0); 1289 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0, 1290 OMAP_DMA_AMODE_POST_INC, start, 0, 0); 1291 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel, 1292 OMAP_DMA_DATA_TYPE_S8, 1293 up->uart_dma.tx_buf_size, 1, 1294 OMAP_DMA_SYNC_ELEMENT, 1295 up->uart_dma.uart_dma_tx, 0); 1296 /* FIXME: Cache maintenance needed here? */ 1297 omap_start_dma(up->uart_dma.tx_dma_channel); 1298 } 1299 1300 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data) 1301 { 1302 struct uart_omap_port *up = (struct uart_omap_port *)data; 1303 struct circ_buf *xmit = &up->port.state->xmit; 1304 1305 xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \ 1306 (UART_XMIT_SIZE - 1); 1307 up->port.icount.tx += up->uart_dma.tx_buf_size; 1308 1309 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1310 uart_write_wakeup(&up->port); 1311 1312 if (uart_circ_empty(xmit)) { 1313 spin_lock(&(up->uart_dma.tx_lock)); 1314 serial_omap_stop_tx(&up->port); 1315 up->uart_dma.tx_dma_used = false; 1316 spin_unlock(&(up->uart_dma.tx_lock)); 1317 } else { 1318 omap_stop_dma(up->uart_dma.tx_dma_channel); 1319 serial_omap_continue_tx(up); 1320 } 1321 up->port_activity = jiffies; 1322 return; 1323 } 1324 1325 static int serial_omap_probe(struct platform_device *pdev) 1326 { 1327 struct uart_omap_port *up; 1328 struct resource *mem, *irq, *dma_tx, *dma_rx; 1329 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data; 1330 int ret = -ENOSPC; 1331 1332 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1333 if (!mem) { 1334 dev_err(&pdev->dev, "no mem resource?\n"); 1335 return -ENODEV; 1336 } 1337 1338 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1339 if (!irq) { 1340 dev_err(&pdev->dev, "no irq resource?\n"); 1341 return -ENODEV; 1342 } 1343 1344 if (!request_mem_region(mem->start, resource_size(mem), 1345 pdev->dev.driver->name)) { 1346 dev_err(&pdev->dev, "memory region already claimed\n"); 1347 return -EBUSY; 1348 } 1349 1350 dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 1351 if (!dma_rx) { 1352 ret = -EINVAL; 1353 goto err; 1354 } 1355 1356 dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 1357 if (!dma_tx) { 1358 ret = -EINVAL; 1359 goto err; 1360 } 1361 1362 up = kzalloc(sizeof(*up), GFP_KERNEL); 1363 if (up == NULL) { 1364 ret = -ENOMEM; 1365 goto do_release_region; 1366 } 1367 sprintf(up->name, "OMAP UART%d", pdev->id); 1368 up->pdev = pdev; 1369 up->port.dev = &pdev->dev; 1370 up->port.type = PORT_OMAP; 1371 up->port.iotype = UPIO_MEM; 1372 up->port.irq = irq->start; 1373 1374 up->port.regshift = 2; 1375 up->port.fifosize = 64; 1376 up->port.ops = &serial_omap_pops; 1377 up->port.line = pdev->id; 1378 1379 up->port.mapbase = mem->start; 1380 up->port.membase = ioremap(mem->start, resource_size(mem)); 1381 if (!up->port.membase) { 1382 dev_err(&pdev->dev, "can't ioremap UART\n"); 1383 ret = -ENOMEM; 1384 goto err; 1385 } 1386 1387 up->port.flags = omap_up_info->flags; 1388 up->port.uartclk = omap_up_info->uartclk; 1389 up->uart_dma.uart_base = mem->start; 1390 up->errata = omap_up_info->errata; 1391 1392 if (omap_up_info->dma_enabled) { 1393 up->uart_dma.uart_dma_tx = dma_tx->start; 1394 up->uart_dma.uart_dma_rx = dma_rx->start; 1395 up->use_dma = 1; 1396 up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size; 1397 up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout; 1398 up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate; 1399 spin_lock_init(&(up->uart_dma.tx_lock)); 1400 spin_lock_init(&(up->uart_dma.rx_lock)); 1401 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE; 1402 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE; 1403 } 1404 1405 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1406 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1407 pm_qos_add_request(&up->pm_qos_request, 1408 PM_QOS_CPU_DMA_LATENCY, up->latency); 1409 serial_omap_uart_wq = create_singlethread_workqueue(up->name); 1410 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); 1411 1412 pm_runtime_use_autosuspend(&pdev->dev); 1413 pm_runtime_set_autosuspend_delay(&pdev->dev, 1414 omap_up_info->autosuspend_timeout); 1415 1416 pm_runtime_irq_safe(&pdev->dev); 1417 pm_runtime_enable(&pdev->dev); 1418 pm_runtime_get_sync(&pdev->dev); 1419 1420 ui[pdev->id] = up; 1421 serial_omap_add_console_port(up); 1422 1423 ret = uart_add_one_port(&serial_omap_reg, &up->port); 1424 if (ret != 0) 1425 goto do_release_region; 1426 1427 pm_runtime_put(&pdev->dev); 1428 platform_set_drvdata(pdev, up); 1429 return 0; 1430 err: 1431 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n", 1432 pdev->id, __func__, ret); 1433 do_release_region: 1434 release_mem_region(mem->start, resource_size(mem)); 1435 return ret; 1436 } 1437 1438 static int serial_omap_remove(struct platform_device *dev) 1439 { 1440 struct uart_omap_port *up = platform_get_drvdata(dev); 1441 1442 if (up) { 1443 pm_runtime_disable(&up->pdev->dev); 1444 uart_remove_one_port(&serial_omap_reg, &up->port); 1445 pm_qos_remove_request(&up->pm_qos_request); 1446 1447 kfree(up); 1448 } 1449 1450 platform_set_drvdata(dev, NULL); 1451 return 0; 1452 } 1453 1454 /* 1455 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 1456 * The access to uart register after MDR1 Access 1457 * causes UART to corrupt data. 1458 * 1459 * Need a delay = 1460 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 1461 * give 10 times as much 1462 */ 1463 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1) 1464 { 1465 u8 timeout = 255; 1466 1467 serial_out(up, UART_OMAP_MDR1, mdr1); 1468 udelay(2); 1469 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 1470 UART_FCR_CLEAR_RCVR); 1471 /* 1472 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 1473 * TX_FIFO_E bit is 1. 1474 */ 1475 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 1476 (UART_LSR_THRE | UART_LSR_DR))) { 1477 timeout--; 1478 if (!timeout) { 1479 /* Should *never* happen. we warn and carry on */ 1480 dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n", 1481 serial_in(up, UART_LSR)); 1482 break; 1483 } 1484 udelay(1); 1485 } 1486 } 1487 1488 static void serial_omap_restore_context(struct uart_omap_port *up) 1489 { 1490 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1491 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE); 1492 else 1493 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); 1494 1495 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1496 serial_out(up, UART_EFR, UART_EFR_ECB); 1497 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1498 serial_out(up, UART_IER, 0x0); 1499 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1500 serial_out(up, UART_DLL, up->dll); 1501 serial_out(up, UART_DLM, up->dlh); 1502 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1503 serial_out(up, UART_IER, up->ier); 1504 serial_out(up, UART_FCR, up->fcr); 1505 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1506 serial_out(up, UART_MCR, up->mcr); 1507 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1508 serial_out(up, UART_OMAP_SCR, up->scr); 1509 serial_out(up, UART_EFR, up->efr); 1510 serial_out(up, UART_LCR, up->lcr); 1511 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1512 serial_omap_mdr1_errataset(up, up->mdr1); 1513 else 1514 serial_out(up, UART_OMAP_MDR1, up->mdr1); 1515 } 1516 1517 #ifdef CONFIG_PM_RUNTIME 1518 static int serial_omap_runtime_suspend(struct device *dev) 1519 { 1520 struct uart_omap_port *up = dev_get_drvdata(dev); 1521 struct omap_uart_port_info *pdata = dev->platform_data; 1522 1523 if (!up) 1524 return -EINVAL; 1525 1526 if (!pdata->enable_wakeup) 1527 return 0; 1528 1529 if (pdata->get_context_loss_count) 1530 up->context_loss_cnt = pdata->get_context_loss_count(dev); 1531 1532 if (device_may_wakeup(dev)) { 1533 if (!up->wakeups_enabled) { 1534 pdata->enable_wakeup(up->pdev, true); 1535 up->wakeups_enabled = true; 1536 } 1537 } else { 1538 if (up->wakeups_enabled) { 1539 pdata->enable_wakeup(up->pdev, false); 1540 up->wakeups_enabled = false; 1541 } 1542 } 1543 1544 /* Errata i291 */ 1545 if (up->use_dma && pdata->set_forceidle && 1546 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE)) 1547 pdata->set_forceidle(up->pdev); 1548 1549 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1550 schedule_work(&up->qos_work); 1551 1552 return 0; 1553 } 1554 1555 static int serial_omap_runtime_resume(struct device *dev) 1556 { 1557 struct uart_omap_port *up = dev_get_drvdata(dev); 1558 struct omap_uart_port_info *pdata = dev->platform_data; 1559 1560 if (up) { 1561 if (pdata->get_context_loss_count) { 1562 u32 loss_cnt = pdata->get_context_loss_count(dev); 1563 1564 if (up->context_loss_cnt != loss_cnt) 1565 serial_omap_restore_context(up); 1566 } 1567 1568 /* Errata i291 */ 1569 if (up->use_dma && pdata->set_noidle && 1570 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE)) 1571 pdata->set_noidle(up->pdev); 1572 1573 up->latency = up->calc_latency; 1574 schedule_work(&up->qos_work); 1575 } 1576 1577 return 0; 1578 } 1579 #endif 1580 1581 static const struct dev_pm_ops serial_omap_dev_pm_ops = { 1582 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume) 1583 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend, 1584 serial_omap_runtime_resume, NULL) 1585 }; 1586 1587 static struct platform_driver serial_omap_driver = { 1588 .probe = serial_omap_probe, 1589 .remove = serial_omap_remove, 1590 .driver = { 1591 .name = DRIVER_NAME, 1592 .pm = &serial_omap_dev_pm_ops, 1593 }, 1594 }; 1595 1596 static int __init serial_omap_init(void) 1597 { 1598 int ret; 1599 1600 ret = uart_register_driver(&serial_omap_reg); 1601 if (ret != 0) 1602 return ret; 1603 ret = platform_driver_register(&serial_omap_driver); 1604 if (ret != 0) 1605 uart_unregister_driver(&serial_omap_reg); 1606 return ret; 1607 } 1608 1609 static void __exit serial_omap_exit(void) 1610 { 1611 platform_driver_unregister(&serial_omap_driver); 1612 uart_unregister_driver(&serial_omap_reg); 1613 } 1614 1615 module_init(serial_omap_init); 1616 module_exit(serial_omap_exit); 1617 1618 MODULE_DESCRIPTION("OMAP High Speed UART driver"); 1619 MODULE_LICENSE("GPL"); 1620 MODULE_AUTHOR("Texas Instruments Inc"); 1621