1 /* 2 * Freescale STMP37XX/STMP378X Application UART driver 3 * 4 * Author: dmitry pervushin <dimka@embeddedalley.com> 5 * 6 * Copyright 2008-2010 Freescale Semiconductor, Inc. 7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. 8 * 9 * The code contained herein is licensed under the GNU General Public 10 * License. You may obtain a copy of the GNU General Public License 11 * Version 2 or later at the following locations: 12 * 13 * http://www.opensource.org/licenses/gpl-license.html 14 * http://www.gnu.org/copyleft/gpl.html 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/console.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/slab.h> 24 #include <linux/wait.h> 25 #include <linux/tty.h> 26 #include <linux/tty_driver.h> 27 #include <linux/tty_flip.h> 28 #include <linux/serial.h> 29 #include <linux/serial_core.h> 30 #include <linux/platform_device.h> 31 #include <linux/device.h> 32 #include <linux/clk.h> 33 #include <linux/delay.h> 34 #include <linux/io.h> 35 #include <linux/pinctrl/consumer.h> 36 #include <linux/of_device.h> 37 #include <linux/dma-mapping.h> 38 #include <linux/fsl/mxs-dma.h> 39 40 #include <asm/cacheflush.h> 41 42 #define MXS_AUART_PORTS 5 43 44 #define AUART_CTRL0 0x00000000 45 #define AUART_CTRL0_SET 0x00000004 46 #define AUART_CTRL0_CLR 0x00000008 47 #define AUART_CTRL0_TOG 0x0000000c 48 #define AUART_CTRL1 0x00000010 49 #define AUART_CTRL1_SET 0x00000014 50 #define AUART_CTRL1_CLR 0x00000018 51 #define AUART_CTRL1_TOG 0x0000001c 52 #define AUART_CTRL2 0x00000020 53 #define AUART_CTRL2_SET 0x00000024 54 #define AUART_CTRL2_CLR 0x00000028 55 #define AUART_CTRL2_TOG 0x0000002c 56 #define AUART_LINECTRL 0x00000030 57 #define AUART_LINECTRL_SET 0x00000034 58 #define AUART_LINECTRL_CLR 0x00000038 59 #define AUART_LINECTRL_TOG 0x0000003c 60 #define AUART_LINECTRL2 0x00000040 61 #define AUART_LINECTRL2_SET 0x00000044 62 #define AUART_LINECTRL2_CLR 0x00000048 63 #define AUART_LINECTRL2_TOG 0x0000004c 64 #define AUART_INTR 0x00000050 65 #define AUART_INTR_SET 0x00000054 66 #define AUART_INTR_CLR 0x00000058 67 #define AUART_INTR_TOG 0x0000005c 68 #define AUART_DATA 0x00000060 69 #define AUART_STAT 0x00000070 70 #define AUART_DEBUG 0x00000080 71 #define AUART_VERSION 0x00000090 72 #define AUART_AUTOBAUD 0x000000a0 73 74 #define AUART_CTRL0_SFTRST (1 << 31) 75 #define AUART_CTRL0_CLKGATE (1 << 30) 76 #define AUART_CTRL0_RXTO_ENABLE (1 << 27) 77 #define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16) 78 #define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff) 79 80 #define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff) 81 82 #define AUART_CTRL2_DMAONERR (1 << 26) 83 #define AUART_CTRL2_TXDMAE (1 << 25) 84 #define AUART_CTRL2_RXDMAE (1 << 24) 85 86 #define AUART_CTRL2_CTSEN (1 << 15) 87 #define AUART_CTRL2_RTSEN (1 << 14) 88 #define AUART_CTRL2_RTS (1 << 11) 89 #define AUART_CTRL2_RXE (1 << 9) 90 #define AUART_CTRL2_TXE (1 << 8) 91 #define AUART_CTRL2_UARTEN (1 << 0) 92 93 #define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16 94 #define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000 95 #define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16) 96 #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8 97 #define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00 98 #define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8) 99 #define AUART_LINECTRL_WLEN_MASK 0x00000060 100 #define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5) 101 #define AUART_LINECTRL_FEN (1 << 4) 102 #define AUART_LINECTRL_STP2 (1 << 3) 103 #define AUART_LINECTRL_EPS (1 << 2) 104 #define AUART_LINECTRL_PEN (1 << 1) 105 #define AUART_LINECTRL_BRK (1 << 0) 106 107 #define AUART_INTR_RTIEN (1 << 22) 108 #define AUART_INTR_TXIEN (1 << 21) 109 #define AUART_INTR_RXIEN (1 << 20) 110 #define AUART_INTR_CTSMIEN (1 << 17) 111 #define AUART_INTR_RTIS (1 << 6) 112 #define AUART_INTR_TXIS (1 << 5) 113 #define AUART_INTR_RXIS (1 << 4) 114 #define AUART_INTR_CTSMIS (1 << 1) 115 116 #define AUART_STAT_BUSY (1 << 29) 117 #define AUART_STAT_CTS (1 << 28) 118 #define AUART_STAT_TXFE (1 << 27) 119 #define AUART_STAT_TXFF (1 << 25) 120 #define AUART_STAT_RXFE (1 << 24) 121 #define AUART_STAT_OERR (1 << 19) 122 #define AUART_STAT_BERR (1 << 18) 123 #define AUART_STAT_PERR (1 << 17) 124 #define AUART_STAT_FERR (1 << 16) 125 #define AUART_STAT_RXCOUNT_MASK 0xffff 126 127 static struct uart_driver auart_driver; 128 129 enum mxs_auart_type { 130 IMX23_AUART, 131 IMX28_AUART, 132 }; 133 134 struct mxs_auart_port { 135 struct uart_port port; 136 137 #define MXS_AUART_DMA_CONFIG 0x1 138 #define MXS_AUART_DMA_ENABLED 0x2 139 #define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */ 140 #define MXS_AUART_DMA_RX_READY 3 /* bit 3 */ 141 unsigned long flags; 142 unsigned int ctrl; 143 enum mxs_auart_type devtype; 144 145 unsigned int irq; 146 147 struct clk *clk; 148 struct device *dev; 149 150 /* for DMA */ 151 struct mxs_dma_data dma_data; 152 int dma_channel_rx, dma_channel_tx; 153 int dma_irq_rx, dma_irq_tx; 154 int dma_channel; 155 156 struct scatterlist tx_sgl; 157 struct dma_chan *tx_dma_chan; 158 void *tx_dma_buf; 159 160 struct scatterlist rx_sgl; 161 struct dma_chan *rx_dma_chan; 162 void *rx_dma_buf; 163 }; 164 165 static struct platform_device_id mxs_auart_devtype[] = { 166 { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART }, 167 { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART }, 168 { /* sentinel */ } 169 }; 170 MODULE_DEVICE_TABLE(platform, mxs_auart_devtype); 171 172 static struct of_device_id mxs_auart_dt_ids[] = { 173 { 174 .compatible = "fsl,imx28-auart", 175 .data = &mxs_auart_devtype[IMX28_AUART] 176 }, { 177 .compatible = "fsl,imx23-auart", 178 .data = &mxs_auart_devtype[IMX23_AUART] 179 }, { /* sentinel */ } 180 }; 181 MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids); 182 183 static inline int is_imx28_auart(struct mxs_auart_port *s) 184 { 185 return s->devtype == IMX28_AUART; 186 } 187 188 static inline bool auart_dma_enabled(struct mxs_auart_port *s) 189 { 190 return s->flags & MXS_AUART_DMA_ENABLED; 191 } 192 193 static void mxs_auart_stop_tx(struct uart_port *u); 194 195 #define to_auart_port(u) container_of(u, struct mxs_auart_port, port) 196 197 static void mxs_auart_tx_chars(struct mxs_auart_port *s); 198 199 static void dma_tx_callback(void *param) 200 { 201 struct mxs_auart_port *s = param; 202 struct circ_buf *xmit = &s->port.state->xmit; 203 204 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE); 205 206 /* clear the bit used to serialize the DMA tx. */ 207 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); 208 smp_mb__after_clear_bit(); 209 210 /* wake up the possible processes. */ 211 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 212 uart_write_wakeup(&s->port); 213 214 mxs_auart_tx_chars(s); 215 } 216 217 static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size) 218 { 219 struct dma_async_tx_descriptor *desc; 220 struct scatterlist *sgl = &s->tx_sgl; 221 struct dma_chan *channel = s->tx_dma_chan; 222 u32 pio; 223 224 /* [1] : send PIO. Note, the first pio word is CTRL1. */ 225 pio = AUART_CTRL1_XFER_COUNT(size); 226 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio, 227 1, DMA_TRANS_NONE, 0); 228 if (!desc) { 229 dev_err(s->dev, "step 1 error\n"); 230 return -EINVAL; 231 } 232 233 /* [2] : set DMA buffer. */ 234 sg_init_one(sgl, s->tx_dma_buf, size); 235 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE); 236 desc = dmaengine_prep_slave_sg(channel, sgl, 237 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 238 if (!desc) { 239 dev_err(s->dev, "step 2 error\n"); 240 return -EINVAL; 241 } 242 243 /* [3] : submit the DMA */ 244 desc->callback = dma_tx_callback; 245 desc->callback_param = s; 246 dmaengine_submit(desc); 247 dma_async_issue_pending(channel); 248 return 0; 249 } 250 251 static void mxs_auart_tx_chars(struct mxs_auart_port *s) 252 { 253 struct circ_buf *xmit = &s->port.state->xmit; 254 255 if (auart_dma_enabled(s)) { 256 int i = 0; 257 int size; 258 void *buffer = s->tx_dma_buf; 259 260 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags)) 261 return; 262 263 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { 264 size = min_t(u32, UART_XMIT_SIZE - i, 265 CIRC_CNT_TO_END(xmit->head, 266 xmit->tail, 267 UART_XMIT_SIZE)); 268 memcpy(buffer + i, xmit->buf + xmit->tail, size); 269 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1); 270 271 i += size; 272 if (i >= UART_XMIT_SIZE) 273 break; 274 } 275 276 if (uart_tx_stopped(&s->port)) 277 mxs_auart_stop_tx(&s->port); 278 279 if (i) { 280 mxs_auart_dma_tx(s, i); 281 } else { 282 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); 283 smp_mb__after_clear_bit(); 284 } 285 return; 286 } 287 288 289 while (!(readl(s->port.membase + AUART_STAT) & 290 AUART_STAT_TXFF)) { 291 if (s->port.x_char) { 292 s->port.icount.tx++; 293 writel(s->port.x_char, 294 s->port.membase + AUART_DATA); 295 s->port.x_char = 0; 296 continue; 297 } 298 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { 299 s->port.icount.tx++; 300 writel(xmit->buf[xmit->tail], 301 s->port.membase + AUART_DATA); 302 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 303 } else 304 break; 305 } 306 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 307 uart_write_wakeup(&s->port); 308 309 if (uart_circ_empty(&(s->port.state->xmit))) 310 writel(AUART_INTR_TXIEN, 311 s->port.membase + AUART_INTR_CLR); 312 else 313 writel(AUART_INTR_TXIEN, 314 s->port.membase + AUART_INTR_SET); 315 316 if (uart_tx_stopped(&s->port)) 317 mxs_auart_stop_tx(&s->port); 318 } 319 320 static void mxs_auart_rx_char(struct mxs_auart_port *s) 321 { 322 int flag; 323 u32 stat; 324 u8 c; 325 326 c = readl(s->port.membase + AUART_DATA); 327 stat = readl(s->port.membase + AUART_STAT); 328 329 flag = TTY_NORMAL; 330 s->port.icount.rx++; 331 332 if (stat & AUART_STAT_BERR) { 333 s->port.icount.brk++; 334 if (uart_handle_break(&s->port)) 335 goto out; 336 } else if (stat & AUART_STAT_PERR) { 337 s->port.icount.parity++; 338 } else if (stat & AUART_STAT_FERR) { 339 s->port.icount.frame++; 340 } 341 342 /* 343 * Mask off conditions which should be ingored. 344 */ 345 stat &= s->port.read_status_mask; 346 347 if (stat & AUART_STAT_BERR) { 348 flag = TTY_BREAK; 349 } else if (stat & AUART_STAT_PERR) 350 flag = TTY_PARITY; 351 else if (stat & AUART_STAT_FERR) 352 flag = TTY_FRAME; 353 354 if (stat & AUART_STAT_OERR) 355 s->port.icount.overrun++; 356 357 if (uart_handle_sysrq_char(&s->port, c)) 358 goto out; 359 360 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag); 361 out: 362 writel(stat, s->port.membase + AUART_STAT); 363 } 364 365 static void mxs_auart_rx_chars(struct mxs_auart_port *s) 366 { 367 struct tty_struct *tty = s->port.state->port.tty; 368 u32 stat = 0; 369 370 for (;;) { 371 stat = readl(s->port.membase + AUART_STAT); 372 if (stat & AUART_STAT_RXFE) 373 break; 374 mxs_auart_rx_char(s); 375 } 376 377 writel(stat, s->port.membase + AUART_STAT); 378 tty_flip_buffer_push(tty); 379 } 380 381 static int mxs_auart_request_port(struct uart_port *u) 382 { 383 return 0; 384 } 385 386 static int mxs_auart_verify_port(struct uart_port *u, 387 struct serial_struct *ser) 388 { 389 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX) 390 return -EINVAL; 391 return 0; 392 } 393 394 static void mxs_auart_config_port(struct uart_port *u, int flags) 395 { 396 } 397 398 static const char *mxs_auart_type(struct uart_port *u) 399 { 400 struct mxs_auart_port *s = to_auart_port(u); 401 402 return dev_name(s->dev); 403 } 404 405 static void mxs_auart_release_port(struct uart_port *u) 406 { 407 } 408 409 static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl) 410 { 411 struct mxs_auart_port *s = to_auart_port(u); 412 413 u32 ctrl = readl(u->membase + AUART_CTRL2); 414 415 ctrl &= ~AUART_CTRL2_RTSEN; 416 if (mctrl & TIOCM_RTS) { 417 if (tty_port_cts_enabled(&u->state->port)) 418 ctrl |= AUART_CTRL2_RTSEN; 419 } 420 421 s->ctrl = mctrl; 422 writel(ctrl, u->membase + AUART_CTRL2); 423 } 424 425 static u32 mxs_auart_get_mctrl(struct uart_port *u) 426 { 427 struct mxs_auart_port *s = to_auart_port(u); 428 u32 stat = readl(u->membase + AUART_STAT); 429 int ctrl2 = readl(u->membase + AUART_CTRL2); 430 u32 mctrl = s->ctrl; 431 432 mctrl &= ~TIOCM_CTS; 433 if (stat & AUART_STAT_CTS) 434 mctrl |= TIOCM_CTS; 435 436 if (ctrl2 & AUART_CTRL2_RTS) 437 mctrl |= TIOCM_RTS; 438 439 return mctrl; 440 } 441 442 static bool mxs_auart_dma_filter(struct dma_chan *chan, void *param) 443 { 444 struct mxs_auart_port *s = param; 445 446 if (!mxs_dma_is_apbx(chan)) 447 return false; 448 449 if (s->dma_channel == chan->chan_id) { 450 chan->private = &s->dma_data; 451 return true; 452 } 453 return false; 454 } 455 456 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s); 457 static void dma_rx_callback(void *arg) 458 { 459 struct mxs_auart_port *s = (struct mxs_auart_port *) arg; 460 struct tty_struct *tty = s->port.state->port.tty; 461 int count; 462 u32 stat; 463 464 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE); 465 466 stat = readl(s->port.membase + AUART_STAT); 467 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR | 468 AUART_STAT_PERR | AUART_STAT_FERR); 469 470 count = stat & AUART_STAT_RXCOUNT_MASK; 471 tty_insert_flip_string(tty, s->rx_dma_buf, count); 472 473 writel(stat, s->port.membase + AUART_STAT); 474 tty_flip_buffer_push(tty); 475 476 /* start the next DMA for RX. */ 477 mxs_auart_dma_prep_rx(s); 478 } 479 480 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s) 481 { 482 struct dma_async_tx_descriptor *desc; 483 struct scatterlist *sgl = &s->rx_sgl; 484 struct dma_chan *channel = s->rx_dma_chan; 485 u32 pio[1]; 486 487 /* [1] : send PIO */ 488 pio[0] = AUART_CTRL0_RXTO_ENABLE 489 | AUART_CTRL0_RXTIMEOUT(0x80) 490 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE); 491 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio, 492 1, DMA_TRANS_NONE, 0); 493 if (!desc) { 494 dev_err(s->dev, "step 1 error\n"); 495 return -EINVAL; 496 } 497 498 /* [2] : send DMA request */ 499 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE); 500 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE); 501 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM, 502 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 503 if (!desc) { 504 dev_err(s->dev, "step 2 error\n"); 505 return -1; 506 } 507 508 /* [3] : submit the DMA, but do not issue it. */ 509 desc->callback = dma_rx_callback; 510 desc->callback_param = s; 511 dmaengine_submit(desc); 512 dma_async_issue_pending(channel); 513 return 0; 514 } 515 516 static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s) 517 { 518 if (s->tx_dma_chan) { 519 dma_release_channel(s->tx_dma_chan); 520 s->tx_dma_chan = NULL; 521 } 522 if (s->rx_dma_chan) { 523 dma_release_channel(s->rx_dma_chan); 524 s->rx_dma_chan = NULL; 525 } 526 527 kfree(s->tx_dma_buf); 528 kfree(s->rx_dma_buf); 529 s->tx_dma_buf = NULL; 530 s->rx_dma_buf = NULL; 531 } 532 533 static void mxs_auart_dma_exit(struct mxs_auart_port *s) 534 { 535 536 writel(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR, 537 s->port.membase + AUART_CTRL2_CLR); 538 539 mxs_auart_dma_exit_channel(s); 540 s->flags &= ~MXS_AUART_DMA_ENABLED; 541 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); 542 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags); 543 } 544 545 static int mxs_auart_dma_init(struct mxs_auart_port *s) 546 { 547 dma_cap_mask_t mask; 548 549 if (auart_dma_enabled(s)) 550 return 0; 551 552 /* We do not get the right DMA channels. */ 553 if (s->dma_channel_rx == -1 || s->dma_channel_rx == -1) 554 return -EINVAL; 555 556 /* init for RX */ 557 dma_cap_zero(mask); 558 dma_cap_set(DMA_SLAVE, mask); 559 s->dma_channel = s->dma_channel_rx; 560 s->dma_data.chan_irq = s->dma_irq_rx; 561 s->rx_dma_chan = dma_request_channel(mask, mxs_auart_dma_filter, s); 562 if (!s->rx_dma_chan) 563 goto err_out; 564 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA); 565 if (!s->rx_dma_buf) 566 goto err_out; 567 568 /* init for TX */ 569 s->dma_channel = s->dma_channel_tx; 570 s->dma_data.chan_irq = s->dma_irq_tx; 571 s->tx_dma_chan = dma_request_channel(mask, mxs_auart_dma_filter, s); 572 if (!s->tx_dma_chan) 573 goto err_out; 574 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA); 575 if (!s->tx_dma_buf) 576 goto err_out; 577 578 /* set the flags */ 579 s->flags |= MXS_AUART_DMA_ENABLED; 580 dev_dbg(s->dev, "enabled the DMA support."); 581 582 return 0; 583 584 err_out: 585 mxs_auart_dma_exit_channel(s); 586 return -EINVAL; 587 588 } 589 590 static void mxs_auart_settermios(struct uart_port *u, 591 struct ktermios *termios, 592 struct ktermios *old) 593 { 594 struct mxs_auart_port *s = to_auart_port(u); 595 u32 bm, ctrl, ctrl2, div; 596 unsigned int cflag, baud; 597 598 cflag = termios->c_cflag; 599 600 ctrl = AUART_LINECTRL_FEN; 601 ctrl2 = readl(u->membase + AUART_CTRL2); 602 603 /* byte size */ 604 switch (cflag & CSIZE) { 605 case CS5: 606 bm = 0; 607 break; 608 case CS6: 609 bm = 1; 610 break; 611 case CS7: 612 bm = 2; 613 break; 614 case CS8: 615 bm = 3; 616 break; 617 default: 618 return; 619 } 620 621 ctrl |= AUART_LINECTRL_WLEN(bm); 622 623 /* parity */ 624 if (cflag & PARENB) { 625 ctrl |= AUART_LINECTRL_PEN; 626 if ((cflag & PARODD) == 0) 627 ctrl |= AUART_LINECTRL_EPS; 628 } 629 630 u->read_status_mask = 0; 631 632 if (termios->c_iflag & INPCK) 633 u->read_status_mask |= AUART_STAT_PERR; 634 if (termios->c_iflag & (BRKINT | PARMRK)) 635 u->read_status_mask |= AUART_STAT_BERR; 636 637 /* 638 * Characters to ignore 639 */ 640 u->ignore_status_mask = 0; 641 if (termios->c_iflag & IGNPAR) 642 u->ignore_status_mask |= AUART_STAT_PERR; 643 if (termios->c_iflag & IGNBRK) { 644 u->ignore_status_mask |= AUART_STAT_BERR; 645 /* 646 * If we're ignoring parity and break indicators, 647 * ignore overruns too (for real raw support). 648 */ 649 if (termios->c_iflag & IGNPAR) 650 u->ignore_status_mask |= AUART_STAT_OERR; 651 } 652 653 /* 654 * ignore all characters if CREAD is not set 655 */ 656 if (cflag & CREAD) 657 ctrl2 |= AUART_CTRL2_RXE; 658 else 659 ctrl2 &= ~AUART_CTRL2_RXE; 660 661 /* figure out the stop bits requested */ 662 if (cflag & CSTOPB) 663 ctrl |= AUART_LINECTRL_STP2; 664 665 /* figure out the hardware flow control settings */ 666 if (cflag & CRTSCTS) { 667 /* 668 * The DMA has a bug(see errata:2836) in mx23. 669 * So we can not implement the DMA for auart in mx23, 670 * we can only implement the DMA support for auart 671 * in mx28. 672 */ 673 if (is_imx28_auart(s) && (s->flags & MXS_AUART_DMA_CONFIG)) { 674 if (!mxs_auart_dma_init(s)) 675 /* enable DMA tranfer */ 676 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE 677 | AUART_CTRL2_DMAONERR; 678 } 679 ctrl2 |= AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN; 680 } else { 681 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN); 682 } 683 684 /* set baud rate */ 685 baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk); 686 div = u->uartclk * 32 / baud; 687 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F); 688 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6); 689 690 writel(ctrl, u->membase + AUART_LINECTRL); 691 writel(ctrl2, u->membase + AUART_CTRL2); 692 693 uart_update_timeout(u, termios->c_cflag, baud); 694 695 /* prepare for the DMA RX. */ 696 if (auart_dma_enabled(s) && 697 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) { 698 if (!mxs_auart_dma_prep_rx(s)) { 699 /* Disable the normal RX interrupt. */ 700 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN, 701 u->membase + AUART_INTR_CLR); 702 } else { 703 mxs_auart_dma_exit(s); 704 dev_err(s->dev, "We can not start up the DMA.\n"); 705 } 706 } 707 } 708 709 static irqreturn_t mxs_auart_irq_handle(int irq, void *context) 710 { 711 u32 istatus, istat; 712 struct mxs_auart_port *s = context; 713 u32 stat = readl(s->port.membase + AUART_STAT); 714 715 istatus = istat = readl(s->port.membase + AUART_INTR); 716 717 if (istat & AUART_INTR_CTSMIS) { 718 uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS); 719 writel(AUART_INTR_CTSMIS, 720 s->port.membase + AUART_INTR_CLR); 721 istat &= ~AUART_INTR_CTSMIS; 722 } 723 724 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) { 725 if (!auart_dma_enabled(s)) 726 mxs_auart_rx_chars(s); 727 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS); 728 } 729 730 if (istat & AUART_INTR_TXIS) { 731 mxs_auart_tx_chars(s); 732 istat &= ~AUART_INTR_TXIS; 733 } 734 735 writel(istatus & (AUART_INTR_RTIS 736 | AUART_INTR_TXIS 737 | AUART_INTR_RXIS 738 | AUART_INTR_CTSMIS), 739 s->port.membase + AUART_INTR_CLR); 740 741 return IRQ_HANDLED; 742 } 743 744 static void mxs_auart_reset(struct uart_port *u) 745 { 746 int i; 747 unsigned int reg; 748 749 writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR); 750 751 for (i = 0; i < 10000; i++) { 752 reg = readl(u->membase + AUART_CTRL0); 753 if (!(reg & AUART_CTRL0_SFTRST)) 754 break; 755 udelay(3); 756 } 757 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR); 758 } 759 760 static int mxs_auart_startup(struct uart_port *u) 761 { 762 struct mxs_auart_port *s = to_auart_port(u); 763 764 clk_prepare_enable(s->clk); 765 766 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR); 767 768 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET); 769 770 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN, 771 u->membase + AUART_INTR); 772 773 /* 774 * Enable fifo so all four bytes of a DMA word are written to 775 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes) 776 */ 777 writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET); 778 779 return 0; 780 } 781 782 static void mxs_auart_shutdown(struct uart_port *u) 783 { 784 struct mxs_auart_port *s = to_auart_port(u); 785 786 if (auart_dma_enabled(s)) 787 mxs_auart_dma_exit(s); 788 789 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR); 790 791 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN, 792 u->membase + AUART_INTR_CLR); 793 794 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET); 795 796 clk_disable_unprepare(s->clk); 797 } 798 799 static unsigned int mxs_auart_tx_empty(struct uart_port *u) 800 { 801 if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE) 802 return TIOCSER_TEMT; 803 else 804 return 0; 805 } 806 807 static void mxs_auart_start_tx(struct uart_port *u) 808 { 809 struct mxs_auart_port *s = to_auart_port(u); 810 811 /* enable transmitter */ 812 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET); 813 814 mxs_auart_tx_chars(s); 815 } 816 817 static void mxs_auart_stop_tx(struct uart_port *u) 818 { 819 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR); 820 } 821 822 static void mxs_auart_stop_rx(struct uart_port *u) 823 { 824 writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR); 825 } 826 827 static void mxs_auart_break_ctl(struct uart_port *u, int ctl) 828 { 829 if (ctl) 830 writel(AUART_LINECTRL_BRK, 831 u->membase + AUART_LINECTRL_SET); 832 else 833 writel(AUART_LINECTRL_BRK, 834 u->membase + AUART_LINECTRL_CLR); 835 } 836 837 static void mxs_auart_enable_ms(struct uart_port *port) 838 { 839 /* just empty */ 840 } 841 842 static struct uart_ops mxs_auart_ops = { 843 .tx_empty = mxs_auart_tx_empty, 844 .start_tx = mxs_auart_start_tx, 845 .stop_tx = mxs_auart_stop_tx, 846 .stop_rx = mxs_auart_stop_rx, 847 .enable_ms = mxs_auart_enable_ms, 848 .break_ctl = mxs_auart_break_ctl, 849 .set_mctrl = mxs_auart_set_mctrl, 850 .get_mctrl = mxs_auart_get_mctrl, 851 .startup = mxs_auart_startup, 852 .shutdown = mxs_auart_shutdown, 853 .set_termios = mxs_auart_settermios, 854 .type = mxs_auart_type, 855 .release_port = mxs_auart_release_port, 856 .request_port = mxs_auart_request_port, 857 .config_port = mxs_auart_config_port, 858 .verify_port = mxs_auart_verify_port, 859 }; 860 861 static struct mxs_auart_port *auart_port[MXS_AUART_PORTS]; 862 863 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE 864 static void mxs_auart_console_putchar(struct uart_port *port, int ch) 865 { 866 unsigned int to = 1000; 867 868 while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) { 869 if (!to--) 870 break; 871 udelay(1); 872 } 873 874 writel(ch, port->membase + AUART_DATA); 875 } 876 877 static void 878 auart_console_write(struct console *co, const char *str, unsigned int count) 879 { 880 struct mxs_auart_port *s; 881 struct uart_port *port; 882 unsigned int old_ctrl0, old_ctrl2; 883 unsigned int to = 1000; 884 885 if (co->index > MXS_AUART_PORTS || co->index < 0) 886 return; 887 888 s = auart_port[co->index]; 889 port = &s->port; 890 891 clk_enable(s->clk); 892 893 /* First save the CR then disable the interrupts */ 894 old_ctrl2 = readl(port->membase + AUART_CTRL2); 895 old_ctrl0 = readl(port->membase + AUART_CTRL0); 896 897 writel(AUART_CTRL0_CLKGATE, 898 port->membase + AUART_CTRL0_CLR); 899 writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, 900 port->membase + AUART_CTRL2_SET); 901 902 uart_console_write(port, str, count, mxs_auart_console_putchar); 903 904 /* 905 * Finally, wait for transmitter to become empty 906 * and restore the TCR 907 */ 908 while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) { 909 if (!to--) 910 break; 911 udelay(1); 912 } 913 914 writel(old_ctrl0, port->membase + AUART_CTRL0); 915 writel(old_ctrl2, port->membase + AUART_CTRL2); 916 917 clk_disable(s->clk); 918 } 919 920 static void __init 921 auart_console_get_options(struct uart_port *port, int *baud, 922 int *parity, int *bits) 923 { 924 unsigned int lcr_h, quot; 925 926 if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN)) 927 return; 928 929 lcr_h = readl(port->membase + AUART_LINECTRL); 930 931 *parity = 'n'; 932 if (lcr_h & AUART_LINECTRL_PEN) { 933 if (lcr_h & AUART_LINECTRL_EPS) 934 *parity = 'e'; 935 else 936 *parity = 'o'; 937 } 938 939 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2)) 940 *bits = 7; 941 else 942 *bits = 8; 943 944 quot = ((readl(port->membase + AUART_LINECTRL) 945 & AUART_LINECTRL_BAUD_DIVINT_MASK)) 946 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6); 947 quot |= ((readl(port->membase + AUART_LINECTRL) 948 & AUART_LINECTRL_BAUD_DIVFRAC_MASK)) 949 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT; 950 if (quot == 0) 951 quot = 1; 952 953 *baud = (port->uartclk << 2) / quot; 954 } 955 956 static int __init 957 auart_console_setup(struct console *co, char *options) 958 { 959 struct mxs_auart_port *s; 960 int baud = 9600; 961 int bits = 8; 962 int parity = 'n'; 963 int flow = 'n'; 964 int ret; 965 966 /* 967 * Check whether an invalid uart number has been specified, and 968 * if so, search for the first available port that does have 969 * console support. 970 */ 971 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port)) 972 co->index = 0; 973 s = auart_port[co->index]; 974 if (!s) 975 return -ENODEV; 976 977 clk_prepare_enable(s->clk); 978 979 if (options) 980 uart_parse_options(options, &baud, &parity, &bits, &flow); 981 else 982 auart_console_get_options(&s->port, &baud, &parity, &bits); 983 984 ret = uart_set_options(&s->port, co, baud, parity, bits, flow); 985 986 clk_disable_unprepare(s->clk); 987 988 return ret; 989 } 990 991 static struct console auart_console = { 992 .name = "ttyAPP", 993 .write = auart_console_write, 994 .device = uart_console_device, 995 .setup = auart_console_setup, 996 .flags = CON_PRINTBUFFER, 997 .index = -1, 998 .data = &auart_driver, 999 }; 1000 #endif 1001 1002 static struct uart_driver auart_driver = { 1003 .owner = THIS_MODULE, 1004 .driver_name = "ttyAPP", 1005 .dev_name = "ttyAPP", 1006 .major = 0, 1007 .minor = 0, 1008 .nr = MXS_AUART_PORTS, 1009 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE 1010 .cons = &auart_console, 1011 #endif 1012 }; 1013 1014 /* 1015 * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it 1016 * could successfully get all information from dt or a negative errno. 1017 */ 1018 static int serial_mxs_probe_dt(struct mxs_auart_port *s, 1019 struct platform_device *pdev) 1020 { 1021 struct device_node *np = pdev->dev.of_node; 1022 u32 dma_channel[2]; 1023 int ret; 1024 1025 if (!np) 1026 /* no device tree device */ 1027 return 1; 1028 1029 ret = of_alias_get_id(np, "serial"); 1030 if (ret < 0) { 1031 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret); 1032 return ret; 1033 } 1034 s->port.line = ret; 1035 1036 s->dma_irq_rx = platform_get_irq(pdev, 1); 1037 s->dma_irq_tx = platform_get_irq(pdev, 2); 1038 1039 ret = of_property_read_u32_array(np, "fsl,auart-dma-channel", 1040 dma_channel, 2); 1041 if (ret == 0) { 1042 s->dma_channel_rx = dma_channel[0]; 1043 s->dma_channel_tx = dma_channel[1]; 1044 1045 s->flags |= MXS_AUART_DMA_CONFIG; 1046 } else { 1047 s->dma_channel_rx = -1; 1048 s->dma_channel_tx = -1; 1049 } 1050 return 0; 1051 } 1052 1053 static int mxs_auart_probe(struct platform_device *pdev) 1054 { 1055 const struct of_device_id *of_id = 1056 of_match_device(mxs_auart_dt_ids, &pdev->dev); 1057 struct mxs_auart_port *s; 1058 u32 version; 1059 int ret = 0; 1060 struct resource *r; 1061 struct pinctrl *pinctrl; 1062 1063 s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL); 1064 if (!s) { 1065 ret = -ENOMEM; 1066 goto out; 1067 } 1068 1069 ret = serial_mxs_probe_dt(s, pdev); 1070 if (ret > 0) 1071 s->port.line = pdev->id < 0 ? 0 : pdev->id; 1072 else if (ret < 0) 1073 goto out_free; 1074 1075 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 1076 if (IS_ERR(pinctrl)) { 1077 ret = PTR_ERR(pinctrl); 1078 goto out_free; 1079 } 1080 1081 if (of_id) { 1082 pdev->id_entry = of_id->data; 1083 s->devtype = pdev->id_entry->driver_data; 1084 } 1085 1086 s->clk = clk_get(&pdev->dev, NULL); 1087 if (IS_ERR(s->clk)) { 1088 ret = PTR_ERR(s->clk); 1089 goto out_free; 1090 } 1091 1092 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1093 if (!r) { 1094 ret = -ENXIO; 1095 goto out_free_clk; 1096 } 1097 1098 s->port.mapbase = r->start; 1099 s->port.membase = ioremap(r->start, resource_size(r)); 1100 s->port.ops = &mxs_auart_ops; 1101 s->port.iotype = UPIO_MEM; 1102 s->port.fifosize = 16; 1103 s->port.uartclk = clk_get_rate(s->clk); 1104 s->port.type = PORT_IMX; 1105 s->port.dev = s->dev = get_device(&pdev->dev); 1106 1107 s->ctrl = 0; 1108 1109 s->irq = platform_get_irq(pdev, 0); 1110 s->port.irq = s->irq; 1111 ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s); 1112 if (ret) 1113 goto out_free_clk; 1114 1115 platform_set_drvdata(pdev, s); 1116 1117 auart_port[s->port.line] = s; 1118 1119 mxs_auart_reset(&s->port); 1120 1121 ret = uart_add_one_port(&auart_driver, &s->port); 1122 if (ret) 1123 goto out_free_irq; 1124 1125 version = readl(s->port.membase + AUART_VERSION); 1126 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n", 1127 (version >> 24) & 0xff, 1128 (version >> 16) & 0xff, version & 0xffff); 1129 1130 return 0; 1131 1132 out_free_irq: 1133 auart_port[pdev->id] = NULL; 1134 free_irq(s->irq, s); 1135 out_free_clk: 1136 put_device(s->dev); 1137 clk_put(s->clk); 1138 out_free: 1139 kfree(s); 1140 out: 1141 return ret; 1142 } 1143 1144 static int mxs_auart_remove(struct platform_device *pdev) 1145 { 1146 struct mxs_auart_port *s = platform_get_drvdata(pdev); 1147 1148 uart_remove_one_port(&auart_driver, &s->port); 1149 1150 auart_port[pdev->id] = NULL; 1151 1152 put_device(s->dev); 1153 clk_put(s->clk); 1154 free_irq(s->irq, s); 1155 kfree(s); 1156 1157 return 0; 1158 } 1159 1160 static struct platform_driver mxs_auart_driver = { 1161 .probe = mxs_auart_probe, 1162 .remove = mxs_auart_remove, 1163 .driver = { 1164 .name = "mxs-auart", 1165 .owner = THIS_MODULE, 1166 .of_match_table = mxs_auart_dt_ids, 1167 }, 1168 }; 1169 1170 static int __init mxs_auart_init(void) 1171 { 1172 int r; 1173 1174 r = uart_register_driver(&auart_driver); 1175 if (r) 1176 goto out; 1177 1178 r = platform_driver_register(&mxs_auart_driver); 1179 if (r) 1180 goto out_err; 1181 1182 return 0; 1183 out_err: 1184 uart_unregister_driver(&auart_driver); 1185 out: 1186 return r; 1187 } 1188 1189 static void __exit mxs_auart_exit(void) 1190 { 1191 platform_driver_unregister(&mxs_auart_driver); 1192 uart_unregister_driver(&auart_driver); 1193 } 1194 1195 module_init(mxs_auart_init); 1196 module_exit(mxs_auart_exit); 1197 MODULE_LICENSE("GPL"); 1198 MODULE_DESCRIPTION("Freescale MXS application uart driver"); 1199 MODULE_ALIAS("platform:mxs-auart"); 1200