1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * *************************************************************************** 4 * Marvell Armada-3700 Serial Driver 5 * Author: Wilson Ding <dingwei@marvell.com> 6 * Copyright (C) 2015 Marvell International Ltd. 7 * *************************************************************************** 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/console.h> 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/init.h> 16 #include <linux/io.h> 17 #include <linux/iopoll.h> 18 #include <linux/math64.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_device.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_platform.h> 24 #include <linux/platform_device.h> 25 #include <linux/serial.h> 26 #include <linux/serial_core.h> 27 #include <linux/slab.h> 28 #include <linux/tty.h> 29 #include <linux/tty_flip.h> 30 31 /* Register Map */ 32 #define UART_STD_RBR 0x00 33 #define UART_EXT_RBR 0x18 34 35 #define UART_STD_TSH 0x04 36 #define UART_EXT_TSH 0x1C 37 38 #define UART_STD_CTRL1 0x08 39 #define UART_EXT_CTRL1 0x04 40 #define CTRL_SOFT_RST BIT(31) 41 #define CTRL_TXFIFO_RST BIT(15) 42 #define CTRL_RXFIFO_RST BIT(14) 43 #define CTRL_SND_BRK_SEQ BIT(11) 44 #define CTRL_BRK_DET_INT BIT(3) 45 #define CTRL_FRM_ERR_INT BIT(2) 46 #define CTRL_PAR_ERR_INT BIT(1) 47 #define CTRL_OVR_ERR_INT BIT(0) 48 #define CTRL_BRK_INT (CTRL_BRK_DET_INT | CTRL_FRM_ERR_INT | \ 49 CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT) 50 51 #define UART_STD_CTRL2 UART_STD_CTRL1 52 #define UART_EXT_CTRL2 0x20 53 #define CTRL_STD_TX_RDY_INT BIT(5) 54 #define CTRL_EXT_TX_RDY_INT BIT(6) 55 #define CTRL_STD_RX_RDY_INT BIT(4) 56 #define CTRL_EXT_RX_RDY_INT BIT(5) 57 58 #define UART_STAT 0x0C 59 #define STAT_TX_FIFO_EMP BIT(13) 60 #define STAT_TX_FIFO_FUL BIT(11) 61 #define STAT_TX_EMP BIT(6) 62 #define STAT_STD_TX_RDY BIT(5) 63 #define STAT_EXT_TX_RDY BIT(15) 64 #define STAT_STD_RX_RDY BIT(4) 65 #define STAT_EXT_RX_RDY BIT(14) 66 #define STAT_BRK_DET BIT(3) 67 #define STAT_FRM_ERR BIT(2) 68 #define STAT_PAR_ERR BIT(1) 69 #define STAT_OVR_ERR BIT(0) 70 #define STAT_BRK_ERR (STAT_BRK_DET | STAT_FRM_ERR \ 71 | STAT_PAR_ERR | STAT_OVR_ERR) 72 73 /* 74 * Marvell Armada 3700 Functional Specifications describes that bit 21 of UART 75 * Clock Control register controls UART1 and bit 20 controls UART2. But in 76 * reality bit 21 controls UART2 and bit 20 controls UART1. This seems to be an 77 * error in Marvell's documentation. Hence following CLK_DIS macros are swapped. 78 */ 79 80 #define UART_BRDV 0x10 81 /* These bits are located in UART1 address space and control UART2 */ 82 #define UART2_CLK_DIS BIT(21) 83 /* These bits are located in UART1 address space and control UART1 */ 84 #define UART1_CLK_DIS BIT(20) 85 /* These bits are located in UART1 address space and control both UARTs */ 86 #define CLK_NO_XTAL BIT(19) 87 #define CLK_TBG_DIV1_SHIFT 15 88 #define CLK_TBG_DIV1_MASK 0x7 89 #define CLK_TBG_DIV1_MAX 6 90 #define CLK_TBG_DIV2_SHIFT 12 91 #define CLK_TBG_DIV2_MASK 0x7 92 #define CLK_TBG_DIV2_MAX 6 93 #define CLK_TBG_SEL_SHIFT 10 94 #define CLK_TBG_SEL_MASK 0x3 95 /* These bits are located in both UARTs address space */ 96 #define BRDV_BAUD_MASK 0x3FF 97 #define BRDV_BAUD_MAX BRDV_BAUD_MASK 98 99 #define UART_OSAMP 0x14 100 #define OSAMP_DEFAULT_DIVISOR 16 101 #define OSAMP_DIVISORS_MASK 0x3F3F3F3F 102 #define OSAMP_MAX_DIVISOR 63 103 104 #define MVEBU_NR_UARTS 2 105 106 #define MVEBU_UART_TYPE "mvebu-uart" 107 #define DRIVER_NAME "mvebu_serial" 108 109 enum { 110 /* Either there is only one summed IRQ... */ 111 UART_IRQ_SUM = 0, 112 /* ...or there are two separate IRQ for RX and TX */ 113 UART_RX_IRQ = 0, 114 UART_TX_IRQ, 115 UART_IRQ_COUNT 116 }; 117 118 /* Diverging register offsets */ 119 struct uart_regs_layout { 120 unsigned int rbr; 121 unsigned int tsh; 122 unsigned int ctrl; 123 unsigned int intr; 124 }; 125 126 /* Diverging flags */ 127 struct uart_flags { 128 unsigned int ctrl_tx_rdy_int; 129 unsigned int ctrl_rx_rdy_int; 130 unsigned int stat_tx_rdy; 131 unsigned int stat_rx_rdy; 132 }; 133 134 /* Driver data, a structure for each UART port */ 135 struct mvebu_uart_driver_data { 136 bool is_ext; 137 struct uart_regs_layout regs; 138 struct uart_flags flags; 139 }; 140 141 /* Saved registers during suspend */ 142 struct mvebu_uart_pm_regs { 143 unsigned int rbr; 144 unsigned int tsh; 145 unsigned int ctrl; 146 unsigned int intr; 147 unsigned int stat; 148 unsigned int brdv; 149 unsigned int osamp; 150 }; 151 152 /* MVEBU UART driver structure */ 153 struct mvebu_uart { 154 struct uart_port *port; 155 struct clk *clk; 156 int irq[UART_IRQ_COUNT]; 157 struct mvebu_uart_driver_data *data; 158 #if defined(CONFIG_PM) 159 struct mvebu_uart_pm_regs pm_regs; 160 #endif /* CONFIG_PM */ 161 }; 162 163 static struct mvebu_uart *to_mvuart(struct uart_port *port) 164 { 165 return (struct mvebu_uart *)port->private_data; 166 } 167 168 #define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext) 169 170 #define UART_RBR(port) (to_mvuart(port)->data->regs.rbr) 171 #define UART_TSH(port) (to_mvuart(port)->data->regs.tsh) 172 #define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl) 173 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr) 174 175 #define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int) 176 #define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int) 177 #define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy) 178 #define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy) 179 180 static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS]; 181 182 static DEFINE_SPINLOCK(mvebu_uart_lock); 183 184 /* Core UART Driver Operations */ 185 static unsigned int mvebu_uart_tx_empty(struct uart_port *port) 186 { 187 unsigned long flags; 188 unsigned int st; 189 190 uart_port_lock_irqsave(port, &flags); 191 st = readl(port->membase + UART_STAT); 192 uart_port_unlock_irqrestore(port, flags); 193 194 return (st & STAT_TX_EMP) ? TIOCSER_TEMT : 0; 195 } 196 197 static unsigned int mvebu_uart_get_mctrl(struct uart_port *port) 198 { 199 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 200 } 201 202 static void mvebu_uart_set_mctrl(struct uart_port *port, 203 unsigned int mctrl) 204 { 205 /* 206 * Even if we do not support configuring the modem control lines, this 207 * function must be proided to the serial core 208 */ 209 } 210 211 static void mvebu_uart_stop_tx(struct uart_port *port) 212 { 213 unsigned int ctl = readl(port->membase + UART_INTR(port)); 214 215 ctl &= ~CTRL_TX_RDY_INT(port); 216 writel(ctl, port->membase + UART_INTR(port)); 217 } 218 219 static void mvebu_uart_start_tx(struct uart_port *port) 220 { 221 unsigned int ctl; 222 unsigned char c; 223 224 if (IS_EXTENDED(port) && uart_fifo_get(port, &c)) 225 writel(c, port->membase + UART_TSH(port)); 226 227 ctl = readl(port->membase + UART_INTR(port)); 228 ctl |= CTRL_TX_RDY_INT(port); 229 writel(ctl, port->membase + UART_INTR(port)); 230 } 231 232 static void mvebu_uart_stop_rx(struct uart_port *port) 233 { 234 unsigned int ctl; 235 236 ctl = readl(port->membase + UART_CTRL(port)); 237 ctl &= ~CTRL_BRK_INT; 238 writel(ctl, port->membase + UART_CTRL(port)); 239 240 ctl = readl(port->membase + UART_INTR(port)); 241 ctl &= ~CTRL_RX_RDY_INT(port); 242 writel(ctl, port->membase + UART_INTR(port)); 243 } 244 245 static void mvebu_uart_break_ctl(struct uart_port *port, int brk) 246 { 247 unsigned int ctl; 248 unsigned long flags; 249 250 uart_port_lock_irqsave(port, &flags); 251 ctl = readl(port->membase + UART_CTRL(port)); 252 if (brk == -1) 253 ctl |= CTRL_SND_BRK_SEQ; 254 else 255 ctl &= ~CTRL_SND_BRK_SEQ; 256 writel(ctl, port->membase + UART_CTRL(port)); 257 uart_port_unlock_irqrestore(port, flags); 258 } 259 260 static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status) 261 { 262 struct tty_port *tport = &port->state->port; 263 unsigned char ch = 0; 264 char flag = 0; 265 int ret; 266 267 do { 268 if (status & STAT_RX_RDY(port)) { 269 ch = readl(port->membase + UART_RBR(port)); 270 ch &= 0xff; 271 flag = TTY_NORMAL; 272 port->icount.rx++; 273 274 if (status & STAT_PAR_ERR) 275 port->icount.parity++; 276 } 277 278 /* 279 * For UART2, error bits are not cleared on buffer read. 280 * This causes interrupt loop and system hang. 281 */ 282 if (IS_EXTENDED(port) && (status & STAT_BRK_ERR)) { 283 ret = readl(port->membase + UART_STAT); 284 ret |= STAT_BRK_ERR; 285 writel(ret, port->membase + UART_STAT); 286 } 287 288 if (status & STAT_BRK_DET) { 289 port->icount.brk++; 290 status &= ~(STAT_FRM_ERR | STAT_PAR_ERR); 291 if (uart_handle_break(port)) 292 goto ignore_char; 293 } 294 295 if (status & STAT_OVR_ERR) 296 port->icount.overrun++; 297 298 if (status & STAT_FRM_ERR) 299 port->icount.frame++; 300 301 if (uart_handle_sysrq_char(port, ch)) 302 goto ignore_char; 303 304 if (status & port->ignore_status_mask & STAT_PAR_ERR) 305 status &= ~STAT_RX_RDY(port); 306 307 status &= port->read_status_mask; 308 309 if (status & STAT_PAR_ERR) 310 flag = TTY_PARITY; 311 312 status &= ~port->ignore_status_mask; 313 314 if (status & STAT_RX_RDY(port)) 315 tty_insert_flip_char(tport, ch, flag); 316 317 if (status & STAT_BRK_DET) 318 tty_insert_flip_char(tport, 0, TTY_BREAK); 319 320 if (status & STAT_FRM_ERR) 321 tty_insert_flip_char(tport, 0, TTY_FRAME); 322 323 if (status & STAT_OVR_ERR) 324 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 325 326 ignore_char: 327 status = readl(port->membase + UART_STAT); 328 } while (status & (STAT_RX_RDY(port) | STAT_BRK_DET)); 329 330 tty_flip_buffer_push(tport); 331 } 332 333 static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status) 334 { 335 u8 ch; 336 337 uart_port_tx_limited(port, ch, port->fifosize, 338 !(readl(port->membase + UART_STAT) & STAT_TX_FIFO_FUL), 339 writel(ch, port->membase + UART_TSH(port)), 340 ({})); 341 } 342 343 static irqreturn_t mvebu_uart_isr(int irq, void *dev_id) 344 { 345 struct uart_port *port = (struct uart_port *)dev_id; 346 unsigned int st = readl(port->membase + UART_STAT); 347 348 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR | 349 STAT_BRK_DET)) 350 mvebu_uart_rx_chars(port, st); 351 352 if (st & STAT_TX_RDY(port)) 353 mvebu_uart_tx_chars(port, st); 354 355 return IRQ_HANDLED; 356 } 357 358 static irqreturn_t mvebu_uart_rx_isr(int irq, void *dev_id) 359 { 360 struct uart_port *port = (struct uart_port *)dev_id; 361 unsigned int st = readl(port->membase + UART_STAT); 362 363 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR | 364 STAT_BRK_DET)) 365 mvebu_uart_rx_chars(port, st); 366 367 return IRQ_HANDLED; 368 } 369 370 static irqreturn_t mvebu_uart_tx_isr(int irq, void *dev_id) 371 { 372 struct uart_port *port = (struct uart_port *)dev_id; 373 unsigned int st = readl(port->membase + UART_STAT); 374 375 if (st & STAT_TX_RDY(port)) 376 mvebu_uart_tx_chars(port, st); 377 378 return IRQ_HANDLED; 379 } 380 381 static int mvebu_uart_startup(struct uart_port *port) 382 { 383 struct mvebu_uart *mvuart = to_mvuart(port); 384 unsigned int ctl; 385 int ret; 386 387 writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST, 388 port->membase + UART_CTRL(port)); 389 udelay(1); 390 391 /* Clear the error bits of state register before IRQ request */ 392 ret = readl(port->membase + UART_STAT); 393 ret |= STAT_BRK_ERR; 394 writel(ret, port->membase + UART_STAT); 395 396 writel(CTRL_BRK_INT, port->membase + UART_CTRL(port)); 397 398 ctl = readl(port->membase + UART_INTR(port)); 399 ctl |= CTRL_RX_RDY_INT(port); 400 writel(ctl, port->membase + UART_INTR(port)); 401 402 if (!mvuart->irq[UART_TX_IRQ]) { 403 /* Old bindings with just one interrupt (UART0 only) */ 404 ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM], 405 mvebu_uart_isr, port->irqflags, 406 dev_name(port->dev), port); 407 if (ret) 408 return ret; 409 } else { 410 /* New bindings with an IRQ for RX and TX (both UART) */ 411 ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ], 412 mvebu_uart_rx_isr, port->irqflags, 413 dev_name(port->dev), port); 414 if (ret) 415 return ret; 416 417 ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ], 418 mvebu_uart_tx_isr, port->irqflags, 419 dev_name(port->dev), 420 port); 421 if (ret) { 422 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], 423 port); 424 return ret; 425 } 426 } 427 428 return 0; 429 } 430 431 static void mvebu_uart_shutdown(struct uart_port *port) 432 { 433 struct mvebu_uart *mvuart = to_mvuart(port); 434 435 writel(0, port->membase + UART_INTR(port)); 436 437 if (!mvuart->irq[UART_TX_IRQ]) { 438 devm_free_irq(port->dev, mvuart->irq[UART_IRQ_SUM], port); 439 } else { 440 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], port); 441 devm_free_irq(port->dev, mvuart->irq[UART_TX_IRQ], port); 442 } 443 } 444 445 static unsigned int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud) 446 { 447 unsigned int d_divisor, m_divisor; 448 unsigned long flags; 449 u32 brdv, osamp; 450 451 if (!port->uartclk) 452 return 0; 453 454 /* 455 * The baudrate is derived from the UART clock thanks to divisors: 456 * > d1 * d2 ("TBG divisors"): can divide only TBG clock from 1 to 6 457 * > D ("baud generator"): can divide the clock from 1 to 1023 458 * > M ("fractional divisor"): allows a better accuracy (from 1 to 63) 459 * 460 * Exact formulas for calculating baudrate: 461 * 462 * with default x16 scheme: 463 * baudrate = xtal / (d * 16) 464 * baudrate = tbg / (d1 * d2 * d * 16) 465 * 466 * with fractional divisor: 467 * baudrate = 10 * xtal / (d * (3 * (m1 + m2) + 2 * (m3 + m4))) 468 * baudrate = 10 * tbg / (d1*d2 * d * (3 * (m1 + m2) + 2 * (m3 + m4))) 469 * 470 * Oversampling value: 471 * osamp = (m1 << 0) | (m2 << 8) | (m3 << 16) | (m4 << 24); 472 * 473 * Where m1 controls number of clock cycles per bit for bits 1,2,3; 474 * m2 for bits 4,5,6; m3 for bits 7,8 and m4 for bits 9,10. 475 * 476 * To simplify baudrate setup set all the M prescalers to the same 477 * value. For baudrates 9600 Bd and higher, it is enough to use the 478 * default (x16) divisor or fractional divisor with M = 63, so there 479 * is no need to use real fractional support (where the M prescalers 480 * are not equal). 481 * 482 * When all the M prescalers are zeroed then default (x16) divisor is 483 * used. Default x16 scheme is more stable than M (fractional divisor), 484 * so use M only when D divisor is not enough to derive baudrate. 485 * 486 * Member port->uartclk is either xtal clock rate or TBG clock rate 487 * divided by (d1 * d2). So d1 and d2 are already set by the UART clock 488 * driver (and UART driver itself cannot change them). Moreover they are 489 * shared between both UARTs. 490 */ 491 492 m_divisor = OSAMP_DEFAULT_DIVISOR; 493 d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor); 494 495 if (d_divisor > BRDV_BAUD_MAX) { 496 /* 497 * Experiments show that small M divisors are unstable. 498 * Use maximal possible M = 63 and calculate D divisor. 499 */ 500 m_divisor = OSAMP_MAX_DIVISOR; 501 d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor); 502 } 503 504 if (d_divisor < 1) 505 d_divisor = 1; 506 else if (d_divisor > BRDV_BAUD_MAX) 507 d_divisor = BRDV_BAUD_MAX; 508 509 spin_lock_irqsave(&mvebu_uart_lock, flags); 510 brdv = readl(port->membase + UART_BRDV); 511 brdv &= ~BRDV_BAUD_MASK; 512 brdv |= d_divisor; 513 writel(brdv, port->membase + UART_BRDV); 514 spin_unlock_irqrestore(&mvebu_uart_lock, flags); 515 516 osamp = readl(port->membase + UART_OSAMP); 517 osamp &= ~OSAMP_DIVISORS_MASK; 518 if (m_divisor != OSAMP_DEFAULT_DIVISOR) 519 osamp |= (m_divisor << 0) | (m_divisor << 8) | 520 (m_divisor << 16) | (m_divisor << 24); 521 writel(osamp, port->membase + UART_OSAMP); 522 523 return DIV_ROUND_CLOSEST(port->uartclk, d_divisor * m_divisor); 524 } 525 526 static void mvebu_uart_set_termios(struct uart_port *port, 527 struct ktermios *termios, 528 const struct ktermios *old) 529 { 530 unsigned long flags; 531 unsigned int baud, min_baud, max_baud; 532 533 uart_port_lock_irqsave(port, &flags); 534 535 port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR | 536 STAT_TX_RDY(port) | STAT_TX_FIFO_FUL; 537 538 if (termios->c_iflag & INPCK) 539 port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR; 540 541 port->ignore_status_mask = 0; 542 if (termios->c_iflag & IGNPAR) 543 port->ignore_status_mask |= 544 STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR; 545 546 if ((termios->c_cflag & CREAD) == 0) 547 port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR; 548 549 /* 550 * Maximal divisor is 1023 and maximal fractional divisor is 63. And 551 * experiments show that baudrates above 1/80 of parent clock rate are 552 * not stable. So disallow baudrates above 1/80 of the parent clock 553 * rate. If port->uartclk is not available, then 554 * mvebu_uart_baud_rate_set() fails, so values min_baud and max_baud 555 * in this case do not matter. 556 */ 557 min_baud = DIV_ROUND_UP(port->uartclk, BRDV_BAUD_MAX * 558 OSAMP_MAX_DIVISOR); 559 max_baud = port->uartclk / 80; 560 561 baud = uart_get_baud_rate(port, termios, old, min_baud, max_baud); 562 baud = mvebu_uart_baud_rate_set(port, baud); 563 564 /* In case baudrate cannot be changed, report previous old value */ 565 if (baud == 0 && old) 566 baud = tty_termios_baud_rate(old); 567 568 /* Only the following flag changes are supported */ 569 if (old) { 570 termios->c_iflag &= INPCK | IGNPAR; 571 termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR); 572 termios->c_cflag &= CREAD | CBAUD; 573 termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD); 574 termios->c_cflag |= CS8; 575 } 576 577 if (baud != 0) { 578 tty_termios_encode_baud_rate(termios, baud, baud); 579 uart_update_timeout(port, termios->c_cflag, baud); 580 } 581 582 uart_port_unlock_irqrestore(port, flags); 583 } 584 585 static const char *mvebu_uart_type(struct uart_port *port) 586 { 587 return MVEBU_UART_TYPE; 588 } 589 590 static void mvebu_uart_release_port(struct uart_port *port) 591 { 592 /* Nothing to do here */ 593 } 594 595 static int mvebu_uart_request_port(struct uart_port *port) 596 { 597 return 0; 598 } 599 600 #ifdef CONFIG_CONSOLE_POLL 601 static int mvebu_uart_get_poll_char(struct uart_port *port) 602 { 603 unsigned int st = readl(port->membase + UART_STAT); 604 605 if (!(st & STAT_RX_RDY(port))) 606 return NO_POLL_CHAR; 607 608 return readl(port->membase + UART_RBR(port)); 609 } 610 611 static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c) 612 { 613 unsigned int st; 614 615 for (;;) { 616 st = readl(port->membase + UART_STAT); 617 618 if (!(st & STAT_TX_FIFO_FUL)) 619 break; 620 621 udelay(1); 622 } 623 624 writel(c, port->membase + UART_TSH(port)); 625 } 626 #endif 627 628 static const struct uart_ops mvebu_uart_ops = { 629 .tx_empty = mvebu_uart_tx_empty, 630 .set_mctrl = mvebu_uart_set_mctrl, 631 .get_mctrl = mvebu_uart_get_mctrl, 632 .stop_tx = mvebu_uart_stop_tx, 633 .start_tx = mvebu_uart_start_tx, 634 .stop_rx = mvebu_uart_stop_rx, 635 .break_ctl = mvebu_uart_break_ctl, 636 .startup = mvebu_uart_startup, 637 .shutdown = mvebu_uart_shutdown, 638 .set_termios = mvebu_uart_set_termios, 639 .type = mvebu_uart_type, 640 .release_port = mvebu_uart_release_port, 641 .request_port = mvebu_uart_request_port, 642 #ifdef CONFIG_CONSOLE_POLL 643 .poll_get_char = mvebu_uart_get_poll_char, 644 .poll_put_char = mvebu_uart_put_poll_char, 645 #endif 646 }; 647 648 /* Console Driver Operations */ 649 650 #ifdef CONFIG_SERIAL_MVEBU_CONSOLE 651 /* Early Console */ 652 static void mvebu_uart_putc(struct uart_port *port, unsigned char c) 653 { 654 unsigned int st; 655 656 for (;;) { 657 st = readl(port->membase + UART_STAT); 658 if (!(st & STAT_TX_FIFO_FUL)) 659 break; 660 } 661 662 /* At early stage, DT is not parsed yet, only use UART0 */ 663 writel(c, port->membase + UART_STD_TSH); 664 665 for (;;) { 666 st = readl(port->membase + UART_STAT); 667 if (st & STAT_TX_FIFO_EMP) 668 break; 669 } 670 } 671 672 static void mvebu_uart_putc_early_write(struct console *con, 673 const char *s, 674 unsigned int n) 675 { 676 struct earlycon_device *dev = con->data; 677 678 uart_console_write(&dev->port, s, n, mvebu_uart_putc); 679 } 680 681 static int __init 682 mvebu_uart_early_console_setup(struct earlycon_device *device, 683 const char *opt) 684 { 685 if (!device->port.membase) 686 return -ENODEV; 687 688 device->con->write = mvebu_uart_putc_early_write; 689 690 return 0; 691 } 692 693 EARLYCON_DECLARE(ar3700_uart, mvebu_uart_early_console_setup); 694 OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart", 695 mvebu_uart_early_console_setup); 696 697 static void wait_for_xmitr(struct uart_port *port) 698 { 699 u32 val; 700 701 readl_poll_timeout_atomic(port->membase + UART_STAT, val, 702 (val & STAT_TX_RDY(port)), 1, 10000); 703 } 704 705 static void wait_for_xmite(struct uart_port *port) 706 { 707 u32 val; 708 709 readl_poll_timeout_atomic(port->membase + UART_STAT, val, 710 (val & STAT_TX_EMP), 1, 10000); 711 } 712 713 static void mvebu_uart_console_putchar(struct uart_port *port, unsigned char ch) 714 { 715 wait_for_xmitr(port); 716 writel(ch, port->membase + UART_TSH(port)); 717 } 718 719 static void mvebu_uart_console_write(struct console *co, const char *s, 720 unsigned int count) 721 { 722 struct uart_port *port = &mvebu_uart_ports[co->index]; 723 unsigned long flags; 724 unsigned int ier, intr, ctl; 725 int locked = 1; 726 727 if (oops_in_progress) 728 locked = uart_port_trylock_irqsave(port, &flags); 729 else 730 uart_port_lock_irqsave(port, &flags); 731 732 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT; 733 intr = readl(port->membase + UART_INTR(port)) & 734 (CTRL_RX_RDY_INT(port) | CTRL_TX_RDY_INT(port)); 735 writel(0, port->membase + UART_CTRL(port)); 736 writel(0, port->membase + UART_INTR(port)); 737 738 uart_console_write(port, s, count, mvebu_uart_console_putchar); 739 740 wait_for_xmite(port); 741 742 if (ier) 743 writel(ier, port->membase + UART_CTRL(port)); 744 745 if (intr) { 746 ctl = intr | readl(port->membase + UART_INTR(port)); 747 writel(ctl, port->membase + UART_INTR(port)); 748 } 749 750 if (locked) 751 uart_port_unlock_irqrestore(port, flags); 752 } 753 754 static int mvebu_uart_console_setup(struct console *co, char *options) 755 { 756 struct uart_port *port; 757 int baud = 9600; 758 int bits = 8; 759 int parity = 'n'; 760 int flow = 'n'; 761 762 if (co->index < 0 || co->index >= MVEBU_NR_UARTS) 763 return -EINVAL; 764 765 port = &mvebu_uart_ports[co->index]; 766 767 if (!port->mapbase || !port->membase) { 768 pr_debug("console on ttyMV%i not present\n", co->index); 769 return -ENODEV; 770 } 771 772 if (options) 773 uart_parse_options(options, &baud, &parity, &bits, &flow); 774 775 return uart_set_options(port, co, baud, parity, bits, flow); 776 } 777 778 static struct uart_driver mvebu_uart_driver; 779 780 static struct console mvebu_uart_console = { 781 .name = "ttyMV", 782 .write = mvebu_uart_console_write, 783 .device = uart_console_device, 784 .setup = mvebu_uart_console_setup, 785 .flags = CON_PRINTBUFFER, 786 .index = -1, 787 .data = &mvebu_uart_driver, 788 }; 789 790 static int __init mvebu_uart_console_init(void) 791 { 792 register_console(&mvebu_uart_console); 793 return 0; 794 } 795 796 console_initcall(mvebu_uart_console_init); 797 798 799 #endif /* CONFIG_SERIAL_MVEBU_CONSOLE */ 800 801 static struct uart_driver mvebu_uart_driver = { 802 .owner = THIS_MODULE, 803 .driver_name = DRIVER_NAME, 804 .dev_name = "ttyMV", 805 .nr = MVEBU_NR_UARTS, 806 #ifdef CONFIG_SERIAL_MVEBU_CONSOLE 807 .cons = &mvebu_uart_console, 808 #endif 809 }; 810 811 #if defined(CONFIG_PM) 812 static int mvebu_uart_suspend(struct device *dev) 813 { 814 struct mvebu_uart *mvuart = dev_get_drvdata(dev); 815 struct uart_port *port = mvuart->port; 816 unsigned long flags; 817 818 uart_suspend_port(&mvebu_uart_driver, port); 819 820 mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port)); 821 mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port)); 822 mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port)); 823 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port)); 824 mvuart->pm_regs.stat = readl(port->membase + UART_STAT); 825 spin_lock_irqsave(&mvebu_uart_lock, flags); 826 mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV); 827 spin_unlock_irqrestore(&mvebu_uart_lock, flags); 828 mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP); 829 830 device_set_wakeup_enable(dev, true); 831 832 return 0; 833 } 834 835 static int mvebu_uart_resume(struct device *dev) 836 { 837 struct mvebu_uart *mvuart = dev_get_drvdata(dev); 838 struct uart_port *port = mvuart->port; 839 unsigned long flags; 840 841 writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port)); 842 writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port)); 843 writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port)); 844 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port)); 845 writel(mvuart->pm_regs.stat, port->membase + UART_STAT); 846 spin_lock_irqsave(&mvebu_uart_lock, flags); 847 writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV); 848 spin_unlock_irqrestore(&mvebu_uart_lock, flags); 849 writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP); 850 851 uart_resume_port(&mvebu_uart_driver, port); 852 853 return 0; 854 } 855 856 static const struct dev_pm_ops mvebu_uart_pm_ops = { 857 .suspend = mvebu_uart_suspend, 858 .resume = mvebu_uart_resume, 859 }; 860 #endif /* CONFIG_PM */ 861 862 static const struct of_device_id mvebu_uart_of_match[]; 863 864 /* Counter to keep track of each UART port id when not using CONFIG_OF */ 865 static int uart_num_counter; 866 867 static int mvebu_uart_probe(struct platform_device *pdev) 868 { 869 const struct of_device_id *match = of_match_device(mvebu_uart_of_match, 870 &pdev->dev); 871 struct uart_port *port; 872 struct mvebu_uart *mvuart; 873 struct resource *reg; 874 int id, irq; 875 876 /* Assume that all UART ports have a DT alias or none has */ 877 id = of_alias_get_id(pdev->dev.of_node, "serial"); 878 if (!pdev->dev.of_node || id < 0) 879 pdev->id = uart_num_counter++; 880 else 881 pdev->id = id; 882 883 if (pdev->id >= MVEBU_NR_UARTS) { 884 dev_err(&pdev->dev, "cannot have more than %d UART ports\n", 885 MVEBU_NR_UARTS); 886 return -EINVAL; 887 } 888 889 port = &mvebu_uart_ports[pdev->id]; 890 891 spin_lock_init(&port->lock); 892 893 port->dev = &pdev->dev; 894 port->type = PORT_MVEBU; 895 port->ops = &mvebu_uart_ops; 896 port->regshift = 0; 897 898 port->fifosize = 32; 899 port->iotype = UPIO_MEM32; 900 port->flags = UPF_FIXED_PORT; 901 port->line = pdev->id; 902 903 /* 904 * IRQ number is not stored in this structure because we may have two of 905 * them per port (RX and TX). Instead, use the driver UART structure 906 * array so called ->irq[]. 907 */ 908 port->irq = 0; 909 port->irqflags = 0; 910 911 port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, ®); 912 if (IS_ERR(port->membase)) 913 return PTR_ERR(port->membase); 914 port->mapbase = reg->start; 915 916 mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart), 917 GFP_KERNEL); 918 if (!mvuart) 919 return -ENOMEM; 920 921 /* Get controller data depending on the compatible string */ 922 mvuart->data = (struct mvebu_uart_driver_data *)match->data; 923 mvuart->port = port; 924 925 port->private_data = mvuart; 926 platform_set_drvdata(pdev, mvuart); 927 928 /* Get fixed clock frequency */ 929 mvuart->clk = devm_clk_get(&pdev->dev, NULL); 930 if (IS_ERR(mvuart->clk)) { 931 if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER) 932 return PTR_ERR(mvuart->clk); 933 934 if (IS_EXTENDED(port)) { 935 dev_err(&pdev->dev, "unable to get UART clock\n"); 936 return PTR_ERR(mvuart->clk); 937 } 938 } else { 939 if (!clk_prepare_enable(mvuart->clk)) 940 port->uartclk = clk_get_rate(mvuart->clk); 941 } 942 943 /* Manage interrupts */ 944 if (platform_irq_count(pdev) == 1) { 945 /* Old bindings: no name on the single unamed UART0 IRQ */ 946 irq = platform_get_irq(pdev, 0); 947 if (irq < 0) 948 return irq; 949 950 mvuart->irq[UART_IRQ_SUM] = irq; 951 } else { 952 /* 953 * New bindings: named interrupts (RX, TX) for both UARTS, 954 * only make use of uart-rx and uart-tx interrupts, do not use 955 * uart-sum of UART0 port. 956 */ 957 irq = platform_get_irq_byname(pdev, "uart-rx"); 958 if (irq < 0) 959 return irq; 960 961 mvuart->irq[UART_RX_IRQ] = irq; 962 963 irq = platform_get_irq_byname(pdev, "uart-tx"); 964 if (irq < 0) 965 return irq; 966 967 mvuart->irq[UART_TX_IRQ] = irq; 968 } 969 970 /* UART Soft Reset*/ 971 writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port)); 972 udelay(1); 973 writel(0, port->membase + UART_CTRL(port)); 974 975 return uart_add_one_port(&mvebu_uart_driver, port); 976 } 977 978 static struct mvebu_uart_driver_data uart_std_driver_data = { 979 .is_ext = false, 980 .regs.rbr = UART_STD_RBR, 981 .regs.tsh = UART_STD_TSH, 982 .regs.ctrl = UART_STD_CTRL1, 983 .regs.intr = UART_STD_CTRL2, 984 .flags.ctrl_tx_rdy_int = CTRL_STD_TX_RDY_INT, 985 .flags.ctrl_rx_rdy_int = CTRL_STD_RX_RDY_INT, 986 .flags.stat_tx_rdy = STAT_STD_TX_RDY, 987 .flags.stat_rx_rdy = STAT_STD_RX_RDY, 988 }; 989 990 static struct mvebu_uart_driver_data uart_ext_driver_data = { 991 .is_ext = true, 992 .regs.rbr = UART_EXT_RBR, 993 .regs.tsh = UART_EXT_TSH, 994 .regs.ctrl = UART_EXT_CTRL1, 995 .regs.intr = UART_EXT_CTRL2, 996 .flags.ctrl_tx_rdy_int = CTRL_EXT_TX_RDY_INT, 997 .flags.ctrl_rx_rdy_int = CTRL_EXT_RX_RDY_INT, 998 .flags.stat_tx_rdy = STAT_EXT_TX_RDY, 999 .flags.stat_rx_rdy = STAT_EXT_RX_RDY, 1000 }; 1001 1002 /* Match table for of_platform binding */ 1003 static const struct of_device_id mvebu_uart_of_match[] = { 1004 { 1005 .compatible = "marvell,armada-3700-uart", 1006 .data = (void *)&uart_std_driver_data, 1007 }, 1008 { 1009 .compatible = "marvell,armada-3700-uart-ext", 1010 .data = (void *)&uart_ext_driver_data, 1011 }, 1012 {} 1013 }; 1014 1015 static struct platform_driver mvebu_uart_platform_driver = { 1016 .probe = mvebu_uart_probe, 1017 .driver = { 1018 .name = "mvebu-uart", 1019 .of_match_table = of_match_ptr(mvebu_uart_of_match), 1020 .suppress_bind_attrs = true, 1021 #if defined(CONFIG_PM) 1022 .pm = &mvebu_uart_pm_ops, 1023 #endif /* CONFIG_PM */ 1024 }, 1025 }; 1026 1027 /* This code is based on clk-fixed-factor.c driver and modified. */ 1028 1029 struct mvebu_uart_clock { 1030 struct clk_hw clk_hw; 1031 int clock_idx; 1032 u32 pm_context_reg1; 1033 u32 pm_context_reg2; 1034 }; 1035 1036 struct mvebu_uart_clock_base { 1037 struct mvebu_uart_clock clocks[2]; 1038 unsigned int parent_rates[5]; 1039 int parent_idx; 1040 unsigned int div; 1041 void __iomem *reg1; 1042 void __iomem *reg2; 1043 bool configured; 1044 }; 1045 1046 #define PARENT_CLOCK_XTAL 4 1047 1048 #define to_uart_clock(hw) container_of(hw, struct mvebu_uart_clock, clk_hw) 1049 #define to_uart_clock_base(uart_clock) container_of(uart_clock, \ 1050 struct mvebu_uart_clock_base, clocks[uart_clock->clock_idx]) 1051 1052 static int mvebu_uart_clock_prepare(struct clk_hw *hw) 1053 { 1054 struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1055 struct mvebu_uart_clock_base *uart_clock_base = 1056 to_uart_clock_base(uart_clock); 1057 unsigned int prev_clock_idx, prev_clock_rate, prev_d1d2; 1058 unsigned int parent_clock_idx, parent_clock_rate; 1059 unsigned long flags; 1060 unsigned int d1, d2; 1061 u64 divisor; 1062 u32 val; 1063 1064 /* 1065 * This function just reconfigures UART Clock Control register (located 1066 * in UART1 address space which controls both UART1 and UART2) to 1067 * selected UART base clock and recalculates current UART1/UART2 1068 * divisors in their address spaces, so that final baudrate will not be 1069 * changed by switching UART parent clock. This is required for 1070 * otherwise kernel's boot log stops working - we need to ensure that 1071 * UART baudrate does not change during this setup. It is a one time 1072 * operation, it will execute only once and set `configured` to true, 1073 * and be skipped on subsequent calls. Because this UART Clock Control 1074 * register (UART_BRDV) is shared between UART1 baudrate function, 1075 * UART1 clock selector and UART2 clock selector, every access to 1076 * UART_BRDV (reg1) needs to be protected by a lock. 1077 */ 1078 1079 spin_lock_irqsave(&mvebu_uart_lock, flags); 1080 1081 if (uart_clock_base->configured) { 1082 spin_unlock_irqrestore(&mvebu_uart_lock, flags); 1083 return 0; 1084 } 1085 1086 parent_clock_idx = uart_clock_base->parent_idx; 1087 parent_clock_rate = uart_clock_base->parent_rates[parent_clock_idx]; 1088 1089 val = readl(uart_clock_base->reg1); 1090 1091 if (uart_clock_base->div > CLK_TBG_DIV1_MAX) { 1092 d1 = CLK_TBG_DIV1_MAX; 1093 d2 = uart_clock_base->div / CLK_TBG_DIV1_MAX; 1094 } else { 1095 d1 = uart_clock_base->div; 1096 d2 = 1; 1097 } 1098 1099 if (val & CLK_NO_XTAL) { 1100 prev_clock_idx = (val >> CLK_TBG_SEL_SHIFT) & CLK_TBG_SEL_MASK; 1101 prev_d1d2 = ((val >> CLK_TBG_DIV1_SHIFT) & CLK_TBG_DIV1_MASK) * 1102 ((val >> CLK_TBG_DIV2_SHIFT) & CLK_TBG_DIV2_MASK); 1103 } else { 1104 prev_clock_idx = PARENT_CLOCK_XTAL; 1105 prev_d1d2 = 1; 1106 } 1107 1108 /* Note that uart_clock_base->parent_rates[i] may not be available */ 1109 prev_clock_rate = uart_clock_base->parent_rates[prev_clock_idx]; 1110 1111 /* Recalculate UART1 divisor so UART1 baudrate does not change */ 1112 if (prev_clock_rate) { 1113 divisor = DIV_U64_ROUND_CLOSEST((u64)(val & BRDV_BAUD_MASK) * 1114 parent_clock_rate * prev_d1d2, 1115 prev_clock_rate * d1 * d2); 1116 if (divisor < 1) 1117 divisor = 1; 1118 else if (divisor > BRDV_BAUD_MAX) 1119 divisor = BRDV_BAUD_MAX; 1120 val = (val & ~BRDV_BAUD_MASK) | divisor; 1121 } 1122 1123 if (parent_clock_idx != PARENT_CLOCK_XTAL) { 1124 /* Do not use XTAL, select TBG clock and TBG d1 * d2 divisors */ 1125 val |= CLK_NO_XTAL; 1126 val &= ~(CLK_TBG_DIV1_MASK << CLK_TBG_DIV1_SHIFT); 1127 val |= d1 << CLK_TBG_DIV1_SHIFT; 1128 val &= ~(CLK_TBG_DIV2_MASK << CLK_TBG_DIV2_SHIFT); 1129 val |= d2 << CLK_TBG_DIV2_SHIFT; 1130 val &= ~(CLK_TBG_SEL_MASK << CLK_TBG_SEL_SHIFT); 1131 val |= parent_clock_idx << CLK_TBG_SEL_SHIFT; 1132 } else { 1133 /* Use XTAL, TBG bits are then ignored */ 1134 val &= ~CLK_NO_XTAL; 1135 } 1136 1137 writel(val, uart_clock_base->reg1); 1138 1139 /* Recalculate UART2 divisor so UART2 baudrate does not change */ 1140 if (prev_clock_rate) { 1141 val = readl(uart_clock_base->reg2); 1142 divisor = DIV_U64_ROUND_CLOSEST((u64)(val & BRDV_BAUD_MASK) * 1143 parent_clock_rate * prev_d1d2, 1144 prev_clock_rate * d1 * d2); 1145 if (divisor < 1) 1146 divisor = 1; 1147 else if (divisor > BRDV_BAUD_MAX) 1148 divisor = BRDV_BAUD_MAX; 1149 val = (val & ~BRDV_BAUD_MASK) | divisor; 1150 writel(val, uart_clock_base->reg2); 1151 } 1152 1153 uart_clock_base->configured = true; 1154 1155 spin_unlock_irqrestore(&mvebu_uart_lock, flags); 1156 1157 return 0; 1158 } 1159 1160 static int mvebu_uart_clock_enable(struct clk_hw *hw) 1161 { 1162 struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1163 struct mvebu_uart_clock_base *uart_clock_base = 1164 to_uart_clock_base(uart_clock); 1165 unsigned long flags; 1166 u32 val; 1167 1168 spin_lock_irqsave(&mvebu_uart_lock, flags); 1169 1170 val = readl(uart_clock_base->reg1); 1171 1172 if (uart_clock->clock_idx == 0) 1173 val &= ~UART1_CLK_DIS; 1174 else 1175 val &= ~UART2_CLK_DIS; 1176 1177 writel(val, uart_clock_base->reg1); 1178 1179 spin_unlock_irqrestore(&mvebu_uart_lock, flags); 1180 1181 return 0; 1182 } 1183 1184 static void mvebu_uart_clock_disable(struct clk_hw *hw) 1185 { 1186 struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1187 struct mvebu_uart_clock_base *uart_clock_base = 1188 to_uart_clock_base(uart_clock); 1189 unsigned long flags; 1190 u32 val; 1191 1192 spin_lock_irqsave(&mvebu_uart_lock, flags); 1193 1194 val = readl(uart_clock_base->reg1); 1195 1196 if (uart_clock->clock_idx == 0) 1197 val |= UART1_CLK_DIS; 1198 else 1199 val |= UART2_CLK_DIS; 1200 1201 writel(val, uart_clock_base->reg1); 1202 1203 spin_unlock_irqrestore(&mvebu_uart_lock, flags); 1204 } 1205 1206 static int mvebu_uart_clock_is_enabled(struct clk_hw *hw) 1207 { 1208 struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1209 struct mvebu_uart_clock_base *uart_clock_base = 1210 to_uart_clock_base(uart_clock); 1211 u32 val; 1212 1213 val = readl(uart_clock_base->reg1); 1214 1215 if (uart_clock->clock_idx == 0) 1216 return !(val & UART1_CLK_DIS); 1217 else 1218 return !(val & UART2_CLK_DIS); 1219 } 1220 1221 static int mvebu_uart_clock_save_context(struct clk_hw *hw) 1222 { 1223 struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1224 struct mvebu_uart_clock_base *uart_clock_base = 1225 to_uart_clock_base(uart_clock); 1226 unsigned long flags; 1227 1228 spin_lock_irqsave(&mvebu_uart_lock, flags); 1229 uart_clock->pm_context_reg1 = readl(uart_clock_base->reg1); 1230 uart_clock->pm_context_reg2 = readl(uart_clock_base->reg2); 1231 spin_unlock_irqrestore(&mvebu_uart_lock, flags); 1232 1233 return 0; 1234 } 1235 1236 static void mvebu_uart_clock_restore_context(struct clk_hw *hw) 1237 { 1238 struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1239 struct mvebu_uart_clock_base *uart_clock_base = 1240 to_uart_clock_base(uart_clock); 1241 unsigned long flags; 1242 1243 spin_lock_irqsave(&mvebu_uart_lock, flags); 1244 writel(uart_clock->pm_context_reg1, uart_clock_base->reg1); 1245 writel(uart_clock->pm_context_reg2, uart_clock_base->reg2); 1246 spin_unlock_irqrestore(&mvebu_uart_lock, flags); 1247 } 1248 1249 static unsigned long mvebu_uart_clock_recalc_rate(struct clk_hw *hw, 1250 unsigned long parent_rate) 1251 { 1252 struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1253 struct mvebu_uart_clock_base *uart_clock_base = 1254 to_uart_clock_base(uart_clock); 1255 1256 return parent_rate / uart_clock_base->div; 1257 } 1258 1259 static int mvebu_uart_clock_determine_rate(struct clk_hw *hw, 1260 struct clk_rate_request *req) 1261 { 1262 struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1263 struct mvebu_uart_clock_base *uart_clock_base = 1264 to_uart_clock_base(uart_clock); 1265 1266 req->rate = req->best_parent_rate / uart_clock_base->div; 1267 1268 return 0; 1269 } 1270 1271 static int mvebu_uart_clock_set_rate(struct clk_hw *hw, unsigned long rate, 1272 unsigned long parent_rate) 1273 { 1274 /* 1275 * We must report success but we can do so unconditionally because 1276 * mvebu_uart_clock_round_rate returns values that ensure this call is a 1277 * nop. 1278 */ 1279 1280 return 0; 1281 } 1282 1283 static const struct clk_ops mvebu_uart_clock_ops = { 1284 .prepare = mvebu_uart_clock_prepare, 1285 .enable = mvebu_uart_clock_enable, 1286 .disable = mvebu_uart_clock_disable, 1287 .is_enabled = mvebu_uart_clock_is_enabled, 1288 .save_context = mvebu_uart_clock_save_context, 1289 .restore_context = mvebu_uart_clock_restore_context, 1290 .determine_rate = mvebu_uart_clock_determine_rate, 1291 .set_rate = mvebu_uart_clock_set_rate, 1292 .recalc_rate = mvebu_uart_clock_recalc_rate, 1293 }; 1294 1295 static int mvebu_uart_clock_register(struct device *dev, 1296 struct mvebu_uart_clock *uart_clock, 1297 const char *name, 1298 const char *parent_name) 1299 { 1300 struct clk_init_data init = { }; 1301 1302 uart_clock->clk_hw.init = &init; 1303 1304 init.name = name; 1305 init.ops = &mvebu_uart_clock_ops; 1306 init.flags = 0; 1307 init.num_parents = 1; 1308 init.parent_names = &parent_name; 1309 1310 return devm_clk_hw_register(dev, &uart_clock->clk_hw); 1311 } 1312 1313 static int mvebu_uart_clock_probe(struct platform_device *pdev) 1314 { 1315 static const char *const uart_clk_names[] = { "uart_1", "uart_2" }; 1316 static const char *const parent_clk_names[] = { "TBG-A-P", "TBG-B-P", 1317 "TBG-A-S", "TBG-B-S", 1318 "xtal" }; 1319 struct clk *parent_clks[ARRAY_SIZE(parent_clk_names)]; 1320 struct mvebu_uart_clock_base *uart_clock_base; 1321 struct clk_hw_onecell_data *hw_clk_data; 1322 struct device *dev = &pdev->dev; 1323 int i, parent_clk_idx, ret; 1324 unsigned long div, rate; 1325 struct resource *res; 1326 unsigned int d1, d2; 1327 1328 BUILD_BUG_ON(ARRAY_SIZE(uart_clk_names) != 1329 ARRAY_SIZE(uart_clock_base->clocks)); 1330 BUILD_BUG_ON(ARRAY_SIZE(parent_clk_names) != 1331 ARRAY_SIZE(uart_clock_base->parent_rates)); 1332 1333 uart_clock_base = devm_kzalloc(dev, 1334 sizeof(*uart_clock_base), 1335 GFP_KERNEL); 1336 if (!uart_clock_base) 1337 return -ENOMEM; 1338 1339 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1340 if (!res) { 1341 dev_err(dev, "Couldn't get first register\n"); 1342 return -ENOENT; 1343 } 1344 1345 /* 1346 * UART Clock Control register (reg1 / UART_BRDV) is in the address 1347 * space of UART1 (standard UART variant), controls parent clock and 1348 * dividers for both UART1 and UART2 and is supplied via DT as the first 1349 * resource. Therefore use ioremap() rather than ioremap_resource() to 1350 * avoid conflicts with UART1 driver. Access to UART_BRDV is protected 1351 * by a lock shared between clock and UART driver. 1352 */ 1353 uart_clock_base->reg1 = devm_ioremap(dev, res->start, 1354 resource_size(res)); 1355 if (!uart_clock_base->reg1) 1356 return -ENOMEM; 1357 1358 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1359 if (!res) { 1360 dev_err(dev, "Couldn't get second register\n"); 1361 return -ENOENT; 1362 } 1363 1364 /* 1365 * UART 2 Baud Rate Divisor register (reg2 / UART_BRDV) is in address 1366 * space of UART2 (extended UART variant), controls only one UART2 1367 * specific divider and is supplied via DT as second resource. 1368 * Therefore use ioremap() rather than ioremap_resource() to avoid 1369 * conflicts with UART2 driver. Access to UART_BRDV is protected by a 1370 * by lock shared between clock and UART driver. 1371 */ 1372 uart_clock_base->reg2 = devm_ioremap(dev, res->start, 1373 resource_size(res)); 1374 if (!uart_clock_base->reg2) 1375 return -ENOMEM; 1376 1377 hw_clk_data = devm_kzalloc(dev, 1378 struct_size(hw_clk_data, hws, 1379 ARRAY_SIZE(uart_clk_names)), 1380 GFP_KERNEL); 1381 if (!hw_clk_data) 1382 return -ENOMEM; 1383 1384 hw_clk_data->num = ARRAY_SIZE(uart_clk_names); 1385 for (i = 0; i < ARRAY_SIZE(uart_clk_names); i++) { 1386 hw_clk_data->hws[i] = &uart_clock_base->clocks[i].clk_hw; 1387 uart_clock_base->clocks[i].clock_idx = i; 1388 } 1389 1390 parent_clk_idx = -1; 1391 1392 for (i = 0; i < ARRAY_SIZE(parent_clk_names); i++) { 1393 parent_clks[i] = devm_clk_get(dev, parent_clk_names[i]); 1394 if (IS_ERR(parent_clks[i])) { 1395 if (PTR_ERR(parent_clks[i]) == -EPROBE_DEFER) 1396 return -EPROBE_DEFER; 1397 dev_warn(dev, "Couldn't get the parent clock %s: %ld\n", 1398 parent_clk_names[i], PTR_ERR(parent_clks[i])); 1399 continue; 1400 } 1401 1402 ret = clk_prepare_enable(parent_clks[i]); 1403 if (ret) { 1404 dev_warn(dev, "Couldn't enable parent clock %s: %d\n", 1405 parent_clk_names[i], ret); 1406 continue; 1407 } 1408 rate = clk_get_rate(parent_clks[i]); 1409 uart_clock_base->parent_rates[i] = rate; 1410 1411 if (i != PARENT_CLOCK_XTAL) { 1412 /* 1413 * Calculate the smallest TBG d1 and d2 divisors that 1414 * still can provide 9600 baudrate. 1415 */ 1416 d1 = DIV_ROUND_UP(rate, 9600 * OSAMP_MAX_DIVISOR * 1417 BRDV_BAUD_MAX); 1418 if (d1 < 1) 1419 d1 = 1; 1420 else if (d1 > CLK_TBG_DIV1_MAX) 1421 d1 = CLK_TBG_DIV1_MAX; 1422 1423 d2 = DIV_ROUND_UP(rate, 9600 * OSAMP_MAX_DIVISOR * 1424 BRDV_BAUD_MAX * d1); 1425 if (d2 < 1) 1426 d2 = 1; 1427 else if (d2 > CLK_TBG_DIV2_MAX) 1428 d2 = CLK_TBG_DIV2_MAX; 1429 } else { 1430 /* 1431 * When UART clock uses XTAL clock as a source then it 1432 * is not possible to use d1 and d2 divisors. 1433 */ 1434 d1 = d2 = 1; 1435 } 1436 1437 /* Skip clock source which cannot provide 9600 baudrate */ 1438 if (rate > 9600 * OSAMP_MAX_DIVISOR * BRDV_BAUD_MAX * d1 * d2) 1439 continue; 1440 1441 /* 1442 * Choose TBG clock source with the smallest divisors. Use XTAL 1443 * clock source only in case TBG is not available as XTAL cannot 1444 * be used for baudrates higher than 230400. 1445 */ 1446 if (parent_clk_idx == -1 || 1447 (i != PARENT_CLOCK_XTAL && div > d1 * d2)) { 1448 parent_clk_idx = i; 1449 div = d1 * d2; 1450 } 1451 } 1452 1453 for (i = 0; i < ARRAY_SIZE(parent_clk_names); i++) { 1454 if (i == parent_clk_idx || IS_ERR(parent_clks[i])) 1455 continue; 1456 clk_disable_unprepare(parent_clks[i]); 1457 devm_clk_put(dev, parent_clks[i]); 1458 } 1459 1460 if (parent_clk_idx == -1) { 1461 dev_err(dev, "No usable parent clock\n"); 1462 return -ENOENT; 1463 } 1464 1465 uart_clock_base->parent_idx = parent_clk_idx; 1466 uart_clock_base->div = div; 1467 1468 dev_notice(dev, "Using parent clock %s as base UART clock\n", 1469 __clk_get_name(parent_clks[parent_clk_idx])); 1470 1471 for (i = 0; i < ARRAY_SIZE(uart_clk_names); i++) { 1472 ret = mvebu_uart_clock_register(dev, 1473 &uart_clock_base->clocks[i], 1474 uart_clk_names[i], 1475 __clk_get_name(parent_clks[parent_clk_idx])); 1476 if (ret) { 1477 dev_err(dev, "Can't register UART clock %d: %d\n", 1478 i, ret); 1479 return ret; 1480 } 1481 } 1482 1483 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, 1484 hw_clk_data); 1485 } 1486 1487 static const struct of_device_id mvebu_uart_clock_of_match[] = { 1488 { .compatible = "marvell,armada-3700-uart-clock", }, 1489 { } 1490 }; 1491 1492 static struct platform_driver mvebu_uart_clock_platform_driver = { 1493 .probe = mvebu_uart_clock_probe, 1494 .driver = { 1495 .name = "mvebu-uart-clock", 1496 .of_match_table = mvebu_uart_clock_of_match, 1497 }, 1498 }; 1499 1500 static int __init mvebu_uart_init(void) 1501 { 1502 int ret; 1503 1504 ret = uart_register_driver(&mvebu_uart_driver); 1505 if (ret) 1506 return ret; 1507 1508 ret = platform_driver_register(&mvebu_uart_clock_platform_driver); 1509 if (ret) { 1510 uart_unregister_driver(&mvebu_uart_driver); 1511 return ret; 1512 } 1513 1514 ret = platform_driver_register(&mvebu_uart_platform_driver); 1515 if (ret) { 1516 platform_driver_unregister(&mvebu_uart_clock_platform_driver); 1517 uart_unregister_driver(&mvebu_uart_driver); 1518 return ret; 1519 } 1520 1521 return 0; 1522 } 1523 arch_initcall(mvebu_uart_init); 1524