1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for msm7k serial device and console 4 * 5 * Copyright (C) 2007 Google, Inc. 6 * Author: Robert Love <rlove@google.com> 7 * Copyright (c) 2011, Code Aurora Forum. All rights reserved. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/atomic.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dmaengine.h> 14 #include <linux/module.h> 15 #include <linux/io.h> 16 #include <linux/ioport.h> 17 #include <linux/interrupt.h> 18 #include <linux/init.h> 19 #include <linux/console.h> 20 #include <linux/tty.h> 21 #include <linux/tty_flip.h> 22 #include <linux/serial_core.h> 23 #include <linux/slab.h> 24 #include <linux/clk.h> 25 #include <linux/platform_device.h> 26 #include <linux/delay.h> 27 #include <linux/of.h> 28 #include <linux/of_device.h> 29 #include <linux/wait.h> 30 31 #define UART_MR1 0x0000 32 33 #define UART_MR1_AUTO_RFR_LEVEL0 0x3F 34 #define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00 35 #define UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00 36 #define UART_MR1_RX_RDY_CTL BIT(7) 37 #define UART_MR1_CTS_CTL BIT(6) 38 39 #define UART_MR2 0x0004 40 #define UART_MR2_ERROR_MODE BIT(6) 41 #define UART_MR2_BITS_PER_CHAR 0x30 42 #define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4) 43 #define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4) 44 #define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4) 45 #define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4) 46 #define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2) 47 #define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2) 48 #define UART_MR2_PARITY_MODE_NONE 0x0 49 #define UART_MR2_PARITY_MODE_ODD 0x1 50 #define UART_MR2_PARITY_MODE_EVEN 0x2 51 #define UART_MR2_PARITY_MODE_SPACE 0x3 52 #define UART_MR2_PARITY_MODE 0x3 53 54 #define UART_CSR 0x0008 55 56 #define UART_TF 0x000C 57 #define UARTDM_TF 0x0070 58 59 #define UART_CR 0x0010 60 #define UART_CR_CMD_NULL (0 << 4) 61 #define UART_CR_CMD_RESET_RX (1 << 4) 62 #define UART_CR_CMD_RESET_TX (2 << 4) 63 #define UART_CR_CMD_RESET_ERR (3 << 4) 64 #define UART_CR_CMD_RESET_BREAK_INT (4 << 4) 65 #define UART_CR_CMD_START_BREAK (5 << 4) 66 #define UART_CR_CMD_STOP_BREAK (6 << 4) 67 #define UART_CR_CMD_RESET_CTS (7 << 4) 68 #define UART_CR_CMD_RESET_STALE_INT (8 << 4) 69 #define UART_CR_CMD_PACKET_MODE (9 << 4) 70 #define UART_CR_CMD_MODE_RESET (12 << 4) 71 #define UART_CR_CMD_SET_RFR (13 << 4) 72 #define UART_CR_CMD_RESET_RFR (14 << 4) 73 #define UART_CR_CMD_PROTECTION_EN (16 << 4) 74 #define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8) 75 #define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4) 76 #define UART_CR_CMD_FORCE_STALE (4 << 8) 77 #define UART_CR_CMD_RESET_TX_READY (3 << 8) 78 #define UART_CR_TX_DISABLE BIT(3) 79 #define UART_CR_TX_ENABLE BIT(2) 80 #define UART_CR_RX_DISABLE BIT(1) 81 #define UART_CR_RX_ENABLE BIT(0) 82 #define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4)) 83 84 #define UART_IMR 0x0014 85 #define UART_IMR_TXLEV BIT(0) 86 #define UART_IMR_RXSTALE BIT(3) 87 #define UART_IMR_RXLEV BIT(4) 88 #define UART_IMR_DELTA_CTS BIT(5) 89 #define UART_IMR_CURRENT_CTS BIT(6) 90 #define UART_IMR_RXBREAK_START BIT(10) 91 92 #define UART_IPR_RXSTALE_LAST 0x20 93 #define UART_IPR_STALE_LSB 0x1F 94 #define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80 95 #define UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80 96 97 #define UART_IPR 0x0018 98 #define UART_TFWR 0x001C 99 #define UART_RFWR 0x0020 100 #define UART_HCR 0x0024 101 102 #define UART_MREG 0x0028 103 #define UART_NREG 0x002C 104 #define UART_DREG 0x0030 105 #define UART_MNDREG 0x0034 106 #define UART_IRDA 0x0038 107 #define UART_MISR_MODE 0x0040 108 #define UART_MISR_RESET 0x0044 109 #define UART_MISR_EXPORT 0x0048 110 #define UART_MISR_VAL 0x004C 111 #define UART_TEST_CTRL 0x0050 112 113 #define UART_SR 0x0008 114 #define UART_SR_HUNT_CHAR BIT(7) 115 #define UART_SR_RX_BREAK BIT(6) 116 #define UART_SR_PAR_FRAME_ERR BIT(5) 117 #define UART_SR_OVERRUN BIT(4) 118 #define UART_SR_TX_EMPTY BIT(3) 119 #define UART_SR_TX_READY BIT(2) 120 #define UART_SR_RX_FULL BIT(1) 121 #define UART_SR_RX_READY BIT(0) 122 123 #define UART_RF 0x000C 124 #define UARTDM_RF 0x0070 125 #define UART_MISR 0x0010 126 #define UART_ISR 0x0014 127 #define UART_ISR_TX_READY BIT(7) 128 129 #define UARTDM_RXFS 0x50 130 #define UARTDM_RXFS_BUF_SHIFT 0x7 131 #define UARTDM_RXFS_BUF_MASK 0x7 132 133 #define UARTDM_DMEN 0x3C 134 #define UARTDM_DMEN_RX_SC_ENABLE BIT(5) 135 #define UARTDM_DMEN_TX_SC_ENABLE BIT(4) 136 137 #define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */ 138 #define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */ 139 140 #define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */ 141 #define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */ 142 143 #define UARTDM_DMRX 0x34 144 #define UARTDM_NCF_TX 0x40 145 #define UARTDM_RX_TOTAL_SNAP 0x38 146 147 #define UARTDM_BURST_SIZE 16 /* in bytes */ 148 #define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */ 149 #define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */ 150 #define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4) 151 152 enum { 153 UARTDM_1P1 = 1, 154 UARTDM_1P2, 155 UARTDM_1P3, 156 UARTDM_1P4, 157 }; 158 159 struct msm_dma { 160 struct dma_chan *chan; 161 enum dma_data_direction dir; 162 dma_addr_t phys; 163 unsigned char *virt; 164 dma_cookie_t cookie; 165 u32 enable_bit; 166 unsigned int count; 167 struct dma_async_tx_descriptor *desc; 168 }; 169 170 struct msm_port { 171 struct uart_port uart; 172 char name[16]; 173 struct clk *clk; 174 struct clk *pclk; 175 unsigned int imr; 176 int is_uartdm; 177 unsigned int old_snap_state; 178 bool break_detected; 179 struct msm_dma tx_dma; 180 struct msm_dma rx_dma; 181 }; 182 183 #define UART_TO_MSM(uart_port) container_of(uart_port, struct msm_port, uart) 184 185 static 186 void msm_write(struct uart_port *port, unsigned int val, unsigned int off) 187 { 188 writel_relaxed(val, port->membase + off); 189 } 190 191 static 192 unsigned int msm_read(struct uart_port *port, unsigned int off) 193 { 194 return readl_relaxed(port->membase + off); 195 } 196 197 /* 198 * Setup the MND registers to use the TCXO clock. 199 */ 200 static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port) 201 { 202 msm_write(port, 0x06, UART_MREG); 203 msm_write(port, 0xF1, UART_NREG); 204 msm_write(port, 0x0F, UART_DREG); 205 msm_write(port, 0x1A, UART_MNDREG); 206 port->uartclk = 1843200; 207 } 208 209 /* 210 * Setup the MND registers to use the TCXO clock divided by 4. 211 */ 212 static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port) 213 { 214 msm_write(port, 0x18, UART_MREG); 215 msm_write(port, 0xF6, UART_NREG); 216 msm_write(port, 0x0F, UART_DREG); 217 msm_write(port, 0x0A, UART_MNDREG); 218 port->uartclk = 1843200; 219 } 220 221 static void msm_serial_set_mnd_regs(struct uart_port *port) 222 { 223 struct msm_port *msm_port = UART_TO_MSM(port); 224 225 /* 226 * These registers don't exist so we change the clk input rate 227 * on uartdm hardware instead 228 */ 229 if (msm_port->is_uartdm) 230 return; 231 232 if (port->uartclk == 19200000) 233 msm_serial_set_mnd_regs_tcxo(port); 234 else if (port->uartclk == 4800000) 235 msm_serial_set_mnd_regs_tcxoby4(port); 236 } 237 238 static void msm_handle_tx(struct uart_port *port); 239 static void msm_start_rx_dma(struct msm_port *msm_port); 240 241 static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma) 242 { 243 struct device *dev = port->dev; 244 unsigned int mapped; 245 u32 val; 246 247 mapped = dma->count; 248 dma->count = 0; 249 250 dmaengine_terminate_all(dma->chan); 251 252 /* 253 * DMA Stall happens if enqueue and flush command happens concurrently. 254 * For example before changing the baud rate/protocol configuration and 255 * sending flush command to ADM, disable the channel of UARTDM. 256 * Note: should not reset the receiver here immediately as it is not 257 * suggested to do disable/reset or reset/disable at the same time. 258 */ 259 val = msm_read(port, UARTDM_DMEN); 260 val &= ~dma->enable_bit; 261 msm_write(port, val, UARTDM_DMEN); 262 263 if (mapped) 264 dma_unmap_single(dev, dma->phys, mapped, dma->dir); 265 } 266 267 static void msm_release_dma(struct msm_port *msm_port) 268 { 269 struct msm_dma *dma; 270 271 dma = &msm_port->tx_dma; 272 if (dma->chan) { 273 msm_stop_dma(&msm_port->uart, dma); 274 dma_release_channel(dma->chan); 275 } 276 277 memset(dma, 0, sizeof(*dma)); 278 279 dma = &msm_port->rx_dma; 280 if (dma->chan) { 281 msm_stop_dma(&msm_port->uart, dma); 282 dma_release_channel(dma->chan); 283 kfree(dma->virt); 284 } 285 286 memset(dma, 0, sizeof(*dma)); 287 } 288 289 static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base) 290 { 291 struct device *dev = msm_port->uart.dev; 292 struct dma_slave_config conf; 293 struct msm_dma *dma; 294 u32 crci = 0; 295 int ret; 296 297 dma = &msm_port->tx_dma; 298 299 /* allocate DMA resources, if available */ 300 dma->chan = dma_request_chan(dev, "tx"); 301 if (IS_ERR(dma->chan)) 302 goto no_tx; 303 304 of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci); 305 306 memset(&conf, 0, sizeof(conf)); 307 conf.direction = DMA_MEM_TO_DEV; 308 conf.device_fc = true; 309 conf.dst_addr = base + UARTDM_TF; 310 conf.dst_maxburst = UARTDM_BURST_SIZE; 311 conf.slave_id = crci; 312 313 ret = dmaengine_slave_config(dma->chan, &conf); 314 if (ret) 315 goto rel_tx; 316 317 dma->dir = DMA_TO_DEVICE; 318 319 if (msm_port->is_uartdm < UARTDM_1P4) 320 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE; 321 else 322 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE; 323 324 return; 325 326 rel_tx: 327 dma_release_channel(dma->chan); 328 no_tx: 329 memset(dma, 0, sizeof(*dma)); 330 } 331 332 static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base) 333 { 334 struct device *dev = msm_port->uart.dev; 335 struct dma_slave_config conf; 336 struct msm_dma *dma; 337 u32 crci = 0; 338 int ret; 339 340 dma = &msm_port->rx_dma; 341 342 /* allocate DMA resources, if available */ 343 dma->chan = dma_request_chan(dev, "rx"); 344 if (IS_ERR(dma->chan)) 345 goto no_rx; 346 347 of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci); 348 349 dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL); 350 if (!dma->virt) 351 goto rel_rx; 352 353 memset(&conf, 0, sizeof(conf)); 354 conf.direction = DMA_DEV_TO_MEM; 355 conf.device_fc = true; 356 conf.src_addr = base + UARTDM_RF; 357 conf.src_maxburst = UARTDM_BURST_SIZE; 358 conf.slave_id = crci; 359 360 ret = dmaengine_slave_config(dma->chan, &conf); 361 if (ret) 362 goto err; 363 364 dma->dir = DMA_FROM_DEVICE; 365 366 if (msm_port->is_uartdm < UARTDM_1P4) 367 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE; 368 else 369 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE; 370 371 return; 372 err: 373 kfree(dma->virt); 374 rel_rx: 375 dma_release_channel(dma->chan); 376 no_rx: 377 memset(dma, 0, sizeof(*dma)); 378 } 379 380 static inline void msm_wait_for_xmitr(struct uart_port *port) 381 { 382 unsigned int timeout = 500000; 383 384 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) { 385 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY) 386 break; 387 udelay(1); 388 if (!timeout--) 389 break; 390 } 391 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR); 392 } 393 394 static void msm_stop_tx(struct uart_port *port) 395 { 396 struct msm_port *msm_port = UART_TO_MSM(port); 397 398 msm_port->imr &= ~UART_IMR_TXLEV; 399 msm_write(port, msm_port->imr, UART_IMR); 400 } 401 402 static void msm_start_tx(struct uart_port *port) 403 { 404 struct msm_port *msm_port = UART_TO_MSM(port); 405 struct msm_dma *dma = &msm_port->tx_dma; 406 407 /* Already started in DMA mode */ 408 if (dma->count) 409 return; 410 411 msm_port->imr |= UART_IMR_TXLEV; 412 msm_write(port, msm_port->imr, UART_IMR); 413 } 414 415 static void msm_reset_dm_count(struct uart_port *port, int count) 416 { 417 msm_wait_for_xmitr(port); 418 msm_write(port, count, UARTDM_NCF_TX); 419 msm_read(port, UARTDM_NCF_TX); 420 } 421 422 static void msm_complete_tx_dma(void *args) 423 { 424 struct msm_port *msm_port = args; 425 struct uart_port *port = &msm_port->uart; 426 struct circ_buf *xmit = &port->state->xmit; 427 struct msm_dma *dma = &msm_port->tx_dma; 428 struct dma_tx_state state; 429 unsigned long flags; 430 unsigned int count; 431 u32 val; 432 433 spin_lock_irqsave(&port->lock, flags); 434 435 /* Already stopped */ 436 if (!dma->count) 437 goto done; 438 439 dmaengine_tx_status(dma->chan, dma->cookie, &state); 440 441 dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir); 442 443 val = msm_read(port, UARTDM_DMEN); 444 val &= ~dma->enable_bit; 445 msm_write(port, val, UARTDM_DMEN); 446 447 if (msm_port->is_uartdm > UARTDM_1P3) { 448 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR); 449 msm_write(port, UART_CR_TX_ENABLE, UART_CR); 450 } 451 452 count = dma->count - state.residue; 453 port->icount.tx += count; 454 dma->count = 0; 455 456 xmit->tail += count; 457 xmit->tail &= UART_XMIT_SIZE - 1; 458 459 /* Restore "Tx FIFO below watermark" interrupt */ 460 msm_port->imr |= UART_IMR_TXLEV; 461 msm_write(port, msm_port->imr, UART_IMR); 462 463 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 464 uart_write_wakeup(port); 465 466 msm_handle_tx(port); 467 done: 468 spin_unlock_irqrestore(&port->lock, flags); 469 } 470 471 static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count) 472 { 473 struct circ_buf *xmit = &msm_port->uart.state->xmit; 474 struct uart_port *port = &msm_port->uart; 475 struct msm_dma *dma = &msm_port->tx_dma; 476 void *cpu_addr; 477 int ret; 478 u32 val; 479 480 cpu_addr = &xmit->buf[xmit->tail]; 481 482 dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir); 483 ret = dma_mapping_error(port->dev, dma->phys); 484 if (ret) 485 return ret; 486 487 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys, 488 count, DMA_MEM_TO_DEV, 489 DMA_PREP_INTERRUPT | 490 DMA_PREP_FENCE); 491 if (!dma->desc) { 492 ret = -EIO; 493 goto unmap; 494 } 495 496 dma->desc->callback = msm_complete_tx_dma; 497 dma->desc->callback_param = msm_port; 498 499 dma->cookie = dmaengine_submit(dma->desc); 500 ret = dma_submit_error(dma->cookie); 501 if (ret) 502 goto unmap; 503 504 /* 505 * Using DMA complete for Tx FIFO reload, no need for 506 * "Tx FIFO below watermark" one, disable it 507 */ 508 msm_port->imr &= ~UART_IMR_TXLEV; 509 msm_write(port, msm_port->imr, UART_IMR); 510 511 dma->count = count; 512 513 val = msm_read(port, UARTDM_DMEN); 514 val |= dma->enable_bit; 515 516 if (msm_port->is_uartdm < UARTDM_1P4) 517 msm_write(port, val, UARTDM_DMEN); 518 519 msm_reset_dm_count(port, count); 520 521 if (msm_port->is_uartdm > UARTDM_1P3) 522 msm_write(port, val, UARTDM_DMEN); 523 524 dma_async_issue_pending(dma->chan); 525 return 0; 526 unmap: 527 dma_unmap_single(port->dev, dma->phys, count, dma->dir); 528 return ret; 529 } 530 531 static void msm_complete_rx_dma(void *args) 532 { 533 struct msm_port *msm_port = args; 534 struct uart_port *port = &msm_port->uart; 535 struct tty_port *tport = &port->state->port; 536 struct msm_dma *dma = &msm_port->rx_dma; 537 int count = 0, i, sysrq; 538 unsigned long flags; 539 u32 val; 540 541 spin_lock_irqsave(&port->lock, flags); 542 543 /* Already stopped */ 544 if (!dma->count) 545 goto done; 546 547 val = msm_read(port, UARTDM_DMEN); 548 val &= ~dma->enable_bit; 549 msm_write(port, val, UARTDM_DMEN); 550 551 if (msm_read(port, UART_SR) & UART_SR_OVERRUN) { 552 port->icount.overrun++; 553 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 554 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 555 } 556 557 count = msm_read(port, UARTDM_RX_TOTAL_SNAP); 558 559 port->icount.rx += count; 560 561 dma->count = 0; 562 563 dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir); 564 565 for (i = 0; i < count; i++) { 566 char flag = TTY_NORMAL; 567 568 if (msm_port->break_detected && dma->virt[i] == 0) { 569 port->icount.brk++; 570 flag = TTY_BREAK; 571 msm_port->break_detected = false; 572 if (uart_handle_break(port)) 573 continue; 574 } 575 576 if (!(port->read_status_mask & UART_SR_RX_BREAK)) 577 flag = TTY_NORMAL; 578 579 spin_unlock_irqrestore(&port->lock, flags); 580 sysrq = uart_handle_sysrq_char(port, dma->virt[i]); 581 spin_lock_irqsave(&port->lock, flags); 582 if (!sysrq) 583 tty_insert_flip_char(tport, dma->virt[i], flag); 584 } 585 586 msm_start_rx_dma(msm_port); 587 done: 588 spin_unlock_irqrestore(&port->lock, flags); 589 590 if (count) 591 tty_flip_buffer_push(tport); 592 } 593 594 static void msm_start_rx_dma(struct msm_port *msm_port) 595 { 596 struct msm_dma *dma = &msm_port->rx_dma; 597 struct uart_port *uart = &msm_port->uart; 598 u32 val; 599 int ret; 600 601 if (!dma->chan) 602 return; 603 604 dma->phys = dma_map_single(uart->dev, dma->virt, 605 UARTDM_RX_SIZE, dma->dir); 606 ret = dma_mapping_error(uart->dev, dma->phys); 607 if (ret) 608 goto sw_mode; 609 610 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys, 611 UARTDM_RX_SIZE, DMA_DEV_TO_MEM, 612 DMA_PREP_INTERRUPT); 613 if (!dma->desc) 614 goto unmap; 615 616 dma->desc->callback = msm_complete_rx_dma; 617 dma->desc->callback_param = msm_port; 618 619 dma->cookie = dmaengine_submit(dma->desc); 620 ret = dma_submit_error(dma->cookie); 621 if (ret) 622 goto unmap; 623 /* 624 * Using DMA for FIFO off-load, no need for "Rx FIFO over 625 * watermark" or "stale" interrupts, disable them 626 */ 627 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE); 628 629 /* 630 * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3), 631 * we need RXSTALE to flush input DMA fifo to memory 632 */ 633 if (msm_port->is_uartdm < UARTDM_1P4) 634 msm_port->imr |= UART_IMR_RXSTALE; 635 636 msm_write(uart, msm_port->imr, UART_IMR); 637 638 dma->count = UARTDM_RX_SIZE; 639 640 dma_async_issue_pending(dma->chan); 641 642 msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR); 643 msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 644 645 val = msm_read(uart, UARTDM_DMEN); 646 val |= dma->enable_bit; 647 648 if (msm_port->is_uartdm < UARTDM_1P4) 649 msm_write(uart, val, UARTDM_DMEN); 650 651 msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX); 652 653 if (msm_port->is_uartdm > UARTDM_1P3) 654 msm_write(uart, val, UARTDM_DMEN); 655 656 return; 657 unmap: 658 dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir); 659 660 sw_mode: 661 /* 662 * Switch from DMA to SW/FIFO mode. After clearing Rx BAM (UARTDM_DMEN), 663 * receiver must be reset. 664 */ 665 msm_write(uart, UART_CR_CMD_RESET_RX, UART_CR); 666 msm_write(uart, UART_CR_RX_ENABLE, UART_CR); 667 668 msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR); 669 msm_write(uart, 0xFFFFFF, UARTDM_DMRX); 670 msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 671 672 /* Re-enable RX interrupts */ 673 msm_port->imr |= (UART_IMR_RXLEV | UART_IMR_RXSTALE); 674 msm_write(uart, msm_port->imr, UART_IMR); 675 } 676 677 static void msm_stop_rx(struct uart_port *port) 678 { 679 struct msm_port *msm_port = UART_TO_MSM(port); 680 struct msm_dma *dma = &msm_port->rx_dma; 681 682 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE); 683 msm_write(port, msm_port->imr, UART_IMR); 684 685 if (dma->chan) 686 msm_stop_dma(port, dma); 687 } 688 689 static void msm_enable_ms(struct uart_port *port) 690 { 691 struct msm_port *msm_port = UART_TO_MSM(port); 692 693 msm_port->imr |= UART_IMR_DELTA_CTS; 694 msm_write(port, msm_port->imr, UART_IMR); 695 } 696 697 static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr) 698 __must_hold(&port->lock) 699 { 700 struct tty_port *tport = &port->state->port; 701 unsigned int sr; 702 int count = 0; 703 struct msm_port *msm_port = UART_TO_MSM(port); 704 705 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) { 706 port->icount.overrun++; 707 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 708 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 709 } 710 711 if (misr & UART_IMR_RXSTALE) { 712 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) - 713 msm_port->old_snap_state; 714 msm_port->old_snap_state = 0; 715 } else { 716 count = 4 * (msm_read(port, UART_RFWR)); 717 msm_port->old_snap_state += count; 718 } 719 720 /* TODO: Precise error reporting */ 721 722 port->icount.rx += count; 723 724 while (count > 0) { 725 unsigned char buf[4]; 726 int sysrq, r_count, i; 727 728 sr = msm_read(port, UART_SR); 729 if ((sr & UART_SR_RX_READY) == 0) { 730 msm_port->old_snap_state -= count; 731 break; 732 } 733 734 ioread32_rep(port->membase + UARTDM_RF, buf, 1); 735 r_count = min_t(int, count, sizeof(buf)); 736 737 for (i = 0; i < r_count; i++) { 738 char flag = TTY_NORMAL; 739 740 if (msm_port->break_detected && buf[i] == 0) { 741 port->icount.brk++; 742 flag = TTY_BREAK; 743 msm_port->break_detected = false; 744 if (uart_handle_break(port)) 745 continue; 746 } 747 748 if (!(port->read_status_mask & UART_SR_RX_BREAK)) 749 flag = TTY_NORMAL; 750 751 spin_unlock(&port->lock); 752 sysrq = uart_handle_sysrq_char(port, buf[i]); 753 spin_lock(&port->lock); 754 if (!sysrq) 755 tty_insert_flip_char(tport, buf[i], flag); 756 } 757 count -= r_count; 758 } 759 760 tty_flip_buffer_push(tport); 761 762 if (misr & (UART_IMR_RXSTALE)) 763 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 764 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 765 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 766 767 /* Try to use DMA */ 768 msm_start_rx_dma(msm_port); 769 } 770 771 static void msm_handle_rx(struct uart_port *port) 772 __must_hold(&port->lock) 773 { 774 struct tty_port *tport = &port->state->port; 775 unsigned int sr; 776 777 /* 778 * Handle overrun. My understanding of the hardware is that overrun 779 * is not tied to the RX buffer, so we handle the case out of band. 780 */ 781 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) { 782 port->icount.overrun++; 783 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 784 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 785 } 786 787 /* and now the main RX loop */ 788 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) { 789 unsigned int c; 790 char flag = TTY_NORMAL; 791 int sysrq; 792 793 c = msm_read(port, UART_RF); 794 795 if (sr & UART_SR_RX_BREAK) { 796 port->icount.brk++; 797 if (uart_handle_break(port)) 798 continue; 799 } else if (sr & UART_SR_PAR_FRAME_ERR) { 800 port->icount.frame++; 801 } else { 802 port->icount.rx++; 803 } 804 805 /* Mask conditions we're ignorning. */ 806 sr &= port->read_status_mask; 807 808 if (sr & UART_SR_RX_BREAK) 809 flag = TTY_BREAK; 810 else if (sr & UART_SR_PAR_FRAME_ERR) 811 flag = TTY_FRAME; 812 813 spin_unlock(&port->lock); 814 sysrq = uart_handle_sysrq_char(port, c); 815 spin_lock(&port->lock); 816 if (!sysrq) 817 tty_insert_flip_char(tport, c, flag); 818 } 819 820 tty_flip_buffer_push(tport); 821 } 822 823 static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count) 824 { 825 struct circ_buf *xmit = &port->state->xmit; 826 struct msm_port *msm_port = UART_TO_MSM(port); 827 unsigned int num_chars; 828 unsigned int tf_pointer = 0; 829 void __iomem *tf; 830 831 if (msm_port->is_uartdm) 832 tf = port->membase + UARTDM_TF; 833 else 834 tf = port->membase + UART_TF; 835 836 if (tx_count && msm_port->is_uartdm) 837 msm_reset_dm_count(port, tx_count); 838 839 while (tf_pointer < tx_count) { 840 int i; 841 char buf[4] = { 0 }; 842 843 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 844 break; 845 846 if (msm_port->is_uartdm) 847 num_chars = min(tx_count - tf_pointer, 848 (unsigned int)sizeof(buf)); 849 else 850 num_chars = 1; 851 852 for (i = 0; i < num_chars; i++) { 853 buf[i] = xmit->buf[xmit->tail + i]; 854 port->icount.tx++; 855 } 856 857 iowrite32_rep(tf, buf, 1); 858 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1); 859 tf_pointer += num_chars; 860 } 861 862 /* disable tx interrupts if nothing more to send */ 863 if (uart_circ_empty(xmit)) 864 msm_stop_tx(port); 865 866 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 867 uart_write_wakeup(port); 868 } 869 870 static void msm_handle_tx(struct uart_port *port) 871 { 872 struct msm_port *msm_port = UART_TO_MSM(port); 873 struct circ_buf *xmit = &msm_port->uart.state->xmit; 874 struct msm_dma *dma = &msm_port->tx_dma; 875 unsigned int pio_count, dma_count, dma_min; 876 char buf[4] = { 0 }; 877 void __iomem *tf; 878 int err = 0; 879 880 if (port->x_char) { 881 if (msm_port->is_uartdm) 882 tf = port->membase + UARTDM_TF; 883 else 884 tf = port->membase + UART_TF; 885 886 buf[0] = port->x_char; 887 888 if (msm_port->is_uartdm) 889 msm_reset_dm_count(port, 1); 890 891 iowrite32_rep(tf, buf, 1); 892 port->icount.tx++; 893 port->x_char = 0; 894 return; 895 } 896 897 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 898 msm_stop_tx(port); 899 return; 900 } 901 902 pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 903 dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 904 905 dma_min = 1; /* Always DMA */ 906 if (msm_port->is_uartdm > UARTDM_1P3) { 907 dma_count = UARTDM_TX_AIGN(dma_count); 908 dma_min = UARTDM_BURST_SIZE; 909 } else { 910 if (dma_count > UARTDM_TX_MAX) 911 dma_count = UARTDM_TX_MAX; 912 } 913 914 if (pio_count > port->fifosize) 915 pio_count = port->fifosize; 916 917 if (!dma->chan || dma_count < dma_min) 918 msm_handle_tx_pio(port, pio_count); 919 else 920 err = msm_handle_tx_dma(msm_port, dma_count); 921 922 if (err) /* fall back to PIO mode */ 923 msm_handle_tx_pio(port, pio_count); 924 } 925 926 static void msm_handle_delta_cts(struct uart_port *port) 927 { 928 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); 929 port->icount.cts++; 930 wake_up_interruptible(&port->state->port.delta_msr_wait); 931 } 932 933 static irqreturn_t msm_uart_irq(int irq, void *dev_id) 934 { 935 struct uart_port *port = dev_id; 936 struct msm_port *msm_port = UART_TO_MSM(port); 937 struct msm_dma *dma = &msm_port->rx_dma; 938 unsigned long flags; 939 unsigned int misr; 940 u32 val; 941 942 spin_lock_irqsave(&port->lock, flags); 943 misr = msm_read(port, UART_MISR); 944 msm_write(port, 0, UART_IMR); /* disable interrupt */ 945 946 if (misr & UART_IMR_RXBREAK_START) { 947 msm_port->break_detected = true; 948 msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR); 949 } 950 951 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) { 952 if (dma->count) { 953 val = UART_CR_CMD_STALE_EVENT_DISABLE; 954 msm_write(port, val, UART_CR); 955 val = UART_CR_CMD_RESET_STALE_INT; 956 msm_write(port, val, UART_CR); 957 /* 958 * Flush DMA input fifo to memory, this will also 959 * trigger DMA RX completion 960 */ 961 dmaengine_terminate_all(dma->chan); 962 } else if (msm_port->is_uartdm) { 963 msm_handle_rx_dm(port, misr); 964 } else { 965 msm_handle_rx(port); 966 } 967 } 968 if (misr & UART_IMR_TXLEV) 969 msm_handle_tx(port); 970 if (misr & UART_IMR_DELTA_CTS) 971 msm_handle_delta_cts(port); 972 973 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */ 974 spin_unlock_irqrestore(&port->lock, flags); 975 976 return IRQ_HANDLED; 977 } 978 979 static unsigned int msm_tx_empty(struct uart_port *port) 980 { 981 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0; 982 } 983 984 static unsigned int msm_get_mctrl(struct uart_port *port) 985 { 986 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS; 987 } 988 989 static void msm_reset(struct uart_port *port) 990 { 991 struct msm_port *msm_port = UART_TO_MSM(port); 992 unsigned int mr; 993 994 /* reset everything */ 995 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR); 996 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR); 997 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 998 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR); 999 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); 1000 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR); 1001 mr = msm_read(port, UART_MR1); 1002 mr &= ~UART_MR1_RX_RDY_CTL; 1003 msm_write(port, mr, UART_MR1); 1004 1005 /* Disable DM modes */ 1006 if (msm_port->is_uartdm) 1007 msm_write(port, 0, UARTDM_DMEN); 1008 } 1009 1010 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl) 1011 { 1012 unsigned int mr; 1013 1014 mr = msm_read(port, UART_MR1); 1015 1016 if (!(mctrl & TIOCM_RTS)) { 1017 mr &= ~UART_MR1_RX_RDY_CTL; 1018 msm_write(port, mr, UART_MR1); 1019 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR); 1020 } else { 1021 mr |= UART_MR1_RX_RDY_CTL; 1022 msm_write(port, mr, UART_MR1); 1023 } 1024 } 1025 1026 static void msm_break_ctl(struct uart_port *port, int break_ctl) 1027 { 1028 if (break_ctl) 1029 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR); 1030 else 1031 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR); 1032 } 1033 1034 struct msm_baud_map { 1035 u16 divisor; 1036 u8 code; 1037 u8 rxstale; 1038 }; 1039 1040 static const struct msm_baud_map * 1041 msm_find_best_baud(struct uart_port *port, unsigned int baud, 1042 unsigned long *rate) 1043 { 1044 struct msm_port *msm_port = UART_TO_MSM(port); 1045 unsigned int divisor, result; 1046 unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX; 1047 const struct msm_baud_map *entry, *end, *best; 1048 static const struct msm_baud_map table[] = { 1049 { 1, 0xff, 31 }, 1050 { 2, 0xee, 16 }, 1051 { 3, 0xdd, 8 }, 1052 { 4, 0xcc, 6 }, 1053 { 6, 0xbb, 6 }, 1054 { 8, 0xaa, 6 }, 1055 { 12, 0x99, 6 }, 1056 { 16, 0x88, 1 }, 1057 { 24, 0x77, 1 }, 1058 { 32, 0x66, 1 }, 1059 { 48, 0x55, 1 }, 1060 { 96, 0x44, 1 }, 1061 { 192, 0x33, 1 }, 1062 { 384, 0x22, 1 }, 1063 { 768, 0x11, 1 }, 1064 { 1536, 0x00, 1 }, 1065 }; 1066 1067 best = table; /* Default to smallest divider */ 1068 target = clk_round_rate(msm_port->clk, 16 * baud); 1069 divisor = DIV_ROUND_CLOSEST(target, 16 * baud); 1070 1071 end = table + ARRAY_SIZE(table); 1072 entry = table; 1073 while (entry < end) { 1074 if (entry->divisor <= divisor) { 1075 result = target / entry->divisor / 16; 1076 diff = abs(result - baud); 1077 1078 /* Keep track of best entry */ 1079 if (diff < best_diff) { 1080 best_diff = diff; 1081 best = entry; 1082 best_rate = target; 1083 } 1084 1085 if (result == baud) 1086 break; 1087 } else if (entry->divisor > divisor) { 1088 old = target; 1089 target = clk_round_rate(msm_port->clk, old + 1); 1090 /* 1091 * The rate didn't get any faster so we can't do 1092 * better at dividing it down 1093 */ 1094 if (target == old) 1095 break; 1096 1097 /* Start the divisor search over at this new rate */ 1098 entry = table; 1099 divisor = DIV_ROUND_CLOSEST(target, 16 * baud); 1100 continue; 1101 } 1102 entry++; 1103 } 1104 1105 *rate = best_rate; 1106 return best; 1107 } 1108 1109 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud, 1110 unsigned long *saved_flags) 1111 { 1112 unsigned int rxstale, watermark, mask; 1113 struct msm_port *msm_port = UART_TO_MSM(port); 1114 const struct msm_baud_map *entry; 1115 unsigned long flags, rate; 1116 1117 flags = *saved_flags; 1118 spin_unlock_irqrestore(&port->lock, flags); 1119 1120 entry = msm_find_best_baud(port, baud, &rate); 1121 clk_set_rate(msm_port->clk, rate); 1122 baud = rate / 16 / entry->divisor; 1123 1124 spin_lock_irqsave(&port->lock, flags); 1125 *saved_flags = flags; 1126 port->uartclk = rate; 1127 1128 msm_write(port, entry->code, UART_CSR); 1129 1130 /* RX stale watermark */ 1131 rxstale = entry->rxstale; 1132 watermark = UART_IPR_STALE_LSB & rxstale; 1133 if (msm_port->is_uartdm) { 1134 mask = UART_DM_IPR_STALE_TIMEOUT_MSB; 1135 } else { 1136 watermark |= UART_IPR_RXSTALE_LAST; 1137 mask = UART_IPR_STALE_TIMEOUT_MSB; 1138 } 1139 1140 watermark |= mask & (rxstale << 2); 1141 1142 msm_write(port, watermark, UART_IPR); 1143 1144 /* set RX watermark */ 1145 watermark = (port->fifosize * 3) / 4; 1146 msm_write(port, watermark, UART_RFWR); 1147 1148 /* set TX watermark */ 1149 msm_write(port, 10, UART_TFWR); 1150 1151 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR); 1152 msm_reset(port); 1153 1154 /* Enable RX and TX */ 1155 msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR); 1156 1157 /* turn on RX and CTS interrupts */ 1158 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE | 1159 UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START; 1160 1161 msm_write(port, msm_port->imr, UART_IMR); 1162 1163 if (msm_port->is_uartdm) { 1164 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 1165 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 1166 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 1167 } 1168 1169 return baud; 1170 } 1171 1172 static void msm_init_clock(struct uart_port *port) 1173 { 1174 struct msm_port *msm_port = UART_TO_MSM(port); 1175 1176 clk_prepare_enable(msm_port->clk); 1177 clk_prepare_enable(msm_port->pclk); 1178 msm_serial_set_mnd_regs(port); 1179 } 1180 1181 static int msm_startup(struct uart_port *port) 1182 { 1183 struct msm_port *msm_port = UART_TO_MSM(port); 1184 unsigned int data, rfr_level, mask; 1185 int ret; 1186 1187 snprintf(msm_port->name, sizeof(msm_port->name), 1188 "msm_serial%d", port->line); 1189 1190 msm_init_clock(port); 1191 1192 if (likely(port->fifosize > 12)) 1193 rfr_level = port->fifosize - 12; 1194 else 1195 rfr_level = port->fifosize; 1196 1197 /* set automatic RFR level */ 1198 data = msm_read(port, UART_MR1); 1199 1200 if (msm_port->is_uartdm) 1201 mask = UART_DM_MR1_AUTO_RFR_LEVEL1; 1202 else 1203 mask = UART_MR1_AUTO_RFR_LEVEL1; 1204 1205 data &= ~mask; 1206 data &= ~UART_MR1_AUTO_RFR_LEVEL0; 1207 data |= mask & (rfr_level << 2); 1208 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level; 1209 msm_write(port, data, UART_MR1); 1210 1211 if (msm_port->is_uartdm) { 1212 msm_request_tx_dma(msm_port, msm_port->uart.mapbase); 1213 msm_request_rx_dma(msm_port, msm_port->uart.mapbase); 1214 } 1215 1216 ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH, 1217 msm_port->name, port); 1218 if (unlikely(ret)) 1219 goto err_irq; 1220 1221 return 0; 1222 1223 err_irq: 1224 if (msm_port->is_uartdm) 1225 msm_release_dma(msm_port); 1226 1227 clk_disable_unprepare(msm_port->pclk); 1228 clk_disable_unprepare(msm_port->clk); 1229 1230 return ret; 1231 } 1232 1233 static void msm_shutdown(struct uart_port *port) 1234 { 1235 struct msm_port *msm_port = UART_TO_MSM(port); 1236 1237 msm_port->imr = 0; 1238 msm_write(port, 0, UART_IMR); /* disable interrupts */ 1239 1240 if (msm_port->is_uartdm) 1241 msm_release_dma(msm_port); 1242 1243 clk_disable_unprepare(msm_port->clk); 1244 1245 free_irq(port->irq, port); 1246 } 1247 1248 static void msm_set_termios(struct uart_port *port, struct ktermios *termios, 1249 struct ktermios *old) 1250 { 1251 struct msm_port *msm_port = UART_TO_MSM(port); 1252 struct msm_dma *dma = &msm_port->rx_dma; 1253 unsigned long flags; 1254 unsigned int baud, mr; 1255 1256 spin_lock_irqsave(&port->lock, flags); 1257 1258 if (dma->chan) /* Terminate if any */ 1259 msm_stop_dma(port, dma); 1260 1261 /* calculate and set baud rate */ 1262 baud = uart_get_baud_rate(port, termios, old, 300, 4000000); 1263 baud = msm_set_baud_rate(port, baud, &flags); 1264 if (tty_termios_baud_rate(termios)) 1265 tty_termios_encode_baud_rate(termios, baud, baud); 1266 1267 /* calculate parity */ 1268 mr = msm_read(port, UART_MR2); 1269 mr &= ~UART_MR2_PARITY_MODE; 1270 if (termios->c_cflag & PARENB) { 1271 if (termios->c_cflag & PARODD) 1272 mr |= UART_MR2_PARITY_MODE_ODD; 1273 else if (termios->c_cflag & CMSPAR) 1274 mr |= UART_MR2_PARITY_MODE_SPACE; 1275 else 1276 mr |= UART_MR2_PARITY_MODE_EVEN; 1277 } 1278 1279 /* calculate bits per char */ 1280 mr &= ~UART_MR2_BITS_PER_CHAR; 1281 switch (termios->c_cflag & CSIZE) { 1282 case CS5: 1283 mr |= UART_MR2_BITS_PER_CHAR_5; 1284 break; 1285 case CS6: 1286 mr |= UART_MR2_BITS_PER_CHAR_6; 1287 break; 1288 case CS7: 1289 mr |= UART_MR2_BITS_PER_CHAR_7; 1290 break; 1291 case CS8: 1292 default: 1293 mr |= UART_MR2_BITS_PER_CHAR_8; 1294 break; 1295 } 1296 1297 /* calculate stop bits */ 1298 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO); 1299 if (termios->c_cflag & CSTOPB) 1300 mr |= UART_MR2_STOP_BIT_LEN_TWO; 1301 else 1302 mr |= UART_MR2_STOP_BIT_LEN_ONE; 1303 1304 /* set parity, bits per char, and stop bit */ 1305 msm_write(port, mr, UART_MR2); 1306 1307 /* calculate and set hardware flow control */ 1308 mr = msm_read(port, UART_MR1); 1309 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL); 1310 if (termios->c_cflag & CRTSCTS) { 1311 mr |= UART_MR1_CTS_CTL; 1312 mr |= UART_MR1_RX_RDY_CTL; 1313 } 1314 msm_write(port, mr, UART_MR1); 1315 1316 /* Configure status bits to ignore based on termio flags. */ 1317 port->read_status_mask = 0; 1318 if (termios->c_iflag & INPCK) 1319 port->read_status_mask |= UART_SR_PAR_FRAME_ERR; 1320 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1321 port->read_status_mask |= UART_SR_RX_BREAK; 1322 1323 uart_update_timeout(port, termios->c_cflag, baud); 1324 1325 /* Try to use DMA */ 1326 msm_start_rx_dma(msm_port); 1327 1328 spin_unlock_irqrestore(&port->lock, flags); 1329 } 1330 1331 static const char *msm_type(struct uart_port *port) 1332 { 1333 return "MSM"; 1334 } 1335 1336 static void msm_release_port(struct uart_port *port) 1337 { 1338 struct platform_device *pdev = to_platform_device(port->dev); 1339 struct resource *uart_resource; 1340 resource_size_t size; 1341 1342 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1343 if (unlikely(!uart_resource)) 1344 return; 1345 size = resource_size(uart_resource); 1346 1347 release_mem_region(port->mapbase, size); 1348 iounmap(port->membase); 1349 port->membase = NULL; 1350 } 1351 1352 static int msm_request_port(struct uart_port *port) 1353 { 1354 struct platform_device *pdev = to_platform_device(port->dev); 1355 struct resource *uart_resource; 1356 resource_size_t size; 1357 int ret; 1358 1359 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1360 if (unlikely(!uart_resource)) 1361 return -ENXIO; 1362 1363 size = resource_size(uart_resource); 1364 1365 if (!request_mem_region(port->mapbase, size, "msm_serial")) 1366 return -EBUSY; 1367 1368 port->membase = ioremap(port->mapbase, size); 1369 if (!port->membase) { 1370 ret = -EBUSY; 1371 goto fail_release_port; 1372 } 1373 1374 return 0; 1375 1376 fail_release_port: 1377 release_mem_region(port->mapbase, size); 1378 return ret; 1379 } 1380 1381 static void msm_config_port(struct uart_port *port, int flags) 1382 { 1383 int ret; 1384 1385 if (flags & UART_CONFIG_TYPE) { 1386 port->type = PORT_MSM; 1387 ret = msm_request_port(port); 1388 if (ret) 1389 return; 1390 } 1391 } 1392 1393 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser) 1394 { 1395 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM)) 1396 return -EINVAL; 1397 if (unlikely(port->irq != ser->irq)) 1398 return -EINVAL; 1399 return 0; 1400 } 1401 1402 static void msm_power(struct uart_port *port, unsigned int state, 1403 unsigned int oldstate) 1404 { 1405 struct msm_port *msm_port = UART_TO_MSM(port); 1406 1407 switch (state) { 1408 case 0: 1409 clk_prepare_enable(msm_port->clk); 1410 clk_prepare_enable(msm_port->pclk); 1411 break; 1412 case 3: 1413 clk_disable_unprepare(msm_port->clk); 1414 clk_disable_unprepare(msm_port->pclk); 1415 break; 1416 default: 1417 pr_err("msm_serial: Unknown PM state %d\n", state); 1418 } 1419 } 1420 1421 #ifdef CONFIG_CONSOLE_POLL 1422 static int msm_poll_get_char_single(struct uart_port *port) 1423 { 1424 struct msm_port *msm_port = UART_TO_MSM(port); 1425 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF; 1426 1427 if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) 1428 return NO_POLL_CHAR; 1429 1430 return msm_read(port, rf_reg) & 0xff; 1431 } 1432 1433 static int msm_poll_get_char_dm(struct uart_port *port) 1434 { 1435 int c; 1436 static u32 slop; 1437 static int count; 1438 unsigned char *sp = (unsigned char *)&slop; 1439 1440 /* Check if a previous read had more than one char */ 1441 if (count) { 1442 c = sp[sizeof(slop) - count]; 1443 count--; 1444 /* Or if FIFO is empty */ 1445 } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) { 1446 /* 1447 * If RX packing buffer has less than a word, force stale to 1448 * push contents into RX FIFO 1449 */ 1450 count = msm_read(port, UARTDM_RXFS); 1451 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK; 1452 if (count) { 1453 msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR); 1454 slop = msm_read(port, UARTDM_RF); 1455 c = sp[0]; 1456 count--; 1457 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 1458 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 1459 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, 1460 UART_CR); 1461 } else { 1462 c = NO_POLL_CHAR; 1463 } 1464 /* FIFO has a word */ 1465 } else { 1466 slop = msm_read(port, UARTDM_RF); 1467 c = sp[0]; 1468 count = sizeof(slop) - 1; 1469 } 1470 1471 return c; 1472 } 1473 1474 static int msm_poll_get_char(struct uart_port *port) 1475 { 1476 u32 imr; 1477 int c; 1478 struct msm_port *msm_port = UART_TO_MSM(port); 1479 1480 /* Disable all interrupts */ 1481 imr = msm_read(port, UART_IMR); 1482 msm_write(port, 0, UART_IMR); 1483 1484 if (msm_port->is_uartdm) 1485 c = msm_poll_get_char_dm(port); 1486 else 1487 c = msm_poll_get_char_single(port); 1488 1489 /* Enable interrupts */ 1490 msm_write(port, imr, UART_IMR); 1491 1492 return c; 1493 } 1494 1495 static void msm_poll_put_char(struct uart_port *port, unsigned char c) 1496 { 1497 u32 imr; 1498 struct msm_port *msm_port = UART_TO_MSM(port); 1499 1500 /* Disable all interrupts */ 1501 imr = msm_read(port, UART_IMR); 1502 msm_write(port, 0, UART_IMR); 1503 1504 if (msm_port->is_uartdm) 1505 msm_reset_dm_count(port, 1); 1506 1507 /* Wait until FIFO is empty */ 1508 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 1509 cpu_relax(); 1510 1511 /* Write a character */ 1512 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF); 1513 1514 /* Wait until FIFO is empty */ 1515 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 1516 cpu_relax(); 1517 1518 /* Enable interrupts */ 1519 msm_write(port, imr, UART_IMR); 1520 } 1521 #endif 1522 1523 static const struct uart_ops msm_uart_pops = { 1524 .tx_empty = msm_tx_empty, 1525 .set_mctrl = msm_set_mctrl, 1526 .get_mctrl = msm_get_mctrl, 1527 .stop_tx = msm_stop_tx, 1528 .start_tx = msm_start_tx, 1529 .stop_rx = msm_stop_rx, 1530 .enable_ms = msm_enable_ms, 1531 .break_ctl = msm_break_ctl, 1532 .startup = msm_startup, 1533 .shutdown = msm_shutdown, 1534 .set_termios = msm_set_termios, 1535 .type = msm_type, 1536 .release_port = msm_release_port, 1537 .request_port = msm_request_port, 1538 .config_port = msm_config_port, 1539 .verify_port = msm_verify_port, 1540 .pm = msm_power, 1541 #ifdef CONFIG_CONSOLE_POLL 1542 .poll_get_char = msm_poll_get_char, 1543 .poll_put_char = msm_poll_put_char, 1544 #endif 1545 }; 1546 1547 static struct msm_port msm_uart_ports[] = { 1548 { 1549 .uart = { 1550 .iotype = UPIO_MEM, 1551 .ops = &msm_uart_pops, 1552 .flags = UPF_BOOT_AUTOCONF, 1553 .fifosize = 64, 1554 .line = 0, 1555 }, 1556 }, 1557 { 1558 .uart = { 1559 .iotype = UPIO_MEM, 1560 .ops = &msm_uart_pops, 1561 .flags = UPF_BOOT_AUTOCONF, 1562 .fifosize = 64, 1563 .line = 1, 1564 }, 1565 }, 1566 { 1567 .uart = { 1568 .iotype = UPIO_MEM, 1569 .ops = &msm_uart_pops, 1570 .flags = UPF_BOOT_AUTOCONF, 1571 .fifosize = 64, 1572 .line = 2, 1573 }, 1574 }, 1575 }; 1576 1577 #define UART_NR ARRAY_SIZE(msm_uart_ports) 1578 1579 static inline struct uart_port *msm_get_port_from_line(unsigned int line) 1580 { 1581 return &msm_uart_ports[line].uart; 1582 } 1583 1584 #ifdef CONFIG_SERIAL_MSM_CONSOLE 1585 static void __msm_console_write(struct uart_port *port, const char *s, 1586 unsigned int count, bool is_uartdm) 1587 { 1588 int i; 1589 int num_newlines = 0; 1590 bool replaced = false; 1591 void __iomem *tf; 1592 int locked = 1; 1593 1594 if (is_uartdm) 1595 tf = port->membase + UARTDM_TF; 1596 else 1597 tf = port->membase + UART_TF; 1598 1599 /* Account for newlines that will get a carriage return added */ 1600 for (i = 0; i < count; i++) 1601 if (s[i] == '\n') 1602 num_newlines++; 1603 count += num_newlines; 1604 1605 if (port->sysrq) 1606 locked = 0; 1607 else if (oops_in_progress) 1608 locked = spin_trylock(&port->lock); 1609 else 1610 spin_lock(&port->lock); 1611 1612 if (is_uartdm) 1613 msm_reset_dm_count(port, count); 1614 1615 i = 0; 1616 while (i < count) { 1617 int j; 1618 unsigned int num_chars; 1619 char buf[4] = { 0 }; 1620 1621 if (is_uartdm) 1622 num_chars = min(count - i, (unsigned int)sizeof(buf)); 1623 else 1624 num_chars = 1; 1625 1626 for (j = 0; j < num_chars; j++) { 1627 char c = *s; 1628 1629 if (c == '\n' && !replaced) { 1630 buf[j] = '\r'; 1631 j++; 1632 replaced = true; 1633 } 1634 if (j < num_chars) { 1635 buf[j] = c; 1636 s++; 1637 replaced = false; 1638 } 1639 } 1640 1641 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 1642 cpu_relax(); 1643 1644 iowrite32_rep(tf, buf, 1); 1645 i += num_chars; 1646 } 1647 1648 if (locked) 1649 spin_unlock(&port->lock); 1650 } 1651 1652 static void msm_console_write(struct console *co, const char *s, 1653 unsigned int count) 1654 { 1655 struct uart_port *port; 1656 struct msm_port *msm_port; 1657 1658 BUG_ON(co->index < 0 || co->index >= UART_NR); 1659 1660 port = msm_get_port_from_line(co->index); 1661 msm_port = UART_TO_MSM(port); 1662 1663 __msm_console_write(port, s, count, msm_port->is_uartdm); 1664 } 1665 1666 static int msm_console_setup(struct console *co, char *options) 1667 { 1668 struct uart_port *port; 1669 int baud = 115200; 1670 int bits = 8; 1671 int parity = 'n'; 1672 int flow = 'n'; 1673 1674 if (unlikely(co->index >= UART_NR || co->index < 0)) 1675 return -ENXIO; 1676 1677 port = msm_get_port_from_line(co->index); 1678 1679 if (unlikely(!port->membase)) 1680 return -ENXIO; 1681 1682 msm_init_clock(port); 1683 1684 if (options) 1685 uart_parse_options(options, &baud, &parity, &bits, &flow); 1686 1687 pr_info("msm_serial: console setup on port #%d\n", port->line); 1688 1689 return uart_set_options(port, co, baud, parity, bits, flow); 1690 } 1691 1692 static void 1693 msm_serial_early_write(struct console *con, const char *s, unsigned n) 1694 { 1695 struct earlycon_device *dev = con->data; 1696 1697 __msm_console_write(&dev->port, s, n, false); 1698 } 1699 1700 static int __init 1701 msm_serial_early_console_setup(struct earlycon_device *device, const char *opt) 1702 { 1703 if (!device->port.membase) 1704 return -ENODEV; 1705 1706 device->con->write = msm_serial_early_write; 1707 return 0; 1708 } 1709 OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart", 1710 msm_serial_early_console_setup); 1711 1712 static void 1713 msm_serial_early_write_dm(struct console *con, const char *s, unsigned n) 1714 { 1715 struct earlycon_device *dev = con->data; 1716 1717 __msm_console_write(&dev->port, s, n, true); 1718 } 1719 1720 static int __init 1721 msm_serial_early_console_setup_dm(struct earlycon_device *device, 1722 const char *opt) 1723 { 1724 if (!device->port.membase) 1725 return -ENODEV; 1726 1727 device->con->write = msm_serial_early_write_dm; 1728 return 0; 1729 } 1730 OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm", 1731 msm_serial_early_console_setup_dm); 1732 1733 static struct uart_driver msm_uart_driver; 1734 1735 static struct console msm_console = { 1736 .name = "ttyMSM", 1737 .write = msm_console_write, 1738 .device = uart_console_device, 1739 .setup = msm_console_setup, 1740 .flags = CON_PRINTBUFFER, 1741 .index = -1, 1742 .data = &msm_uart_driver, 1743 }; 1744 1745 #define MSM_CONSOLE (&msm_console) 1746 1747 #else 1748 #define MSM_CONSOLE NULL 1749 #endif 1750 1751 static struct uart_driver msm_uart_driver = { 1752 .owner = THIS_MODULE, 1753 .driver_name = "msm_serial", 1754 .dev_name = "ttyMSM", 1755 .nr = UART_NR, 1756 .cons = MSM_CONSOLE, 1757 }; 1758 1759 static atomic_t msm_uart_next_id = ATOMIC_INIT(0); 1760 1761 static const struct of_device_id msm_uartdm_table[] = { 1762 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 }, 1763 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 }, 1764 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 }, 1765 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 }, 1766 { } 1767 }; 1768 1769 static int msm_serial_probe(struct platform_device *pdev) 1770 { 1771 struct msm_port *msm_port; 1772 struct resource *resource; 1773 struct uart_port *port; 1774 const struct of_device_id *id; 1775 int irq, line; 1776 1777 if (pdev->dev.of_node) 1778 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1779 else 1780 line = pdev->id; 1781 1782 if (line < 0) 1783 line = atomic_inc_return(&msm_uart_next_id) - 1; 1784 1785 if (unlikely(line < 0 || line >= UART_NR)) 1786 return -ENXIO; 1787 1788 dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line); 1789 1790 port = msm_get_port_from_line(line); 1791 port->dev = &pdev->dev; 1792 msm_port = UART_TO_MSM(port); 1793 1794 id = of_match_device(msm_uartdm_table, &pdev->dev); 1795 if (id) 1796 msm_port->is_uartdm = (unsigned long)id->data; 1797 else 1798 msm_port->is_uartdm = 0; 1799 1800 msm_port->clk = devm_clk_get(&pdev->dev, "core"); 1801 if (IS_ERR(msm_port->clk)) 1802 return PTR_ERR(msm_port->clk); 1803 1804 if (msm_port->is_uartdm) { 1805 msm_port->pclk = devm_clk_get(&pdev->dev, "iface"); 1806 if (IS_ERR(msm_port->pclk)) 1807 return PTR_ERR(msm_port->pclk); 1808 } 1809 1810 port->uartclk = clk_get_rate(msm_port->clk); 1811 dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk); 1812 1813 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1814 if (unlikely(!resource)) 1815 return -ENXIO; 1816 port->mapbase = resource->start; 1817 1818 irq = platform_get_irq(pdev, 0); 1819 if (unlikely(irq < 0)) 1820 return -ENXIO; 1821 port->irq = irq; 1822 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MSM_CONSOLE); 1823 1824 platform_set_drvdata(pdev, port); 1825 1826 return uart_add_one_port(&msm_uart_driver, port); 1827 } 1828 1829 static int msm_serial_remove(struct platform_device *pdev) 1830 { 1831 struct uart_port *port = platform_get_drvdata(pdev); 1832 1833 uart_remove_one_port(&msm_uart_driver, port); 1834 1835 return 0; 1836 } 1837 1838 static const struct of_device_id msm_match_table[] = { 1839 { .compatible = "qcom,msm-uart" }, 1840 { .compatible = "qcom,msm-uartdm" }, 1841 {} 1842 }; 1843 MODULE_DEVICE_TABLE(of, msm_match_table); 1844 1845 static int __maybe_unused msm_serial_suspend(struct device *dev) 1846 { 1847 struct msm_port *port = dev_get_drvdata(dev); 1848 1849 uart_suspend_port(&msm_uart_driver, &port->uart); 1850 1851 return 0; 1852 } 1853 1854 static int __maybe_unused msm_serial_resume(struct device *dev) 1855 { 1856 struct msm_port *port = dev_get_drvdata(dev); 1857 1858 uart_resume_port(&msm_uart_driver, &port->uart); 1859 1860 return 0; 1861 } 1862 1863 static const struct dev_pm_ops msm_serial_dev_pm_ops = { 1864 SET_SYSTEM_SLEEP_PM_OPS(msm_serial_suspend, msm_serial_resume) 1865 }; 1866 1867 static struct platform_driver msm_platform_driver = { 1868 .remove = msm_serial_remove, 1869 .probe = msm_serial_probe, 1870 .driver = { 1871 .name = "msm_serial", 1872 .pm = &msm_serial_dev_pm_ops, 1873 .of_match_table = msm_match_table, 1874 }, 1875 }; 1876 1877 static int __init msm_serial_init(void) 1878 { 1879 int ret; 1880 1881 ret = uart_register_driver(&msm_uart_driver); 1882 if (unlikely(ret)) 1883 return ret; 1884 1885 ret = platform_driver_register(&msm_platform_driver); 1886 if (unlikely(ret)) 1887 uart_unregister_driver(&msm_uart_driver); 1888 1889 pr_info("msm_serial: driver initialized\n"); 1890 1891 return ret; 1892 } 1893 1894 static void __exit msm_serial_exit(void) 1895 { 1896 platform_driver_unregister(&msm_platform_driver); 1897 uart_unregister_driver(&msm_uart_driver); 1898 } 1899 1900 module_init(msm_serial_init); 1901 module_exit(msm_serial_exit); 1902 1903 MODULE_AUTHOR("Robert Love <rlove@google.com>"); 1904 MODULE_DESCRIPTION("Driver for msm7x serial device"); 1905 MODULE_LICENSE("GPL"); 1906