1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for msm7k serial device and console 4 * 5 * Copyright (C) 2007 Google, Inc. 6 * Author: Robert Love <rlove@google.com> 7 * Copyright (c) 2011, Code Aurora Forum. All rights reserved. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/atomic.h> 12 #include <linux/dma/qcom_adm.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/dmaengine.h> 15 #include <linux/module.h> 16 #include <linux/io.h> 17 #include <linux/ioport.h> 18 #include <linux/interrupt.h> 19 #include <linux/init.h> 20 #include <linux/console.h> 21 #include <linux/tty.h> 22 #include <linux/tty_flip.h> 23 #include <linux/serial_core.h> 24 #include <linux/slab.h> 25 #include <linux/clk.h> 26 #include <linux/platform_device.h> 27 #include <linux/delay.h> 28 #include <linux/of.h> 29 #include <linux/of_device.h> 30 #include <linux/wait.h> 31 32 #define MSM_UART_MR1 0x0000 33 34 #define MSM_UART_MR1_AUTO_RFR_LEVEL0 0x3F 35 #define MSM_UART_MR1_AUTO_RFR_LEVEL1 0x3FF00 36 #define MSM_UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00 37 #define MSM_UART_MR1_RX_RDY_CTL BIT(7) 38 #define MSM_UART_MR1_CTS_CTL BIT(6) 39 40 #define MSM_UART_MR2 0x0004 41 #define MSM_UART_MR2_ERROR_MODE BIT(6) 42 #define MSM_UART_MR2_BITS_PER_CHAR 0x30 43 #define MSM_UART_MR2_BITS_PER_CHAR_5 (0x0 << 4) 44 #define MSM_UART_MR2_BITS_PER_CHAR_6 (0x1 << 4) 45 #define MSM_UART_MR2_BITS_PER_CHAR_7 (0x2 << 4) 46 #define MSM_UART_MR2_BITS_PER_CHAR_8 (0x3 << 4) 47 #define MSM_UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2) 48 #define MSM_UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2) 49 #define MSM_UART_MR2_PARITY_MODE_NONE 0x0 50 #define MSM_UART_MR2_PARITY_MODE_ODD 0x1 51 #define MSM_UART_MR2_PARITY_MODE_EVEN 0x2 52 #define MSM_UART_MR2_PARITY_MODE_SPACE 0x3 53 #define MSM_UART_MR2_PARITY_MODE 0x3 54 55 #define MSM_UART_CSR 0x0008 56 57 #define MSM_UART_TF 0x000C 58 #define UARTDM_TF 0x0070 59 60 #define MSM_UART_CR 0x0010 61 #define MSM_UART_CR_CMD_NULL (0 << 4) 62 #define MSM_UART_CR_CMD_RESET_RX (1 << 4) 63 #define MSM_UART_CR_CMD_RESET_TX (2 << 4) 64 #define MSM_UART_CR_CMD_RESET_ERR (3 << 4) 65 #define MSM_UART_CR_CMD_RESET_BREAK_INT (4 << 4) 66 #define MSM_UART_CR_CMD_START_BREAK (5 << 4) 67 #define MSM_UART_CR_CMD_STOP_BREAK (6 << 4) 68 #define MSM_UART_CR_CMD_RESET_CTS (7 << 4) 69 #define MSM_UART_CR_CMD_RESET_STALE_INT (8 << 4) 70 #define MSM_UART_CR_CMD_PACKET_MODE (9 << 4) 71 #define MSM_UART_CR_CMD_MODE_RESET (12 << 4) 72 #define MSM_UART_CR_CMD_SET_RFR (13 << 4) 73 #define MSM_UART_CR_CMD_RESET_RFR (14 << 4) 74 #define MSM_UART_CR_CMD_PROTECTION_EN (16 << 4) 75 #define MSM_UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8) 76 #define MSM_UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4) 77 #define MSM_UART_CR_CMD_FORCE_STALE (4 << 8) 78 #define MSM_UART_CR_CMD_RESET_TX_READY (3 << 8) 79 #define MSM_UART_CR_TX_DISABLE BIT(3) 80 #define MSM_UART_CR_TX_ENABLE BIT(2) 81 #define MSM_UART_CR_RX_DISABLE BIT(1) 82 #define MSM_UART_CR_RX_ENABLE BIT(0) 83 #define MSM_UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4)) 84 85 #define MSM_UART_IMR 0x0014 86 #define MSM_UART_IMR_TXLEV BIT(0) 87 #define MSM_UART_IMR_RXSTALE BIT(3) 88 #define MSM_UART_IMR_RXLEV BIT(4) 89 #define MSM_UART_IMR_DELTA_CTS BIT(5) 90 #define MSM_UART_IMR_CURRENT_CTS BIT(6) 91 #define MSM_UART_IMR_RXBREAK_START BIT(10) 92 93 #define MSM_UART_IPR_RXSTALE_LAST 0x20 94 #define MSM_UART_IPR_STALE_LSB 0x1F 95 #define MSM_UART_IPR_STALE_TIMEOUT_MSB 0x3FF80 96 #define MSM_UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80 97 98 #define MSM_UART_IPR 0x0018 99 #define MSM_UART_TFWR 0x001C 100 #define MSM_UART_RFWR 0x0020 101 #define MSM_UART_HCR 0x0024 102 103 #define MSM_UART_MREG 0x0028 104 #define MSM_UART_NREG 0x002C 105 #define MSM_UART_DREG 0x0030 106 #define MSM_UART_MNDREG 0x0034 107 #define MSM_UART_IRDA 0x0038 108 #define MSM_UART_MISR_MODE 0x0040 109 #define MSM_UART_MISR_RESET 0x0044 110 #define MSM_UART_MISR_EXPORT 0x0048 111 #define MSM_UART_MISR_VAL 0x004C 112 #define MSM_UART_TEST_CTRL 0x0050 113 114 #define MSM_UART_SR 0x0008 115 #define MSM_UART_SR_HUNT_CHAR BIT(7) 116 #define MSM_UART_SR_RX_BREAK BIT(6) 117 #define MSM_UART_SR_PAR_FRAME_ERR BIT(5) 118 #define MSM_UART_SR_OVERRUN BIT(4) 119 #define MSM_UART_SR_TX_EMPTY BIT(3) 120 #define MSM_UART_SR_TX_READY BIT(2) 121 #define MSM_UART_SR_RX_FULL BIT(1) 122 #define MSM_UART_SR_RX_READY BIT(0) 123 124 #define MSM_UART_RF 0x000C 125 #define UARTDM_RF 0x0070 126 #define MSM_UART_MISR 0x0010 127 #define MSM_UART_ISR 0x0014 128 #define MSM_UART_ISR_TX_READY BIT(7) 129 130 #define UARTDM_RXFS 0x50 131 #define UARTDM_RXFS_BUF_SHIFT 0x7 132 #define UARTDM_RXFS_BUF_MASK 0x7 133 134 #define UARTDM_DMEN 0x3C 135 #define UARTDM_DMEN_RX_SC_ENABLE BIT(5) 136 #define UARTDM_DMEN_TX_SC_ENABLE BIT(4) 137 138 #define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */ 139 #define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */ 140 141 #define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */ 142 #define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */ 143 144 #define UARTDM_DMRX 0x34 145 #define UARTDM_NCF_TX 0x40 146 #define UARTDM_RX_TOTAL_SNAP 0x38 147 148 #define UARTDM_BURST_SIZE 16 /* in bytes */ 149 #define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */ 150 #define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */ 151 #define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4) 152 153 enum { 154 UARTDM_1P1 = 1, 155 UARTDM_1P2, 156 UARTDM_1P3, 157 UARTDM_1P4, 158 }; 159 160 struct msm_dma { 161 struct dma_chan *chan; 162 enum dma_data_direction dir; 163 dma_addr_t phys; 164 unsigned char *virt; 165 dma_cookie_t cookie; 166 u32 enable_bit; 167 unsigned int count; 168 struct dma_async_tx_descriptor *desc; 169 }; 170 171 struct msm_port { 172 struct uart_port uart; 173 char name[16]; 174 struct clk *clk; 175 struct clk *pclk; 176 unsigned int imr; 177 int is_uartdm; 178 unsigned int old_snap_state; 179 bool break_detected; 180 struct msm_dma tx_dma; 181 struct msm_dma rx_dma; 182 }; 183 184 static inline struct msm_port *to_msm_port(struct uart_port *up) 185 { 186 return container_of(up, struct msm_port, uart); 187 } 188 189 static 190 void msm_write(struct uart_port *port, unsigned int val, unsigned int off) 191 { 192 writel_relaxed(val, port->membase + off); 193 } 194 195 static 196 unsigned int msm_read(struct uart_port *port, unsigned int off) 197 { 198 return readl_relaxed(port->membase + off); 199 } 200 201 /* 202 * Setup the MND registers to use the TCXO clock. 203 */ 204 static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port) 205 { 206 msm_write(port, 0x06, MSM_UART_MREG); 207 msm_write(port, 0xF1, MSM_UART_NREG); 208 msm_write(port, 0x0F, MSM_UART_DREG); 209 msm_write(port, 0x1A, MSM_UART_MNDREG); 210 port->uartclk = 1843200; 211 } 212 213 /* 214 * Setup the MND registers to use the TCXO clock divided by 4. 215 */ 216 static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port) 217 { 218 msm_write(port, 0x18, MSM_UART_MREG); 219 msm_write(port, 0xF6, MSM_UART_NREG); 220 msm_write(port, 0x0F, MSM_UART_DREG); 221 msm_write(port, 0x0A, MSM_UART_MNDREG); 222 port->uartclk = 1843200; 223 } 224 225 static void msm_serial_set_mnd_regs(struct uart_port *port) 226 { 227 struct msm_port *msm_port = to_msm_port(port); 228 229 /* 230 * These registers don't exist so we change the clk input rate 231 * on uartdm hardware instead 232 */ 233 if (msm_port->is_uartdm) 234 return; 235 236 if (port->uartclk == 19200000) 237 msm_serial_set_mnd_regs_tcxo(port); 238 else if (port->uartclk == 4800000) 239 msm_serial_set_mnd_regs_tcxoby4(port); 240 } 241 242 static void msm_handle_tx(struct uart_port *port); 243 static void msm_start_rx_dma(struct msm_port *msm_port); 244 245 static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma) 246 { 247 struct device *dev = port->dev; 248 unsigned int mapped; 249 u32 val; 250 251 mapped = dma->count; 252 dma->count = 0; 253 254 dmaengine_terminate_all(dma->chan); 255 256 /* 257 * DMA Stall happens if enqueue and flush command happens concurrently. 258 * For example before changing the baud rate/protocol configuration and 259 * sending flush command to ADM, disable the channel of UARTDM. 260 * Note: should not reset the receiver here immediately as it is not 261 * suggested to do disable/reset or reset/disable at the same time. 262 */ 263 val = msm_read(port, UARTDM_DMEN); 264 val &= ~dma->enable_bit; 265 msm_write(port, val, UARTDM_DMEN); 266 267 if (mapped) 268 dma_unmap_single(dev, dma->phys, mapped, dma->dir); 269 } 270 271 static void msm_release_dma(struct msm_port *msm_port) 272 { 273 struct msm_dma *dma; 274 275 dma = &msm_port->tx_dma; 276 if (dma->chan) { 277 msm_stop_dma(&msm_port->uart, dma); 278 dma_release_channel(dma->chan); 279 } 280 281 memset(dma, 0, sizeof(*dma)); 282 283 dma = &msm_port->rx_dma; 284 if (dma->chan) { 285 msm_stop_dma(&msm_port->uart, dma); 286 dma_release_channel(dma->chan); 287 kfree(dma->virt); 288 } 289 290 memset(dma, 0, sizeof(*dma)); 291 } 292 293 static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base) 294 { 295 struct device *dev = msm_port->uart.dev; 296 struct dma_slave_config conf; 297 struct qcom_adm_peripheral_config periph_conf = {}; 298 struct msm_dma *dma; 299 u32 crci = 0; 300 int ret; 301 302 dma = &msm_port->tx_dma; 303 304 /* allocate DMA resources, if available */ 305 dma->chan = dma_request_chan(dev, "tx"); 306 if (IS_ERR(dma->chan)) 307 goto no_tx; 308 309 of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci); 310 311 memset(&conf, 0, sizeof(conf)); 312 conf.direction = DMA_MEM_TO_DEV; 313 conf.device_fc = true; 314 conf.dst_addr = base + UARTDM_TF; 315 conf.dst_maxburst = UARTDM_BURST_SIZE; 316 if (crci) { 317 conf.peripheral_config = &periph_conf; 318 conf.peripheral_size = sizeof(periph_conf); 319 periph_conf.crci = crci; 320 } 321 322 ret = dmaengine_slave_config(dma->chan, &conf); 323 if (ret) 324 goto rel_tx; 325 326 dma->dir = DMA_TO_DEVICE; 327 328 if (msm_port->is_uartdm < UARTDM_1P4) 329 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE; 330 else 331 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE; 332 333 return; 334 335 rel_tx: 336 dma_release_channel(dma->chan); 337 no_tx: 338 memset(dma, 0, sizeof(*dma)); 339 } 340 341 static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base) 342 { 343 struct device *dev = msm_port->uart.dev; 344 struct dma_slave_config conf; 345 struct qcom_adm_peripheral_config periph_conf = {}; 346 struct msm_dma *dma; 347 u32 crci = 0; 348 int ret; 349 350 dma = &msm_port->rx_dma; 351 352 /* allocate DMA resources, if available */ 353 dma->chan = dma_request_chan(dev, "rx"); 354 if (IS_ERR(dma->chan)) 355 goto no_rx; 356 357 of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci); 358 359 dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL); 360 if (!dma->virt) 361 goto rel_rx; 362 363 memset(&conf, 0, sizeof(conf)); 364 conf.direction = DMA_DEV_TO_MEM; 365 conf.device_fc = true; 366 conf.src_addr = base + UARTDM_RF; 367 conf.src_maxburst = UARTDM_BURST_SIZE; 368 if (crci) { 369 conf.peripheral_config = &periph_conf; 370 conf.peripheral_size = sizeof(periph_conf); 371 periph_conf.crci = crci; 372 } 373 374 ret = dmaengine_slave_config(dma->chan, &conf); 375 if (ret) 376 goto err; 377 378 dma->dir = DMA_FROM_DEVICE; 379 380 if (msm_port->is_uartdm < UARTDM_1P4) 381 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE; 382 else 383 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE; 384 385 return; 386 err: 387 kfree(dma->virt); 388 rel_rx: 389 dma_release_channel(dma->chan); 390 no_rx: 391 memset(dma, 0, sizeof(*dma)); 392 } 393 394 static inline void msm_wait_for_xmitr(struct uart_port *port) 395 { 396 unsigned int timeout = 500000; 397 398 while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_EMPTY)) { 399 if (msm_read(port, MSM_UART_ISR) & MSM_UART_ISR_TX_READY) 400 break; 401 udelay(1); 402 if (!timeout--) 403 break; 404 } 405 msm_write(port, MSM_UART_CR_CMD_RESET_TX_READY, MSM_UART_CR); 406 } 407 408 static void msm_stop_tx(struct uart_port *port) 409 { 410 struct msm_port *msm_port = to_msm_port(port); 411 412 msm_port->imr &= ~MSM_UART_IMR_TXLEV; 413 msm_write(port, msm_port->imr, MSM_UART_IMR); 414 } 415 416 static void msm_start_tx(struct uart_port *port) 417 { 418 struct msm_port *msm_port = to_msm_port(port); 419 struct msm_dma *dma = &msm_port->tx_dma; 420 421 /* Already started in DMA mode */ 422 if (dma->count) 423 return; 424 425 msm_port->imr |= MSM_UART_IMR_TXLEV; 426 msm_write(port, msm_port->imr, MSM_UART_IMR); 427 } 428 429 static void msm_reset_dm_count(struct uart_port *port, int count) 430 { 431 msm_wait_for_xmitr(port); 432 msm_write(port, count, UARTDM_NCF_TX); 433 msm_read(port, UARTDM_NCF_TX); 434 } 435 436 static void msm_complete_tx_dma(void *args) 437 { 438 struct msm_port *msm_port = args; 439 struct uart_port *port = &msm_port->uart; 440 struct circ_buf *xmit = &port->state->xmit; 441 struct msm_dma *dma = &msm_port->tx_dma; 442 struct dma_tx_state state; 443 unsigned long flags; 444 unsigned int count; 445 u32 val; 446 447 spin_lock_irqsave(&port->lock, flags); 448 449 /* Already stopped */ 450 if (!dma->count) 451 goto done; 452 453 dmaengine_tx_status(dma->chan, dma->cookie, &state); 454 455 dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir); 456 457 val = msm_read(port, UARTDM_DMEN); 458 val &= ~dma->enable_bit; 459 msm_write(port, val, UARTDM_DMEN); 460 461 if (msm_port->is_uartdm > UARTDM_1P3) { 462 msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR); 463 msm_write(port, MSM_UART_CR_TX_ENABLE, MSM_UART_CR); 464 } 465 466 count = dma->count - state.residue; 467 uart_xmit_advance(port, count); 468 dma->count = 0; 469 470 /* Restore "Tx FIFO below watermark" interrupt */ 471 msm_port->imr |= MSM_UART_IMR_TXLEV; 472 msm_write(port, msm_port->imr, MSM_UART_IMR); 473 474 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 475 uart_write_wakeup(port); 476 477 msm_handle_tx(port); 478 done: 479 spin_unlock_irqrestore(&port->lock, flags); 480 } 481 482 static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count) 483 { 484 struct circ_buf *xmit = &msm_port->uart.state->xmit; 485 struct uart_port *port = &msm_port->uart; 486 struct msm_dma *dma = &msm_port->tx_dma; 487 void *cpu_addr; 488 int ret; 489 u32 val; 490 491 cpu_addr = &xmit->buf[xmit->tail]; 492 493 dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir); 494 ret = dma_mapping_error(port->dev, dma->phys); 495 if (ret) 496 return ret; 497 498 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys, 499 count, DMA_MEM_TO_DEV, 500 DMA_PREP_INTERRUPT | 501 DMA_PREP_FENCE); 502 if (!dma->desc) { 503 ret = -EIO; 504 goto unmap; 505 } 506 507 dma->desc->callback = msm_complete_tx_dma; 508 dma->desc->callback_param = msm_port; 509 510 dma->cookie = dmaengine_submit(dma->desc); 511 ret = dma_submit_error(dma->cookie); 512 if (ret) 513 goto unmap; 514 515 /* 516 * Using DMA complete for Tx FIFO reload, no need for 517 * "Tx FIFO below watermark" one, disable it 518 */ 519 msm_port->imr &= ~MSM_UART_IMR_TXLEV; 520 msm_write(port, msm_port->imr, MSM_UART_IMR); 521 522 dma->count = count; 523 524 val = msm_read(port, UARTDM_DMEN); 525 val |= dma->enable_bit; 526 527 if (msm_port->is_uartdm < UARTDM_1P4) 528 msm_write(port, val, UARTDM_DMEN); 529 530 msm_reset_dm_count(port, count); 531 532 if (msm_port->is_uartdm > UARTDM_1P3) 533 msm_write(port, val, UARTDM_DMEN); 534 535 dma_async_issue_pending(dma->chan); 536 return 0; 537 unmap: 538 dma_unmap_single(port->dev, dma->phys, count, dma->dir); 539 return ret; 540 } 541 542 static void msm_complete_rx_dma(void *args) 543 { 544 struct msm_port *msm_port = args; 545 struct uart_port *port = &msm_port->uart; 546 struct tty_port *tport = &port->state->port; 547 struct msm_dma *dma = &msm_port->rx_dma; 548 int count = 0, i, sysrq; 549 unsigned long flags; 550 u32 val; 551 552 spin_lock_irqsave(&port->lock, flags); 553 554 /* Already stopped */ 555 if (!dma->count) 556 goto done; 557 558 val = msm_read(port, UARTDM_DMEN); 559 val &= ~dma->enable_bit; 560 msm_write(port, val, UARTDM_DMEN); 561 562 if (msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN) { 563 port->icount.overrun++; 564 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 565 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR); 566 } 567 568 count = msm_read(port, UARTDM_RX_TOTAL_SNAP); 569 570 port->icount.rx += count; 571 572 dma->count = 0; 573 574 dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir); 575 576 for (i = 0; i < count; i++) { 577 char flag = TTY_NORMAL; 578 579 if (msm_port->break_detected && dma->virt[i] == 0) { 580 port->icount.brk++; 581 flag = TTY_BREAK; 582 msm_port->break_detected = false; 583 if (uart_handle_break(port)) 584 continue; 585 } 586 587 if (!(port->read_status_mask & MSM_UART_SR_RX_BREAK)) 588 flag = TTY_NORMAL; 589 590 spin_unlock_irqrestore(&port->lock, flags); 591 sysrq = uart_handle_sysrq_char(port, dma->virt[i]); 592 spin_lock_irqsave(&port->lock, flags); 593 if (!sysrq) 594 tty_insert_flip_char(tport, dma->virt[i], flag); 595 } 596 597 msm_start_rx_dma(msm_port); 598 done: 599 spin_unlock_irqrestore(&port->lock, flags); 600 601 if (count) 602 tty_flip_buffer_push(tport); 603 } 604 605 static void msm_start_rx_dma(struct msm_port *msm_port) 606 { 607 struct msm_dma *dma = &msm_port->rx_dma; 608 struct uart_port *uart = &msm_port->uart; 609 u32 val; 610 int ret; 611 612 if (IS_ENABLED(CONFIG_CONSOLE_POLL)) 613 return; 614 615 if (!dma->chan) 616 return; 617 618 dma->phys = dma_map_single(uart->dev, dma->virt, 619 UARTDM_RX_SIZE, dma->dir); 620 ret = dma_mapping_error(uart->dev, dma->phys); 621 if (ret) 622 goto sw_mode; 623 624 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys, 625 UARTDM_RX_SIZE, DMA_DEV_TO_MEM, 626 DMA_PREP_INTERRUPT); 627 if (!dma->desc) 628 goto unmap; 629 630 dma->desc->callback = msm_complete_rx_dma; 631 dma->desc->callback_param = msm_port; 632 633 dma->cookie = dmaengine_submit(dma->desc); 634 ret = dma_submit_error(dma->cookie); 635 if (ret) 636 goto unmap; 637 /* 638 * Using DMA for FIFO off-load, no need for "Rx FIFO over 639 * watermark" or "stale" interrupts, disable them 640 */ 641 msm_port->imr &= ~(MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE); 642 643 /* 644 * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3), 645 * we need RXSTALE to flush input DMA fifo to memory 646 */ 647 if (msm_port->is_uartdm < UARTDM_1P4) 648 msm_port->imr |= MSM_UART_IMR_RXSTALE; 649 650 msm_write(uart, msm_port->imr, MSM_UART_IMR); 651 652 dma->count = UARTDM_RX_SIZE; 653 654 dma_async_issue_pending(dma->chan); 655 656 msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR); 657 msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR); 658 659 val = msm_read(uart, UARTDM_DMEN); 660 val |= dma->enable_bit; 661 662 if (msm_port->is_uartdm < UARTDM_1P4) 663 msm_write(uart, val, UARTDM_DMEN); 664 665 msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX); 666 667 if (msm_port->is_uartdm > UARTDM_1P3) 668 msm_write(uart, val, UARTDM_DMEN); 669 670 return; 671 unmap: 672 dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir); 673 674 sw_mode: 675 /* 676 * Switch from DMA to SW/FIFO mode. After clearing Rx BAM (UARTDM_DMEN), 677 * receiver must be reset. 678 */ 679 msm_write(uart, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR); 680 msm_write(uart, MSM_UART_CR_RX_ENABLE, MSM_UART_CR); 681 682 msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR); 683 msm_write(uart, 0xFFFFFF, UARTDM_DMRX); 684 msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR); 685 686 /* Re-enable RX interrupts */ 687 msm_port->imr |= MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE; 688 msm_write(uart, msm_port->imr, MSM_UART_IMR); 689 } 690 691 static void msm_stop_rx(struct uart_port *port) 692 { 693 struct msm_port *msm_port = to_msm_port(port); 694 struct msm_dma *dma = &msm_port->rx_dma; 695 696 msm_port->imr &= ~(MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE); 697 msm_write(port, msm_port->imr, MSM_UART_IMR); 698 699 if (dma->chan) 700 msm_stop_dma(port, dma); 701 } 702 703 static void msm_enable_ms(struct uart_port *port) 704 { 705 struct msm_port *msm_port = to_msm_port(port); 706 707 msm_port->imr |= MSM_UART_IMR_DELTA_CTS; 708 msm_write(port, msm_port->imr, MSM_UART_IMR); 709 } 710 711 static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr) 712 __must_hold(&port->lock) 713 { 714 struct tty_port *tport = &port->state->port; 715 unsigned int sr; 716 int count = 0; 717 struct msm_port *msm_port = to_msm_port(port); 718 719 if ((msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN)) { 720 port->icount.overrun++; 721 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 722 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR); 723 } 724 725 if (misr & MSM_UART_IMR_RXSTALE) { 726 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) - 727 msm_port->old_snap_state; 728 msm_port->old_snap_state = 0; 729 } else { 730 count = 4 * (msm_read(port, MSM_UART_RFWR)); 731 msm_port->old_snap_state += count; 732 } 733 734 /* TODO: Precise error reporting */ 735 736 port->icount.rx += count; 737 738 while (count > 0) { 739 unsigned char buf[4]; 740 int sysrq, r_count, i; 741 742 sr = msm_read(port, MSM_UART_SR); 743 if ((sr & MSM_UART_SR_RX_READY) == 0) { 744 msm_port->old_snap_state -= count; 745 break; 746 } 747 748 ioread32_rep(port->membase + UARTDM_RF, buf, 1); 749 r_count = min_t(int, count, sizeof(buf)); 750 751 for (i = 0; i < r_count; i++) { 752 char flag = TTY_NORMAL; 753 754 if (msm_port->break_detected && buf[i] == 0) { 755 port->icount.brk++; 756 flag = TTY_BREAK; 757 msm_port->break_detected = false; 758 if (uart_handle_break(port)) 759 continue; 760 } 761 762 if (!(port->read_status_mask & MSM_UART_SR_RX_BREAK)) 763 flag = TTY_NORMAL; 764 765 spin_unlock(&port->lock); 766 sysrq = uart_handle_sysrq_char(port, buf[i]); 767 spin_lock(&port->lock); 768 if (!sysrq) 769 tty_insert_flip_char(tport, buf[i], flag); 770 } 771 count -= r_count; 772 } 773 774 tty_flip_buffer_push(tport); 775 776 if (misr & (MSM_UART_IMR_RXSTALE)) 777 msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR); 778 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 779 msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR); 780 781 /* Try to use DMA */ 782 msm_start_rx_dma(msm_port); 783 } 784 785 static void msm_handle_rx(struct uart_port *port) 786 __must_hold(&port->lock) 787 { 788 struct tty_port *tport = &port->state->port; 789 unsigned int sr; 790 791 /* 792 * Handle overrun. My understanding of the hardware is that overrun 793 * is not tied to the RX buffer, so we handle the case out of band. 794 */ 795 if ((msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN)) { 796 port->icount.overrun++; 797 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 798 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR); 799 } 800 801 /* and now the main RX loop */ 802 while ((sr = msm_read(port, MSM_UART_SR)) & MSM_UART_SR_RX_READY) { 803 unsigned int c; 804 char flag = TTY_NORMAL; 805 int sysrq; 806 807 c = msm_read(port, MSM_UART_RF); 808 809 if (sr & MSM_UART_SR_RX_BREAK) { 810 port->icount.brk++; 811 if (uart_handle_break(port)) 812 continue; 813 } else if (sr & MSM_UART_SR_PAR_FRAME_ERR) { 814 port->icount.frame++; 815 } else { 816 port->icount.rx++; 817 } 818 819 /* Mask conditions we're ignoring. */ 820 sr &= port->read_status_mask; 821 822 if (sr & MSM_UART_SR_RX_BREAK) 823 flag = TTY_BREAK; 824 else if (sr & MSM_UART_SR_PAR_FRAME_ERR) 825 flag = TTY_FRAME; 826 827 spin_unlock(&port->lock); 828 sysrq = uart_handle_sysrq_char(port, c); 829 spin_lock(&port->lock); 830 if (!sysrq) 831 tty_insert_flip_char(tport, c, flag); 832 } 833 834 tty_flip_buffer_push(tport); 835 } 836 837 static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count) 838 { 839 struct circ_buf *xmit = &port->state->xmit; 840 struct msm_port *msm_port = to_msm_port(port); 841 unsigned int num_chars; 842 unsigned int tf_pointer = 0; 843 void __iomem *tf; 844 845 if (msm_port->is_uartdm) 846 tf = port->membase + UARTDM_TF; 847 else 848 tf = port->membase + MSM_UART_TF; 849 850 if (tx_count && msm_port->is_uartdm) 851 msm_reset_dm_count(port, tx_count); 852 853 while (tf_pointer < tx_count) { 854 int i; 855 char buf[4] = { 0 }; 856 857 if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY)) 858 break; 859 860 if (msm_port->is_uartdm) 861 num_chars = min(tx_count - tf_pointer, 862 (unsigned int)sizeof(buf)); 863 else 864 num_chars = 1; 865 866 for (i = 0; i < num_chars; i++) 867 buf[i] = xmit->buf[xmit->tail + i]; 868 869 iowrite32_rep(tf, buf, 1); 870 uart_xmit_advance(port, num_chars); 871 tf_pointer += num_chars; 872 } 873 874 /* disable tx interrupts if nothing more to send */ 875 if (uart_circ_empty(xmit)) 876 msm_stop_tx(port); 877 878 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 879 uart_write_wakeup(port); 880 } 881 882 static void msm_handle_tx(struct uart_port *port) 883 { 884 struct msm_port *msm_port = to_msm_port(port); 885 struct circ_buf *xmit = &msm_port->uart.state->xmit; 886 struct msm_dma *dma = &msm_port->tx_dma; 887 unsigned int pio_count, dma_count, dma_min; 888 char buf[4] = { 0 }; 889 void __iomem *tf; 890 int err = 0; 891 892 if (port->x_char) { 893 if (msm_port->is_uartdm) 894 tf = port->membase + UARTDM_TF; 895 else 896 tf = port->membase + MSM_UART_TF; 897 898 buf[0] = port->x_char; 899 900 if (msm_port->is_uartdm) 901 msm_reset_dm_count(port, 1); 902 903 iowrite32_rep(tf, buf, 1); 904 port->icount.tx++; 905 port->x_char = 0; 906 return; 907 } 908 909 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 910 msm_stop_tx(port); 911 return; 912 } 913 914 pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 915 dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 916 917 dma_min = 1; /* Always DMA */ 918 if (msm_port->is_uartdm > UARTDM_1P3) { 919 dma_count = UARTDM_TX_AIGN(dma_count); 920 dma_min = UARTDM_BURST_SIZE; 921 } else { 922 if (dma_count > UARTDM_TX_MAX) 923 dma_count = UARTDM_TX_MAX; 924 } 925 926 if (pio_count > port->fifosize) 927 pio_count = port->fifosize; 928 929 if (!dma->chan || dma_count < dma_min) 930 msm_handle_tx_pio(port, pio_count); 931 else 932 err = msm_handle_tx_dma(msm_port, dma_count); 933 934 if (err) /* fall back to PIO mode */ 935 msm_handle_tx_pio(port, pio_count); 936 } 937 938 static void msm_handle_delta_cts(struct uart_port *port) 939 { 940 msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR); 941 port->icount.cts++; 942 wake_up_interruptible(&port->state->port.delta_msr_wait); 943 } 944 945 static irqreturn_t msm_uart_irq(int irq, void *dev_id) 946 { 947 struct uart_port *port = dev_id; 948 struct msm_port *msm_port = to_msm_port(port); 949 struct msm_dma *dma = &msm_port->rx_dma; 950 unsigned long flags; 951 unsigned int misr; 952 u32 val; 953 954 spin_lock_irqsave(&port->lock, flags); 955 misr = msm_read(port, MSM_UART_MISR); 956 msm_write(port, 0, MSM_UART_IMR); /* disable interrupt */ 957 958 if (misr & MSM_UART_IMR_RXBREAK_START) { 959 msm_port->break_detected = true; 960 msm_write(port, MSM_UART_CR_CMD_RESET_RXBREAK_START, MSM_UART_CR); 961 } 962 963 if (misr & (MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE)) { 964 if (dma->count) { 965 val = MSM_UART_CR_CMD_STALE_EVENT_DISABLE; 966 msm_write(port, val, MSM_UART_CR); 967 val = MSM_UART_CR_CMD_RESET_STALE_INT; 968 msm_write(port, val, MSM_UART_CR); 969 /* 970 * Flush DMA input fifo to memory, this will also 971 * trigger DMA RX completion 972 */ 973 dmaengine_terminate_all(dma->chan); 974 } else if (msm_port->is_uartdm) { 975 msm_handle_rx_dm(port, misr); 976 } else { 977 msm_handle_rx(port); 978 } 979 } 980 if (misr & MSM_UART_IMR_TXLEV) 981 msm_handle_tx(port); 982 if (misr & MSM_UART_IMR_DELTA_CTS) 983 msm_handle_delta_cts(port); 984 985 msm_write(port, msm_port->imr, MSM_UART_IMR); /* restore interrupt */ 986 spin_unlock_irqrestore(&port->lock, flags); 987 988 return IRQ_HANDLED; 989 } 990 991 static unsigned int msm_tx_empty(struct uart_port *port) 992 { 993 return (msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0; 994 } 995 996 static unsigned int msm_get_mctrl(struct uart_port *port) 997 { 998 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS; 999 } 1000 1001 static void msm_reset(struct uart_port *port) 1002 { 1003 struct msm_port *msm_port = to_msm_port(port); 1004 unsigned int mr; 1005 1006 /* reset everything */ 1007 msm_write(port, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR); 1008 msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR); 1009 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR); 1010 msm_write(port, MSM_UART_CR_CMD_RESET_BREAK_INT, MSM_UART_CR); 1011 msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR); 1012 msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR); 1013 mr = msm_read(port, MSM_UART_MR1); 1014 mr &= ~MSM_UART_MR1_RX_RDY_CTL; 1015 msm_write(port, mr, MSM_UART_MR1); 1016 1017 /* Disable DM modes */ 1018 if (msm_port->is_uartdm) 1019 msm_write(port, 0, UARTDM_DMEN); 1020 } 1021 1022 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl) 1023 { 1024 unsigned int mr; 1025 1026 mr = msm_read(port, MSM_UART_MR1); 1027 1028 if (!(mctrl & TIOCM_RTS)) { 1029 mr &= ~MSM_UART_MR1_RX_RDY_CTL; 1030 msm_write(port, mr, MSM_UART_MR1); 1031 msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR); 1032 } else { 1033 mr |= MSM_UART_MR1_RX_RDY_CTL; 1034 msm_write(port, mr, MSM_UART_MR1); 1035 } 1036 } 1037 1038 static void msm_break_ctl(struct uart_port *port, int break_ctl) 1039 { 1040 if (break_ctl) 1041 msm_write(port, MSM_UART_CR_CMD_START_BREAK, MSM_UART_CR); 1042 else 1043 msm_write(port, MSM_UART_CR_CMD_STOP_BREAK, MSM_UART_CR); 1044 } 1045 1046 struct msm_baud_map { 1047 u16 divisor; 1048 u8 code; 1049 u8 rxstale; 1050 }; 1051 1052 static const struct msm_baud_map * 1053 msm_find_best_baud(struct uart_port *port, unsigned int baud, 1054 unsigned long *rate) 1055 { 1056 struct msm_port *msm_port = to_msm_port(port); 1057 unsigned int divisor, result; 1058 unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX; 1059 const struct msm_baud_map *entry, *end, *best; 1060 static const struct msm_baud_map table[] = { 1061 { 1, 0xff, 31 }, 1062 { 2, 0xee, 16 }, 1063 { 3, 0xdd, 8 }, 1064 { 4, 0xcc, 6 }, 1065 { 6, 0xbb, 6 }, 1066 { 8, 0xaa, 6 }, 1067 { 12, 0x99, 6 }, 1068 { 16, 0x88, 1 }, 1069 { 24, 0x77, 1 }, 1070 { 32, 0x66, 1 }, 1071 { 48, 0x55, 1 }, 1072 { 96, 0x44, 1 }, 1073 { 192, 0x33, 1 }, 1074 { 384, 0x22, 1 }, 1075 { 768, 0x11, 1 }, 1076 { 1536, 0x00, 1 }, 1077 }; 1078 1079 best = table; /* Default to smallest divider */ 1080 target = clk_round_rate(msm_port->clk, 16 * baud); 1081 divisor = DIV_ROUND_CLOSEST(target, 16 * baud); 1082 1083 end = table + ARRAY_SIZE(table); 1084 entry = table; 1085 while (entry < end) { 1086 if (entry->divisor <= divisor) { 1087 result = target / entry->divisor / 16; 1088 diff = abs(result - baud); 1089 1090 /* Keep track of best entry */ 1091 if (diff < best_diff) { 1092 best_diff = diff; 1093 best = entry; 1094 best_rate = target; 1095 } 1096 1097 if (result == baud) 1098 break; 1099 } else if (entry->divisor > divisor) { 1100 old = target; 1101 target = clk_round_rate(msm_port->clk, old + 1); 1102 /* 1103 * The rate didn't get any faster so we can't do 1104 * better at dividing it down 1105 */ 1106 if (target == old) 1107 break; 1108 1109 /* Start the divisor search over at this new rate */ 1110 entry = table; 1111 divisor = DIV_ROUND_CLOSEST(target, 16 * baud); 1112 continue; 1113 } 1114 entry++; 1115 } 1116 1117 *rate = best_rate; 1118 return best; 1119 } 1120 1121 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud, 1122 unsigned long *saved_flags) 1123 { 1124 unsigned int rxstale, watermark, mask; 1125 struct msm_port *msm_port = to_msm_port(port); 1126 const struct msm_baud_map *entry; 1127 unsigned long flags, rate; 1128 1129 flags = *saved_flags; 1130 spin_unlock_irqrestore(&port->lock, flags); 1131 1132 entry = msm_find_best_baud(port, baud, &rate); 1133 clk_set_rate(msm_port->clk, rate); 1134 baud = rate / 16 / entry->divisor; 1135 1136 spin_lock_irqsave(&port->lock, flags); 1137 *saved_flags = flags; 1138 port->uartclk = rate; 1139 1140 msm_write(port, entry->code, MSM_UART_CSR); 1141 1142 /* RX stale watermark */ 1143 rxstale = entry->rxstale; 1144 watermark = MSM_UART_IPR_STALE_LSB & rxstale; 1145 if (msm_port->is_uartdm) { 1146 mask = MSM_UART_DM_IPR_STALE_TIMEOUT_MSB; 1147 } else { 1148 watermark |= MSM_UART_IPR_RXSTALE_LAST; 1149 mask = MSM_UART_IPR_STALE_TIMEOUT_MSB; 1150 } 1151 1152 watermark |= mask & (rxstale << 2); 1153 1154 msm_write(port, watermark, MSM_UART_IPR); 1155 1156 /* set RX watermark */ 1157 watermark = (port->fifosize * 3) / 4; 1158 msm_write(port, watermark, MSM_UART_RFWR); 1159 1160 /* set TX watermark */ 1161 msm_write(port, 10, MSM_UART_TFWR); 1162 1163 msm_write(port, MSM_UART_CR_CMD_PROTECTION_EN, MSM_UART_CR); 1164 msm_reset(port); 1165 1166 /* Enable RX and TX */ 1167 msm_write(port, MSM_UART_CR_TX_ENABLE | MSM_UART_CR_RX_ENABLE, MSM_UART_CR); 1168 1169 /* turn on RX and CTS interrupts */ 1170 msm_port->imr = MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE | 1171 MSM_UART_IMR_CURRENT_CTS | MSM_UART_IMR_RXBREAK_START; 1172 1173 msm_write(port, msm_port->imr, MSM_UART_IMR); 1174 1175 if (msm_port->is_uartdm) { 1176 msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR); 1177 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 1178 msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR); 1179 } 1180 1181 return baud; 1182 } 1183 1184 static void msm_init_clock(struct uart_port *port) 1185 { 1186 struct msm_port *msm_port = to_msm_port(port); 1187 1188 clk_prepare_enable(msm_port->clk); 1189 clk_prepare_enable(msm_port->pclk); 1190 msm_serial_set_mnd_regs(port); 1191 } 1192 1193 static int msm_startup(struct uart_port *port) 1194 { 1195 struct msm_port *msm_port = to_msm_port(port); 1196 unsigned int data, rfr_level, mask; 1197 int ret; 1198 1199 snprintf(msm_port->name, sizeof(msm_port->name), 1200 "msm_serial%d", port->line); 1201 1202 msm_init_clock(port); 1203 1204 if (likely(port->fifosize > 12)) 1205 rfr_level = port->fifosize - 12; 1206 else 1207 rfr_level = port->fifosize; 1208 1209 /* set automatic RFR level */ 1210 data = msm_read(port, MSM_UART_MR1); 1211 1212 if (msm_port->is_uartdm) 1213 mask = MSM_UART_DM_MR1_AUTO_RFR_LEVEL1; 1214 else 1215 mask = MSM_UART_MR1_AUTO_RFR_LEVEL1; 1216 1217 data &= ~mask; 1218 data &= ~MSM_UART_MR1_AUTO_RFR_LEVEL0; 1219 data |= mask & (rfr_level << 2); 1220 data |= MSM_UART_MR1_AUTO_RFR_LEVEL0 & rfr_level; 1221 msm_write(port, data, MSM_UART_MR1); 1222 1223 if (msm_port->is_uartdm) { 1224 msm_request_tx_dma(msm_port, msm_port->uart.mapbase); 1225 msm_request_rx_dma(msm_port, msm_port->uart.mapbase); 1226 } 1227 1228 ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH, 1229 msm_port->name, port); 1230 if (unlikely(ret)) 1231 goto err_irq; 1232 1233 return 0; 1234 1235 err_irq: 1236 if (msm_port->is_uartdm) 1237 msm_release_dma(msm_port); 1238 1239 clk_disable_unprepare(msm_port->pclk); 1240 clk_disable_unprepare(msm_port->clk); 1241 1242 return ret; 1243 } 1244 1245 static void msm_shutdown(struct uart_port *port) 1246 { 1247 struct msm_port *msm_port = to_msm_port(port); 1248 1249 msm_port->imr = 0; 1250 msm_write(port, 0, MSM_UART_IMR); /* disable interrupts */ 1251 1252 if (msm_port->is_uartdm) 1253 msm_release_dma(msm_port); 1254 1255 clk_disable_unprepare(msm_port->clk); 1256 1257 free_irq(port->irq, port); 1258 } 1259 1260 static void msm_set_termios(struct uart_port *port, struct ktermios *termios, 1261 const struct ktermios *old) 1262 { 1263 struct msm_port *msm_port = to_msm_port(port); 1264 struct msm_dma *dma = &msm_port->rx_dma; 1265 unsigned long flags; 1266 unsigned int baud, mr; 1267 1268 spin_lock_irqsave(&port->lock, flags); 1269 1270 if (dma->chan) /* Terminate if any */ 1271 msm_stop_dma(port, dma); 1272 1273 /* calculate and set baud rate */ 1274 baud = uart_get_baud_rate(port, termios, old, 300, 4000000); 1275 baud = msm_set_baud_rate(port, baud, &flags); 1276 if (tty_termios_baud_rate(termios)) 1277 tty_termios_encode_baud_rate(termios, baud, baud); 1278 1279 /* calculate parity */ 1280 mr = msm_read(port, MSM_UART_MR2); 1281 mr &= ~MSM_UART_MR2_PARITY_MODE; 1282 if (termios->c_cflag & PARENB) { 1283 if (termios->c_cflag & PARODD) 1284 mr |= MSM_UART_MR2_PARITY_MODE_ODD; 1285 else if (termios->c_cflag & CMSPAR) 1286 mr |= MSM_UART_MR2_PARITY_MODE_SPACE; 1287 else 1288 mr |= MSM_UART_MR2_PARITY_MODE_EVEN; 1289 } 1290 1291 /* calculate bits per char */ 1292 mr &= ~MSM_UART_MR2_BITS_PER_CHAR; 1293 switch (termios->c_cflag & CSIZE) { 1294 case CS5: 1295 mr |= MSM_UART_MR2_BITS_PER_CHAR_5; 1296 break; 1297 case CS6: 1298 mr |= MSM_UART_MR2_BITS_PER_CHAR_6; 1299 break; 1300 case CS7: 1301 mr |= MSM_UART_MR2_BITS_PER_CHAR_7; 1302 break; 1303 case CS8: 1304 default: 1305 mr |= MSM_UART_MR2_BITS_PER_CHAR_8; 1306 break; 1307 } 1308 1309 /* calculate stop bits */ 1310 mr &= ~(MSM_UART_MR2_STOP_BIT_LEN_ONE | MSM_UART_MR2_STOP_BIT_LEN_TWO); 1311 if (termios->c_cflag & CSTOPB) 1312 mr |= MSM_UART_MR2_STOP_BIT_LEN_TWO; 1313 else 1314 mr |= MSM_UART_MR2_STOP_BIT_LEN_ONE; 1315 1316 /* set parity, bits per char, and stop bit */ 1317 msm_write(port, mr, MSM_UART_MR2); 1318 1319 /* calculate and set hardware flow control */ 1320 mr = msm_read(port, MSM_UART_MR1); 1321 mr &= ~(MSM_UART_MR1_CTS_CTL | MSM_UART_MR1_RX_RDY_CTL); 1322 if (termios->c_cflag & CRTSCTS) { 1323 mr |= MSM_UART_MR1_CTS_CTL; 1324 mr |= MSM_UART_MR1_RX_RDY_CTL; 1325 } 1326 msm_write(port, mr, MSM_UART_MR1); 1327 1328 /* Configure status bits to ignore based on termio flags. */ 1329 port->read_status_mask = 0; 1330 if (termios->c_iflag & INPCK) 1331 port->read_status_mask |= MSM_UART_SR_PAR_FRAME_ERR; 1332 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1333 port->read_status_mask |= MSM_UART_SR_RX_BREAK; 1334 1335 uart_update_timeout(port, termios->c_cflag, baud); 1336 1337 /* Try to use DMA */ 1338 msm_start_rx_dma(msm_port); 1339 1340 spin_unlock_irqrestore(&port->lock, flags); 1341 } 1342 1343 static const char *msm_type(struct uart_port *port) 1344 { 1345 return "MSM"; 1346 } 1347 1348 static void msm_release_port(struct uart_port *port) 1349 { 1350 struct platform_device *pdev = to_platform_device(port->dev); 1351 struct resource *uart_resource; 1352 resource_size_t size; 1353 1354 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1355 if (unlikely(!uart_resource)) 1356 return; 1357 size = resource_size(uart_resource); 1358 1359 release_mem_region(port->mapbase, size); 1360 iounmap(port->membase); 1361 port->membase = NULL; 1362 } 1363 1364 static int msm_request_port(struct uart_port *port) 1365 { 1366 struct platform_device *pdev = to_platform_device(port->dev); 1367 struct resource *uart_resource; 1368 resource_size_t size; 1369 int ret; 1370 1371 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1372 if (unlikely(!uart_resource)) 1373 return -ENXIO; 1374 1375 size = resource_size(uart_resource); 1376 1377 if (!request_mem_region(port->mapbase, size, "msm_serial")) 1378 return -EBUSY; 1379 1380 port->membase = ioremap(port->mapbase, size); 1381 if (!port->membase) { 1382 ret = -EBUSY; 1383 goto fail_release_port; 1384 } 1385 1386 return 0; 1387 1388 fail_release_port: 1389 release_mem_region(port->mapbase, size); 1390 return ret; 1391 } 1392 1393 static void msm_config_port(struct uart_port *port, int flags) 1394 { 1395 int ret; 1396 1397 if (flags & UART_CONFIG_TYPE) { 1398 port->type = PORT_MSM; 1399 ret = msm_request_port(port); 1400 if (ret) 1401 return; 1402 } 1403 } 1404 1405 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser) 1406 { 1407 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM)) 1408 return -EINVAL; 1409 if (unlikely(port->irq != ser->irq)) 1410 return -EINVAL; 1411 return 0; 1412 } 1413 1414 static void msm_power(struct uart_port *port, unsigned int state, 1415 unsigned int oldstate) 1416 { 1417 struct msm_port *msm_port = to_msm_port(port); 1418 1419 switch (state) { 1420 case 0: 1421 clk_prepare_enable(msm_port->clk); 1422 clk_prepare_enable(msm_port->pclk); 1423 break; 1424 case 3: 1425 clk_disable_unprepare(msm_port->clk); 1426 clk_disable_unprepare(msm_port->pclk); 1427 break; 1428 default: 1429 pr_err("msm_serial: Unknown PM state %d\n", state); 1430 } 1431 } 1432 1433 #ifdef CONFIG_CONSOLE_POLL 1434 static int msm_poll_get_char_single(struct uart_port *port) 1435 { 1436 struct msm_port *msm_port = to_msm_port(port); 1437 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : MSM_UART_RF; 1438 1439 if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_RX_READY)) 1440 return NO_POLL_CHAR; 1441 1442 return msm_read(port, rf_reg) & 0xff; 1443 } 1444 1445 static int msm_poll_get_char_dm(struct uart_port *port) 1446 { 1447 int c; 1448 static u32 slop; 1449 static int count; 1450 unsigned char *sp = (unsigned char *)&slop; 1451 1452 /* Check if a previous read had more than one char */ 1453 if (count) { 1454 c = sp[sizeof(slop) - count]; 1455 count--; 1456 /* Or if FIFO is empty */ 1457 } else if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_RX_READY)) { 1458 /* 1459 * If RX packing buffer has less than a word, force stale to 1460 * push contents into RX FIFO 1461 */ 1462 count = msm_read(port, UARTDM_RXFS); 1463 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK; 1464 if (count) { 1465 msm_write(port, MSM_UART_CR_CMD_FORCE_STALE, MSM_UART_CR); 1466 slop = msm_read(port, UARTDM_RF); 1467 c = sp[0]; 1468 count--; 1469 msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR); 1470 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 1471 msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR); 1472 } else { 1473 c = NO_POLL_CHAR; 1474 } 1475 /* FIFO has a word */ 1476 } else { 1477 slop = msm_read(port, UARTDM_RF); 1478 c = sp[0]; 1479 count = sizeof(slop) - 1; 1480 } 1481 1482 return c; 1483 } 1484 1485 static int msm_poll_get_char(struct uart_port *port) 1486 { 1487 u32 imr; 1488 int c; 1489 struct msm_port *msm_port = to_msm_port(port); 1490 1491 /* Disable all interrupts */ 1492 imr = msm_read(port, MSM_UART_IMR); 1493 msm_write(port, 0, MSM_UART_IMR); 1494 1495 if (msm_port->is_uartdm) 1496 c = msm_poll_get_char_dm(port); 1497 else 1498 c = msm_poll_get_char_single(port); 1499 1500 /* Enable interrupts */ 1501 msm_write(port, imr, MSM_UART_IMR); 1502 1503 return c; 1504 } 1505 1506 static void msm_poll_put_char(struct uart_port *port, unsigned char c) 1507 { 1508 u32 imr; 1509 struct msm_port *msm_port = to_msm_port(port); 1510 1511 /* Disable all interrupts */ 1512 imr = msm_read(port, MSM_UART_IMR); 1513 msm_write(port, 0, MSM_UART_IMR); 1514 1515 if (msm_port->is_uartdm) 1516 msm_reset_dm_count(port, 1); 1517 1518 /* Wait until FIFO is empty */ 1519 while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY)) 1520 cpu_relax(); 1521 1522 /* Write a character */ 1523 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : MSM_UART_TF); 1524 1525 /* Wait until FIFO is empty */ 1526 while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY)) 1527 cpu_relax(); 1528 1529 /* Enable interrupts */ 1530 msm_write(port, imr, MSM_UART_IMR); 1531 } 1532 #endif 1533 1534 static const struct uart_ops msm_uart_pops = { 1535 .tx_empty = msm_tx_empty, 1536 .set_mctrl = msm_set_mctrl, 1537 .get_mctrl = msm_get_mctrl, 1538 .stop_tx = msm_stop_tx, 1539 .start_tx = msm_start_tx, 1540 .stop_rx = msm_stop_rx, 1541 .enable_ms = msm_enable_ms, 1542 .break_ctl = msm_break_ctl, 1543 .startup = msm_startup, 1544 .shutdown = msm_shutdown, 1545 .set_termios = msm_set_termios, 1546 .type = msm_type, 1547 .release_port = msm_release_port, 1548 .request_port = msm_request_port, 1549 .config_port = msm_config_port, 1550 .verify_port = msm_verify_port, 1551 .pm = msm_power, 1552 #ifdef CONFIG_CONSOLE_POLL 1553 .poll_get_char = msm_poll_get_char, 1554 .poll_put_char = msm_poll_put_char, 1555 #endif 1556 }; 1557 1558 static struct msm_port msm_uart_ports[] = { 1559 { 1560 .uart = { 1561 .iotype = UPIO_MEM, 1562 .ops = &msm_uart_pops, 1563 .flags = UPF_BOOT_AUTOCONF, 1564 .fifosize = 64, 1565 .line = 0, 1566 }, 1567 }, 1568 { 1569 .uart = { 1570 .iotype = UPIO_MEM, 1571 .ops = &msm_uart_pops, 1572 .flags = UPF_BOOT_AUTOCONF, 1573 .fifosize = 64, 1574 .line = 1, 1575 }, 1576 }, 1577 { 1578 .uart = { 1579 .iotype = UPIO_MEM, 1580 .ops = &msm_uart_pops, 1581 .flags = UPF_BOOT_AUTOCONF, 1582 .fifosize = 64, 1583 .line = 2, 1584 }, 1585 }, 1586 }; 1587 1588 #define MSM_UART_NR ARRAY_SIZE(msm_uart_ports) 1589 1590 static inline struct uart_port *msm_get_port_from_line(unsigned int line) 1591 { 1592 return &msm_uart_ports[line].uart; 1593 } 1594 1595 #ifdef CONFIG_SERIAL_MSM_CONSOLE 1596 static void __msm_console_write(struct uart_port *port, const char *s, 1597 unsigned int count, bool is_uartdm) 1598 { 1599 unsigned long flags; 1600 int i; 1601 int num_newlines = 0; 1602 bool replaced = false; 1603 void __iomem *tf; 1604 int locked = 1; 1605 1606 if (is_uartdm) 1607 tf = port->membase + UARTDM_TF; 1608 else 1609 tf = port->membase + MSM_UART_TF; 1610 1611 /* Account for newlines that will get a carriage return added */ 1612 for (i = 0; i < count; i++) 1613 if (s[i] == '\n') 1614 num_newlines++; 1615 count += num_newlines; 1616 1617 local_irq_save(flags); 1618 1619 if (port->sysrq) 1620 locked = 0; 1621 else if (oops_in_progress) 1622 locked = spin_trylock(&port->lock); 1623 else 1624 spin_lock(&port->lock); 1625 1626 if (is_uartdm) 1627 msm_reset_dm_count(port, count); 1628 1629 i = 0; 1630 while (i < count) { 1631 int j; 1632 unsigned int num_chars; 1633 char buf[4] = { 0 }; 1634 1635 if (is_uartdm) 1636 num_chars = min(count - i, (unsigned int)sizeof(buf)); 1637 else 1638 num_chars = 1; 1639 1640 for (j = 0; j < num_chars; j++) { 1641 char c = *s; 1642 1643 if (c == '\n' && !replaced) { 1644 buf[j] = '\r'; 1645 j++; 1646 replaced = true; 1647 } 1648 if (j < num_chars) { 1649 buf[j] = c; 1650 s++; 1651 replaced = false; 1652 } 1653 } 1654 1655 while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY)) 1656 cpu_relax(); 1657 1658 iowrite32_rep(tf, buf, 1); 1659 i += num_chars; 1660 } 1661 1662 if (locked) 1663 spin_unlock(&port->lock); 1664 1665 local_irq_restore(flags); 1666 } 1667 1668 static void msm_console_write(struct console *co, const char *s, 1669 unsigned int count) 1670 { 1671 struct uart_port *port; 1672 struct msm_port *msm_port; 1673 1674 BUG_ON(co->index < 0 || co->index >= MSM_UART_NR); 1675 1676 port = msm_get_port_from_line(co->index); 1677 msm_port = to_msm_port(port); 1678 1679 __msm_console_write(port, s, count, msm_port->is_uartdm); 1680 } 1681 1682 static int msm_console_setup(struct console *co, char *options) 1683 { 1684 struct uart_port *port; 1685 int baud = 115200; 1686 int bits = 8; 1687 int parity = 'n'; 1688 int flow = 'n'; 1689 1690 if (unlikely(co->index >= MSM_UART_NR || co->index < 0)) 1691 return -ENXIO; 1692 1693 port = msm_get_port_from_line(co->index); 1694 1695 if (unlikely(!port->membase)) 1696 return -ENXIO; 1697 1698 msm_init_clock(port); 1699 1700 if (options) 1701 uart_parse_options(options, &baud, &parity, &bits, &flow); 1702 1703 pr_info("msm_serial: console setup on port #%d\n", port->line); 1704 1705 return uart_set_options(port, co, baud, parity, bits, flow); 1706 } 1707 1708 static void 1709 msm_serial_early_write(struct console *con, const char *s, unsigned n) 1710 { 1711 struct earlycon_device *dev = con->data; 1712 1713 __msm_console_write(&dev->port, s, n, false); 1714 } 1715 1716 static int __init 1717 msm_serial_early_console_setup(struct earlycon_device *device, const char *opt) 1718 { 1719 if (!device->port.membase) 1720 return -ENODEV; 1721 1722 device->con->write = msm_serial_early_write; 1723 return 0; 1724 } 1725 OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart", 1726 msm_serial_early_console_setup); 1727 1728 static void 1729 msm_serial_early_write_dm(struct console *con, const char *s, unsigned n) 1730 { 1731 struct earlycon_device *dev = con->data; 1732 1733 __msm_console_write(&dev->port, s, n, true); 1734 } 1735 1736 static int __init 1737 msm_serial_early_console_setup_dm(struct earlycon_device *device, 1738 const char *opt) 1739 { 1740 if (!device->port.membase) 1741 return -ENODEV; 1742 1743 device->con->write = msm_serial_early_write_dm; 1744 return 0; 1745 } 1746 OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm", 1747 msm_serial_early_console_setup_dm); 1748 1749 static struct uart_driver msm_uart_driver; 1750 1751 static struct console msm_console = { 1752 .name = "ttyMSM", 1753 .write = msm_console_write, 1754 .device = uart_console_device, 1755 .setup = msm_console_setup, 1756 .flags = CON_PRINTBUFFER, 1757 .index = -1, 1758 .data = &msm_uart_driver, 1759 }; 1760 1761 #define MSM_CONSOLE (&msm_console) 1762 1763 #else 1764 #define MSM_CONSOLE NULL 1765 #endif 1766 1767 static struct uart_driver msm_uart_driver = { 1768 .owner = THIS_MODULE, 1769 .driver_name = "msm_serial", 1770 .dev_name = "ttyMSM", 1771 .nr = MSM_UART_NR, 1772 .cons = MSM_CONSOLE, 1773 }; 1774 1775 static atomic_t msm_uart_next_id = ATOMIC_INIT(0); 1776 1777 static const struct of_device_id msm_uartdm_table[] = { 1778 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 }, 1779 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 }, 1780 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 }, 1781 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 }, 1782 { } 1783 }; 1784 1785 static int msm_serial_probe(struct platform_device *pdev) 1786 { 1787 struct msm_port *msm_port; 1788 struct resource *resource; 1789 struct uart_port *port; 1790 const struct of_device_id *id; 1791 int irq, line; 1792 1793 if (pdev->dev.of_node) 1794 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1795 else 1796 line = pdev->id; 1797 1798 if (line < 0) 1799 line = atomic_inc_return(&msm_uart_next_id) - 1; 1800 1801 if (unlikely(line < 0 || line >= MSM_UART_NR)) 1802 return -ENXIO; 1803 1804 dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line); 1805 1806 port = msm_get_port_from_line(line); 1807 port->dev = &pdev->dev; 1808 msm_port = to_msm_port(port); 1809 1810 id = of_match_device(msm_uartdm_table, &pdev->dev); 1811 if (id) 1812 msm_port->is_uartdm = (unsigned long)id->data; 1813 else 1814 msm_port->is_uartdm = 0; 1815 1816 msm_port->clk = devm_clk_get(&pdev->dev, "core"); 1817 if (IS_ERR(msm_port->clk)) 1818 return PTR_ERR(msm_port->clk); 1819 1820 if (msm_port->is_uartdm) { 1821 msm_port->pclk = devm_clk_get(&pdev->dev, "iface"); 1822 if (IS_ERR(msm_port->pclk)) 1823 return PTR_ERR(msm_port->pclk); 1824 } 1825 1826 port->uartclk = clk_get_rate(msm_port->clk); 1827 dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk); 1828 1829 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1830 if (unlikely(!resource)) 1831 return -ENXIO; 1832 port->mapbase = resource->start; 1833 1834 irq = platform_get_irq(pdev, 0); 1835 if (unlikely(irq < 0)) 1836 return -ENXIO; 1837 port->irq = irq; 1838 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MSM_CONSOLE); 1839 1840 platform_set_drvdata(pdev, port); 1841 1842 return uart_add_one_port(&msm_uart_driver, port); 1843 } 1844 1845 static int msm_serial_remove(struct platform_device *pdev) 1846 { 1847 struct uart_port *port = platform_get_drvdata(pdev); 1848 1849 uart_remove_one_port(&msm_uart_driver, port); 1850 1851 return 0; 1852 } 1853 1854 static const struct of_device_id msm_match_table[] = { 1855 { .compatible = "qcom,msm-uart" }, 1856 { .compatible = "qcom,msm-uartdm" }, 1857 {} 1858 }; 1859 MODULE_DEVICE_TABLE(of, msm_match_table); 1860 1861 static int __maybe_unused msm_serial_suspend(struct device *dev) 1862 { 1863 struct msm_port *port = dev_get_drvdata(dev); 1864 1865 uart_suspend_port(&msm_uart_driver, &port->uart); 1866 1867 return 0; 1868 } 1869 1870 static int __maybe_unused msm_serial_resume(struct device *dev) 1871 { 1872 struct msm_port *port = dev_get_drvdata(dev); 1873 1874 uart_resume_port(&msm_uart_driver, &port->uart); 1875 1876 return 0; 1877 } 1878 1879 static const struct dev_pm_ops msm_serial_dev_pm_ops = { 1880 SET_SYSTEM_SLEEP_PM_OPS(msm_serial_suspend, msm_serial_resume) 1881 }; 1882 1883 static struct platform_driver msm_platform_driver = { 1884 .remove = msm_serial_remove, 1885 .probe = msm_serial_probe, 1886 .driver = { 1887 .name = "msm_serial", 1888 .pm = &msm_serial_dev_pm_ops, 1889 .of_match_table = msm_match_table, 1890 }, 1891 }; 1892 1893 static int __init msm_serial_init(void) 1894 { 1895 int ret; 1896 1897 ret = uart_register_driver(&msm_uart_driver); 1898 if (unlikely(ret)) 1899 return ret; 1900 1901 ret = platform_driver_register(&msm_platform_driver); 1902 if (unlikely(ret)) 1903 uart_unregister_driver(&msm_uart_driver); 1904 1905 pr_info("msm_serial: driver initialized\n"); 1906 1907 return ret; 1908 } 1909 1910 static void __exit msm_serial_exit(void) 1911 { 1912 platform_driver_unregister(&msm_platform_driver); 1913 uart_unregister_driver(&msm_uart_driver); 1914 } 1915 1916 module_init(msm_serial_init); 1917 module_exit(msm_serial_exit); 1918 1919 MODULE_AUTHOR("Robert Love <rlove@google.com>"); 1920 MODULE_DESCRIPTION("Driver for msm7x serial device"); 1921 MODULE_LICENSE("GPL"); 1922