1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MPS2 UART driver 4 * 5 * Copyright (C) 2015 ARM Limited 6 * 7 * Author: Vladimir Murzin <vladimir.murzin@arm.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * TODO: support for SysRq 14 */ 15 16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 17 18 #include <linux/bitops.h> 19 #include <linux/clk.h> 20 #include <linux/console.h> 21 #include <linux/io.h> 22 #include <linux/kernel.h> 23 #include <linux/of_device.h> 24 #include <linux/of.h> 25 #include <linux/platform_device.h> 26 #include <linux/serial_core.h> 27 #include <linux/tty_flip.h> 28 #include <linux/types.h> 29 30 #define SERIAL_NAME "ttyMPS" 31 #define DRIVER_NAME "mps2-uart" 32 #define MAKE_NAME(x) (DRIVER_NAME # x) 33 34 #define UARTn_DATA 0x00 35 36 #define UARTn_STATE 0x04 37 #define UARTn_STATE_TX_FULL BIT(0) 38 #define UARTn_STATE_RX_FULL BIT(1) 39 #define UARTn_STATE_TX_OVERRUN BIT(2) 40 #define UARTn_STATE_RX_OVERRUN BIT(3) 41 42 #define UARTn_CTRL 0x08 43 #define UARTn_CTRL_TX_ENABLE BIT(0) 44 #define UARTn_CTRL_RX_ENABLE BIT(1) 45 #define UARTn_CTRL_TX_INT_ENABLE BIT(2) 46 #define UARTn_CTRL_RX_INT_ENABLE BIT(3) 47 #define UARTn_CTRL_TX_OVERRUN_INT_ENABLE BIT(4) 48 #define UARTn_CTRL_RX_OVERRUN_INT_ENABLE BIT(5) 49 50 #define UARTn_INT 0x0c 51 #define UARTn_INT_TX BIT(0) 52 #define UARTn_INT_RX BIT(1) 53 #define UARTn_INT_TX_OVERRUN BIT(2) 54 #define UARTn_INT_RX_OVERRUN BIT(3) 55 56 #define UARTn_BAUDDIV 0x10 57 #define UARTn_BAUDDIV_MASK GENMASK(20, 0) 58 59 /* 60 * Helpers to make typical enable/disable operations more readable. 61 */ 62 #define UARTn_CTRL_TX_GRP (UARTn_CTRL_TX_ENABLE |\ 63 UARTn_CTRL_TX_INT_ENABLE |\ 64 UARTn_CTRL_TX_OVERRUN_INT_ENABLE) 65 66 #define UARTn_CTRL_RX_GRP (UARTn_CTRL_RX_ENABLE |\ 67 UARTn_CTRL_RX_INT_ENABLE |\ 68 UARTn_CTRL_RX_OVERRUN_INT_ENABLE) 69 70 #define MPS2_MAX_PORTS 3 71 72 struct mps2_uart_port { 73 struct uart_port port; 74 struct clk *clk; 75 unsigned int tx_irq; 76 unsigned int rx_irq; 77 }; 78 79 static inline struct mps2_uart_port *to_mps2_port(struct uart_port *port) 80 { 81 return container_of(port, struct mps2_uart_port, port); 82 } 83 84 static void mps2_uart_write8(struct uart_port *port, u8 val, unsigned int off) 85 { 86 struct mps2_uart_port *mps_port = to_mps2_port(port); 87 88 writeb(val, mps_port->port.membase + off); 89 } 90 91 static u8 mps2_uart_read8(struct uart_port *port, unsigned int off) 92 { 93 struct mps2_uart_port *mps_port = to_mps2_port(port); 94 95 return readb(mps_port->port.membase + off); 96 } 97 98 static void mps2_uart_write32(struct uart_port *port, u32 val, unsigned int off) 99 { 100 struct mps2_uart_port *mps_port = to_mps2_port(port); 101 102 writel_relaxed(val, mps_port->port.membase + off); 103 } 104 105 static unsigned int mps2_uart_tx_empty(struct uart_port *port) 106 { 107 u8 status = mps2_uart_read8(port, UARTn_STATE); 108 109 return (status & UARTn_STATE_TX_FULL) ? 0 : TIOCSER_TEMT; 110 } 111 112 static void mps2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 113 { 114 } 115 116 static unsigned int mps2_uart_get_mctrl(struct uart_port *port) 117 { 118 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR; 119 } 120 121 static void mps2_uart_stop_tx(struct uart_port *port) 122 { 123 u8 control = mps2_uart_read8(port, UARTn_CTRL); 124 125 control &= ~UARTn_CTRL_TX_INT_ENABLE; 126 127 mps2_uart_write8(port, control, UARTn_CTRL); 128 } 129 130 static void mps2_uart_tx_chars(struct uart_port *port) 131 { 132 struct circ_buf *xmit = &port->state->xmit; 133 134 while (!(mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)) { 135 if (port->x_char) { 136 mps2_uart_write8(port, port->x_char, UARTn_DATA); 137 port->x_char = 0; 138 port->icount.tx++; 139 continue; 140 } 141 142 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 143 break; 144 145 mps2_uart_write8(port, xmit->buf[xmit->tail], UARTn_DATA); 146 xmit->tail = (xmit->tail + 1) % UART_XMIT_SIZE; 147 port->icount.tx++; 148 } 149 150 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 151 uart_write_wakeup(port); 152 153 if (uart_circ_empty(xmit)) 154 mps2_uart_stop_tx(port); 155 } 156 157 static void mps2_uart_start_tx(struct uart_port *port) 158 { 159 u8 control = mps2_uart_read8(port, UARTn_CTRL); 160 161 control |= UARTn_CTRL_TX_INT_ENABLE; 162 163 mps2_uart_write8(port, control, UARTn_CTRL); 164 165 /* 166 * We've just unmasked the TX IRQ and now slow-starting via 167 * polling; if there is enough data to fill up the internal 168 * write buffer in one go, the TX IRQ should assert, at which 169 * point we switch to fully interrupt-driven TX. 170 */ 171 172 mps2_uart_tx_chars(port); 173 } 174 175 static void mps2_uart_stop_rx(struct uart_port *port) 176 { 177 u8 control = mps2_uart_read8(port, UARTn_CTRL); 178 179 control &= ~UARTn_CTRL_RX_GRP; 180 181 mps2_uart_write8(port, control, UARTn_CTRL); 182 } 183 184 static void mps2_uart_break_ctl(struct uart_port *port, int ctl) 185 { 186 } 187 188 static void mps2_uart_rx_chars(struct uart_port *port) 189 { 190 struct tty_port *tport = &port->state->port; 191 192 while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_RX_FULL) { 193 u8 rxdata = mps2_uart_read8(port, UARTn_DATA); 194 195 port->icount.rx++; 196 tty_insert_flip_char(&port->state->port, rxdata, TTY_NORMAL); 197 } 198 199 tty_flip_buffer_push(tport); 200 } 201 202 static irqreturn_t mps2_uart_rxirq(int irq, void *data) 203 { 204 struct uart_port *port = data; 205 u8 irqflag = mps2_uart_read8(port, UARTn_INT); 206 207 if (unlikely(!(irqflag & UARTn_INT_RX))) 208 return IRQ_NONE; 209 210 spin_lock(&port->lock); 211 212 mps2_uart_write8(port, UARTn_INT_RX, UARTn_INT); 213 mps2_uart_rx_chars(port); 214 215 spin_unlock(&port->lock); 216 217 return IRQ_HANDLED; 218 } 219 220 static irqreturn_t mps2_uart_txirq(int irq, void *data) 221 { 222 struct uart_port *port = data; 223 u8 irqflag = mps2_uart_read8(port, UARTn_INT); 224 225 if (unlikely(!(irqflag & UARTn_INT_TX))) 226 return IRQ_NONE; 227 228 spin_lock(&port->lock); 229 230 mps2_uart_write8(port, UARTn_INT_TX, UARTn_INT); 231 mps2_uart_tx_chars(port); 232 233 spin_unlock(&port->lock); 234 235 return IRQ_HANDLED; 236 } 237 238 static irqreturn_t mps2_uart_oerrirq(int irq, void *data) 239 { 240 irqreturn_t handled = IRQ_NONE; 241 struct uart_port *port = data; 242 u8 irqflag = mps2_uart_read8(port, UARTn_INT); 243 244 spin_lock(&port->lock); 245 246 if (irqflag & UARTn_INT_RX_OVERRUN) { 247 struct tty_port *tport = &port->state->port; 248 249 mps2_uart_write8(port, UARTn_INT_RX_OVERRUN, UARTn_INT); 250 port->icount.overrun++; 251 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 252 tty_flip_buffer_push(tport); 253 handled = IRQ_HANDLED; 254 } 255 256 /* 257 * It's never been seen in practice and it never *should* happen since 258 * we check if there is enough room in TX buffer before sending data. 259 * So we keep this check in case something suspicious has happened. 260 */ 261 if (irqflag & UARTn_INT_TX_OVERRUN) { 262 mps2_uart_write8(port, UARTn_INT_TX_OVERRUN, UARTn_INT); 263 handled = IRQ_HANDLED; 264 } 265 266 spin_unlock(&port->lock); 267 268 return handled; 269 } 270 271 static int mps2_uart_startup(struct uart_port *port) 272 { 273 struct mps2_uart_port *mps_port = to_mps2_port(port); 274 u8 control = mps2_uart_read8(port, UARTn_CTRL); 275 int ret; 276 277 control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP); 278 279 mps2_uart_write8(port, control, UARTn_CTRL); 280 281 ret = request_irq(mps_port->rx_irq, mps2_uart_rxirq, 0, 282 MAKE_NAME(-rx), mps_port); 283 if (ret) { 284 dev_err(port->dev, "failed to register rxirq (%d)\n", ret); 285 return ret; 286 } 287 288 ret = request_irq(mps_port->tx_irq, mps2_uart_txirq, 0, 289 MAKE_NAME(-tx), mps_port); 290 if (ret) { 291 dev_err(port->dev, "failed to register txirq (%d)\n", ret); 292 goto err_free_rxirq; 293 } 294 295 ret = request_irq(port->irq, mps2_uart_oerrirq, IRQF_SHARED, 296 MAKE_NAME(-overrun), mps_port); 297 298 if (ret) { 299 dev_err(port->dev, "failed to register oerrirq (%d)\n", ret); 300 goto err_free_txirq; 301 } 302 303 control |= UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP; 304 305 mps2_uart_write8(port, control, UARTn_CTRL); 306 307 return 0; 308 309 err_free_txirq: 310 free_irq(mps_port->tx_irq, mps_port); 311 err_free_rxirq: 312 free_irq(mps_port->rx_irq, mps_port); 313 314 return ret; 315 } 316 317 static void mps2_uart_shutdown(struct uart_port *port) 318 { 319 struct mps2_uart_port *mps_port = to_mps2_port(port); 320 u8 control = mps2_uart_read8(port, UARTn_CTRL); 321 322 control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP); 323 324 mps2_uart_write8(port, control, UARTn_CTRL); 325 326 free_irq(mps_port->rx_irq, mps_port); 327 free_irq(mps_port->tx_irq, mps_port); 328 free_irq(port->irq, mps_port); 329 } 330 331 static void 332 mps2_uart_set_termios(struct uart_port *port, struct ktermios *termios, 333 struct ktermios *old) 334 { 335 unsigned long flags; 336 unsigned int baud, bauddiv; 337 338 termios->c_cflag &= ~(CRTSCTS | CMSPAR); 339 termios->c_cflag &= ~CSIZE; 340 termios->c_cflag |= CS8; 341 termios->c_cflag &= ~PARENB; 342 termios->c_cflag &= ~CSTOPB; 343 344 baud = uart_get_baud_rate(port, termios, old, 345 DIV_ROUND_CLOSEST(port->uartclk, UARTn_BAUDDIV_MASK), 346 DIV_ROUND_CLOSEST(port->uartclk, 16)); 347 348 bauddiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 349 350 spin_lock_irqsave(&port->lock, flags); 351 352 uart_update_timeout(port, termios->c_cflag, baud); 353 mps2_uart_write32(port, bauddiv, UARTn_BAUDDIV); 354 355 spin_unlock_irqrestore(&port->lock, flags); 356 357 if (tty_termios_baud_rate(termios)) 358 tty_termios_encode_baud_rate(termios, baud, baud); 359 } 360 361 static const char *mps2_uart_type(struct uart_port *port) 362 { 363 return (port->type == PORT_MPS2UART) ? DRIVER_NAME : NULL; 364 } 365 366 static void mps2_uart_release_port(struct uart_port *port) 367 { 368 } 369 370 static int mps2_uart_request_port(struct uart_port *port) 371 { 372 return 0; 373 } 374 375 static void mps2_uart_config_port(struct uart_port *port, int type) 376 { 377 if (type & UART_CONFIG_TYPE && !mps2_uart_request_port(port)) 378 port->type = PORT_MPS2UART; 379 } 380 381 static int mps2_uart_verify_port(struct uart_port *port, struct serial_struct *serinfo) 382 { 383 return -EINVAL; 384 } 385 386 static const struct uart_ops mps2_uart_pops = { 387 .tx_empty = mps2_uart_tx_empty, 388 .set_mctrl = mps2_uart_set_mctrl, 389 .get_mctrl = mps2_uart_get_mctrl, 390 .stop_tx = mps2_uart_stop_tx, 391 .start_tx = mps2_uart_start_tx, 392 .stop_rx = mps2_uart_stop_rx, 393 .break_ctl = mps2_uart_break_ctl, 394 .startup = mps2_uart_startup, 395 .shutdown = mps2_uart_shutdown, 396 .set_termios = mps2_uart_set_termios, 397 .type = mps2_uart_type, 398 .release_port = mps2_uart_release_port, 399 .request_port = mps2_uart_request_port, 400 .config_port = mps2_uart_config_port, 401 .verify_port = mps2_uart_verify_port, 402 }; 403 404 static struct mps2_uart_port mps2_uart_ports[MPS2_MAX_PORTS]; 405 406 #ifdef CONFIG_SERIAL_MPS2_UART_CONSOLE 407 static void mps2_uart_console_putchar(struct uart_port *port, int ch) 408 { 409 while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL) 410 cpu_relax(); 411 412 mps2_uart_write8(port, ch, UARTn_DATA); 413 } 414 415 static void mps2_uart_console_write(struct console *co, const char *s, unsigned int cnt) 416 { 417 struct uart_port *port = &mps2_uart_ports[co->index].port; 418 419 uart_console_write(port, s, cnt, mps2_uart_console_putchar); 420 } 421 422 static int mps2_uart_console_setup(struct console *co, char *options) 423 { 424 struct mps2_uart_port *mps_port; 425 int baud = 9600; 426 int bits = 8; 427 int parity = 'n'; 428 int flow = 'n'; 429 430 if (co->index < 0 || co->index >= MPS2_MAX_PORTS) 431 return -ENODEV; 432 433 mps_port = &mps2_uart_ports[co->index]; 434 435 if (options) 436 uart_parse_options(options, &baud, &parity, &bits, &flow); 437 438 return uart_set_options(&mps_port->port, co, baud, parity, bits, flow); 439 } 440 441 static struct uart_driver mps2_uart_driver; 442 443 static struct console mps2_uart_console = { 444 .name = SERIAL_NAME, 445 .device = uart_console_device, 446 .write = mps2_uart_console_write, 447 .setup = mps2_uart_console_setup, 448 .flags = CON_PRINTBUFFER, 449 .index = -1, 450 .data = &mps2_uart_driver, 451 }; 452 453 #define MPS2_SERIAL_CONSOLE (&mps2_uart_console) 454 455 static void mps2_early_putchar(struct uart_port *port, int ch) 456 { 457 while (readb(port->membase + UARTn_STATE) & UARTn_STATE_TX_FULL) 458 cpu_relax(); 459 460 writeb((unsigned char)ch, port->membase + UARTn_DATA); 461 } 462 463 static void mps2_early_write(struct console *con, const char *s, unsigned int n) 464 { 465 struct earlycon_device *dev = con->data; 466 467 uart_console_write(&dev->port, s, n, mps2_early_putchar); 468 } 469 470 static int __init mps2_early_console_setup(struct earlycon_device *device, 471 const char *opt) 472 { 473 if (!device->port.membase) 474 return -ENODEV; 475 476 device->con->write = mps2_early_write; 477 478 return 0; 479 } 480 481 OF_EARLYCON_DECLARE(mps2, "arm,mps2-uart", mps2_early_console_setup); 482 483 #else 484 #define MPS2_SERIAL_CONSOLE NULL 485 #endif 486 487 static struct uart_driver mps2_uart_driver = { 488 .driver_name = DRIVER_NAME, 489 .dev_name = SERIAL_NAME, 490 .nr = MPS2_MAX_PORTS, 491 .cons = MPS2_SERIAL_CONSOLE, 492 }; 493 494 static struct mps2_uart_port *mps2_of_get_port(struct platform_device *pdev) 495 { 496 struct device_node *np = pdev->dev.of_node; 497 int id; 498 499 if (!np) 500 return NULL; 501 502 id = of_alias_get_id(np, "serial"); 503 if (id < 0) 504 id = 0; 505 506 if (WARN_ON(id >= MPS2_MAX_PORTS)) 507 return NULL; 508 509 mps2_uart_ports[id].port.line = id; 510 return &mps2_uart_ports[id]; 511 } 512 513 static int mps2_init_port(struct mps2_uart_port *mps_port, 514 struct platform_device *pdev) 515 { 516 struct resource *res; 517 int ret; 518 519 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 520 mps_port->port.membase = devm_ioremap_resource(&pdev->dev, res); 521 if (IS_ERR(mps_port->port.membase)) 522 return PTR_ERR(mps_port->port.membase); 523 524 mps_port->port.mapbase = res->start; 525 mps_port->port.mapsize = resource_size(res); 526 527 mps_port->rx_irq = platform_get_irq(pdev, 0); 528 mps_port->tx_irq = platform_get_irq(pdev, 1); 529 mps_port->port.irq = platform_get_irq(pdev, 2); 530 531 mps_port->port.iotype = UPIO_MEM; 532 mps_port->port.flags = UPF_BOOT_AUTOCONF; 533 mps_port->port.fifosize = 1; 534 mps_port->port.ops = &mps2_uart_pops; 535 mps_port->port.dev = &pdev->dev; 536 537 mps_port->clk = devm_clk_get(&pdev->dev, NULL); 538 if (IS_ERR(mps_port->clk)) 539 return PTR_ERR(mps_port->clk); 540 541 ret = clk_prepare_enable(mps_port->clk); 542 if (ret) 543 return ret; 544 545 mps_port->port.uartclk = clk_get_rate(mps_port->clk); 546 547 clk_disable_unprepare(mps_port->clk); 548 549 return ret; 550 } 551 552 static int mps2_serial_probe(struct platform_device *pdev) 553 { 554 struct mps2_uart_port *mps_port; 555 int ret; 556 557 mps_port = mps2_of_get_port(pdev); 558 if (!mps_port) 559 return -ENODEV; 560 561 ret = mps2_init_port(mps_port, pdev); 562 if (ret) 563 return ret; 564 565 ret = uart_add_one_port(&mps2_uart_driver, &mps_port->port); 566 if (ret) 567 return ret; 568 569 platform_set_drvdata(pdev, mps_port); 570 571 return 0; 572 } 573 574 #ifdef CONFIG_OF 575 static const struct of_device_id mps2_match[] = { 576 { .compatible = "arm,mps2-uart", }, 577 {}, 578 }; 579 #endif 580 581 static struct platform_driver mps2_serial_driver = { 582 .probe = mps2_serial_probe, 583 584 .driver = { 585 .name = DRIVER_NAME, 586 .of_match_table = of_match_ptr(mps2_match), 587 .suppress_bind_attrs = true, 588 }, 589 }; 590 591 static int __init mps2_uart_init(void) 592 { 593 int ret; 594 595 ret = uart_register_driver(&mps2_uart_driver); 596 if (ret) 597 return ret; 598 599 ret = platform_driver_register(&mps2_serial_driver); 600 if (ret) 601 uart_unregister_driver(&mps2_uart_driver); 602 603 return ret; 604 } 605 arch_initcall(mps2_uart_init); 606