1 /* 2 * Copyright (C) 2015 ARM Limited 3 * 4 * Author: Vladimir Murzin <vladimir.murzin@arm.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * TODO: support for SysRq 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/bitops.h> 16 #include <linux/clk.h> 17 #include <linux/console.h> 18 #include <linux/io.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/of_device.h> 22 #include <linux/of.h> 23 #include <linux/platform_device.h> 24 #include <linux/serial_core.h> 25 #include <linux/tty_flip.h> 26 #include <linux/types.h> 27 28 #define SERIAL_NAME "ttyMPS" 29 #define DRIVER_NAME "mps2-uart" 30 #define MAKE_NAME(x) (DRIVER_NAME # x) 31 32 #define UARTn_DATA 0x00 33 34 #define UARTn_STATE 0x04 35 #define UARTn_STATE_TX_FULL BIT(0) 36 #define UARTn_STATE_RX_FULL BIT(1) 37 #define UARTn_STATE_TX_OVERRUN BIT(2) 38 #define UARTn_STATE_RX_OVERRUN BIT(3) 39 40 #define UARTn_CTRL 0x08 41 #define UARTn_CTRL_TX_ENABLE BIT(0) 42 #define UARTn_CTRL_RX_ENABLE BIT(1) 43 #define UARTn_CTRL_TX_INT_ENABLE BIT(2) 44 #define UARTn_CTRL_RX_INT_ENABLE BIT(3) 45 #define UARTn_CTRL_TX_OVERRUN_INT_ENABLE BIT(4) 46 #define UARTn_CTRL_RX_OVERRUN_INT_ENABLE BIT(5) 47 48 #define UARTn_INT 0x0c 49 #define UARTn_INT_TX BIT(0) 50 #define UARTn_INT_RX BIT(1) 51 #define UARTn_INT_TX_OVERRUN BIT(2) 52 #define UARTn_INT_RX_OVERRUN BIT(3) 53 54 #define UARTn_BAUDDIV 0x10 55 #define UARTn_BAUDDIV_MASK GENMASK(20, 0) 56 57 /* 58 * Helpers to make typical enable/disable operations more readable. 59 */ 60 #define UARTn_CTRL_TX_GRP (UARTn_CTRL_TX_ENABLE |\ 61 UARTn_CTRL_TX_INT_ENABLE |\ 62 UARTn_CTRL_TX_OVERRUN_INT_ENABLE) 63 64 #define UARTn_CTRL_RX_GRP (UARTn_CTRL_RX_ENABLE |\ 65 UARTn_CTRL_RX_INT_ENABLE |\ 66 UARTn_CTRL_RX_OVERRUN_INT_ENABLE) 67 68 #define MPS2_MAX_PORTS 3 69 70 struct mps2_uart_port { 71 struct uart_port port; 72 struct clk *clk; 73 unsigned int tx_irq; 74 unsigned int rx_irq; 75 }; 76 77 static inline struct mps2_uart_port *to_mps2_port(struct uart_port *port) 78 { 79 return container_of(port, struct mps2_uart_port, port); 80 } 81 82 static void mps2_uart_write8(struct uart_port *port, u8 val, unsigned int off) 83 { 84 struct mps2_uart_port *mps_port = to_mps2_port(port); 85 86 writeb(val, mps_port->port.membase + off); 87 } 88 89 static u8 mps2_uart_read8(struct uart_port *port, unsigned int off) 90 { 91 struct mps2_uart_port *mps_port = to_mps2_port(port); 92 93 return readb(mps_port->port.membase + off); 94 } 95 96 static void mps2_uart_write32(struct uart_port *port, u32 val, unsigned int off) 97 { 98 struct mps2_uart_port *mps_port = to_mps2_port(port); 99 100 writel_relaxed(val, mps_port->port.membase + off); 101 } 102 103 static unsigned int mps2_uart_tx_empty(struct uart_port *port) 104 { 105 u8 status = mps2_uart_read8(port, UARTn_STATE); 106 107 return (status & UARTn_STATE_TX_FULL) ? 0 : TIOCSER_TEMT; 108 } 109 110 static void mps2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 111 { 112 } 113 114 static unsigned int mps2_uart_get_mctrl(struct uart_port *port) 115 { 116 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR; 117 } 118 119 static void mps2_uart_stop_tx(struct uart_port *port) 120 { 121 u8 control = mps2_uart_read8(port, UARTn_CTRL); 122 123 control &= ~UARTn_CTRL_TX_INT_ENABLE; 124 125 mps2_uart_write8(port, control, UARTn_CTRL); 126 } 127 128 static void mps2_uart_tx_chars(struct uart_port *port) 129 { 130 struct circ_buf *xmit = &port->state->xmit; 131 132 while (!(mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)) { 133 if (port->x_char) { 134 mps2_uart_write8(port, port->x_char, UARTn_DATA); 135 port->x_char = 0; 136 port->icount.tx++; 137 continue; 138 } 139 140 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 141 break; 142 143 mps2_uart_write8(port, xmit->buf[xmit->tail], UARTn_DATA); 144 xmit->tail = (xmit->tail + 1) % UART_XMIT_SIZE; 145 port->icount.tx++; 146 } 147 148 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 149 uart_write_wakeup(port); 150 151 if (uart_circ_empty(xmit)) 152 mps2_uart_stop_tx(port); 153 } 154 155 static void mps2_uart_start_tx(struct uart_port *port) 156 { 157 u8 control = mps2_uart_read8(port, UARTn_CTRL); 158 159 control |= UARTn_CTRL_TX_INT_ENABLE; 160 161 mps2_uart_write8(port, control, UARTn_CTRL); 162 163 /* 164 * We've just unmasked the TX IRQ and now slow-starting via 165 * polling; if there is enough data to fill up the internal 166 * write buffer in one go, the TX IRQ should assert, at which 167 * point we switch to fully interrupt-driven TX. 168 */ 169 170 mps2_uart_tx_chars(port); 171 } 172 173 static void mps2_uart_stop_rx(struct uart_port *port) 174 { 175 u8 control = mps2_uart_read8(port, UARTn_CTRL); 176 177 control &= ~UARTn_CTRL_RX_GRP; 178 179 mps2_uart_write8(port, control, UARTn_CTRL); 180 } 181 182 static void mps2_uart_break_ctl(struct uart_port *port, int ctl) 183 { 184 } 185 186 static void mps2_uart_rx_chars(struct uart_port *port) 187 { 188 struct tty_port *tport = &port->state->port; 189 190 while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_RX_FULL) { 191 u8 rxdata = mps2_uart_read8(port, UARTn_DATA); 192 193 port->icount.rx++; 194 tty_insert_flip_char(&port->state->port, rxdata, TTY_NORMAL); 195 } 196 197 tty_flip_buffer_push(tport); 198 } 199 200 static irqreturn_t mps2_uart_rxirq(int irq, void *data) 201 { 202 struct uart_port *port = data; 203 u8 irqflag = mps2_uart_read8(port, UARTn_INT); 204 205 if (unlikely(!(irqflag & UARTn_INT_RX))) 206 return IRQ_NONE; 207 208 spin_lock(&port->lock); 209 210 mps2_uart_write8(port, UARTn_INT_RX, UARTn_INT); 211 mps2_uart_rx_chars(port); 212 213 spin_unlock(&port->lock); 214 215 return IRQ_HANDLED; 216 } 217 218 static irqreturn_t mps2_uart_txirq(int irq, void *data) 219 { 220 struct uart_port *port = data; 221 u8 irqflag = mps2_uart_read8(port, UARTn_INT); 222 223 if (unlikely(!(irqflag & UARTn_INT_TX))) 224 return IRQ_NONE; 225 226 spin_lock(&port->lock); 227 228 mps2_uart_write8(port, UARTn_INT_TX, UARTn_INT); 229 mps2_uart_tx_chars(port); 230 231 spin_unlock(&port->lock); 232 233 return IRQ_HANDLED; 234 } 235 236 static irqreturn_t mps2_uart_oerrirq(int irq, void *data) 237 { 238 irqreturn_t handled = IRQ_NONE; 239 struct uart_port *port = data; 240 u8 irqflag = mps2_uart_read8(port, UARTn_INT); 241 242 spin_lock(&port->lock); 243 244 if (irqflag & UARTn_INT_RX_OVERRUN) { 245 struct tty_port *tport = &port->state->port; 246 247 mps2_uart_write8(port, UARTn_INT_RX_OVERRUN, UARTn_INT); 248 port->icount.overrun++; 249 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 250 tty_flip_buffer_push(tport); 251 handled = IRQ_HANDLED; 252 } 253 254 /* 255 * It's never been seen in practice and it never *should* happen since 256 * we check if there is enough room in TX buffer before sending data. 257 * So we keep this check in case something suspicious has happened. 258 */ 259 if (irqflag & UARTn_INT_TX_OVERRUN) { 260 mps2_uart_write8(port, UARTn_INT_TX_OVERRUN, UARTn_INT); 261 handled = IRQ_HANDLED; 262 } 263 264 spin_unlock(&port->lock); 265 266 return handled; 267 } 268 269 static int mps2_uart_startup(struct uart_port *port) 270 { 271 struct mps2_uart_port *mps_port = to_mps2_port(port); 272 u8 control = mps2_uart_read8(port, UARTn_CTRL); 273 int ret; 274 275 control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP); 276 277 mps2_uart_write8(port, control, UARTn_CTRL); 278 279 ret = request_irq(mps_port->rx_irq, mps2_uart_rxirq, 0, 280 MAKE_NAME(-rx), mps_port); 281 if (ret) { 282 dev_err(port->dev, "failed to register rxirq (%d)\n", ret); 283 return ret; 284 } 285 286 ret = request_irq(mps_port->tx_irq, mps2_uart_txirq, 0, 287 MAKE_NAME(-tx), mps_port); 288 if (ret) { 289 dev_err(port->dev, "failed to register txirq (%d)\n", ret); 290 goto err_free_rxirq; 291 } 292 293 ret = request_irq(port->irq, mps2_uart_oerrirq, IRQF_SHARED, 294 MAKE_NAME(-overrun), mps_port); 295 296 if (ret) { 297 dev_err(port->dev, "failed to register oerrirq (%d)\n", ret); 298 goto err_free_txirq; 299 } 300 301 control |= UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP; 302 303 mps2_uart_write8(port, control, UARTn_CTRL); 304 305 return 0; 306 307 err_free_txirq: 308 free_irq(mps_port->tx_irq, mps_port); 309 err_free_rxirq: 310 free_irq(mps_port->rx_irq, mps_port); 311 312 return ret; 313 } 314 315 static void mps2_uart_shutdown(struct uart_port *port) 316 { 317 struct mps2_uart_port *mps_port = to_mps2_port(port); 318 u8 control = mps2_uart_read8(port, UARTn_CTRL); 319 320 control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP); 321 322 mps2_uart_write8(port, control, UARTn_CTRL); 323 324 free_irq(mps_port->rx_irq, mps_port); 325 free_irq(mps_port->tx_irq, mps_port); 326 free_irq(port->irq, mps_port); 327 } 328 329 static void 330 mps2_uart_set_termios(struct uart_port *port, struct ktermios *termios, 331 struct ktermios *old) 332 { 333 unsigned long flags; 334 unsigned int baud, bauddiv; 335 336 termios->c_cflag &= ~(CRTSCTS | CMSPAR); 337 termios->c_cflag &= ~CSIZE; 338 termios->c_cflag |= CS8; 339 termios->c_cflag &= ~PARENB; 340 termios->c_cflag &= ~CSTOPB; 341 342 baud = uart_get_baud_rate(port, termios, old, 343 DIV_ROUND_CLOSEST(port->uartclk, UARTn_BAUDDIV_MASK), 344 DIV_ROUND_CLOSEST(port->uartclk, 16)); 345 346 bauddiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 347 348 spin_lock_irqsave(&port->lock, flags); 349 350 uart_update_timeout(port, termios->c_cflag, baud); 351 mps2_uart_write32(port, bauddiv, UARTn_BAUDDIV); 352 353 spin_unlock_irqrestore(&port->lock, flags); 354 355 if (tty_termios_baud_rate(termios)) 356 tty_termios_encode_baud_rate(termios, baud, baud); 357 } 358 359 static const char *mps2_uart_type(struct uart_port *port) 360 { 361 return (port->type == PORT_MPS2UART) ? DRIVER_NAME : NULL; 362 } 363 364 static void mps2_uart_release_port(struct uart_port *port) 365 { 366 } 367 368 static int mps2_uart_request_port(struct uart_port *port) 369 { 370 return 0; 371 } 372 373 static void mps2_uart_config_port(struct uart_port *port, int type) 374 { 375 if (type & UART_CONFIG_TYPE && !mps2_uart_request_port(port)) 376 port->type = PORT_MPS2UART; 377 } 378 379 static int mps2_uart_verify_port(struct uart_port *port, struct serial_struct *serinfo) 380 { 381 return -EINVAL; 382 } 383 384 static const struct uart_ops mps2_uart_pops = { 385 .tx_empty = mps2_uart_tx_empty, 386 .set_mctrl = mps2_uart_set_mctrl, 387 .get_mctrl = mps2_uart_get_mctrl, 388 .stop_tx = mps2_uart_stop_tx, 389 .start_tx = mps2_uart_start_tx, 390 .stop_rx = mps2_uart_stop_rx, 391 .break_ctl = mps2_uart_break_ctl, 392 .startup = mps2_uart_startup, 393 .shutdown = mps2_uart_shutdown, 394 .set_termios = mps2_uart_set_termios, 395 .type = mps2_uart_type, 396 .release_port = mps2_uart_release_port, 397 .request_port = mps2_uart_request_port, 398 .config_port = mps2_uart_config_port, 399 .verify_port = mps2_uart_verify_port, 400 }; 401 402 static struct mps2_uart_port mps2_uart_ports[MPS2_MAX_PORTS]; 403 404 #ifdef CONFIG_SERIAL_MPS2_UART_CONSOLE 405 static void mps2_uart_console_putchar(struct uart_port *port, int ch) 406 { 407 while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL) 408 cpu_relax(); 409 410 mps2_uart_write8(port, ch, UARTn_DATA); 411 } 412 413 static void mps2_uart_console_write(struct console *co, const char *s, unsigned int cnt) 414 { 415 struct uart_port *port = &mps2_uart_ports[co->index].port; 416 417 uart_console_write(port, s, cnt, mps2_uart_console_putchar); 418 } 419 420 static int mps2_uart_console_setup(struct console *co, char *options) 421 { 422 struct mps2_uart_port *mps_port; 423 int baud = 9600; 424 int bits = 8; 425 int parity = 'n'; 426 int flow = 'n'; 427 428 if (co->index < 0 || co->index >= MPS2_MAX_PORTS) 429 return -ENODEV; 430 431 mps_port = &mps2_uart_ports[co->index]; 432 433 if (options) 434 uart_parse_options(options, &baud, &parity, &bits, &flow); 435 436 return uart_set_options(&mps_port->port, co, baud, parity, bits, flow); 437 } 438 439 static struct uart_driver mps2_uart_driver; 440 441 static struct console mps2_uart_console = { 442 .name = SERIAL_NAME, 443 .device = uart_console_device, 444 .write = mps2_uart_console_write, 445 .setup = mps2_uart_console_setup, 446 .flags = CON_PRINTBUFFER, 447 .index = -1, 448 .data = &mps2_uart_driver, 449 }; 450 451 #define MPS2_SERIAL_CONSOLE (&mps2_uart_console) 452 453 static void mps2_early_putchar(struct uart_port *port, int ch) 454 { 455 while (readb(port->membase + UARTn_STATE) & UARTn_STATE_TX_FULL) 456 cpu_relax(); 457 458 writeb((unsigned char)ch, port->membase + UARTn_DATA); 459 } 460 461 static void mps2_early_write(struct console *con, const char *s, unsigned int n) 462 { 463 struct earlycon_device *dev = con->data; 464 465 uart_console_write(&dev->port, s, n, mps2_early_putchar); 466 } 467 468 static int __init mps2_early_console_setup(struct earlycon_device *device, 469 const char *opt) 470 { 471 if (!device->port.membase) 472 return -ENODEV; 473 474 device->con->write = mps2_early_write; 475 476 return 0; 477 } 478 479 OF_EARLYCON_DECLARE(mps2, "arm,mps2-uart", mps2_early_console_setup); 480 481 #else 482 #define MPS2_SERIAL_CONSOLE NULL 483 #endif 484 485 static struct uart_driver mps2_uart_driver = { 486 .driver_name = DRIVER_NAME, 487 .dev_name = SERIAL_NAME, 488 .nr = MPS2_MAX_PORTS, 489 .cons = MPS2_SERIAL_CONSOLE, 490 }; 491 492 static struct mps2_uart_port *mps2_of_get_port(struct platform_device *pdev) 493 { 494 struct device_node *np = pdev->dev.of_node; 495 int id; 496 497 if (!np) 498 return NULL; 499 500 id = of_alias_get_id(np, "serial"); 501 if (id < 0) 502 id = 0; 503 504 if (WARN_ON(id >= MPS2_MAX_PORTS)) 505 return NULL; 506 507 mps2_uart_ports[id].port.line = id; 508 return &mps2_uart_ports[id]; 509 } 510 511 static int mps2_init_port(struct mps2_uart_port *mps_port, 512 struct platform_device *pdev) 513 { 514 struct resource *res; 515 int ret; 516 517 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 518 mps_port->port.membase = devm_ioremap_resource(&pdev->dev, res); 519 if (IS_ERR(mps_port->port.membase)) 520 return PTR_ERR(mps_port->port.membase); 521 522 mps_port->port.mapbase = res->start; 523 mps_port->port.mapsize = resource_size(res); 524 525 mps_port->rx_irq = platform_get_irq(pdev, 0); 526 mps_port->tx_irq = platform_get_irq(pdev, 1); 527 mps_port->port.irq = platform_get_irq(pdev, 2); 528 529 mps_port->port.iotype = UPIO_MEM; 530 mps_port->port.flags = UPF_BOOT_AUTOCONF; 531 mps_port->port.fifosize = 1; 532 mps_port->port.ops = &mps2_uart_pops; 533 mps_port->port.dev = &pdev->dev; 534 535 mps_port->clk = devm_clk_get(&pdev->dev, NULL); 536 if (IS_ERR(mps_port->clk)) 537 return PTR_ERR(mps_port->clk); 538 539 ret = clk_prepare_enable(mps_port->clk); 540 if (ret) 541 return ret; 542 543 mps_port->port.uartclk = clk_get_rate(mps_port->clk); 544 545 clk_disable_unprepare(mps_port->clk); 546 547 return ret; 548 } 549 550 static int mps2_serial_probe(struct platform_device *pdev) 551 { 552 struct mps2_uart_port *mps_port; 553 int ret; 554 555 mps_port = mps2_of_get_port(pdev); 556 if (!mps_port) 557 return -ENODEV; 558 559 ret = mps2_init_port(mps_port, pdev); 560 if (ret) 561 return ret; 562 563 ret = uart_add_one_port(&mps2_uart_driver, &mps_port->port); 564 if (ret) 565 return ret; 566 567 platform_set_drvdata(pdev, mps_port); 568 569 return 0; 570 } 571 572 static int mps2_serial_remove(struct platform_device *pdev) 573 { 574 struct mps2_uart_port *mps_port = platform_get_drvdata(pdev); 575 576 uart_remove_one_port(&mps2_uart_driver, &mps_port->port); 577 578 return 0; 579 } 580 581 #ifdef CONFIG_OF 582 static const struct of_device_id mps2_match[] = { 583 { .compatible = "arm,mps2-uart", }, 584 {}, 585 }; 586 MODULE_DEVICE_TABLE(of, mps2_match); 587 #endif 588 589 static struct platform_driver mps2_serial_driver = { 590 .probe = mps2_serial_probe, 591 .remove = mps2_serial_remove, 592 593 .driver = { 594 .name = DRIVER_NAME, 595 .of_match_table = of_match_ptr(mps2_match), 596 }, 597 }; 598 599 static int __init mps2_uart_init(void) 600 { 601 int ret; 602 603 ret = uart_register_driver(&mps2_uart_driver); 604 if (ret) 605 return ret; 606 607 ret = platform_driver_register(&mps2_serial_driver); 608 if (ret) 609 uart_unregister_driver(&mps2_uart_driver); 610 611 return ret; 612 } 613 module_init(mps2_uart_init); 614 615 static void __exit mps2_uart_exit(void) 616 { 617 platform_driver_unregister(&mps2_serial_driver); 618 uart_unregister_driver(&mps2_uart_driver); 619 } 620 module_exit(mps2_uart_exit); 621 622 MODULE_AUTHOR("Vladimir Murzin <vladimir.murzin@arm.com>"); 623 MODULE_DESCRIPTION("MPS2 UART driver"); 624 MODULE_LICENSE("GPL v2"); 625 MODULE_ALIAS("platform:" DRIVER_NAME); 626