1 /* 2 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs. 3 * 4 * FIXME According to the usermanual the status bits in the status register 5 * are only updated when the peripherals access the FIFO and not when the 6 * CPU access them. So since we use this bits to know when we stop writing 7 * and reading, they may not be updated in-time and a race condition may 8 * exists. But I haven't be able to prove this and I don't care. But if 9 * any problem arises, it might worth checking. The TX/RX FIFO Stats 10 * registers should be used in addition. 11 * Update: Actually, they seem updated ... At least the bits we use. 12 * 13 * 14 * Maintainer : Sylvain Munaut <tnt@246tNt.com> 15 * 16 * Some of the code has been inspired/copied from the 2.4 code written 17 * by Dale Farnsworth <dfarnsworth@mvista.com>. 18 * 19 * Copyright (C) 2008 Freescale Semiconductor Inc. 20 * John Rigby <jrigby@gmail.com> 21 * Added support for MPC5121 22 * Copyright (C) 2006 Secret Lab Technologies Ltd. 23 * Grant Likely <grant.likely@secretlab.ca> 24 * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com> 25 * Copyright (C) 2003 MontaVista, Software, Inc. 26 * 27 * This file is licensed under the terms of the GNU General Public License 28 * version 2. This program is licensed "as is" without any warranty of any 29 * kind, whether express or implied. 30 */ 31 32 #undef DEBUG 33 34 #include <linux/device.h> 35 #include <linux/module.h> 36 #include <linux/tty.h> 37 #include <linux/tty_flip.h> 38 #include <linux/serial.h> 39 #include <linux/sysrq.h> 40 #include <linux/console.h> 41 #include <linux/delay.h> 42 #include <linux/io.h> 43 #include <linux/of.h> 44 #include <linux/of_platform.h> 45 #include <linux/clk.h> 46 47 #include <asm/mpc52xx.h> 48 #include <asm/mpc52xx_psc.h> 49 50 #if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 51 #define SUPPORT_SYSRQ 52 #endif 53 54 #include <linux/serial_core.h> 55 56 57 /* We've been assigned a range on the "Low-density serial ports" major */ 58 #define SERIAL_PSC_MAJOR 204 59 #define SERIAL_PSC_MINOR 148 60 61 62 #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */ 63 64 65 static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM]; 66 /* Rem: - We use the read_status_mask as a shadow of 67 * psc->mpc52xx_psc_imr 68 * - It's important that is array is all zero on start as we 69 * use it to know if it's initialized or not ! If it's not sure 70 * it's cleared, then a memset(...,0,...) should be added to 71 * the console_init 72 */ 73 74 /* lookup table for matching device nodes to index numbers */ 75 static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM]; 76 77 static void mpc52xx_uart_of_enumerate(void); 78 79 80 #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase)) 81 82 83 /* Forward declaration of the interruption handling routine */ 84 static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id); 85 static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port); 86 87 /* ======================================================================== */ 88 /* PSC fifo operations for isolating differences between 52xx and 512x */ 89 /* ======================================================================== */ 90 91 struct psc_ops { 92 void (*fifo_init)(struct uart_port *port); 93 int (*raw_rx_rdy)(struct uart_port *port); 94 int (*raw_tx_rdy)(struct uart_port *port); 95 int (*rx_rdy)(struct uart_port *port); 96 int (*tx_rdy)(struct uart_port *port); 97 int (*tx_empty)(struct uart_port *port); 98 void (*stop_rx)(struct uart_port *port); 99 void (*start_tx)(struct uart_port *port); 100 void (*stop_tx)(struct uart_port *port); 101 void (*rx_clr_irq)(struct uart_port *port); 102 void (*tx_clr_irq)(struct uart_port *port); 103 void (*write_char)(struct uart_port *port, unsigned char c); 104 unsigned char (*read_char)(struct uart_port *port); 105 void (*cw_disable_ints)(struct uart_port *port); 106 void (*cw_restore_ints)(struct uart_port *port); 107 unsigned int (*set_baudrate)(struct uart_port *port, 108 struct ktermios *new, 109 struct ktermios *old); 110 int (*clock)(struct uart_port *port, int enable); 111 int (*fifoc_init)(void); 112 void (*fifoc_uninit)(void); 113 void (*get_irq)(struct uart_port *, struct device_node *); 114 irqreturn_t (*handle_irq)(struct uart_port *port); 115 u16 (*get_status)(struct uart_port *port); 116 u8 (*get_ipcr)(struct uart_port *port); 117 void (*command)(struct uart_port *port, u8 cmd); 118 void (*set_mode)(struct uart_port *port, u8 mr1, u8 mr2); 119 void (*set_rts)(struct uart_port *port, int state); 120 void (*enable_ms)(struct uart_port *port); 121 void (*set_sicr)(struct uart_port *port, u32 val); 122 void (*set_imr)(struct uart_port *port, u16 val); 123 u8 (*get_mr1)(struct uart_port *port); 124 }; 125 126 /* setting the prescaler and divisor reg is common for all chips */ 127 static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc, 128 u16 prescaler, unsigned int divisor) 129 { 130 /* select prescaler */ 131 out_be16(&psc->mpc52xx_psc_clock_select, prescaler); 132 out_8(&psc->ctur, divisor >> 8); 133 out_8(&psc->ctlr, divisor & 0xff); 134 } 135 136 static u16 mpc52xx_psc_get_status(struct uart_port *port) 137 { 138 return in_be16(&PSC(port)->mpc52xx_psc_status); 139 } 140 141 static u8 mpc52xx_psc_get_ipcr(struct uart_port *port) 142 { 143 return in_8(&PSC(port)->mpc52xx_psc_ipcr); 144 } 145 146 static void mpc52xx_psc_command(struct uart_port *port, u8 cmd) 147 { 148 out_8(&PSC(port)->command, cmd); 149 } 150 151 static void mpc52xx_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2) 152 { 153 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1); 154 out_8(&PSC(port)->mode, mr1); 155 out_8(&PSC(port)->mode, mr2); 156 } 157 158 static void mpc52xx_psc_set_rts(struct uart_port *port, int state) 159 { 160 if (state) 161 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS); 162 else 163 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS); 164 } 165 166 static void mpc52xx_psc_enable_ms(struct uart_port *port) 167 { 168 struct mpc52xx_psc __iomem *psc = PSC(port); 169 170 /* clear D_*-bits by reading them */ 171 in_8(&psc->mpc52xx_psc_ipcr); 172 /* enable CTS and DCD as IPC interrupts */ 173 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD); 174 175 port->read_status_mask |= MPC52xx_PSC_IMR_IPC; 176 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); 177 } 178 179 static void mpc52xx_psc_set_sicr(struct uart_port *port, u32 val) 180 { 181 out_be32(&PSC(port)->sicr, val); 182 } 183 184 static void mpc52xx_psc_set_imr(struct uart_port *port, u16 val) 185 { 186 out_be16(&PSC(port)->mpc52xx_psc_imr, val); 187 } 188 189 static u8 mpc52xx_psc_get_mr1(struct uart_port *port) 190 { 191 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1); 192 return in_8(&PSC(port)->mode); 193 } 194 195 #ifdef CONFIG_PPC_MPC52xx 196 #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1)) 197 static void mpc52xx_psc_fifo_init(struct uart_port *port) 198 { 199 struct mpc52xx_psc __iomem *psc = PSC(port); 200 struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port); 201 202 out_8(&fifo->rfcntl, 0x00); 203 out_be16(&fifo->rfalarm, 0x1ff); 204 out_8(&fifo->tfcntl, 0x07); 205 out_be16(&fifo->tfalarm, 0x80); 206 207 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY; 208 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); 209 } 210 211 static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port) 212 { 213 return in_be16(&PSC(port)->mpc52xx_psc_status) 214 & MPC52xx_PSC_SR_RXRDY; 215 } 216 217 static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port) 218 { 219 return in_be16(&PSC(port)->mpc52xx_psc_status) 220 & MPC52xx_PSC_SR_TXRDY; 221 } 222 223 224 static int mpc52xx_psc_rx_rdy(struct uart_port *port) 225 { 226 return in_be16(&PSC(port)->mpc52xx_psc_isr) 227 & port->read_status_mask 228 & MPC52xx_PSC_IMR_RXRDY; 229 } 230 231 static int mpc52xx_psc_tx_rdy(struct uart_port *port) 232 { 233 return in_be16(&PSC(port)->mpc52xx_psc_isr) 234 & port->read_status_mask 235 & MPC52xx_PSC_IMR_TXRDY; 236 } 237 238 static int mpc52xx_psc_tx_empty(struct uart_port *port) 239 { 240 return in_be16(&PSC(port)->mpc52xx_psc_status) 241 & MPC52xx_PSC_SR_TXEMP; 242 } 243 244 static void mpc52xx_psc_start_tx(struct uart_port *port) 245 { 246 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY; 247 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); 248 } 249 250 static void mpc52xx_psc_stop_tx(struct uart_port *port) 251 { 252 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY; 253 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); 254 } 255 256 static void mpc52xx_psc_stop_rx(struct uart_port *port) 257 { 258 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY; 259 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); 260 } 261 262 static void mpc52xx_psc_rx_clr_irq(struct uart_port *port) 263 { 264 } 265 266 static void mpc52xx_psc_tx_clr_irq(struct uart_port *port) 267 { 268 } 269 270 static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c) 271 { 272 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c); 273 } 274 275 static unsigned char mpc52xx_psc_read_char(struct uart_port *port) 276 { 277 return in_8(&PSC(port)->mpc52xx_psc_buffer_8); 278 } 279 280 static void mpc52xx_psc_cw_disable_ints(struct uart_port *port) 281 { 282 out_be16(&PSC(port)->mpc52xx_psc_imr, 0); 283 } 284 285 static void mpc52xx_psc_cw_restore_ints(struct uart_port *port) 286 { 287 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); 288 } 289 290 static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port, 291 struct ktermios *new, 292 struct ktermios *old) 293 { 294 unsigned int baud; 295 unsigned int divisor; 296 297 /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */ 298 baud = uart_get_baud_rate(port, new, old, 299 port->uartclk / (32 * 0xffff) + 1, 300 port->uartclk / 32); 301 divisor = (port->uartclk + 16 * baud) / (32 * baud); 302 303 /* enable the /32 prescaler and set the divisor */ 304 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor); 305 return baud; 306 } 307 308 static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port, 309 struct ktermios *new, 310 struct ktermios *old) 311 { 312 unsigned int baud; 313 unsigned int divisor; 314 u16 prescaler; 315 316 /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the 317 * ipb freq */ 318 baud = uart_get_baud_rate(port, new, old, 319 port->uartclk / (32 * 0xffff) + 1, 320 port->uartclk / 4); 321 divisor = (port->uartclk + 2 * baud) / (4 * baud); 322 323 /* select the proper prescaler and set the divisor 324 * prefer high prescaler for more tolerance on low baudrates */ 325 if (divisor > 0xffff || baud <= 115200) { 326 divisor = (divisor + 4) / 8; 327 prescaler = 0xdd00; /* /32 */ 328 } else 329 prescaler = 0xff00; /* /4 */ 330 mpc52xx_set_divisor(PSC(port), prescaler, divisor); 331 return baud; 332 } 333 334 static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np) 335 { 336 port->irqflags = 0; 337 port->irq = irq_of_parse_and_map(np, 0); 338 } 339 340 /* 52xx specific interrupt handler. The caller holds the port lock */ 341 static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port) 342 { 343 return mpc5xxx_uart_process_int(port); 344 } 345 346 static struct psc_ops mpc52xx_psc_ops = { 347 .fifo_init = mpc52xx_psc_fifo_init, 348 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy, 349 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy, 350 .rx_rdy = mpc52xx_psc_rx_rdy, 351 .tx_rdy = mpc52xx_psc_tx_rdy, 352 .tx_empty = mpc52xx_psc_tx_empty, 353 .stop_rx = mpc52xx_psc_stop_rx, 354 .start_tx = mpc52xx_psc_start_tx, 355 .stop_tx = mpc52xx_psc_stop_tx, 356 .rx_clr_irq = mpc52xx_psc_rx_clr_irq, 357 .tx_clr_irq = mpc52xx_psc_tx_clr_irq, 358 .write_char = mpc52xx_psc_write_char, 359 .read_char = mpc52xx_psc_read_char, 360 .cw_disable_ints = mpc52xx_psc_cw_disable_ints, 361 .cw_restore_ints = mpc52xx_psc_cw_restore_ints, 362 .set_baudrate = mpc5200_psc_set_baudrate, 363 .get_irq = mpc52xx_psc_get_irq, 364 .handle_irq = mpc52xx_psc_handle_irq, 365 .get_status = mpc52xx_psc_get_status, 366 .get_ipcr = mpc52xx_psc_get_ipcr, 367 .command = mpc52xx_psc_command, 368 .set_mode = mpc52xx_psc_set_mode, 369 .set_rts = mpc52xx_psc_set_rts, 370 .enable_ms = mpc52xx_psc_enable_ms, 371 .set_sicr = mpc52xx_psc_set_sicr, 372 .set_imr = mpc52xx_psc_set_imr, 373 .get_mr1 = mpc52xx_psc_get_mr1, 374 }; 375 376 static struct psc_ops mpc5200b_psc_ops = { 377 .fifo_init = mpc52xx_psc_fifo_init, 378 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy, 379 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy, 380 .rx_rdy = mpc52xx_psc_rx_rdy, 381 .tx_rdy = mpc52xx_psc_tx_rdy, 382 .tx_empty = mpc52xx_psc_tx_empty, 383 .stop_rx = mpc52xx_psc_stop_rx, 384 .start_tx = mpc52xx_psc_start_tx, 385 .stop_tx = mpc52xx_psc_stop_tx, 386 .rx_clr_irq = mpc52xx_psc_rx_clr_irq, 387 .tx_clr_irq = mpc52xx_psc_tx_clr_irq, 388 .write_char = mpc52xx_psc_write_char, 389 .read_char = mpc52xx_psc_read_char, 390 .cw_disable_ints = mpc52xx_psc_cw_disable_ints, 391 .cw_restore_ints = mpc52xx_psc_cw_restore_ints, 392 .set_baudrate = mpc5200b_psc_set_baudrate, 393 .get_irq = mpc52xx_psc_get_irq, 394 .handle_irq = mpc52xx_psc_handle_irq, 395 .get_status = mpc52xx_psc_get_status, 396 .get_ipcr = mpc52xx_psc_get_ipcr, 397 .command = mpc52xx_psc_command, 398 .set_mode = mpc52xx_psc_set_mode, 399 .set_rts = mpc52xx_psc_set_rts, 400 .enable_ms = mpc52xx_psc_enable_ms, 401 .set_sicr = mpc52xx_psc_set_sicr, 402 .set_imr = mpc52xx_psc_set_imr, 403 .get_mr1 = mpc52xx_psc_get_mr1, 404 }; 405 406 #endif /* CONFIG_MPC52xx */ 407 408 #ifdef CONFIG_PPC_MPC512x 409 #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1)) 410 411 /* PSC FIFO Controller for mpc512x */ 412 struct psc_fifoc { 413 u32 fifoc_cmd; 414 u32 fifoc_int; 415 u32 fifoc_dma; 416 u32 fifoc_axe; 417 u32 fifoc_debug; 418 }; 419 420 static struct psc_fifoc __iomem *psc_fifoc; 421 static unsigned int psc_fifoc_irq; 422 423 static void mpc512x_psc_fifo_init(struct uart_port *port) 424 { 425 /* /32 prescaler */ 426 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00); 427 428 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE); 429 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); 430 out_be32(&FIFO_512x(port)->txalarm, 1); 431 out_be32(&FIFO_512x(port)->tximr, 0); 432 433 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE); 434 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); 435 out_be32(&FIFO_512x(port)->rxalarm, 1); 436 out_be32(&FIFO_512x(port)->rximr, 0); 437 438 out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM); 439 out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM); 440 } 441 442 static int mpc512x_psc_raw_rx_rdy(struct uart_port *port) 443 { 444 return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY); 445 } 446 447 static int mpc512x_psc_raw_tx_rdy(struct uart_port *port) 448 { 449 return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL); 450 } 451 452 static int mpc512x_psc_rx_rdy(struct uart_port *port) 453 { 454 return in_be32(&FIFO_512x(port)->rxsr) 455 & in_be32(&FIFO_512x(port)->rximr) 456 & MPC512x_PSC_FIFO_ALARM; 457 } 458 459 static int mpc512x_psc_tx_rdy(struct uart_port *port) 460 { 461 return in_be32(&FIFO_512x(port)->txsr) 462 & in_be32(&FIFO_512x(port)->tximr) 463 & MPC512x_PSC_FIFO_ALARM; 464 } 465 466 static int mpc512x_psc_tx_empty(struct uart_port *port) 467 { 468 return in_be32(&FIFO_512x(port)->txsr) 469 & MPC512x_PSC_FIFO_EMPTY; 470 } 471 472 static void mpc512x_psc_stop_rx(struct uart_port *port) 473 { 474 unsigned long rx_fifo_imr; 475 476 rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr); 477 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; 478 out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr); 479 } 480 481 static void mpc512x_psc_start_tx(struct uart_port *port) 482 { 483 unsigned long tx_fifo_imr; 484 485 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); 486 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM; 487 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); 488 } 489 490 static void mpc512x_psc_stop_tx(struct uart_port *port) 491 { 492 unsigned long tx_fifo_imr; 493 494 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); 495 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; 496 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); 497 } 498 499 static void mpc512x_psc_rx_clr_irq(struct uart_port *port) 500 { 501 out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr)); 502 } 503 504 static void mpc512x_psc_tx_clr_irq(struct uart_port *port) 505 { 506 out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr)); 507 } 508 509 static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c) 510 { 511 out_8(&FIFO_512x(port)->txdata_8, c); 512 } 513 514 static unsigned char mpc512x_psc_read_char(struct uart_port *port) 515 { 516 return in_8(&FIFO_512x(port)->rxdata_8); 517 } 518 519 static void mpc512x_psc_cw_disable_ints(struct uart_port *port) 520 { 521 port->read_status_mask = 522 in_be32(&FIFO_512x(port)->tximr) << 16 | 523 in_be32(&FIFO_512x(port)->rximr); 524 out_be32(&FIFO_512x(port)->tximr, 0); 525 out_be32(&FIFO_512x(port)->rximr, 0); 526 } 527 528 static void mpc512x_psc_cw_restore_ints(struct uart_port *port) 529 { 530 out_be32(&FIFO_512x(port)->tximr, 531 (port->read_status_mask >> 16) & 0x7f); 532 out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f); 533 } 534 535 static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port, 536 struct ktermios *new, 537 struct ktermios *old) 538 { 539 unsigned int baud; 540 unsigned int divisor; 541 542 /* 543 * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on 544 * pg. 30-10 that the chip supports a /32 and a /10 prescaler. 545 * Furthermore, it states that "After reset, the prescaler by 10 546 * for the UART mode is selected", but the reset register value is 547 * 0x0000 which means a /32 prescaler. This is wrong. 548 * 549 * In reality using /32 prescaler doesn't work, as it is not supported! 550 * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide", 551 * Chapter 4.1 PSC in UART Mode. 552 * Calculate with a /16 prescaler here. 553 */ 554 555 /* uartclk contains the ips freq */ 556 baud = uart_get_baud_rate(port, new, old, 557 port->uartclk / (16 * 0xffff) + 1, 558 port->uartclk / 16); 559 divisor = (port->uartclk + 8 * baud) / (16 * baud); 560 561 /* enable the /16 prescaler and set the divisor */ 562 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor); 563 return baud; 564 } 565 566 /* Init PSC FIFO Controller */ 567 static int __init mpc512x_psc_fifoc_init(void) 568 { 569 struct device_node *np; 570 571 np = of_find_compatible_node(NULL, NULL, 572 "fsl,mpc5121-psc-fifo"); 573 if (!np) { 574 pr_err("%s: Can't find FIFOC node\n", __func__); 575 return -ENODEV; 576 } 577 578 psc_fifoc = of_iomap(np, 0); 579 if (!psc_fifoc) { 580 pr_err("%s: Can't map FIFOC\n", __func__); 581 of_node_put(np); 582 return -ENODEV; 583 } 584 585 psc_fifoc_irq = irq_of_parse_and_map(np, 0); 586 of_node_put(np); 587 if (psc_fifoc_irq == 0) { 588 pr_err("%s: Can't get FIFOC irq\n", __func__); 589 iounmap(psc_fifoc); 590 return -ENODEV; 591 } 592 593 return 0; 594 } 595 596 static void __exit mpc512x_psc_fifoc_uninit(void) 597 { 598 iounmap(psc_fifoc); 599 } 600 601 /* 512x specific interrupt handler. The caller holds the port lock */ 602 static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port) 603 { 604 unsigned long fifoc_int; 605 int psc_num; 606 607 /* Read pending PSC FIFOC interrupts */ 608 fifoc_int = in_be32(&psc_fifoc->fifoc_int); 609 610 /* Check if it is an interrupt for this port */ 611 psc_num = (port->mapbase & 0xf00) >> 8; 612 if (test_bit(psc_num, &fifoc_int) || 613 test_bit(psc_num + 16, &fifoc_int)) 614 return mpc5xxx_uart_process_int(port); 615 616 return IRQ_NONE; 617 } 618 619 static int mpc512x_psc_clock(struct uart_port *port, int enable) 620 { 621 struct clk *psc_clk; 622 int psc_num; 623 char clk_name[10]; 624 625 if (uart_console(port)) 626 return 0; 627 628 psc_num = (port->mapbase & 0xf00) >> 8; 629 snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num); 630 psc_clk = clk_get(port->dev, clk_name); 631 if (IS_ERR(psc_clk)) { 632 dev_err(port->dev, "Failed to get PSC clock entry!\n"); 633 return -ENODEV; 634 } 635 636 dev_dbg(port->dev, "%s %sable\n", clk_name, enable ? "en" : "dis"); 637 638 if (enable) 639 clk_enable(psc_clk); 640 else 641 clk_disable(psc_clk); 642 643 return 0; 644 } 645 646 static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np) 647 { 648 port->irqflags = IRQF_SHARED; 649 port->irq = psc_fifoc_irq; 650 } 651 #endif 652 653 #ifdef CONFIG_PPC_MPC512x 654 655 #define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase)) 656 #define FIFO_5125(port) ((struct mpc512x_psc_fifo __iomem *)(PSC_5125(port)+1)) 657 658 static void mpc5125_psc_fifo_init(struct uart_port *port) 659 { 660 /* /32 prescaler */ 661 out_8(&PSC_5125(port)->mpc52xx_psc_clock_select, 0xdd); 662 663 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE); 664 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); 665 out_be32(&FIFO_5125(port)->txalarm, 1); 666 out_be32(&FIFO_5125(port)->tximr, 0); 667 668 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE); 669 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); 670 out_be32(&FIFO_5125(port)->rxalarm, 1); 671 out_be32(&FIFO_5125(port)->rximr, 0); 672 673 out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM); 674 out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM); 675 } 676 677 static int mpc5125_psc_raw_rx_rdy(struct uart_port *port) 678 { 679 return !(in_be32(&FIFO_5125(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY); 680 } 681 682 static int mpc5125_psc_raw_tx_rdy(struct uart_port *port) 683 { 684 return !(in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_FULL); 685 } 686 687 static int mpc5125_psc_rx_rdy(struct uart_port *port) 688 { 689 return in_be32(&FIFO_5125(port)->rxsr) & 690 in_be32(&FIFO_5125(port)->rximr) & MPC512x_PSC_FIFO_ALARM; 691 } 692 693 static int mpc5125_psc_tx_rdy(struct uart_port *port) 694 { 695 return in_be32(&FIFO_5125(port)->txsr) & 696 in_be32(&FIFO_5125(port)->tximr) & MPC512x_PSC_FIFO_ALARM; 697 } 698 699 static int mpc5125_psc_tx_empty(struct uart_port *port) 700 { 701 return in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_EMPTY; 702 } 703 704 static void mpc5125_psc_stop_rx(struct uart_port *port) 705 { 706 unsigned long rx_fifo_imr; 707 708 rx_fifo_imr = in_be32(&FIFO_5125(port)->rximr); 709 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; 710 out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr); 711 } 712 713 static void mpc5125_psc_start_tx(struct uart_port *port) 714 { 715 unsigned long tx_fifo_imr; 716 717 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr); 718 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM; 719 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr); 720 } 721 722 static void mpc5125_psc_stop_tx(struct uart_port *port) 723 { 724 unsigned long tx_fifo_imr; 725 726 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr); 727 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; 728 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr); 729 } 730 731 static void mpc5125_psc_rx_clr_irq(struct uart_port *port) 732 { 733 out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr)); 734 } 735 736 static void mpc5125_psc_tx_clr_irq(struct uart_port *port) 737 { 738 out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr)); 739 } 740 741 static void mpc5125_psc_write_char(struct uart_port *port, unsigned char c) 742 { 743 out_8(&FIFO_5125(port)->txdata_8, c); 744 } 745 746 static unsigned char mpc5125_psc_read_char(struct uart_port *port) 747 { 748 return in_8(&FIFO_5125(port)->rxdata_8); 749 } 750 751 static void mpc5125_psc_cw_disable_ints(struct uart_port *port) 752 { 753 port->read_status_mask = 754 in_be32(&FIFO_5125(port)->tximr) << 16 | 755 in_be32(&FIFO_5125(port)->rximr); 756 out_be32(&FIFO_5125(port)->tximr, 0); 757 out_be32(&FIFO_5125(port)->rximr, 0); 758 } 759 760 static void mpc5125_psc_cw_restore_ints(struct uart_port *port) 761 { 762 out_be32(&FIFO_5125(port)->tximr, 763 (port->read_status_mask >> 16) & 0x7f); 764 out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f); 765 } 766 767 static inline void mpc5125_set_divisor(struct mpc5125_psc __iomem *psc, 768 u8 prescaler, unsigned int divisor) 769 { 770 /* select prescaler */ 771 out_8(&psc->mpc52xx_psc_clock_select, prescaler); 772 out_8(&psc->ctur, divisor >> 8); 773 out_8(&psc->ctlr, divisor & 0xff); 774 } 775 776 static unsigned int mpc5125_psc_set_baudrate(struct uart_port *port, 777 struct ktermios *new, 778 struct ktermios *old) 779 { 780 unsigned int baud; 781 unsigned int divisor; 782 783 /* 784 * Calculate with a /16 prescaler here. 785 */ 786 787 /* uartclk contains the ips freq */ 788 baud = uart_get_baud_rate(port, new, old, 789 port->uartclk / (16 * 0xffff) + 1, 790 port->uartclk / 16); 791 divisor = (port->uartclk + 8 * baud) / (16 * baud); 792 793 /* enable the /16 prescaler and set the divisor */ 794 mpc5125_set_divisor(PSC_5125(port), 0xdd, divisor); 795 return baud; 796 } 797 798 /* 799 * MPC5125 have compatible PSC FIFO Controller. 800 * Special init not needed. 801 */ 802 static u16 mpc5125_psc_get_status(struct uart_port *port) 803 { 804 return in_be16(&PSC_5125(port)->mpc52xx_psc_status); 805 } 806 807 static u8 mpc5125_psc_get_ipcr(struct uart_port *port) 808 { 809 return in_8(&PSC_5125(port)->mpc52xx_psc_ipcr); 810 } 811 812 static void mpc5125_psc_command(struct uart_port *port, u8 cmd) 813 { 814 out_8(&PSC_5125(port)->command, cmd); 815 } 816 817 static void mpc5125_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2) 818 { 819 out_8(&PSC_5125(port)->mr1, mr1); 820 out_8(&PSC_5125(port)->mr2, mr2); 821 } 822 823 static void mpc5125_psc_set_rts(struct uart_port *port, int state) 824 { 825 if (state & TIOCM_RTS) 826 out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS); 827 else 828 out_8(&PSC_5125(port)->op0, MPC52xx_PSC_OP_RTS); 829 } 830 831 static void mpc5125_psc_enable_ms(struct uart_port *port) 832 { 833 struct mpc5125_psc __iomem *psc = PSC_5125(port); 834 835 /* clear D_*-bits by reading them */ 836 in_8(&psc->mpc52xx_psc_ipcr); 837 /* enable CTS and DCD as IPC interrupts */ 838 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD); 839 840 port->read_status_mask |= MPC52xx_PSC_IMR_IPC; 841 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); 842 } 843 844 static void mpc5125_psc_set_sicr(struct uart_port *port, u32 val) 845 { 846 out_be32(&PSC_5125(port)->sicr, val); 847 } 848 849 static void mpc5125_psc_set_imr(struct uart_port *port, u16 val) 850 { 851 out_be16(&PSC_5125(port)->mpc52xx_psc_imr, val); 852 } 853 854 static u8 mpc5125_psc_get_mr1(struct uart_port *port) 855 { 856 return in_8(&PSC_5125(port)->mr1); 857 } 858 859 static struct psc_ops mpc5125_psc_ops = { 860 .fifo_init = mpc5125_psc_fifo_init, 861 .raw_rx_rdy = mpc5125_psc_raw_rx_rdy, 862 .raw_tx_rdy = mpc5125_psc_raw_tx_rdy, 863 .rx_rdy = mpc5125_psc_rx_rdy, 864 .tx_rdy = mpc5125_psc_tx_rdy, 865 .tx_empty = mpc5125_psc_tx_empty, 866 .stop_rx = mpc5125_psc_stop_rx, 867 .start_tx = mpc5125_psc_start_tx, 868 .stop_tx = mpc5125_psc_stop_tx, 869 .rx_clr_irq = mpc5125_psc_rx_clr_irq, 870 .tx_clr_irq = mpc5125_psc_tx_clr_irq, 871 .write_char = mpc5125_psc_write_char, 872 .read_char = mpc5125_psc_read_char, 873 .cw_disable_ints = mpc5125_psc_cw_disable_ints, 874 .cw_restore_ints = mpc5125_psc_cw_restore_ints, 875 .set_baudrate = mpc5125_psc_set_baudrate, 876 .clock = mpc512x_psc_clock, 877 .fifoc_init = mpc512x_psc_fifoc_init, 878 .fifoc_uninit = mpc512x_psc_fifoc_uninit, 879 .get_irq = mpc512x_psc_get_irq, 880 .handle_irq = mpc512x_psc_handle_irq, 881 .get_status = mpc5125_psc_get_status, 882 .get_ipcr = mpc5125_psc_get_ipcr, 883 .command = mpc5125_psc_command, 884 .set_mode = mpc5125_psc_set_mode, 885 .set_rts = mpc5125_psc_set_rts, 886 .enable_ms = mpc5125_psc_enable_ms, 887 .set_sicr = mpc5125_psc_set_sicr, 888 .set_imr = mpc5125_psc_set_imr, 889 .get_mr1 = mpc5125_psc_get_mr1, 890 }; 891 892 static struct psc_ops mpc512x_psc_ops = { 893 .fifo_init = mpc512x_psc_fifo_init, 894 .raw_rx_rdy = mpc512x_psc_raw_rx_rdy, 895 .raw_tx_rdy = mpc512x_psc_raw_tx_rdy, 896 .rx_rdy = mpc512x_psc_rx_rdy, 897 .tx_rdy = mpc512x_psc_tx_rdy, 898 .tx_empty = mpc512x_psc_tx_empty, 899 .stop_rx = mpc512x_psc_stop_rx, 900 .start_tx = mpc512x_psc_start_tx, 901 .stop_tx = mpc512x_psc_stop_tx, 902 .rx_clr_irq = mpc512x_psc_rx_clr_irq, 903 .tx_clr_irq = mpc512x_psc_tx_clr_irq, 904 .write_char = mpc512x_psc_write_char, 905 .read_char = mpc512x_psc_read_char, 906 .cw_disable_ints = mpc512x_psc_cw_disable_ints, 907 .cw_restore_ints = mpc512x_psc_cw_restore_ints, 908 .set_baudrate = mpc512x_psc_set_baudrate, 909 .clock = mpc512x_psc_clock, 910 .fifoc_init = mpc512x_psc_fifoc_init, 911 .fifoc_uninit = mpc512x_psc_fifoc_uninit, 912 .get_irq = mpc512x_psc_get_irq, 913 .handle_irq = mpc512x_psc_handle_irq, 914 .get_status = mpc52xx_psc_get_status, 915 .get_ipcr = mpc52xx_psc_get_ipcr, 916 .command = mpc52xx_psc_command, 917 .set_mode = mpc52xx_psc_set_mode, 918 .set_rts = mpc52xx_psc_set_rts, 919 .enable_ms = mpc52xx_psc_enable_ms, 920 .set_sicr = mpc52xx_psc_set_sicr, 921 .set_imr = mpc52xx_psc_set_imr, 922 .get_mr1 = mpc52xx_psc_get_mr1, 923 }; 924 #endif /* CONFIG_PPC_MPC512x */ 925 926 927 static const struct psc_ops *psc_ops; 928 929 /* ======================================================================== */ 930 /* UART operations */ 931 /* ======================================================================== */ 932 933 static unsigned int 934 mpc52xx_uart_tx_empty(struct uart_port *port) 935 { 936 return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0; 937 } 938 939 static void 940 mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 941 { 942 psc_ops->set_rts(port, mctrl & TIOCM_RTS); 943 } 944 945 static unsigned int 946 mpc52xx_uart_get_mctrl(struct uart_port *port) 947 { 948 unsigned int ret = TIOCM_DSR; 949 u8 status = psc_ops->get_ipcr(port); 950 951 if (!(status & MPC52xx_PSC_CTS)) 952 ret |= TIOCM_CTS; 953 if (!(status & MPC52xx_PSC_DCD)) 954 ret |= TIOCM_CAR; 955 956 return ret; 957 } 958 959 static void 960 mpc52xx_uart_stop_tx(struct uart_port *port) 961 { 962 /* port->lock taken by caller */ 963 psc_ops->stop_tx(port); 964 } 965 966 static void 967 mpc52xx_uart_start_tx(struct uart_port *port) 968 { 969 /* port->lock taken by caller */ 970 psc_ops->start_tx(port); 971 } 972 973 static void 974 mpc52xx_uart_send_xchar(struct uart_port *port, char ch) 975 { 976 unsigned long flags; 977 spin_lock_irqsave(&port->lock, flags); 978 979 port->x_char = ch; 980 if (ch) { 981 /* Make sure tx interrupts are on */ 982 /* Truly necessary ??? They should be anyway */ 983 psc_ops->start_tx(port); 984 } 985 986 spin_unlock_irqrestore(&port->lock, flags); 987 } 988 989 static void 990 mpc52xx_uart_stop_rx(struct uart_port *port) 991 { 992 /* port->lock taken by caller */ 993 psc_ops->stop_rx(port); 994 } 995 996 static void 997 mpc52xx_uart_enable_ms(struct uart_port *port) 998 { 999 psc_ops->enable_ms(port); 1000 } 1001 1002 static void 1003 mpc52xx_uart_break_ctl(struct uart_port *port, int ctl) 1004 { 1005 unsigned long flags; 1006 spin_lock_irqsave(&port->lock, flags); 1007 1008 if (ctl == -1) 1009 psc_ops->command(port, MPC52xx_PSC_START_BRK); 1010 else 1011 psc_ops->command(port, MPC52xx_PSC_STOP_BRK); 1012 1013 spin_unlock_irqrestore(&port->lock, flags); 1014 } 1015 1016 static int 1017 mpc52xx_uart_startup(struct uart_port *port) 1018 { 1019 int ret; 1020 1021 if (psc_ops->clock) { 1022 ret = psc_ops->clock(port, 1); 1023 if (ret) 1024 return ret; 1025 } 1026 1027 /* Request IRQ */ 1028 ret = request_irq(port->irq, mpc52xx_uart_int, 1029 port->irqflags, "mpc52xx_psc_uart", port); 1030 if (ret) 1031 return ret; 1032 1033 /* Reset/activate the port, clear and enable interrupts */ 1034 psc_ops->command(port, MPC52xx_PSC_RST_RX); 1035 psc_ops->command(port, MPC52xx_PSC_RST_TX); 1036 1037 psc_ops->set_sicr(port, 0); /* UART mode DCD ignored */ 1038 1039 psc_ops->fifo_init(port); 1040 1041 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE); 1042 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE); 1043 1044 return 0; 1045 } 1046 1047 static void 1048 mpc52xx_uart_shutdown(struct uart_port *port) 1049 { 1050 /* Shut down the port. Leave TX active if on a console port */ 1051 psc_ops->command(port, MPC52xx_PSC_RST_RX); 1052 if (!uart_console(port)) 1053 psc_ops->command(port, MPC52xx_PSC_RST_TX); 1054 1055 port->read_status_mask = 0; 1056 psc_ops->set_imr(port, port->read_status_mask); 1057 1058 if (psc_ops->clock) 1059 psc_ops->clock(port, 0); 1060 1061 /* Disable interrupt */ 1062 psc_ops->cw_disable_ints(port); 1063 1064 /* Release interrupt */ 1065 free_irq(port->irq, port); 1066 } 1067 1068 static void 1069 mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new, 1070 struct ktermios *old) 1071 { 1072 unsigned long flags; 1073 unsigned char mr1, mr2; 1074 unsigned int j; 1075 unsigned int baud; 1076 1077 /* Prepare what we're gonna write */ 1078 mr1 = 0; 1079 1080 switch (new->c_cflag & CSIZE) { 1081 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS; 1082 break; 1083 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS; 1084 break; 1085 case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS; 1086 break; 1087 case CS8: 1088 default: mr1 |= MPC52xx_PSC_MODE_8_BITS; 1089 } 1090 1091 if (new->c_cflag & PARENB) { 1092 if (new->c_cflag & CMSPAR) 1093 mr1 |= MPC52xx_PSC_MODE_PARFORCE; 1094 1095 /* With CMSPAR, PARODD also means high parity (same as termios) */ 1096 mr1 |= (new->c_cflag & PARODD) ? 1097 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN; 1098 } else { 1099 mr1 |= MPC52xx_PSC_MODE_PARNONE; 1100 } 1101 1102 mr2 = 0; 1103 1104 if (new->c_cflag & CSTOPB) 1105 mr2 |= MPC52xx_PSC_MODE_TWO_STOP; 1106 else 1107 mr2 |= ((new->c_cflag & CSIZE) == CS5) ? 1108 MPC52xx_PSC_MODE_ONE_STOP_5_BITS : 1109 MPC52xx_PSC_MODE_ONE_STOP; 1110 1111 if (new->c_cflag & CRTSCTS) { 1112 mr1 |= MPC52xx_PSC_MODE_RXRTS; 1113 mr2 |= MPC52xx_PSC_MODE_TXCTS; 1114 } 1115 1116 /* Get the lock */ 1117 spin_lock_irqsave(&port->lock, flags); 1118 1119 /* Do our best to flush TX & RX, so we don't lose anything */ 1120 /* But we don't wait indefinitely ! */ 1121 j = 5000000; /* Maximum wait */ 1122 /* FIXME Can't receive chars since set_termios might be called at early 1123 * boot for the console, all stuff is not yet ready to receive at that 1124 * time and that just makes the kernel oops */ 1125 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */ 1126 while (!mpc52xx_uart_tx_empty(port) && --j) 1127 udelay(1); 1128 1129 if (!j) 1130 printk(KERN_ERR "mpc52xx_uart.c: " 1131 "Unable to flush RX & TX fifos in-time in set_termios." 1132 "Some chars may have been lost.\n"); 1133 1134 /* Reset the TX & RX */ 1135 psc_ops->command(port, MPC52xx_PSC_RST_RX); 1136 psc_ops->command(port, MPC52xx_PSC_RST_TX); 1137 1138 /* Send new mode settings */ 1139 psc_ops->set_mode(port, mr1, mr2); 1140 baud = psc_ops->set_baudrate(port, new, old); 1141 1142 /* Update the per-port timeout */ 1143 uart_update_timeout(port, new->c_cflag, baud); 1144 1145 if (UART_ENABLE_MS(port, new->c_cflag)) 1146 mpc52xx_uart_enable_ms(port); 1147 1148 /* Reenable TX & RX */ 1149 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE); 1150 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE); 1151 1152 /* We're all set, release the lock */ 1153 spin_unlock_irqrestore(&port->lock, flags); 1154 } 1155 1156 static const char * 1157 mpc52xx_uart_type(struct uart_port *port) 1158 { 1159 /* 1160 * We keep using PORT_MPC52xx for historic reasons although it applies 1161 * for MPC512x, too, but print "MPC5xxx" to not irritate users 1162 */ 1163 return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL; 1164 } 1165 1166 static void 1167 mpc52xx_uart_release_port(struct uart_port *port) 1168 { 1169 /* remapped by us ? */ 1170 if (port->flags & UPF_IOREMAP) { 1171 iounmap(port->membase); 1172 port->membase = NULL; 1173 } 1174 1175 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc)); 1176 } 1177 1178 static int 1179 mpc52xx_uart_request_port(struct uart_port *port) 1180 { 1181 int err; 1182 1183 if (port->flags & UPF_IOREMAP) /* Need to remap ? */ 1184 port->membase = ioremap(port->mapbase, 1185 sizeof(struct mpc52xx_psc)); 1186 1187 if (!port->membase) 1188 return -EINVAL; 1189 1190 err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc), 1191 "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY; 1192 1193 if (err && (port->flags & UPF_IOREMAP)) { 1194 iounmap(port->membase); 1195 port->membase = NULL; 1196 } 1197 1198 return err; 1199 } 1200 1201 static void 1202 mpc52xx_uart_config_port(struct uart_port *port, int flags) 1203 { 1204 if ((flags & UART_CONFIG_TYPE) 1205 && (mpc52xx_uart_request_port(port) == 0)) 1206 port->type = PORT_MPC52xx; 1207 } 1208 1209 static int 1210 mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1211 { 1212 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx) 1213 return -EINVAL; 1214 1215 if ((ser->irq != port->irq) || 1216 (ser->io_type != UPIO_MEM) || 1217 (ser->baud_base != port->uartclk) || 1218 (ser->iomem_base != (void *)port->mapbase) || 1219 (ser->hub6 != 0)) 1220 return -EINVAL; 1221 1222 return 0; 1223 } 1224 1225 1226 static struct uart_ops mpc52xx_uart_ops = { 1227 .tx_empty = mpc52xx_uart_tx_empty, 1228 .set_mctrl = mpc52xx_uart_set_mctrl, 1229 .get_mctrl = mpc52xx_uart_get_mctrl, 1230 .stop_tx = mpc52xx_uart_stop_tx, 1231 .start_tx = mpc52xx_uart_start_tx, 1232 .send_xchar = mpc52xx_uart_send_xchar, 1233 .stop_rx = mpc52xx_uart_stop_rx, 1234 .enable_ms = mpc52xx_uart_enable_ms, 1235 .break_ctl = mpc52xx_uart_break_ctl, 1236 .startup = mpc52xx_uart_startup, 1237 .shutdown = mpc52xx_uart_shutdown, 1238 .set_termios = mpc52xx_uart_set_termios, 1239 /* .pm = mpc52xx_uart_pm, Not supported yet */ 1240 /* .set_wake = mpc52xx_uart_set_wake, Not supported yet */ 1241 .type = mpc52xx_uart_type, 1242 .release_port = mpc52xx_uart_release_port, 1243 .request_port = mpc52xx_uart_request_port, 1244 .config_port = mpc52xx_uart_config_port, 1245 .verify_port = mpc52xx_uart_verify_port 1246 }; 1247 1248 1249 /* ======================================================================== */ 1250 /* Interrupt handling */ 1251 /* ======================================================================== */ 1252 1253 static inline int 1254 mpc52xx_uart_int_rx_chars(struct uart_port *port) 1255 { 1256 struct tty_port *tport = &port->state->port; 1257 unsigned char ch, flag; 1258 unsigned short status; 1259 1260 /* While we can read, do so ! */ 1261 while (psc_ops->raw_rx_rdy(port)) { 1262 /* Get the char */ 1263 ch = psc_ops->read_char(port); 1264 1265 /* Handle sysreq char */ 1266 #ifdef SUPPORT_SYSRQ 1267 if (uart_handle_sysrq_char(port, ch)) { 1268 port->sysrq = 0; 1269 continue; 1270 } 1271 #endif 1272 1273 /* Store it */ 1274 1275 flag = TTY_NORMAL; 1276 port->icount.rx++; 1277 1278 status = psc_ops->get_status(port); 1279 1280 if (status & (MPC52xx_PSC_SR_PE | 1281 MPC52xx_PSC_SR_FE | 1282 MPC52xx_PSC_SR_RB)) { 1283 1284 if (status & MPC52xx_PSC_SR_RB) { 1285 flag = TTY_BREAK; 1286 uart_handle_break(port); 1287 port->icount.brk++; 1288 } else if (status & MPC52xx_PSC_SR_PE) { 1289 flag = TTY_PARITY; 1290 port->icount.parity++; 1291 } 1292 else if (status & MPC52xx_PSC_SR_FE) { 1293 flag = TTY_FRAME; 1294 port->icount.frame++; 1295 } 1296 1297 /* Clear error condition */ 1298 psc_ops->command(port, MPC52xx_PSC_RST_ERR_STAT); 1299 1300 } 1301 tty_insert_flip_char(tport, ch, flag); 1302 if (status & MPC52xx_PSC_SR_OE) { 1303 /* 1304 * Overrun is special, since it's 1305 * reported immediately, and doesn't 1306 * affect the current character 1307 */ 1308 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 1309 port->icount.overrun++; 1310 } 1311 } 1312 1313 spin_unlock(&port->lock); 1314 tty_flip_buffer_push(tport); 1315 spin_lock(&port->lock); 1316 1317 return psc_ops->raw_rx_rdy(port); 1318 } 1319 1320 static inline int 1321 mpc52xx_uart_int_tx_chars(struct uart_port *port) 1322 { 1323 struct circ_buf *xmit = &port->state->xmit; 1324 1325 /* Process out of band chars */ 1326 if (port->x_char) { 1327 psc_ops->write_char(port, port->x_char); 1328 port->icount.tx++; 1329 port->x_char = 0; 1330 return 1; 1331 } 1332 1333 /* Nothing to do ? */ 1334 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 1335 mpc52xx_uart_stop_tx(port); 1336 return 0; 1337 } 1338 1339 /* Send chars */ 1340 while (psc_ops->raw_tx_rdy(port)) { 1341 psc_ops->write_char(port, xmit->buf[xmit->tail]); 1342 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 1343 port->icount.tx++; 1344 if (uart_circ_empty(xmit)) 1345 break; 1346 } 1347 1348 /* Wake up */ 1349 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1350 uart_write_wakeup(port); 1351 1352 /* Maybe we're done after all */ 1353 if (uart_circ_empty(xmit)) { 1354 mpc52xx_uart_stop_tx(port); 1355 return 0; 1356 } 1357 1358 return 1; 1359 } 1360 1361 static irqreturn_t 1362 mpc5xxx_uart_process_int(struct uart_port *port) 1363 { 1364 unsigned long pass = ISR_PASS_LIMIT; 1365 unsigned int keepgoing; 1366 u8 status; 1367 1368 /* While we have stuff to do, we continue */ 1369 do { 1370 /* If we don't find anything to do, we stop */ 1371 keepgoing = 0; 1372 1373 psc_ops->rx_clr_irq(port); 1374 if (psc_ops->rx_rdy(port)) 1375 keepgoing |= mpc52xx_uart_int_rx_chars(port); 1376 1377 psc_ops->tx_clr_irq(port); 1378 if (psc_ops->tx_rdy(port)) 1379 keepgoing |= mpc52xx_uart_int_tx_chars(port); 1380 1381 status = psc_ops->get_ipcr(port); 1382 if (status & MPC52xx_PSC_D_DCD) 1383 uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD)); 1384 1385 if (status & MPC52xx_PSC_D_CTS) 1386 uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS)); 1387 1388 /* Limit number of iteration */ 1389 if (!(--pass)) 1390 keepgoing = 0; 1391 1392 } while (keepgoing); 1393 1394 return IRQ_HANDLED; 1395 } 1396 1397 static irqreturn_t 1398 mpc52xx_uart_int(int irq, void *dev_id) 1399 { 1400 struct uart_port *port = dev_id; 1401 irqreturn_t ret; 1402 1403 spin_lock(&port->lock); 1404 1405 ret = psc_ops->handle_irq(port); 1406 1407 spin_unlock(&port->lock); 1408 1409 return ret; 1410 } 1411 1412 /* ======================================================================== */ 1413 /* Console ( if applicable ) */ 1414 /* ======================================================================== */ 1415 1416 #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE 1417 1418 static void __init 1419 mpc52xx_console_get_options(struct uart_port *port, 1420 int *baud, int *parity, int *bits, int *flow) 1421 { 1422 unsigned char mr1; 1423 1424 pr_debug("mpc52xx_console_get_options(port=%p)\n", port); 1425 1426 /* Read the mode registers */ 1427 mr1 = psc_ops->get_mr1(port); 1428 1429 /* CT{U,L}R are write-only ! */ 1430 *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; 1431 1432 /* Parse them */ 1433 switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) { 1434 case MPC52xx_PSC_MODE_5_BITS: 1435 *bits = 5; 1436 break; 1437 case MPC52xx_PSC_MODE_6_BITS: 1438 *bits = 6; 1439 break; 1440 case MPC52xx_PSC_MODE_7_BITS: 1441 *bits = 7; 1442 break; 1443 case MPC52xx_PSC_MODE_8_BITS: 1444 default: 1445 *bits = 8; 1446 } 1447 1448 if (mr1 & MPC52xx_PSC_MODE_PARNONE) 1449 *parity = 'n'; 1450 else 1451 *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e'; 1452 } 1453 1454 static void 1455 mpc52xx_console_write(struct console *co, const char *s, unsigned int count) 1456 { 1457 struct uart_port *port = &mpc52xx_uart_ports[co->index]; 1458 unsigned int i, j; 1459 1460 /* Disable interrupts */ 1461 psc_ops->cw_disable_ints(port); 1462 1463 /* Wait the TX buffer to be empty */ 1464 j = 5000000; /* Maximum wait */ 1465 while (!mpc52xx_uart_tx_empty(port) && --j) 1466 udelay(1); 1467 1468 /* Write all the chars */ 1469 for (i = 0; i < count; i++, s++) { 1470 /* Line return handling */ 1471 if (*s == '\n') 1472 psc_ops->write_char(port, '\r'); 1473 1474 /* Send the char */ 1475 psc_ops->write_char(port, *s); 1476 1477 /* Wait the TX buffer to be empty */ 1478 j = 20000; /* Maximum wait */ 1479 while (!mpc52xx_uart_tx_empty(port) && --j) 1480 udelay(1); 1481 } 1482 1483 /* Restore interrupt state */ 1484 psc_ops->cw_restore_ints(port); 1485 } 1486 1487 1488 static int __init 1489 mpc52xx_console_setup(struct console *co, char *options) 1490 { 1491 struct uart_port *port = &mpc52xx_uart_ports[co->index]; 1492 struct device_node *np = mpc52xx_uart_nodes[co->index]; 1493 unsigned int uartclk; 1494 struct resource res; 1495 int ret; 1496 1497 int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; 1498 int bits = 8; 1499 int parity = 'n'; 1500 int flow = 'n'; 1501 1502 pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n", 1503 co, co->index, options); 1504 1505 if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) { 1506 pr_debug("PSC%x out of range\n", co->index); 1507 return -EINVAL; 1508 } 1509 1510 if (!np) { 1511 pr_debug("PSC%x not found in device tree\n", co->index); 1512 return -EINVAL; 1513 } 1514 1515 pr_debug("Console on ttyPSC%x is %s\n", 1516 co->index, mpc52xx_uart_nodes[co->index]->full_name); 1517 1518 /* Fetch register locations */ 1519 ret = of_address_to_resource(np, 0, &res); 1520 if (ret) { 1521 pr_debug("Could not get resources for PSC%x\n", co->index); 1522 return ret; 1523 } 1524 1525 uartclk = mpc5xxx_get_bus_frequency(np); 1526 if (uartclk == 0) { 1527 pr_debug("Could not find uart clock frequency!\n"); 1528 return -EINVAL; 1529 } 1530 1531 /* Basic port init. Needed since we use some uart_??? func before 1532 * real init for early access */ 1533 spin_lock_init(&port->lock); 1534 port->uartclk = uartclk; 1535 port->ops = &mpc52xx_uart_ops; 1536 port->mapbase = res.start; 1537 port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc)); 1538 port->irq = irq_of_parse_and_map(np, 0); 1539 1540 if (port->membase == NULL) 1541 return -EINVAL; 1542 1543 pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n", 1544 (void *)port->mapbase, port->membase, 1545 port->irq, port->uartclk); 1546 1547 /* Setup the port parameters accoding to options */ 1548 if (options) 1549 uart_parse_options(options, &baud, &parity, &bits, &flow); 1550 else 1551 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow); 1552 1553 pr_debug("Setting console parameters: %i %i%c1 flow=%c\n", 1554 baud, bits, parity, flow); 1555 1556 return uart_set_options(port, co, baud, parity, bits, flow); 1557 } 1558 1559 1560 static struct uart_driver mpc52xx_uart_driver; 1561 1562 static struct console mpc52xx_console = { 1563 .name = "ttyPSC", 1564 .write = mpc52xx_console_write, 1565 .device = uart_console_device, 1566 .setup = mpc52xx_console_setup, 1567 .flags = CON_PRINTBUFFER, 1568 .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */ 1569 .data = &mpc52xx_uart_driver, 1570 }; 1571 1572 1573 static int __init 1574 mpc52xx_console_init(void) 1575 { 1576 mpc52xx_uart_of_enumerate(); 1577 register_console(&mpc52xx_console); 1578 return 0; 1579 } 1580 1581 console_initcall(mpc52xx_console_init); 1582 1583 #define MPC52xx_PSC_CONSOLE &mpc52xx_console 1584 #else 1585 #define MPC52xx_PSC_CONSOLE NULL 1586 #endif 1587 1588 1589 /* ======================================================================== */ 1590 /* UART Driver */ 1591 /* ======================================================================== */ 1592 1593 static struct uart_driver mpc52xx_uart_driver = { 1594 .driver_name = "mpc52xx_psc_uart", 1595 .dev_name = "ttyPSC", 1596 .major = SERIAL_PSC_MAJOR, 1597 .minor = SERIAL_PSC_MINOR, 1598 .nr = MPC52xx_PSC_MAXNUM, 1599 .cons = MPC52xx_PSC_CONSOLE, 1600 }; 1601 1602 /* ======================================================================== */ 1603 /* OF Platform Driver */ 1604 /* ======================================================================== */ 1605 1606 static struct of_device_id mpc52xx_uart_of_match[] = { 1607 #ifdef CONFIG_PPC_MPC52xx 1608 { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, }, 1609 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, 1610 /* binding used by old lite5200 device trees: */ 1611 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, 1612 /* binding used by efika: */ 1613 { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, }, 1614 #endif 1615 #ifdef CONFIG_PPC_MPC512x 1616 { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, }, 1617 { .compatible = "fsl,mpc5125-psc-uart", .data = &mpc5125_psc_ops, }, 1618 #endif 1619 {}, 1620 }; 1621 1622 static int mpc52xx_uart_of_probe(struct platform_device *op) 1623 { 1624 int idx = -1; 1625 unsigned int uartclk; 1626 struct uart_port *port = NULL; 1627 struct resource res; 1628 int ret; 1629 1630 /* Check validity & presence */ 1631 for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++) 1632 if (mpc52xx_uart_nodes[idx] == op->dev.of_node) 1633 break; 1634 if (idx >= MPC52xx_PSC_MAXNUM) 1635 return -EINVAL; 1636 pr_debug("Found %s assigned to ttyPSC%x\n", 1637 mpc52xx_uart_nodes[idx]->full_name, idx); 1638 1639 /* set the uart clock to the input clock of the psc, the different 1640 * prescalers are taken into account in the set_baudrate() methods 1641 * of the respective chip */ 1642 uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node); 1643 if (uartclk == 0) { 1644 dev_dbg(&op->dev, "Could not find uart clock frequency!\n"); 1645 return -EINVAL; 1646 } 1647 1648 /* Init the port structure */ 1649 port = &mpc52xx_uart_ports[idx]; 1650 1651 spin_lock_init(&port->lock); 1652 port->uartclk = uartclk; 1653 port->fifosize = 512; 1654 port->iotype = UPIO_MEM; 1655 port->flags = UPF_BOOT_AUTOCONF | 1656 (uart_console(port) ? 0 : UPF_IOREMAP); 1657 port->line = idx; 1658 port->ops = &mpc52xx_uart_ops; 1659 port->dev = &op->dev; 1660 1661 /* Search for IRQ and mapbase */ 1662 ret = of_address_to_resource(op->dev.of_node, 0, &res); 1663 if (ret) 1664 return ret; 1665 1666 port->mapbase = res.start; 1667 if (!port->mapbase) { 1668 dev_dbg(&op->dev, "Could not allocate resources for PSC\n"); 1669 return -EINVAL; 1670 } 1671 1672 psc_ops->get_irq(port, op->dev.of_node); 1673 if (port->irq == 0) { 1674 dev_dbg(&op->dev, "Could not get irq\n"); 1675 return -EINVAL; 1676 } 1677 1678 dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n", 1679 (void *)port->mapbase, port->irq, port->uartclk); 1680 1681 /* Add the port to the uart sub-system */ 1682 ret = uart_add_one_port(&mpc52xx_uart_driver, port); 1683 if (ret) 1684 return ret; 1685 1686 platform_set_drvdata(op, (void *)port); 1687 return 0; 1688 } 1689 1690 static int 1691 mpc52xx_uart_of_remove(struct platform_device *op) 1692 { 1693 struct uart_port *port = platform_get_drvdata(op); 1694 1695 if (port) 1696 uart_remove_one_port(&mpc52xx_uart_driver, port); 1697 1698 return 0; 1699 } 1700 1701 #ifdef CONFIG_PM 1702 static int 1703 mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state) 1704 { 1705 struct uart_port *port = (struct uart_port *) platform_get_drvdata(op); 1706 1707 if (port) 1708 uart_suspend_port(&mpc52xx_uart_driver, port); 1709 1710 return 0; 1711 } 1712 1713 static int 1714 mpc52xx_uart_of_resume(struct platform_device *op) 1715 { 1716 struct uart_port *port = (struct uart_port *) platform_get_drvdata(op); 1717 1718 if (port) 1719 uart_resume_port(&mpc52xx_uart_driver, port); 1720 1721 return 0; 1722 } 1723 #endif 1724 1725 static void 1726 mpc52xx_uart_of_assign(struct device_node *np) 1727 { 1728 int i; 1729 1730 /* Find the first free PSC number */ 1731 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { 1732 if (mpc52xx_uart_nodes[i] == NULL) { 1733 of_node_get(np); 1734 mpc52xx_uart_nodes[i] = np; 1735 return; 1736 } 1737 } 1738 } 1739 1740 static void 1741 mpc52xx_uart_of_enumerate(void) 1742 { 1743 static int enum_done; 1744 struct device_node *np; 1745 const struct of_device_id *match; 1746 int i; 1747 1748 if (enum_done) 1749 return; 1750 1751 /* Assign index to each PSC in device tree */ 1752 for_each_matching_node(np, mpc52xx_uart_of_match) { 1753 match = of_match_node(mpc52xx_uart_of_match, np); 1754 psc_ops = match->data; 1755 mpc52xx_uart_of_assign(np); 1756 } 1757 1758 enum_done = 1; 1759 1760 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { 1761 if (mpc52xx_uart_nodes[i]) 1762 pr_debug("%s assigned to ttyPSC%x\n", 1763 mpc52xx_uart_nodes[i]->full_name, i); 1764 } 1765 } 1766 1767 MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match); 1768 1769 static struct platform_driver mpc52xx_uart_of_driver = { 1770 .probe = mpc52xx_uart_of_probe, 1771 .remove = mpc52xx_uart_of_remove, 1772 #ifdef CONFIG_PM 1773 .suspend = mpc52xx_uart_of_suspend, 1774 .resume = mpc52xx_uart_of_resume, 1775 #endif 1776 .driver = { 1777 .name = "mpc52xx-psc-uart", 1778 .owner = THIS_MODULE, 1779 .of_match_table = mpc52xx_uart_of_match, 1780 }, 1781 }; 1782 1783 1784 /* ======================================================================== */ 1785 /* Module */ 1786 /* ======================================================================== */ 1787 1788 static int __init 1789 mpc52xx_uart_init(void) 1790 { 1791 int ret; 1792 1793 printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n"); 1794 1795 ret = uart_register_driver(&mpc52xx_uart_driver); 1796 if (ret) { 1797 printk(KERN_ERR "%s: uart_register_driver failed (%i)\n", 1798 __FILE__, ret); 1799 return ret; 1800 } 1801 1802 mpc52xx_uart_of_enumerate(); 1803 1804 /* 1805 * Map the PSC FIFO Controller and init if on MPC512x. 1806 */ 1807 if (psc_ops && psc_ops->fifoc_init) { 1808 ret = psc_ops->fifoc_init(); 1809 if (ret) 1810 goto err_init; 1811 } 1812 1813 ret = platform_driver_register(&mpc52xx_uart_of_driver); 1814 if (ret) { 1815 printk(KERN_ERR "%s: platform_driver_register failed (%i)\n", 1816 __FILE__, ret); 1817 goto err_reg; 1818 } 1819 1820 return 0; 1821 err_reg: 1822 if (psc_ops && psc_ops->fifoc_uninit) 1823 psc_ops->fifoc_uninit(); 1824 err_init: 1825 uart_unregister_driver(&mpc52xx_uart_driver); 1826 return ret; 1827 } 1828 1829 static void __exit 1830 mpc52xx_uart_exit(void) 1831 { 1832 if (psc_ops->fifoc_uninit) 1833 psc_ops->fifoc_uninit(); 1834 1835 platform_driver_unregister(&mpc52xx_uart_of_driver); 1836 uart_unregister_driver(&mpc52xx_uart_driver); 1837 } 1838 1839 1840 module_init(mpc52xx_uart_init); 1841 module_exit(mpc52xx_uart_exit); 1842 1843 MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>"); 1844 MODULE_DESCRIPTION("Freescale MPC52xx PSC UART"); 1845 MODULE_LICENSE("GPL"); 1846