1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs. 4 * 5 * FIXME According to the usermanual the status bits in the status register 6 * are only updated when the peripherals access the FIFO and not when the 7 * CPU access them. So since we use this bits to know when we stop writing 8 * and reading, they may not be updated in-time and a race condition may 9 * exists. But I haven't be able to prove this and I don't care. But if 10 * any problem arises, it might worth checking. The TX/RX FIFO Stats 11 * registers should be used in addition. 12 * Update: Actually, they seem updated ... At least the bits we use. 13 * 14 * 15 * Maintainer : Sylvain Munaut <tnt@246tNt.com> 16 * 17 * Some of the code has been inspired/copied from the 2.4 code written 18 * by Dale Farnsworth <dfarnsworth@mvista.com>. 19 * 20 * Copyright (C) 2008 Freescale Semiconductor Inc. 21 * John Rigby <jrigby@gmail.com> 22 * Added support for MPC5121 23 * Copyright (C) 2006 Secret Lab Technologies Ltd. 24 * Grant Likely <grant.likely@secretlab.ca> 25 * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com> 26 * Copyright (C) 2003 MontaVista, Software, Inc. 27 */ 28 29 #undef DEBUG 30 31 #include <linux/device.h> 32 #include <linux/module.h> 33 #include <linux/tty.h> 34 #include <linux/tty_flip.h> 35 #include <linux/serial.h> 36 #include <linux/sysrq.h> 37 #include <linux/console.h> 38 #include <linux/delay.h> 39 #include <linux/io.h> 40 #include <linux/of.h> 41 #include <linux/of_address.h> 42 #include <linux/of_irq.h> 43 #include <linux/platform_device.h> 44 #include <linux/clk.h> 45 46 #include <asm/mpc52xx.h> 47 #include <asm/mpc52xx_psc.h> 48 49 #include <linux/serial_core.h> 50 51 52 /* We've been assigned a range on the "Low-density serial ports" major */ 53 #define SERIAL_PSC_MAJOR 204 54 #define SERIAL_PSC_MINOR 148 55 56 57 #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */ 58 59 60 static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM]; 61 /* Rem: - We use the read_status_mask as a shadow of 62 * psc->mpc52xx_psc_imr 63 * - It's important that is array is all zero on start as we 64 * use it to know if it's initialized or not ! If it's not sure 65 * it's cleared, then a memset(...,0,...) should be added to 66 * the console_init 67 */ 68 69 /* lookup table for matching device nodes to index numbers */ 70 static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM]; 71 72 static void mpc52xx_uart_of_enumerate(void); 73 74 75 #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase)) 76 77 78 /* Forward declaration of the interruption handling routine */ 79 static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id); 80 static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port); 81 82 /* ======================================================================== */ 83 /* PSC fifo operations for isolating differences between 52xx and 512x */ 84 /* ======================================================================== */ 85 86 struct psc_ops { 87 void (*fifo_init)(struct uart_port *port); 88 unsigned int (*raw_rx_rdy)(struct uart_port *port); 89 unsigned int (*raw_tx_rdy)(struct uart_port *port); 90 unsigned int (*rx_rdy)(struct uart_port *port); 91 unsigned int (*tx_rdy)(struct uart_port *port); 92 unsigned int (*tx_empty)(struct uart_port *port); 93 void (*stop_rx)(struct uart_port *port); 94 void (*start_tx)(struct uart_port *port); 95 void (*stop_tx)(struct uart_port *port); 96 void (*rx_clr_irq)(struct uart_port *port); 97 void (*tx_clr_irq)(struct uart_port *port); 98 void (*write_char)(struct uart_port *port, unsigned char c); 99 unsigned char (*read_char)(struct uart_port *port); 100 void (*cw_disable_ints)(struct uart_port *port); 101 void (*cw_restore_ints)(struct uart_port *port); 102 unsigned int (*set_baudrate)(struct uart_port *port, 103 struct ktermios *new, 104 const struct ktermios *old); 105 int (*clock_alloc)(struct uart_port *port); 106 void (*clock_relse)(struct uart_port *port); 107 int (*clock)(struct uart_port *port, int enable); 108 int (*fifoc_init)(void); 109 void (*fifoc_uninit)(void); 110 void (*get_irq)(struct uart_port *, struct device_node *); 111 irqreturn_t (*handle_irq)(struct uart_port *port); 112 u16 (*get_status)(struct uart_port *port); 113 u8 (*get_ipcr)(struct uart_port *port); 114 void (*command)(struct uart_port *port, u8 cmd); 115 void (*set_mode)(struct uart_port *port, u8 mr1, u8 mr2); 116 void (*set_rts)(struct uart_port *port, int state); 117 void (*enable_ms)(struct uart_port *port); 118 void (*set_sicr)(struct uart_port *port, u32 val); 119 void (*set_imr)(struct uart_port *port, u16 val); 120 u8 (*get_mr1)(struct uart_port *port); 121 }; 122 123 /* setting the prescaler and divisor reg is common for all chips */ 124 static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc, 125 u16 prescaler, unsigned int divisor) 126 { 127 /* select prescaler */ 128 out_be16(&psc->mpc52xx_psc_clock_select, prescaler); 129 out_8(&psc->ctur, divisor >> 8); 130 out_8(&psc->ctlr, divisor & 0xff); 131 } 132 133 static u16 mpc52xx_psc_get_status(struct uart_port *port) 134 { 135 return in_be16(&PSC(port)->mpc52xx_psc_status); 136 } 137 138 static u8 mpc52xx_psc_get_ipcr(struct uart_port *port) 139 { 140 return in_8(&PSC(port)->mpc52xx_psc_ipcr); 141 } 142 143 static void mpc52xx_psc_command(struct uart_port *port, u8 cmd) 144 { 145 out_8(&PSC(port)->command, cmd); 146 } 147 148 static void mpc52xx_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2) 149 { 150 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1); 151 out_8(&PSC(port)->mode, mr1); 152 out_8(&PSC(port)->mode, mr2); 153 } 154 155 static void mpc52xx_psc_set_rts(struct uart_port *port, int state) 156 { 157 if (state) 158 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS); 159 else 160 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS); 161 } 162 163 static void mpc52xx_psc_enable_ms(struct uart_port *port) 164 { 165 struct mpc52xx_psc __iomem *psc = PSC(port); 166 167 /* clear D_*-bits by reading them */ 168 in_8(&psc->mpc52xx_psc_ipcr); 169 /* enable CTS and DCD as IPC interrupts */ 170 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD); 171 172 port->read_status_mask |= MPC52xx_PSC_IMR_IPC; 173 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); 174 } 175 176 static void mpc52xx_psc_set_sicr(struct uart_port *port, u32 val) 177 { 178 out_be32(&PSC(port)->sicr, val); 179 } 180 181 static void mpc52xx_psc_set_imr(struct uart_port *port, u16 val) 182 { 183 out_be16(&PSC(port)->mpc52xx_psc_imr, val); 184 } 185 186 static u8 mpc52xx_psc_get_mr1(struct uart_port *port) 187 { 188 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1); 189 return in_8(&PSC(port)->mode); 190 } 191 192 #ifdef CONFIG_PPC_MPC52xx 193 #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1)) 194 static void mpc52xx_psc_fifo_init(struct uart_port *port) 195 { 196 struct mpc52xx_psc __iomem *psc = PSC(port); 197 struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port); 198 199 out_8(&fifo->rfcntl, 0x00); 200 out_be16(&fifo->rfalarm, 0x1ff); 201 out_8(&fifo->tfcntl, 0x07); 202 out_be16(&fifo->tfalarm, 0x80); 203 204 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY; 205 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); 206 } 207 208 static unsigned int mpc52xx_psc_raw_rx_rdy(struct uart_port *port) 209 { 210 return in_be16(&PSC(port)->mpc52xx_psc_status) 211 & MPC52xx_PSC_SR_RXRDY; 212 } 213 214 static unsigned int mpc52xx_psc_raw_tx_rdy(struct uart_port *port) 215 { 216 return in_be16(&PSC(port)->mpc52xx_psc_status) 217 & MPC52xx_PSC_SR_TXRDY; 218 } 219 220 221 static unsigned int mpc52xx_psc_rx_rdy(struct uart_port *port) 222 { 223 return in_be16(&PSC(port)->mpc52xx_psc_isr) 224 & port->read_status_mask 225 & MPC52xx_PSC_IMR_RXRDY; 226 } 227 228 static unsigned int mpc52xx_psc_tx_rdy(struct uart_port *port) 229 { 230 return in_be16(&PSC(port)->mpc52xx_psc_isr) 231 & port->read_status_mask 232 & MPC52xx_PSC_IMR_TXRDY; 233 } 234 235 static unsigned int mpc52xx_psc_tx_empty(struct uart_port *port) 236 { 237 u16 sts = in_be16(&PSC(port)->mpc52xx_psc_status); 238 239 return (sts & MPC52xx_PSC_SR_TXEMP) ? TIOCSER_TEMT : 0; 240 } 241 242 static void mpc52xx_psc_start_tx(struct uart_port *port) 243 { 244 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY; 245 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); 246 } 247 248 static void mpc52xx_psc_stop_tx(struct uart_port *port) 249 { 250 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY; 251 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); 252 } 253 254 static void mpc52xx_psc_stop_rx(struct uart_port *port) 255 { 256 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY; 257 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); 258 } 259 260 static void mpc52xx_psc_rx_clr_irq(struct uart_port *port) 261 { 262 } 263 264 static void mpc52xx_psc_tx_clr_irq(struct uart_port *port) 265 { 266 } 267 268 static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c) 269 { 270 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c); 271 } 272 273 static unsigned char mpc52xx_psc_read_char(struct uart_port *port) 274 { 275 return in_8(&PSC(port)->mpc52xx_psc_buffer_8); 276 } 277 278 static void mpc52xx_psc_cw_disable_ints(struct uart_port *port) 279 { 280 out_be16(&PSC(port)->mpc52xx_psc_imr, 0); 281 } 282 283 static void mpc52xx_psc_cw_restore_ints(struct uart_port *port) 284 { 285 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); 286 } 287 288 static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port, 289 struct ktermios *new, 290 const struct ktermios *old) 291 { 292 unsigned int baud; 293 unsigned int divisor; 294 295 /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */ 296 baud = uart_get_baud_rate(port, new, old, 297 port->uartclk / (32 * 0xffff) + 1, 298 port->uartclk / 32); 299 divisor = (port->uartclk + 16 * baud) / (32 * baud); 300 301 /* enable the /32 prescaler and set the divisor */ 302 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor); 303 return baud; 304 } 305 306 static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port, 307 struct ktermios *new, 308 const struct ktermios *old) 309 { 310 unsigned int baud; 311 unsigned int divisor; 312 u16 prescaler; 313 314 /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the 315 * ipb freq */ 316 baud = uart_get_baud_rate(port, new, old, 317 port->uartclk / (32 * 0xffff) + 1, 318 port->uartclk / 4); 319 divisor = (port->uartclk + 2 * baud) / (4 * baud); 320 321 /* select the proper prescaler and set the divisor 322 * prefer high prescaler for more tolerance on low baudrates */ 323 if (divisor > 0xffff || baud <= 115200) { 324 divisor = (divisor + 4) / 8; 325 prescaler = 0xdd00; /* /32 */ 326 } else 327 prescaler = 0xff00; /* /4 */ 328 mpc52xx_set_divisor(PSC(port), prescaler, divisor); 329 return baud; 330 } 331 332 static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np) 333 { 334 port->irqflags = 0; 335 port->irq = irq_of_parse_and_map(np, 0); 336 } 337 338 /* 52xx specific interrupt handler. The caller holds the port lock */ 339 static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port) 340 { 341 return mpc5xxx_uart_process_int(port); 342 } 343 344 static const struct psc_ops mpc52xx_psc_ops = { 345 .fifo_init = mpc52xx_psc_fifo_init, 346 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy, 347 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy, 348 .rx_rdy = mpc52xx_psc_rx_rdy, 349 .tx_rdy = mpc52xx_psc_tx_rdy, 350 .tx_empty = mpc52xx_psc_tx_empty, 351 .stop_rx = mpc52xx_psc_stop_rx, 352 .start_tx = mpc52xx_psc_start_tx, 353 .stop_tx = mpc52xx_psc_stop_tx, 354 .rx_clr_irq = mpc52xx_psc_rx_clr_irq, 355 .tx_clr_irq = mpc52xx_psc_tx_clr_irq, 356 .write_char = mpc52xx_psc_write_char, 357 .read_char = mpc52xx_psc_read_char, 358 .cw_disable_ints = mpc52xx_psc_cw_disable_ints, 359 .cw_restore_ints = mpc52xx_psc_cw_restore_ints, 360 .set_baudrate = mpc5200_psc_set_baudrate, 361 .get_irq = mpc52xx_psc_get_irq, 362 .handle_irq = mpc52xx_psc_handle_irq, 363 .get_status = mpc52xx_psc_get_status, 364 .get_ipcr = mpc52xx_psc_get_ipcr, 365 .command = mpc52xx_psc_command, 366 .set_mode = mpc52xx_psc_set_mode, 367 .set_rts = mpc52xx_psc_set_rts, 368 .enable_ms = mpc52xx_psc_enable_ms, 369 .set_sicr = mpc52xx_psc_set_sicr, 370 .set_imr = mpc52xx_psc_set_imr, 371 .get_mr1 = mpc52xx_psc_get_mr1, 372 }; 373 374 static const struct psc_ops mpc5200b_psc_ops = { 375 .fifo_init = mpc52xx_psc_fifo_init, 376 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy, 377 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy, 378 .rx_rdy = mpc52xx_psc_rx_rdy, 379 .tx_rdy = mpc52xx_psc_tx_rdy, 380 .tx_empty = mpc52xx_psc_tx_empty, 381 .stop_rx = mpc52xx_psc_stop_rx, 382 .start_tx = mpc52xx_psc_start_tx, 383 .stop_tx = mpc52xx_psc_stop_tx, 384 .rx_clr_irq = mpc52xx_psc_rx_clr_irq, 385 .tx_clr_irq = mpc52xx_psc_tx_clr_irq, 386 .write_char = mpc52xx_psc_write_char, 387 .read_char = mpc52xx_psc_read_char, 388 .cw_disable_ints = mpc52xx_psc_cw_disable_ints, 389 .cw_restore_ints = mpc52xx_psc_cw_restore_ints, 390 .set_baudrate = mpc5200b_psc_set_baudrate, 391 .get_irq = mpc52xx_psc_get_irq, 392 .handle_irq = mpc52xx_psc_handle_irq, 393 .get_status = mpc52xx_psc_get_status, 394 .get_ipcr = mpc52xx_psc_get_ipcr, 395 .command = mpc52xx_psc_command, 396 .set_mode = mpc52xx_psc_set_mode, 397 .set_rts = mpc52xx_psc_set_rts, 398 .enable_ms = mpc52xx_psc_enable_ms, 399 .set_sicr = mpc52xx_psc_set_sicr, 400 .set_imr = mpc52xx_psc_set_imr, 401 .get_mr1 = mpc52xx_psc_get_mr1, 402 }; 403 404 #endif /* CONFIG_PPC_MPC52xx */ 405 406 #ifdef CONFIG_PPC_MPC512x 407 #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1)) 408 409 /* PSC FIFO Controller for mpc512x */ 410 struct psc_fifoc { 411 u32 fifoc_cmd; 412 u32 fifoc_int; 413 u32 fifoc_dma; 414 u32 fifoc_axe; 415 u32 fifoc_debug; 416 }; 417 418 static struct psc_fifoc __iomem *psc_fifoc; 419 static unsigned int psc_fifoc_irq; 420 static struct clk *psc_fifoc_clk; 421 422 static void mpc512x_psc_fifo_init(struct uart_port *port) 423 { 424 /* /32 prescaler */ 425 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00); 426 427 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE); 428 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); 429 out_be32(&FIFO_512x(port)->txalarm, 1); 430 out_be32(&FIFO_512x(port)->tximr, 0); 431 432 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE); 433 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); 434 out_be32(&FIFO_512x(port)->rxalarm, 1); 435 out_be32(&FIFO_512x(port)->rximr, 0); 436 437 out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM); 438 out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM); 439 } 440 441 static unsigned int mpc512x_psc_raw_rx_rdy(struct uart_port *port) 442 { 443 return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY); 444 } 445 446 static unsigned int mpc512x_psc_raw_tx_rdy(struct uart_port *port) 447 { 448 return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL); 449 } 450 451 static unsigned int mpc512x_psc_rx_rdy(struct uart_port *port) 452 { 453 return in_be32(&FIFO_512x(port)->rxsr) 454 & in_be32(&FIFO_512x(port)->rximr) 455 & MPC512x_PSC_FIFO_ALARM; 456 } 457 458 static unsigned int mpc512x_psc_tx_rdy(struct uart_port *port) 459 { 460 return in_be32(&FIFO_512x(port)->txsr) 461 & in_be32(&FIFO_512x(port)->tximr) 462 & MPC512x_PSC_FIFO_ALARM; 463 } 464 465 static unsigned int mpc512x_psc_tx_empty(struct uart_port *port) 466 { 467 return in_be32(&FIFO_512x(port)->txsr) 468 & MPC512x_PSC_FIFO_EMPTY; 469 } 470 471 static void mpc512x_psc_stop_rx(struct uart_port *port) 472 { 473 unsigned long rx_fifo_imr; 474 475 rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr); 476 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; 477 out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr); 478 } 479 480 static void mpc512x_psc_start_tx(struct uart_port *port) 481 { 482 unsigned long tx_fifo_imr; 483 484 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); 485 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM; 486 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); 487 } 488 489 static void mpc512x_psc_stop_tx(struct uart_port *port) 490 { 491 unsigned long tx_fifo_imr; 492 493 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); 494 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; 495 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); 496 } 497 498 static void mpc512x_psc_rx_clr_irq(struct uart_port *port) 499 { 500 out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr)); 501 } 502 503 static void mpc512x_psc_tx_clr_irq(struct uart_port *port) 504 { 505 out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr)); 506 } 507 508 static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c) 509 { 510 out_8(&FIFO_512x(port)->txdata_8, c); 511 } 512 513 static unsigned char mpc512x_psc_read_char(struct uart_port *port) 514 { 515 return in_8(&FIFO_512x(port)->rxdata_8); 516 } 517 518 static void mpc512x_psc_cw_disable_ints(struct uart_port *port) 519 { 520 port->read_status_mask = 521 in_be32(&FIFO_512x(port)->tximr) << 16 | 522 in_be32(&FIFO_512x(port)->rximr); 523 out_be32(&FIFO_512x(port)->tximr, 0); 524 out_be32(&FIFO_512x(port)->rximr, 0); 525 } 526 527 static void mpc512x_psc_cw_restore_ints(struct uart_port *port) 528 { 529 out_be32(&FIFO_512x(port)->tximr, 530 (port->read_status_mask >> 16) & 0x7f); 531 out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f); 532 } 533 534 static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port, 535 struct ktermios *new, 536 const struct ktermios *old) 537 { 538 unsigned int baud; 539 unsigned int divisor; 540 541 /* 542 * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on 543 * pg. 30-10 that the chip supports a /32 and a /10 prescaler. 544 * Furthermore, it states that "After reset, the prescaler by 10 545 * for the UART mode is selected", but the reset register value is 546 * 0x0000 which means a /32 prescaler. This is wrong. 547 * 548 * In reality using /32 prescaler doesn't work, as it is not supported! 549 * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide", 550 * Chapter 4.1 PSC in UART Mode. 551 * Calculate with a /16 prescaler here. 552 */ 553 554 /* uartclk contains the ips freq */ 555 baud = uart_get_baud_rate(port, new, old, 556 port->uartclk / (16 * 0xffff) + 1, 557 port->uartclk / 16); 558 divisor = (port->uartclk + 8 * baud) / (16 * baud); 559 560 /* enable the /16 prescaler and set the divisor */ 561 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor); 562 return baud; 563 } 564 565 /* Init PSC FIFO Controller */ 566 static int __init mpc512x_psc_fifoc_init(void) 567 { 568 int err; 569 struct device_node *np; 570 struct clk *clk; 571 572 /* default error code, potentially overwritten by clock calls */ 573 err = -ENODEV; 574 575 np = of_find_compatible_node(NULL, NULL, 576 "fsl,mpc5121-psc-fifo"); 577 if (!np) { 578 pr_err("%s: Can't find FIFOC node\n", __func__); 579 goto out_err; 580 } 581 582 clk = of_clk_get(np, 0); 583 if (IS_ERR(clk)) { 584 /* backwards compat with device trees that lack clock specs */ 585 clk = clk_get_sys(np->name, "ipg"); 586 } 587 if (IS_ERR(clk)) { 588 pr_err("%s: Can't lookup FIFO clock\n", __func__); 589 err = PTR_ERR(clk); 590 goto out_ofnode_put; 591 } 592 if (clk_prepare_enable(clk)) { 593 pr_err("%s: Can't enable FIFO clock\n", __func__); 594 clk_put(clk); 595 goto out_ofnode_put; 596 } 597 psc_fifoc_clk = clk; 598 599 psc_fifoc = of_iomap(np, 0); 600 if (!psc_fifoc) { 601 pr_err("%s: Can't map FIFOC\n", __func__); 602 goto out_clk_disable; 603 } 604 605 psc_fifoc_irq = irq_of_parse_and_map(np, 0); 606 if (psc_fifoc_irq == 0) { 607 pr_err("%s: Can't get FIFOC irq\n", __func__); 608 goto out_unmap; 609 } 610 611 of_node_put(np); 612 return 0; 613 614 out_unmap: 615 iounmap(psc_fifoc); 616 out_clk_disable: 617 clk_disable_unprepare(psc_fifoc_clk); 618 clk_put(psc_fifoc_clk); 619 out_ofnode_put: 620 of_node_put(np); 621 out_err: 622 return err; 623 } 624 625 static void __exit mpc512x_psc_fifoc_uninit(void) 626 { 627 iounmap(psc_fifoc); 628 629 /* disable the clock, errors are not fatal */ 630 if (psc_fifoc_clk) { 631 clk_disable_unprepare(psc_fifoc_clk); 632 clk_put(psc_fifoc_clk); 633 psc_fifoc_clk = NULL; 634 } 635 } 636 637 /* 512x specific interrupt handler. The caller holds the port lock */ 638 static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port) 639 { 640 unsigned long fifoc_int; 641 int psc_num; 642 643 /* Read pending PSC FIFOC interrupts */ 644 fifoc_int = in_be32(&psc_fifoc->fifoc_int); 645 646 /* Check if it is an interrupt for this port */ 647 psc_num = (port->mapbase & 0xf00) >> 8; 648 if (psc_num >= ARRAY_SIZE(psc_mclk_clk)) 649 return IRQ_NONE; 650 if (test_bit(psc_num, &fifoc_int) || 651 test_bit(psc_num + 16, &fifoc_int)) 652 return mpc5xxx_uart_process_int(port); 653 654 return IRQ_NONE; 655 } 656 657 static struct clk *psc_mclk_clk[MPC52xx_PSC_MAXNUM]; 658 static struct clk *psc_ipg_clk[MPC52xx_PSC_MAXNUM]; 659 660 /* called from within the .request_port() callback (allocation) */ 661 static int mpc512x_psc_alloc_clock(struct uart_port *port) 662 { 663 int psc_num; 664 struct clk *clk; 665 int err; 666 667 psc_num = (port->mapbase & 0xf00) >> 8; 668 if (psc_num >= ARRAY_SIZE(psc_mclk_clk)) 669 return -EINVAL; 670 671 clk = devm_clk_get(port->dev, "mclk"); 672 if (IS_ERR(clk)) { 673 dev_err(port->dev, "Failed to get MCLK!\n"); 674 err = PTR_ERR(clk); 675 goto out_err; 676 } 677 err = clk_prepare_enable(clk); 678 if (err) { 679 dev_err(port->dev, "Failed to enable MCLK!\n"); 680 goto out_err; 681 } 682 psc_mclk_clk[psc_num] = clk; 683 684 clk = devm_clk_get(port->dev, "ipg"); 685 if (IS_ERR(clk)) { 686 dev_err(port->dev, "Failed to get IPG clock!\n"); 687 err = PTR_ERR(clk); 688 goto out_err; 689 } 690 err = clk_prepare_enable(clk); 691 if (err) { 692 dev_err(port->dev, "Failed to enable IPG clock!\n"); 693 goto out_err; 694 } 695 psc_ipg_clk[psc_num] = clk; 696 697 return 0; 698 699 out_err: 700 if (psc_mclk_clk[psc_num]) { 701 clk_disable_unprepare(psc_mclk_clk[psc_num]); 702 psc_mclk_clk[psc_num] = NULL; 703 } 704 if (psc_ipg_clk[psc_num]) { 705 clk_disable_unprepare(psc_ipg_clk[psc_num]); 706 psc_ipg_clk[psc_num] = NULL; 707 } 708 return err; 709 } 710 711 /* called from within the .release_port() callback (release) */ 712 static void mpc512x_psc_relse_clock(struct uart_port *port) 713 { 714 int psc_num; 715 struct clk *clk; 716 717 psc_num = (port->mapbase & 0xf00) >> 8; 718 if (psc_num >= ARRAY_SIZE(psc_mclk_clk)) 719 return; 720 clk = psc_mclk_clk[psc_num]; 721 if (clk) { 722 clk_disable_unprepare(clk); 723 psc_mclk_clk[psc_num] = NULL; 724 } 725 if (psc_ipg_clk[psc_num]) { 726 clk_disable_unprepare(psc_ipg_clk[psc_num]); 727 psc_ipg_clk[psc_num] = NULL; 728 } 729 } 730 731 /* implementation of the .clock() callback (enable/disable) */ 732 static int mpc512x_psc_endis_clock(struct uart_port *port, int enable) 733 { 734 int psc_num; 735 struct clk *psc_clk; 736 int ret; 737 738 if (uart_console(port)) 739 return 0; 740 741 psc_num = (port->mapbase & 0xf00) >> 8; 742 if (psc_num >= ARRAY_SIZE(psc_mclk_clk)) 743 return -ENODEV; 744 psc_clk = psc_mclk_clk[psc_num]; 745 if (!psc_clk) { 746 dev_err(port->dev, "Failed to get PSC clock entry!\n"); 747 return -ENODEV; 748 } 749 750 dev_dbg(port->dev, "mclk %sable\n", enable ? "en" : "dis"); 751 if (enable) { 752 ret = clk_enable(psc_clk); 753 if (ret) 754 dev_err(port->dev, "Failed to enable MCLK!\n"); 755 return ret; 756 } else { 757 clk_disable(psc_clk); 758 return 0; 759 } 760 } 761 762 static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np) 763 { 764 port->irqflags = IRQF_SHARED; 765 port->irq = psc_fifoc_irq; 766 } 767 768 #define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase)) 769 #define FIFO_5125(port) ((struct mpc512x_psc_fifo __iomem *)(PSC_5125(port)+1)) 770 771 static void mpc5125_psc_fifo_init(struct uart_port *port) 772 { 773 /* /32 prescaler */ 774 out_8(&PSC_5125(port)->mpc52xx_psc_clock_select, 0xdd); 775 776 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE); 777 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); 778 out_be32(&FIFO_5125(port)->txalarm, 1); 779 out_be32(&FIFO_5125(port)->tximr, 0); 780 781 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE); 782 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); 783 out_be32(&FIFO_5125(port)->rxalarm, 1); 784 out_be32(&FIFO_5125(port)->rximr, 0); 785 786 out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM); 787 out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM); 788 } 789 790 static unsigned int mpc5125_psc_raw_rx_rdy(struct uart_port *port) 791 { 792 return !(in_be32(&FIFO_5125(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY); 793 } 794 795 static unsigned int mpc5125_psc_raw_tx_rdy(struct uart_port *port) 796 { 797 return !(in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_FULL); 798 } 799 800 static unsigned int mpc5125_psc_rx_rdy(struct uart_port *port) 801 { 802 return in_be32(&FIFO_5125(port)->rxsr) & 803 in_be32(&FIFO_5125(port)->rximr) & MPC512x_PSC_FIFO_ALARM; 804 } 805 806 static unsigned int mpc5125_psc_tx_rdy(struct uart_port *port) 807 { 808 return in_be32(&FIFO_5125(port)->txsr) & 809 in_be32(&FIFO_5125(port)->tximr) & MPC512x_PSC_FIFO_ALARM; 810 } 811 812 static unsigned int mpc5125_psc_tx_empty(struct uart_port *port) 813 { 814 return in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_EMPTY; 815 } 816 817 static void mpc5125_psc_stop_rx(struct uart_port *port) 818 { 819 unsigned long rx_fifo_imr; 820 821 rx_fifo_imr = in_be32(&FIFO_5125(port)->rximr); 822 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; 823 out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr); 824 } 825 826 static void mpc5125_psc_start_tx(struct uart_port *port) 827 { 828 unsigned long tx_fifo_imr; 829 830 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr); 831 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM; 832 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr); 833 } 834 835 static void mpc5125_psc_stop_tx(struct uart_port *port) 836 { 837 unsigned long tx_fifo_imr; 838 839 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr); 840 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; 841 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr); 842 } 843 844 static void mpc5125_psc_rx_clr_irq(struct uart_port *port) 845 { 846 out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr)); 847 } 848 849 static void mpc5125_psc_tx_clr_irq(struct uart_port *port) 850 { 851 out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr)); 852 } 853 854 static void mpc5125_psc_write_char(struct uart_port *port, unsigned char c) 855 { 856 out_8(&FIFO_5125(port)->txdata_8, c); 857 } 858 859 static unsigned char mpc5125_psc_read_char(struct uart_port *port) 860 { 861 return in_8(&FIFO_5125(port)->rxdata_8); 862 } 863 864 static void mpc5125_psc_cw_disable_ints(struct uart_port *port) 865 { 866 port->read_status_mask = 867 in_be32(&FIFO_5125(port)->tximr) << 16 | 868 in_be32(&FIFO_5125(port)->rximr); 869 out_be32(&FIFO_5125(port)->tximr, 0); 870 out_be32(&FIFO_5125(port)->rximr, 0); 871 } 872 873 static void mpc5125_psc_cw_restore_ints(struct uart_port *port) 874 { 875 out_be32(&FIFO_5125(port)->tximr, 876 (port->read_status_mask >> 16) & 0x7f); 877 out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f); 878 } 879 880 static inline void mpc5125_set_divisor(struct mpc5125_psc __iomem *psc, 881 u8 prescaler, unsigned int divisor) 882 { 883 /* select prescaler */ 884 out_8(&psc->mpc52xx_psc_clock_select, prescaler); 885 out_8(&psc->ctur, divisor >> 8); 886 out_8(&psc->ctlr, divisor & 0xff); 887 } 888 889 static unsigned int mpc5125_psc_set_baudrate(struct uart_port *port, 890 struct ktermios *new, 891 const struct ktermios *old) 892 { 893 unsigned int baud; 894 unsigned int divisor; 895 896 /* 897 * Calculate with a /16 prescaler here. 898 */ 899 900 /* uartclk contains the ips freq */ 901 baud = uart_get_baud_rate(port, new, old, 902 port->uartclk / (16 * 0xffff) + 1, 903 port->uartclk / 16); 904 divisor = (port->uartclk + 8 * baud) / (16 * baud); 905 906 /* enable the /16 prescaler and set the divisor */ 907 mpc5125_set_divisor(PSC_5125(port), 0xdd, divisor); 908 return baud; 909 } 910 911 /* 912 * MPC5125 have compatible PSC FIFO Controller. 913 * Special init not needed. 914 */ 915 static u16 mpc5125_psc_get_status(struct uart_port *port) 916 { 917 return in_be16(&PSC_5125(port)->mpc52xx_psc_status); 918 } 919 920 static u8 mpc5125_psc_get_ipcr(struct uart_port *port) 921 { 922 return in_8(&PSC_5125(port)->mpc52xx_psc_ipcr); 923 } 924 925 static void mpc5125_psc_command(struct uart_port *port, u8 cmd) 926 { 927 out_8(&PSC_5125(port)->command, cmd); 928 } 929 930 static void mpc5125_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2) 931 { 932 out_8(&PSC_5125(port)->mr1, mr1); 933 out_8(&PSC_5125(port)->mr2, mr2); 934 } 935 936 static void mpc5125_psc_set_rts(struct uart_port *port, int state) 937 { 938 if (state & TIOCM_RTS) 939 out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS); 940 else 941 out_8(&PSC_5125(port)->op0, MPC52xx_PSC_OP_RTS); 942 } 943 944 static void mpc5125_psc_enable_ms(struct uart_port *port) 945 { 946 struct mpc5125_psc __iomem *psc = PSC_5125(port); 947 948 /* clear D_*-bits by reading them */ 949 in_8(&psc->mpc52xx_psc_ipcr); 950 /* enable CTS and DCD as IPC interrupts */ 951 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD); 952 953 port->read_status_mask |= MPC52xx_PSC_IMR_IPC; 954 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); 955 } 956 957 static void mpc5125_psc_set_sicr(struct uart_port *port, u32 val) 958 { 959 out_be32(&PSC_5125(port)->sicr, val); 960 } 961 962 static void mpc5125_psc_set_imr(struct uart_port *port, u16 val) 963 { 964 out_be16(&PSC_5125(port)->mpc52xx_psc_imr, val); 965 } 966 967 static u8 mpc5125_psc_get_mr1(struct uart_port *port) 968 { 969 return in_8(&PSC_5125(port)->mr1); 970 } 971 972 static const struct psc_ops mpc5125_psc_ops = { 973 .fifo_init = mpc5125_psc_fifo_init, 974 .raw_rx_rdy = mpc5125_psc_raw_rx_rdy, 975 .raw_tx_rdy = mpc5125_psc_raw_tx_rdy, 976 .rx_rdy = mpc5125_psc_rx_rdy, 977 .tx_rdy = mpc5125_psc_tx_rdy, 978 .tx_empty = mpc5125_psc_tx_empty, 979 .stop_rx = mpc5125_psc_stop_rx, 980 .start_tx = mpc5125_psc_start_tx, 981 .stop_tx = mpc5125_psc_stop_tx, 982 .rx_clr_irq = mpc5125_psc_rx_clr_irq, 983 .tx_clr_irq = mpc5125_psc_tx_clr_irq, 984 .write_char = mpc5125_psc_write_char, 985 .read_char = mpc5125_psc_read_char, 986 .cw_disable_ints = mpc5125_psc_cw_disable_ints, 987 .cw_restore_ints = mpc5125_psc_cw_restore_ints, 988 .set_baudrate = mpc5125_psc_set_baudrate, 989 .clock_alloc = mpc512x_psc_alloc_clock, 990 .clock_relse = mpc512x_psc_relse_clock, 991 .clock = mpc512x_psc_endis_clock, 992 .fifoc_init = mpc512x_psc_fifoc_init, 993 .fifoc_uninit = mpc512x_psc_fifoc_uninit, 994 .get_irq = mpc512x_psc_get_irq, 995 .handle_irq = mpc512x_psc_handle_irq, 996 .get_status = mpc5125_psc_get_status, 997 .get_ipcr = mpc5125_psc_get_ipcr, 998 .command = mpc5125_psc_command, 999 .set_mode = mpc5125_psc_set_mode, 1000 .set_rts = mpc5125_psc_set_rts, 1001 .enable_ms = mpc5125_psc_enable_ms, 1002 .set_sicr = mpc5125_psc_set_sicr, 1003 .set_imr = mpc5125_psc_set_imr, 1004 .get_mr1 = mpc5125_psc_get_mr1, 1005 }; 1006 1007 static const struct psc_ops mpc512x_psc_ops = { 1008 .fifo_init = mpc512x_psc_fifo_init, 1009 .raw_rx_rdy = mpc512x_psc_raw_rx_rdy, 1010 .raw_tx_rdy = mpc512x_psc_raw_tx_rdy, 1011 .rx_rdy = mpc512x_psc_rx_rdy, 1012 .tx_rdy = mpc512x_psc_tx_rdy, 1013 .tx_empty = mpc512x_psc_tx_empty, 1014 .stop_rx = mpc512x_psc_stop_rx, 1015 .start_tx = mpc512x_psc_start_tx, 1016 .stop_tx = mpc512x_psc_stop_tx, 1017 .rx_clr_irq = mpc512x_psc_rx_clr_irq, 1018 .tx_clr_irq = mpc512x_psc_tx_clr_irq, 1019 .write_char = mpc512x_psc_write_char, 1020 .read_char = mpc512x_psc_read_char, 1021 .cw_disable_ints = mpc512x_psc_cw_disable_ints, 1022 .cw_restore_ints = mpc512x_psc_cw_restore_ints, 1023 .set_baudrate = mpc512x_psc_set_baudrate, 1024 .clock_alloc = mpc512x_psc_alloc_clock, 1025 .clock_relse = mpc512x_psc_relse_clock, 1026 .clock = mpc512x_psc_endis_clock, 1027 .fifoc_init = mpc512x_psc_fifoc_init, 1028 .fifoc_uninit = mpc512x_psc_fifoc_uninit, 1029 .get_irq = mpc512x_psc_get_irq, 1030 .handle_irq = mpc512x_psc_handle_irq, 1031 .get_status = mpc52xx_psc_get_status, 1032 .get_ipcr = mpc52xx_psc_get_ipcr, 1033 .command = mpc52xx_psc_command, 1034 .set_mode = mpc52xx_psc_set_mode, 1035 .set_rts = mpc52xx_psc_set_rts, 1036 .enable_ms = mpc52xx_psc_enable_ms, 1037 .set_sicr = mpc52xx_psc_set_sicr, 1038 .set_imr = mpc52xx_psc_set_imr, 1039 .get_mr1 = mpc52xx_psc_get_mr1, 1040 }; 1041 #endif /* CONFIG_PPC_MPC512x */ 1042 1043 1044 static const struct psc_ops *psc_ops; 1045 1046 /* ======================================================================== */ 1047 /* UART operations */ 1048 /* ======================================================================== */ 1049 1050 static unsigned int 1051 mpc52xx_uart_tx_empty(struct uart_port *port) 1052 { 1053 return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0; 1054 } 1055 1056 static void 1057 mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1058 { 1059 psc_ops->set_rts(port, mctrl & TIOCM_RTS); 1060 } 1061 1062 static unsigned int 1063 mpc52xx_uart_get_mctrl(struct uart_port *port) 1064 { 1065 unsigned int ret = TIOCM_DSR; 1066 u8 status = psc_ops->get_ipcr(port); 1067 1068 if (!(status & MPC52xx_PSC_CTS)) 1069 ret |= TIOCM_CTS; 1070 if (!(status & MPC52xx_PSC_DCD)) 1071 ret |= TIOCM_CAR; 1072 1073 return ret; 1074 } 1075 1076 static void 1077 mpc52xx_uart_stop_tx(struct uart_port *port) 1078 { 1079 /* port->lock taken by caller */ 1080 psc_ops->stop_tx(port); 1081 } 1082 1083 static void 1084 mpc52xx_uart_start_tx(struct uart_port *port) 1085 { 1086 /* port->lock taken by caller */ 1087 psc_ops->start_tx(port); 1088 } 1089 1090 static void 1091 mpc52xx_uart_stop_rx(struct uart_port *port) 1092 { 1093 /* port->lock taken by caller */ 1094 psc_ops->stop_rx(port); 1095 } 1096 1097 static void 1098 mpc52xx_uart_enable_ms(struct uart_port *port) 1099 { 1100 psc_ops->enable_ms(port); 1101 } 1102 1103 static void 1104 mpc52xx_uart_break_ctl(struct uart_port *port, int ctl) 1105 { 1106 unsigned long flags; 1107 uart_port_lock_irqsave(port, &flags); 1108 1109 if (ctl == -1) 1110 psc_ops->command(port, MPC52xx_PSC_START_BRK); 1111 else 1112 psc_ops->command(port, MPC52xx_PSC_STOP_BRK); 1113 1114 uart_port_unlock_irqrestore(port, flags); 1115 } 1116 1117 static int 1118 mpc52xx_uart_startup(struct uart_port *port) 1119 { 1120 int ret; 1121 1122 if (psc_ops->clock) { 1123 ret = psc_ops->clock(port, 1); 1124 if (ret) 1125 return ret; 1126 } 1127 1128 /* Request IRQ */ 1129 ret = request_irq(port->irq, mpc52xx_uart_int, 1130 port->irqflags, "mpc52xx_psc_uart", port); 1131 if (ret) 1132 return ret; 1133 1134 /* Reset/activate the port, clear and enable interrupts */ 1135 psc_ops->command(port, MPC52xx_PSC_RST_RX); 1136 psc_ops->command(port, MPC52xx_PSC_RST_TX); 1137 1138 /* 1139 * According to Freescale's support the RST_TX command can produce a 1140 * spike on the TX pin. So they recommend to delay "for one character". 1141 * One millisecond should be enough for everyone. 1142 */ 1143 msleep(1); 1144 1145 psc_ops->set_sicr(port, 0); /* UART mode DCD ignored */ 1146 1147 psc_ops->fifo_init(port); 1148 1149 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE); 1150 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE); 1151 1152 return 0; 1153 } 1154 1155 static void 1156 mpc52xx_uart_shutdown(struct uart_port *port) 1157 { 1158 /* Shut down the port. Leave TX active if on a console port */ 1159 psc_ops->command(port, MPC52xx_PSC_RST_RX); 1160 if (!uart_console(port)) 1161 psc_ops->command(port, MPC52xx_PSC_RST_TX); 1162 1163 port->read_status_mask = 0; 1164 psc_ops->set_imr(port, port->read_status_mask); 1165 1166 if (psc_ops->clock) 1167 psc_ops->clock(port, 0); 1168 1169 /* Disable interrupt */ 1170 psc_ops->cw_disable_ints(port); 1171 1172 /* Release interrupt */ 1173 free_irq(port->irq, port); 1174 } 1175 1176 static void 1177 mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new, 1178 const struct ktermios *old) 1179 { 1180 unsigned long flags; 1181 unsigned char mr1, mr2; 1182 unsigned int j; 1183 unsigned int baud; 1184 1185 /* Prepare what we're gonna write */ 1186 mr1 = 0; 1187 1188 switch (new->c_cflag & CSIZE) { 1189 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS; 1190 break; 1191 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS; 1192 break; 1193 case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS; 1194 break; 1195 case CS8: 1196 default: mr1 |= MPC52xx_PSC_MODE_8_BITS; 1197 } 1198 1199 if (new->c_cflag & PARENB) { 1200 if (new->c_cflag & CMSPAR) 1201 mr1 |= MPC52xx_PSC_MODE_PARFORCE; 1202 1203 /* With CMSPAR, PARODD also means high parity (same as termios) */ 1204 mr1 |= (new->c_cflag & PARODD) ? 1205 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN; 1206 } else { 1207 mr1 |= MPC52xx_PSC_MODE_PARNONE; 1208 } 1209 1210 mr2 = 0; 1211 1212 if (new->c_cflag & CSTOPB) 1213 mr2 |= MPC52xx_PSC_MODE_TWO_STOP; 1214 else 1215 mr2 |= ((new->c_cflag & CSIZE) == CS5) ? 1216 MPC52xx_PSC_MODE_ONE_STOP_5_BITS : 1217 MPC52xx_PSC_MODE_ONE_STOP; 1218 1219 if (new->c_cflag & CRTSCTS) { 1220 mr1 |= MPC52xx_PSC_MODE_RXRTS; 1221 mr2 |= MPC52xx_PSC_MODE_TXCTS; 1222 } 1223 1224 /* Get the lock */ 1225 uart_port_lock_irqsave(port, &flags); 1226 1227 /* Do our best to flush TX & RX, so we don't lose anything */ 1228 /* But we don't wait indefinitely ! */ 1229 j = 5000000; /* Maximum wait */ 1230 /* FIXME Can't receive chars since set_termios might be called at early 1231 * boot for the console, all stuff is not yet ready to receive at that 1232 * time and that just makes the kernel oops */ 1233 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */ 1234 while (!mpc52xx_uart_tx_empty(port) && --j) 1235 udelay(1); 1236 1237 if (!j) 1238 printk(KERN_ERR "mpc52xx_uart.c: " 1239 "Unable to flush RX & TX fifos in-time in set_termios." 1240 "Some chars may have been lost.\n"); 1241 1242 /* Reset the TX & RX */ 1243 psc_ops->command(port, MPC52xx_PSC_RST_RX); 1244 psc_ops->command(port, MPC52xx_PSC_RST_TX); 1245 1246 /* Send new mode settings */ 1247 psc_ops->set_mode(port, mr1, mr2); 1248 baud = psc_ops->set_baudrate(port, new, old); 1249 1250 /* Update the per-port timeout */ 1251 uart_update_timeout(port, new->c_cflag, baud); 1252 1253 if (UART_ENABLE_MS(port, new->c_cflag)) 1254 mpc52xx_uart_enable_ms(port); 1255 1256 /* Reenable TX & RX */ 1257 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE); 1258 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE); 1259 1260 /* We're all set, release the lock */ 1261 uart_port_unlock_irqrestore(port, flags); 1262 } 1263 1264 static const char * 1265 mpc52xx_uart_type(struct uart_port *port) 1266 { 1267 /* 1268 * We keep using PORT_MPC52xx for historic reasons although it applies 1269 * for MPC512x, too, but print "MPC5xxx" to not irritate users 1270 */ 1271 return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL; 1272 } 1273 1274 static void 1275 mpc52xx_uart_release_port(struct uart_port *port) 1276 { 1277 if (psc_ops->clock_relse) 1278 psc_ops->clock_relse(port); 1279 1280 /* remapped by us ? */ 1281 if (port->flags & UPF_IOREMAP) { 1282 iounmap(port->membase); 1283 port->membase = NULL; 1284 } 1285 1286 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc)); 1287 } 1288 1289 static int 1290 mpc52xx_uart_request_port(struct uart_port *port) 1291 { 1292 int err; 1293 1294 if (port->flags & UPF_IOREMAP) /* Need to remap ? */ 1295 port->membase = ioremap(port->mapbase, 1296 sizeof(struct mpc52xx_psc)); 1297 1298 if (!port->membase) 1299 return -EINVAL; 1300 1301 err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc), 1302 "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY; 1303 1304 if (err) 1305 goto out_membase; 1306 1307 if (psc_ops->clock_alloc) { 1308 err = psc_ops->clock_alloc(port); 1309 if (err) 1310 goto out_mapregion; 1311 } 1312 1313 return 0; 1314 1315 out_mapregion: 1316 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc)); 1317 out_membase: 1318 if (port->flags & UPF_IOREMAP) { 1319 iounmap(port->membase); 1320 port->membase = NULL; 1321 } 1322 return err; 1323 } 1324 1325 static void 1326 mpc52xx_uart_config_port(struct uart_port *port, int flags) 1327 { 1328 if ((flags & UART_CONFIG_TYPE) 1329 && (mpc52xx_uart_request_port(port) == 0)) 1330 port->type = PORT_MPC52xx; 1331 } 1332 1333 static int 1334 mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1335 { 1336 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx) 1337 return -EINVAL; 1338 1339 if ((ser->irq != port->irq) || 1340 (ser->io_type != UPIO_MEM) || 1341 (ser->baud_base != port->uartclk) || 1342 (ser->iomem_base != (void *)port->mapbase) || 1343 (ser->hub6 != 0)) 1344 return -EINVAL; 1345 1346 return 0; 1347 } 1348 1349 1350 static const struct uart_ops mpc52xx_uart_ops = { 1351 .tx_empty = mpc52xx_uart_tx_empty, 1352 .set_mctrl = mpc52xx_uart_set_mctrl, 1353 .get_mctrl = mpc52xx_uart_get_mctrl, 1354 .stop_tx = mpc52xx_uart_stop_tx, 1355 .start_tx = mpc52xx_uart_start_tx, 1356 .stop_rx = mpc52xx_uart_stop_rx, 1357 .enable_ms = mpc52xx_uart_enable_ms, 1358 .break_ctl = mpc52xx_uart_break_ctl, 1359 .startup = mpc52xx_uart_startup, 1360 .shutdown = mpc52xx_uart_shutdown, 1361 .set_termios = mpc52xx_uart_set_termios, 1362 .type = mpc52xx_uart_type, 1363 .release_port = mpc52xx_uart_release_port, 1364 .request_port = mpc52xx_uart_request_port, 1365 .config_port = mpc52xx_uart_config_port, 1366 .verify_port = mpc52xx_uart_verify_port 1367 }; 1368 1369 1370 /* ======================================================================== */ 1371 /* Interrupt handling */ 1372 /* ======================================================================== */ 1373 1374 static inline bool 1375 mpc52xx_uart_int_rx_chars(struct uart_port *port) 1376 { 1377 struct tty_port *tport = &port->state->port; 1378 unsigned char ch, flag; 1379 unsigned short status; 1380 1381 /* While we can read, do so ! */ 1382 while (psc_ops->raw_rx_rdy(port)) { 1383 /* Get the char */ 1384 ch = psc_ops->read_char(port); 1385 1386 /* Handle sysreq char */ 1387 if (uart_handle_sysrq_char(port, ch)) 1388 continue; 1389 1390 /* Store it */ 1391 1392 flag = TTY_NORMAL; 1393 port->icount.rx++; 1394 1395 status = psc_ops->get_status(port); 1396 1397 if (status & (MPC52xx_PSC_SR_PE | 1398 MPC52xx_PSC_SR_FE | 1399 MPC52xx_PSC_SR_RB)) { 1400 1401 if (status & MPC52xx_PSC_SR_RB) { 1402 flag = TTY_BREAK; 1403 uart_handle_break(port); 1404 port->icount.brk++; 1405 } else if (status & MPC52xx_PSC_SR_PE) { 1406 flag = TTY_PARITY; 1407 port->icount.parity++; 1408 } 1409 else if (status & MPC52xx_PSC_SR_FE) { 1410 flag = TTY_FRAME; 1411 port->icount.frame++; 1412 } 1413 1414 /* Clear error condition */ 1415 psc_ops->command(port, MPC52xx_PSC_RST_ERR_STAT); 1416 1417 } 1418 tty_insert_flip_char(tport, ch, flag); 1419 if (status & MPC52xx_PSC_SR_OE) { 1420 /* 1421 * Overrun is special, since it's 1422 * reported immediately, and doesn't 1423 * affect the current character 1424 */ 1425 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 1426 port->icount.overrun++; 1427 } 1428 } 1429 1430 tty_flip_buffer_push(tport); 1431 1432 return psc_ops->raw_rx_rdy(port); 1433 } 1434 1435 static inline bool 1436 mpc52xx_uart_int_tx_chars(struct uart_port *port) 1437 { 1438 u8 ch; 1439 1440 return uart_port_tx(port, ch, 1441 psc_ops->raw_tx_rdy(port), 1442 psc_ops->write_char(port, ch)); 1443 } 1444 1445 static irqreturn_t 1446 mpc5xxx_uart_process_int(struct uart_port *port) 1447 { 1448 unsigned long pass = ISR_PASS_LIMIT; 1449 bool keepgoing; 1450 u8 status; 1451 1452 /* While we have stuff to do, we continue */ 1453 do { 1454 /* If we don't find anything to do, we stop */ 1455 keepgoing = false; 1456 1457 psc_ops->rx_clr_irq(port); 1458 if (psc_ops->rx_rdy(port)) 1459 keepgoing |= mpc52xx_uart_int_rx_chars(port); 1460 1461 psc_ops->tx_clr_irq(port); 1462 if (psc_ops->tx_rdy(port)) 1463 keepgoing |= mpc52xx_uart_int_tx_chars(port); 1464 1465 status = psc_ops->get_ipcr(port); 1466 if (status & MPC52xx_PSC_D_DCD) 1467 uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD)); 1468 1469 if (status & MPC52xx_PSC_D_CTS) 1470 uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS)); 1471 1472 /* Limit number of iteration */ 1473 if (!(--pass)) 1474 keepgoing = false; 1475 1476 } while (keepgoing); 1477 1478 return IRQ_HANDLED; 1479 } 1480 1481 static irqreturn_t 1482 mpc52xx_uart_int(int irq, void *dev_id) 1483 { 1484 struct uart_port *port = dev_id; 1485 irqreturn_t ret; 1486 1487 uart_port_lock(port); 1488 1489 ret = psc_ops->handle_irq(port); 1490 1491 uart_port_unlock(port); 1492 1493 return ret; 1494 } 1495 1496 /* ======================================================================== */ 1497 /* Console ( if applicable ) */ 1498 /* ======================================================================== */ 1499 1500 #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE 1501 1502 static void __init 1503 mpc52xx_console_get_options(struct uart_port *port, 1504 int *baud, int *parity, int *bits, int *flow) 1505 { 1506 unsigned char mr1; 1507 1508 pr_debug("mpc52xx_console_get_options(port=%p)\n", port); 1509 1510 /* Read the mode registers */ 1511 mr1 = psc_ops->get_mr1(port); 1512 1513 /* CT{U,L}R are write-only ! */ 1514 *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; 1515 1516 /* Parse them */ 1517 switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) { 1518 case MPC52xx_PSC_MODE_5_BITS: 1519 *bits = 5; 1520 break; 1521 case MPC52xx_PSC_MODE_6_BITS: 1522 *bits = 6; 1523 break; 1524 case MPC52xx_PSC_MODE_7_BITS: 1525 *bits = 7; 1526 break; 1527 case MPC52xx_PSC_MODE_8_BITS: 1528 default: 1529 *bits = 8; 1530 } 1531 1532 if (mr1 & MPC52xx_PSC_MODE_PARNONE) 1533 *parity = 'n'; 1534 else 1535 *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e'; 1536 } 1537 1538 static void 1539 mpc52xx_console_write(struct console *co, const char *s, unsigned int count) 1540 { 1541 struct uart_port *port = &mpc52xx_uart_ports[co->index]; 1542 unsigned int i, j; 1543 1544 /* Disable interrupts */ 1545 psc_ops->cw_disable_ints(port); 1546 1547 /* Wait the TX buffer to be empty */ 1548 j = 5000000; /* Maximum wait */ 1549 while (!mpc52xx_uart_tx_empty(port) && --j) 1550 udelay(1); 1551 1552 /* Write all the chars */ 1553 for (i = 0; i < count; i++, s++) { 1554 /* Line return handling */ 1555 if (*s == '\n') 1556 psc_ops->write_char(port, '\r'); 1557 1558 /* Send the char */ 1559 psc_ops->write_char(port, *s); 1560 1561 /* Wait the TX buffer to be empty */ 1562 j = 20000; /* Maximum wait */ 1563 while (!mpc52xx_uart_tx_empty(port) && --j) 1564 udelay(1); 1565 } 1566 1567 /* Restore interrupt state */ 1568 psc_ops->cw_restore_ints(port); 1569 } 1570 1571 1572 static int __init 1573 mpc52xx_console_setup(struct console *co, char *options) 1574 { 1575 struct uart_port *port = &mpc52xx_uart_ports[co->index]; 1576 struct device_node *np = mpc52xx_uart_nodes[co->index]; 1577 unsigned int uartclk; 1578 struct resource res; 1579 int ret; 1580 1581 int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; 1582 int bits = 8; 1583 int parity = 'n'; 1584 int flow = 'n'; 1585 1586 pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n", 1587 co, co->index, options); 1588 1589 if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) { 1590 pr_debug("PSC%x out of range\n", co->index); 1591 return -EINVAL; 1592 } 1593 1594 if (!np) { 1595 pr_debug("PSC%x not found in device tree\n", co->index); 1596 return -EINVAL; 1597 } 1598 1599 pr_debug("Console on ttyPSC%x is %pOF\n", 1600 co->index, mpc52xx_uart_nodes[co->index]); 1601 1602 /* Fetch register locations */ 1603 ret = of_address_to_resource(np, 0, &res); 1604 if (ret) { 1605 pr_debug("Could not get resources for PSC%x\n", co->index); 1606 return ret; 1607 } 1608 1609 uartclk = mpc5xxx_fwnode_get_bus_frequency(of_fwnode_handle(np)); 1610 if (uartclk == 0) { 1611 pr_debug("Could not find uart clock frequency!\n"); 1612 return -EINVAL; 1613 } 1614 1615 /* Basic port init. Needed since we use some uart_??? func before 1616 * real init for early access */ 1617 spin_lock_init(&port->lock); 1618 port->uartclk = uartclk; 1619 port->ops = &mpc52xx_uart_ops; 1620 port->mapbase = res.start; 1621 port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc)); 1622 port->irq = irq_of_parse_and_map(np, 0); 1623 1624 if (port->membase == NULL) 1625 return -EINVAL; 1626 1627 pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n", 1628 (void *)port->mapbase, port->membase, 1629 port->irq, port->uartclk); 1630 1631 /* Setup the port parameters according to options */ 1632 if (options) 1633 uart_parse_options(options, &baud, &parity, &bits, &flow); 1634 else 1635 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow); 1636 1637 pr_debug("Setting console parameters: %i %i%c1 flow=%c\n", 1638 baud, bits, parity, flow); 1639 1640 return uart_set_options(port, co, baud, parity, bits, flow); 1641 } 1642 1643 1644 static struct uart_driver mpc52xx_uart_driver; 1645 1646 static struct console mpc52xx_console = { 1647 .name = "ttyPSC", 1648 .write = mpc52xx_console_write, 1649 .device = uart_console_device, 1650 .setup = mpc52xx_console_setup, 1651 .flags = CON_PRINTBUFFER, 1652 .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */ 1653 .data = &mpc52xx_uart_driver, 1654 }; 1655 1656 1657 static int __init 1658 mpc52xx_console_init(void) 1659 { 1660 mpc52xx_uart_of_enumerate(); 1661 register_console(&mpc52xx_console); 1662 return 0; 1663 } 1664 1665 console_initcall(mpc52xx_console_init); 1666 1667 #define MPC52xx_PSC_CONSOLE &mpc52xx_console 1668 #else 1669 #define MPC52xx_PSC_CONSOLE NULL 1670 #endif 1671 1672 1673 /* ======================================================================== */ 1674 /* UART Driver */ 1675 /* ======================================================================== */ 1676 1677 static struct uart_driver mpc52xx_uart_driver = { 1678 .driver_name = "mpc52xx_psc_uart", 1679 .dev_name = "ttyPSC", 1680 .major = SERIAL_PSC_MAJOR, 1681 .minor = SERIAL_PSC_MINOR, 1682 .nr = MPC52xx_PSC_MAXNUM, 1683 .cons = MPC52xx_PSC_CONSOLE, 1684 }; 1685 1686 /* ======================================================================== */ 1687 /* OF Platform Driver */ 1688 /* ======================================================================== */ 1689 1690 static const struct of_device_id mpc52xx_uart_of_match[] = { 1691 #ifdef CONFIG_PPC_MPC52xx 1692 { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, }, 1693 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, 1694 /* binding used by old lite5200 device trees: */ 1695 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, 1696 /* binding used by efika: */ 1697 { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, }, 1698 #endif 1699 #ifdef CONFIG_PPC_MPC512x 1700 { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, }, 1701 { .compatible = "fsl,mpc5125-psc-uart", .data = &mpc5125_psc_ops, }, 1702 #endif 1703 {}, 1704 }; 1705 1706 static int mpc52xx_uart_of_probe(struct platform_device *op) 1707 { 1708 int idx = -1; 1709 unsigned int uartclk; 1710 struct uart_port *port = NULL; 1711 struct resource res; 1712 int ret; 1713 1714 /* Check validity & presence */ 1715 for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++) 1716 if (mpc52xx_uart_nodes[idx] == op->dev.of_node) 1717 break; 1718 if (idx >= MPC52xx_PSC_MAXNUM) 1719 return -EINVAL; 1720 pr_debug("Found %pOF assigned to ttyPSC%x\n", 1721 mpc52xx_uart_nodes[idx], idx); 1722 1723 /* set the uart clock to the input clock of the psc, the different 1724 * prescalers are taken into account in the set_baudrate() methods 1725 * of the respective chip */ 1726 uartclk = mpc5xxx_get_bus_frequency(&op->dev); 1727 if (uartclk == 0) { 1728 dev_dbg(&op->dev, "Could not find uart clock frequency!\n"); 1729 return -EINVAL; 1730 } 1731 1732 /* Init the port structure */ 1733 port = &mpc52xx_uart_ports[idx]; 1734 1735 spin_lock_init(&port->lock); 1736 port->uartclk = uartclk; 1737 port->fifosize = 512; 1738 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MPC52xx_CONSOLE); 1739 port->iotype = UPIO_MEM; 1740 port->flags = UPF_BOOT_AUTOCONF | 1741 (uart_console(port) ? 0 : UPF_IOREMAP); 1742 port->line = idx; 1743 port->ops = &mpc52xx_uart_ops; 1744 port->dev = &op->dev; 1745 1746 /* Search for IRQ and mapbase */ 1747 ret = of_address_to_resource(op->dev.of_node, 0, &res); 1748 if (ret) 1749 return ret; 1750 1751 port->mapbase = res.start; 1752 if (!port->mapbase) { 1753 dev_dbg(&op->dev, "Could not allocate resources for PSC\n"); 1754 return -EINVAL; 1755 } 1756 1757 psc_ops->get_irq(port, op->dev.of_node); 1758 if (port->irq == 0) { 1759 dev_dbg(&op->dev, "Could not get irq\n"); 1760 return -EINVAL; 1761 } 1762 1763 dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n", 1764 (void *)port->mapbase, port->irq, port->uartclk); 1765 1766 /* Add the port to the uart sub-system */ 1767 ret = uart_add_one_port(&mpc52xx_uart_driver, port); 1768 if (ret) 1769 return ret; 1770 1771 platform_set_drvdata(op, (void *)port); 1772 return 0; 1773 } 1774 1775 static void mpc52xx_uart_of_remove(struct platform_device *op) 1776 { 1777 struct uart_port *port = platform_get_drvdata(op); 1778 1779 if (port) 1780 uart_remove_one_port(&mpc52xx_uart_driver, port); 1781 } 1782 1783 #ifdef CONFIG_PM 1784 static int 1785 mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state) 1786 { 1787 struct uart_port *port = platform_get_drvdata(op); 1788 1789 if (port) 1790 uart_suspend_port(&mpc52xx_uart_driver, port); 1791 1792 return 0; 1793 } 1794 1795 static int 1796 mpc52xx_uart_of_resume(struct platform_device *op) 1797 { 1798 struct uart_port *port = platform_get_drvdata(op); 1799 1800 if (port) 1801 uart_resume_port(&mpc52xx_uart_driver, port); 1802 1803 return 0; 1804 } 1805 #endif 1806 1807 static void 1808 mpc52xx_uart_of_assign(struct device_node *np) 1809 { 1810 int i; 1811 1812 /* Find the first free PSC number */ 1813 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { 1814 if (mpc52xx_uart_nodes[i] == NULL) { 1815 of_node_get(np); 1816 mpc52xx_uart_nodes[i] = np; 1817 return; 1818 } 1819 } 1820 } 1821 1822 static void 1823 mpc52xx_uart_of_enumerate(void) 1824 { 1825 static int enum_done; 1826 struct device_node *np; 1827 const struct of_device_id *match; 1828 int i; 1829 1830 if (enum_done) 1831 return; 1832 1833 /* Assign index to each PSC in device tree */ 1834 for_each_matching_node(np, mpc52xx_uart_of_match) { 1835 match = of_match_node(mpc52xx_uart_of_match, np); 1836 psc_ops = match->data; 1837 mpc52xx_uart_of_assign(np); 1838 } 1839 1840 enum_done = 1; 1841 1842 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { 1843 if (mpc52xx_uart_nodes[i]) 1844 pr_debug("%pOF assigned to ttyPSC%x\n", 1845 mpc52xx_uart_nodes[i], i); 1846 } 1847 } 1848 1849 MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match); 1850 1851 static struct platform_driver mpc52xx_uart_of_driver = { 1852 .probe = mpc52xx_uart_of_probe, 1853 .remove = mpc52xx_uart_of_remove, 1854 #ifdef CONFIG_PM 1855 .suspend = mpc52xx_uart_of_suspend, 1856 .resume = mpc52xx_uart_of_resume, 1857 #endif 1858 .driver = { 1859 .name = "mpc52xx-psc-uart", 1860 .of_match_table = mpc52xx_uart_of_match, 1861 }, 1862 }; 1863 1864 1865 /* ======================================================================== */ 1866 /* Module */ 1867 /* ======================================================================== */ 1868 1869 static int __init 1870 mpc52xx_uart_init(void) 1871 { 1872 int ret; 1873 1874 printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n"); 1875 1876 ret = uart_register_driver(&mpc52xx_uart_driver); 1877 if (ret) { 1878 printk(KERN_ERR "%s: uart_register_driver failed (%i)\n", 1879 __FILE__, ret); 1880 return ret; 1881 } 1882 1883 mpc52xx_uart_of_enumerate(); 1884 1885 /* 1886 * Map the PSC FIFO Controller and init if on MPC512x. 1887 */ 1888 if (psc_ops && psc_ops->fifoc_init) { 1889 ret = psc_ops->fifoc_init(); 1890 if (ret) 1891 goto err_init; 1892 } 1893 1894 ret = platform_driver_register(&mpc52xx_uart_of_driver); 1895 if (ret) { 1896 printk(KERN_ERR "%s: platform_driver_register failed (%i)\n", 1897 __FILE__, ret); 1898 goto err_reg; 1899 } 1900 1901 return 0; 1902 err_reg: 1903 if (psc_ops && psc_ops->fifoc_uninit) 1904 psc_ops->fifoc_uninit(); 1905 err_init: 1906 uart_unregister_driver(&mpc52xx_uart_driver); 1907 return ret; 1908 } 1909 1910 static void __exit 1911 mpc52xx_uart_exit(void) 1912 { 1913 if (psc_ops->fifoc_uninit) 1914 psc_ops->fifoc_uninit(); 1915 1916 platform_driver_unregister(&mpc52xx_uart_of_driver); 1917 uart_unregister_driver(&mpc52xx_uart_driver); 1918 } 1919 1920 1921 module_init(mpc52xx_uart_init); 1922 module_exit(mpc52xx_uart_exit); 1923 1924 MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>"); 1925 MODULE_DESCRIPTION("Freescale MPC52xx PSC UART"); 1926 MODULE_LICENSE("GPL"); 1927