xref: /linux/drivers/tty/serial/men_z135_uart.c (revision 95cd2ea7d54b41b0b2828587f108fe270d59eede) 
1 /*
2  * MEN 16z135 High Speed UART
3  *
4  * Copyright (C) 2014 MEN Mikroelektronik GmbH (www.men.de)
5  * Author: Johannes Thumshirn <johannes.thumshirn@men.de>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the Free
9  * Software Foundation; version 2 of the License.
10  */
11 #define pr_fmt(fmt) KBUILD_MODNAME ":" fmt
12 
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/interrupt.h>
16 #include <linux/serial_core.h>
17 #include <linux/ioport.h>
18 #include <linux/io.h>
19 #include <linux/tty_flip.h>
20 #include <linux/bitops.h>
21 #include <linux/mcb.h>
22 
23 #define MEN_Z135_MAX_PORTS		12
24 #define MEN_Z135_BASECLK		29491200
25 #define MEN_Z135_FIFO_SIZE		1024
26 #define MEN_Z135_FIFO_WATERMARK		1020
27 
28 #define MEN_Z135_STAT_REG		0x0
29 #define MEN_Z135_RX_RAM			0x4
30 #define MEN_Z135_TX_RAM			0x400
31 #define MEN_Z135_RX_CTRL		0x800
32 #define MEN_Z135_TX_CTRL		0x804
33 #define MEN_Z135_CONF_REG		0x808
34 #define MEN_Z135_UART_FREQ		0x80c
35 #define MEN_Z135_BAUD_REG		0x810
36 #define MEN_Z135_TIMEOUT		0x814
37 
38 #define MEN_Z135_MEM_SIZE		0x818
39 
40 #define IRQ_ID(x) ((x) & 0x1f)
41 
42 #define MEN_Z135_IER_RXCIEN BIT(0)		/* RX Space IRQ */
43 #define MEN_Z135_IER_TXCIEN BIT(1)		/* TX Space IRQ */
44 #define MEN_Z135_IER_RLSIEN BIT(2)		/* Receiver Line Status IRQ */
45 #define MEN_Z135_IER_MSIEN  BIT(3)		/* Modem Status IRQ */
46 #define MEN_Z135_ALL_IRQS (MEN_Z135_IER_RXCIEN		\
47 				| MEN_Z135_IER_RLSIEN	\
48 				| MEN_Z135_IER_MSIEN	\
49 				| MEN_Z135_IER_TXCIEN)
50 
51 #define MEN_Z135_MCR_DTR	BIT(24)
52 #define MEN_Z135_MCR_RTS	BIT(25)
53 #define MEN_Z135_MCR_OUT1	BIT(26)
54 #define MEN_Z135_MCR_OUT2	BIT(27)
55 #define MEN_Z135_MCR_LOOP	BIT(28)
56 #define MEN_Z135_MCR_RCFC	BIT(29)
57 
58 #define MEN_Z135_MSR_DCTS	BIT(0)
59 #define MEN_Z135_MSR_DDSR	BIT(1)
60 #define MEN_Z135_MSR_DRI	BIT(2)
61 #define MEN_Z135_MSR_DDCD	BIT(3)
62 #define MEN_Z135_MSR_CTS	BIT(4)
63 #define MEN_Z135_MSR_DSR	BIT(5)
64 #define MEN_Z135_MSR_RI		BIT(6)
65 #define MEN_Z135_MSR_DCD	BIT(7)
66 
67 #define MEN_Z135_LCR_SHIFT 8	/* LCR shift mask */
68 
69 #define MEN_Z135_WL5 0		/* CS5 */
70 #define MEN_Z135_WL6 1		/* CS6 */
71 #define MEN_Z135_WL7 2		/* CS7 */
72 #define MEN_Z135_WL8 3		/* CS8 */
73 
74 #define MEN_Z135_STB_SHIFT 2	/* Stopbits */
75 #define MEN_Z135_NSTB1 0
76 #define MEN_Z135_NSTB2 1
77 
78 #define MEN_Z135_PEN_SHIFT 3	/* Parity enable */
79 #define MEN_Z135_PAR_DIS 0
80 #define MEN_Z135_PAR_ENA 1
81 
82 #define MEN_Z135_PTY_SHIFT 4	/* Parity type */
83 #define MEN_Z135_PTY_ODD 0
84 #define MEN_Z135_PTY_EVN 1
85 
86 #define MEN_Z135_LSR_DR BIT(0)
87 #define MEN_Z135_LSR_OE BIT(1)
88 #define MEN_Z135_LSR_PE BIT(2)
89 #define MEN_Z135_LSR_FE BIT(3)
90 #define MEN_Z135_LSR_BI BIT(4)
91 #define MEN_Z135_LSR_THEP BIT(5)
92 #define MEN_Z135_LSR_TEXP BIT(6)
93 #define MEN_Z135_LSR_RXFIFOERR BIT(7)
94 
95 #define MEN_Z135_IRQ_ID_RLS BIT(0)
96 #define MEN_Z135_IRQ_ID_RDA BIT(1)
97 #define MEN_Z135_IRQ_ID_CTI BIT(2)
98 #define MEN_Z135_IRQ_ID_TSA BIT(3)
99 #define MEN_Z135_IRQ_ID_MST BIT(4)
100 
101 #define LCR(x) (((x) >> MEN_Z135_LCR_SHIFT) & 0xff)
102 
103 #define BYTES_TO_ALIGN(x) ((x) & 0x3)
104 
105 static int line;
106 
107 static int txlvl = 5;
108 module_param(txlvl, int, S_IRUGO);
109 MODULE_PARM_DESC(txlvl, "TX IRQ trigger level 0-7, default 5 (128 byte)");
110 
111 static int rxlvl = 6;
112 module_param(rxlvl, int, S_IRUGO);
113 MODULE_PARM_DESC(rxlvl, "RX IRQ trigger level 0-7, default 6 (256 byte)");
114 
115 static int align;
116 module_param(align, int, S_IRUGO);
117 MODULE_PARM_DESC(align, "Keep hardware FIFO write pointer aligned, default 0");
118 
119 static uint rx_timeout;
120 module_param(rx_timeout, uint, S_IRUGO);
121 MODULE_PARM_DESC(rx_timeout, "RX timeout. "
122 		"Timeout in seconds = (timeout_reg * baud_reg * 4) / freq_reg");
123 
124 struct men_z135_port {
125 	struct uart_port port;
126 	struct mcb_device *mdev;
127 	unsigned char *rxbuf;
128 	u32 stat_reg;
129 	spinlock_t lock;
130 	bool automode;
131 };
132 #define to_men_z135(port) container_of((port), struct men_z135_port, port)
133 
134 /**
135  * men_z135_reg_set() - Set value in register
136  * @uart: The UART port
137  * @addr: Register address
138  * @val: value to set
139  */
140 static inline void men_z135_reg_set(struct men_z135_port *uart,
141 				u32 addr, u32 val)
142 {
143 	struct uart_port *port = &uart->port;
144 	unsigned long flags;
145 	u32 reg;
146 
147 	spin_lock_irqsave(&uart->lock, flags);
148 
149 	reg = ioread32(port->membase + addr);
150 	reg |= val;
151 	iowrite32(reg, port->membase + addr);
152 
153 	spin_unlock_irqrestore(&uart->lock, flags);
154 }
155 
156 /**
157  * men_z135_reg_clr() - Unset value in register
158  * @uart: The UART port
159  * @addr: Register address
160  * @val: value to clear
161  */
162 static inline void men_z135_reg_clr(struct men_z135_port *uart,
163 				u32 addr, u32 val)
164 {
165 	struct uart_port *port = &uart->port;
166 	unsigned long flags;
167 	u32 reg;
168 
169 	spin_lock_irqsave(&uart->lock, flags);
170 
171 	reg = ioread32(port->membase + addr);
172 	reg &= ~val;
173 	iowrite32(reg, port->membase + addr);
174 
175 	spin_unlock_irqrestore(&uart->lock, flags);
176 }
177 
178 /**
179  * men_z135_handle_modem_status() - Handle change of modem status
180  * @port: The UART port
181  *
182  * Handle change of modem status register. This is done by reading the "delta"
183  * versions of DCD (Data Carrier Detect) and CTS (Clear To Send).
184  */
185 static void men_z135_handle_modem_status(struct men_z135_port *uart)
186 {
187 	u8 msr;
188 
189 	msr = (uart->stat_reg >> 8) & 0xff;
190 
191 	if (msr & MEN_Z135_MSR_DDCD)
192 		uart_handle_dcd_change(&uart->port,
193 				msr & MEN_Z135_MSR_DCD);
194 	if (msr & MEN_Z135_MSR_DCTS)
195 		uart_handle_cts_change(&uart->port,
196 				msr & MEN_Z135_MSR_CTS);
197 }
198 
199 static void men_z135_handle_lsr(struct men_z135_port *uart)
200 {
201 	struct uart_port *port = &uart->port;
202 	u8 lsr;
203 
204 	lsr = (uart->stat_reg >> 16) & 0xff;
205 
206 	if (lsr & MEN_Z135_LSR_OE)
207 		port->icount.overrun++;
208 	if (lsr & MEN_Z135_LSR_PE)
209 		port->icount.parity++;
210 	if (lsr & MEN_Z135_LSR_FE)
211 		port->icount.frame++;
212 	if (lsr & MEN_Z135_LSR_BI) {
213 		port->icount.brk++;
214 		uart_handle_break(port);
215 	}
216 }
217 
218 /**
219  * get_rx_fifo_content() - Get the number of bytes in RX FIFO
220  * @uart: The UART port
221  *
222  * Read RXC register from hardware and return current FIFO fill size.
223  */
224 static u16 get_rx_fifo_content(struct men_z135_port *uart)
225 {
226 	struct uart_port *port = &uart->port;
227 	u32 stat_reg;
228 	u16 rxc;
229 	u8 rxc_lo;
230 	u8 rxc_hi;
231 
232 	stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG);
233 	rxc_lo = stat_reg >> 24;
234 	rxc_hi = (stat_reg & 0xC0) >> 6;
235 
236 	rxc = rxc_lo | (rxc_hi << 8);
237 
238 	return rxc;
239 }
240 
241 /**
242  * men_z135_handle_rx() - RX tasklet routine
243  * @arg: Pointer to struct men_z135_port
244  *
245  * Copy from RX FIFO and acknowledge number of bytes copied.
246  */
247 static void men_z135_handle_rx(struct men_z135_port *uart)
248 {
249 	struct uart_port *port = &uart->port;
250 	struct tty_port *tport = &port->state->port;
251 	int copied;
252 	u16 size;
253 	int room;
254 
255 	size = get_rx_fifo_content(uart);
256 
257 	if (size == 0)
258 		return;
259 
260 	/* Avoid accidently accessing TX FIFO instead of RX FIFO. Last
261 	 * longword in RX FIFO cannot be read.(0x004-0x3FF)
262 	 */
263 	if (size > MEN_Z135_FIFO_WATERMARK)
264 		size = MEN_Z135_FIFO_WATERMARK;
265 
266 	room = tty_buffer_request_room(tport, size);
267 	if (room != size)
268 		dev_warn(&uart->mdev->dev,
269 			"Not enough room in flip buffer, truncating to %d\n",
270 			room);
271 
272 	if (room == 0)
273 		return;
274 
275 	memcpy_fromio(uart->rxbuf, port->membase + MEN_Z135_RX_RAM, room);
276 	/* Be sure to first copy all data and then acknowledge it */
277 	mb();
278 	iowrite32(room, port->membase +  MEN_Z135_RX_CTRL);
279 
280 	copied = tty_insert_flip_string(tport, uart->rxbuf, room);
281 	if (copied != room)
282 		dev_warn(&uart->mdev->dev,
283 			"Only copied %d instead of %d bytes\n",
284 			copied, room);
285 
286 	port->icount.rx += copied;
287 
288 	tty_flip_buffer_push(tport);
289 
290 }
291 
292 /**
293  * men_z135_handle_tx() - TX tasklet routine
294  * @arg: Pointer to struct men_z135_port
295  *
296  */
297 static void men_z135_handle_tx(struct men_z135_port *uart)
298 {
299 	struct uart_port *port = &uart->port;
300 	struct circ_buf *xmit = &port->state->xmit;
301 	u32 txc;
302 	u32 wptr;
303 	int qlen;
304 	int n;
305 	int txfree;
306 	int head;
307 	int tail;
308 	int s;
309 
310 	if (uart_circ_empty(xmit))
311 		goto out;
312 
313 	if (uart_tx_stopped(port))
314 		goto out;
315 
316 	if (port->x_char)
317 		goto out;
318 
319 	/* calculate bytes to copy */
320 	qlen = uart_circ_chars_pending(xmit);
321 	if (qlen <= 0)
322 		goto out;
323 
324 	wptr = ioread32(port->membase + MEN_Z135_TX_CTRL);
325 	txc = (wptr >> 16) & 0x3ff;
326 	wptr &= 0x3ff;
327 
328 	if (txc > MEN_Z135_FIFO_WATERMARK)
329 		txc = MEN_Z135_FIFO_WATERMARK;
330 
331 	txfree = MEN_Z135_FIFO_WATERMARK - txc;
332 	if (txfree <= 0) {
333 		dev_err(&uart->mdev->dev,
334 			"Not enough room in TX FIFO have %d, need %d\n",
335 			txfree, qlen);
336 		goto irq_en;
337 	}
338 
339 	/* if we're not aligned, it's better to copy only 1 or 2 bytes and
340 	 * then the rest.
341 	 */
342 	if (align && qlen >= 3 && BYTES_TO_ALIGN(wptr))
343 		n = 4 - BYTES_TO_ALIGN(wptr);
344 	else if (qlen > txfree)
345 		n = txfree;
346 	else
347 		n = qlen;
348 
349 	if (n <= 0)
350 		goto irq_en;
351 
352 	head = xmit->head & (UART_XMIT_SIZE - 1);
353 	tail = xmit->tail & (UART_XMIT_SIZE - 1);
354 
355 	s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail;
356 	n = min(n, s);
357 
358 	memcpy_toio(port->membase + MEN_Z135_TX_RAM, &xmit->buf[xmit->tail], n);
359 	xmit->tail = (xmit->tail + n) & (UART_XMIT_SIZE - 1);
360 	mmiowb();
361 
362 	iowrite32(n & 0x3ff, port->membase + MEN_Z135_TX_CTRL);
363 
364 	port->icount.tx += n;
365 
366 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
367 		uart_write_wakeup(port);
368 
369 irq_en:
370 	if (!uart_circ_empty(xmit))
371 		men_z135_reg_set(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
372 	else
373 		men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
374 
375 out:
376 	return;
377 
378 }
379 
380 /**
381  * men_z135_intr() - Handle legacy IRQs
382  * @irq: The IRQ number
383  * @data: Pointer to UART port
384  *
385  * Check IIR register to find the cause of the interrupt and handle it.
386  * It is possible that multiple interrupts reason bits are set and reading
387  * the IIR is a destructive read, so we always need to check for all possible
388  * interrupts and handle them.
389  */
390 static irqreturn_t men_z135_intr(int irq, void *data)
391 {
392 	struct men_z135_port *uart = (struct men_z135_port *)data;
393 	struct uart_port *port = &uart->port;
394 	bool handled = false;
395 	int irq_id;
396 
397 	uart->stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG);
398 	irq_id = IRQ_ID(uart->stat_reg);
399 
400 	if (!irq_id)
401 		goto out;
402 
403 	spin_lock(&port->lock);
404 	/* It's save to write to IIR[7:6] RXC[9:8] */
405 	iowrite8(irq_id, port->membase + MEN_Z135_STAT_REG);
406 
407 	if (irq_id & MEN_Z135_IRQ_ID_RLS) {
408 		men_z135_handle_lsr(uart);
409 		handled = true;
410 	}
411 
412 	if (irq_id & (MEN_Z135_IRQ_ID_RDA | MEN_Z135_IRQ_ID_CTI)) {
413 		if (irq_id & MEN_Z135_IRQ_ID_CTI)
414 			dev_dbg(&uart->mdev->dev, "Character Timeout Indication\n");
415 		men_z135_handle_rx(uart);
416 		handled = true;
417 	}
418 
419 	if (irq_id & MEN_Z135_IRQ_ID_TSA) {
420 		men_z135_handle_tx(uart);
421 		handled = true;
422 	}
423 
424 	if (irq_id & MEN_Z135_IRQ_ID_MST) {
425 		men_z135_handle_modem_status(uart);
426 		handled = true;
427 	}
428 
429 	spin_unlock(&port->lock);
430 out:
431 	return IRQ_RETVAL(handled);
432 }
433 
434 /**
435  * men_z135_request_irq() - Request IRQ for 16z135 core
436  * @uart: z135 private uart port structure
437  *
438  * Request an IRQ for 16z135 to use. First try using MSI, if it fails
439  * fall back to using legacy interrupts.
440  */
441 static int men_z135_request_irq(struct men_z135_port *uart)
442 {
443 	struct device *dev = &uart->mdev->dev;
444 	struct uart_port *port = &uart->port;
445 	int err = 0;
446 
447 	err = request_irq(port->irq, men_z135_intr, IRQF_SHARED,
448 			"men_z135_intr", uart);
449 	if (err)
450 		dev_err(dev, "Error %d getting interrupt\n", err);
451 
452 	return err;
453 }
454 
455 /**
456  * men_z135_tx_empty() - Handle tx_empty call
457  * @port: The UART port
458  *
459  * This function tests whether the TX FIFO and shifter for the port
460  * described by @port is empty.
461  */
462 static unsigned int men_z135_tx_empty(struct uart_port *port)
463 {
464 	u32 wptr;
465 	u16 txc;
466 
467 	wptr = ioread32(port->membase + MEN_Z135_TX_CTRL);
468 	txc = (wptr >> 16) & 0x3ff;
469 
470 	if (txc == 0)
471 		return TIOCSER_TEMT;
472 	else
473 		return 0;
474 }
475 
476 /**
477  * men_z135_set_mctrl() - Set modem control lines
478  * @port: The UART port
479  * @mctrl: The modem control lines
480  *
481  * This function sets the modem control lines for a port described by @port
482  * to the state described by @mctrl
483  */
484 static void men_z135_set_mctrl(struct uart_port *port, unsigned int mctrl)
485 {
486 	u32 old;
487 	u32 conf_reg;
488 
489 	conf_reg = old = ioread32(port->membase + MEN_Z135_CONF_REG);
490 	if (mctrl & TIOCM_RTS)
491 		conf_reg |= MEN_Z135_MCR_RTS;
492 	else
493 		conf_reg &= ~MEN_Z135_MCR_RTS;
494 
495 	if (mctrl & TIOCM_DTR)
496 		conf_reg |= MEN_Z135_MCR_DTR;
497 	else
498 		conf_reg &= ~MEN_Z135_MCR_DTR;
499 
500 	if (mctrl & TIOCM_OUT1)
501 		conf_reg |= MEN_Z135_MCR_OUT1;
502 	else
503 		conf_reg &= ~MEN_Z135_MCR_OUT1;
504 
505 	if (mctrl & TIOCM_OUT2)
506 		conf_reg |= MEN_Z135_MCR_OUT2;
507 	else
508 		conf_reg &= ~MEN_Z135_MCR_OUT2;
509 
510 	if (mctrl & TIOCM_LOOP)
511 		conf_reg |= MEN_Z135_MCR_LOOP;
512 	else
513 		conf_reg &= ~MEN_Z135_MCR_LOOP;
514 
515 	if (conf_reg != old)
516 		iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG);
517 }
518 
519 /**
520  * men_z135_get_mctrl() - Get modem control lines
521  * @port: The UART port
522  *
523  * Retruns the current state of modem control inputs.
524  */
525 static unsigned int men_z135_get_mctrl(struct uart_port *port)
526 {
527 	unsigned int mctrl = 0;
528 	u8 msr;
529 
530 	msr = ioread8(port->membase + MEN_Z135_STAT_REG + 1);
531 
532 	if (msr & MEN_Z135_MSR_CTS)
533 		mctrl |= TIOCM_CTS;
534 	if (msr & MEN_Z135_MSR_DSR)
535 		mctrl |= TIOCM_DSR;
536 	if (msr & MEN_Z135_MSR_RI)
537 		mctrl |= TIOCM_RI;
538 	if (msr & MEN_Z135_MSR_DCD)
539 		mctrl |= TIOCM_CAR;
540 
541 	return mctrl;
542 }
543 
544 /**
545  * men_z135_stop_tx() - Stop transmitting characters
546  * @port: The UART port
547  *
548  * Stop transmitting characters. This might be due to CTS line becomming
549  * inactive or the tty layer indicating we want to stop transmission due to
550  * an XOFF character.
551  */
552 static void men_z135_stop_tx(struct uart_port *port)
553 {
554 	struct men_z135_port *uart = to_men_z135(port);
555 
556 	men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
557 }
558 
559 /*
560  * men_z135_disable_ms() - Disable Modem Status
561  * port: The UART port
562  *
563  * Enable Modem Status IRQ.
564  */
565 static void men_z135_disable_ms(struct uart_port *port)
566 {
567 	struct men_z135_port *uart = to_men_z135(port);
568 
569 	men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_MSIEN);
570 }
571 
572 /**
573  * men_z135_start_tx() - Start transmitting characters
574  * @port: The UART port
575  *
576  * Start transmitting character. This actually doesn't transmit anything, but
577  * fires off the TX tasklet.
578  */
579 static void men_z135_start_tx(struct uart_port *port)
580 {
581 	struct men_z135_port *uart = to_men_z135(port);
582 
583 	if (uart->automode)
584 		men_z135_disable_ms(port);
585 
586 	men_z135_handle_tx(uart);
587 }
588 
589 /**
590  * men_z135_stop_rx() - Stop receiving characters
591  * @port: The UART port
592  *
593  * Stop receiving characters; the port is in the process of being closed.
594  */
595 static void men_z135_stop_rx(struct uart_port *port)
596 {
597 	struct men_z135_port *uart = to_men_z135(port);
598 
599 	men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_RXCIEN);
600 }
601 
602 /**
603  * men_z135_enable_ms() - Enable Modem Status
604  * port:
605  *
606  * Enable Modem Status IRQ.
607  */
608 static void men_z135_enable_ms(struct uart_port *port)
609 {
610 	struct men_z135_port *uart = to_men_z135(port);
611 
612 	men_z135_reg_set(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_MSIEN);
613 }
614 
615 static int men_z135_startup(struct uart_port *port)
616 {
617 	struct men_z135_port *uart = to_men_z135(port);
618 	int err;
619 	u32 conf_reg = 0;
620 
621 	err = men_z135_request_irq(uart);
622 	if (err)
623 		return -ENODEV;
624 
625 	conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG);
626 
627 	/* Activate all but TX space available IRQ */
628 	conf_reg |= MEN_Z135_ALL_IRQS & ~MEN_Z135_IER_TXCIEN;
629 	conf_reg &= ~(0xff << 16);
630 	conf_reg |= (txlvl << 16);
631 	conf_reg |= (rxlvl << 20);
632 
633 	iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG);
634 
635 	if (rx_timeout)
636 		iowrite32(rx_timeout, port->membase + MEN_Z135_TIMEOUT);
637 
638 	return 0;
639 }
640 
641 static void men_z135_shutdown(struct uart_port *port)
642 {
643 	struct men_z135_port *uart = to_men_z135(port);
644 	u32 conf_reg = 0;
645 
646 	conf_reg |= MEN_Z135_ALL_IRQS;
647 
648 	men_z135_reg_clr(uart, MEN_Z135_CONF_REG, conf_reg);
649 
650 	free_irq(uart->port.irq, uart);
651 }
652 
653 static void men_z135_set_termios(struct uart_port *port,
654 				struct ktermios *termios,
655 				struct ktermios *old)
656 {
657 	struct men_z135_port *uart = to_men_z135(port);
658 	unsigned int baud;
659 	u32 conf_reg;
660 	u32 bd_reg;
661 	u32 uart_freq;
662 	u8 lcr;
663 
664 	conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG);
665 	lcr = LCR(conf_reg);
666 
667 	/* byte size */
668 	switch (termios->c_cflag & CSIZE) {
669 	case CS5:
670 		lcr |= MEN_Z135_WL5;
671 		break;
672 	case CS6:
673 		lcr |= MEN_Z135_WL6;
674 		break;
675 	case CS7:
676 		lcr |= MEN_Z135_WL7;
677 		break;
678 	case CS8:
679 		lcr |= MEN_Z135_WL8;
680 		break;
681 	}
682 
683 	/* stop bits */
684 	if (termios->c_cflag & CSTOPB)
685 		lcr |= MEN_Z135_NSTB2 << MEN_Z135_STB_SHIFT;
686 
687 	/* parity */
688 	if (termios->c_cflag & PARENB) {
689 		lcr |= MEN_Z135_PAR_ENA << MEN_Z135_PEN_SHIFT;
690 
691 		if (termios->c_cflag & PARODD)
692 			lcr |= MEN_Z135_PTY_ODD << MEN_Z135_PTY_SHIFT;
693 		else
694 			lcr |= MEN_Z135_PTY_EVN << MEN_Z135_PTY_SHIFT;
695 	} else
696 		lcr |= MEN_Z135_PAR_DIS << MEN_Z135_PEN_SHIFT;
697 
698 	conf_reg |= MEN_Z135_IER_MSIEN;
699 	if (termios->c_cflag & CRTSCTS) {
700 		conf_reg |= MEN_Z135_MCR_RCFC;
701 		uart->automode = true;
702 		termios->c_cflag &= ~CLOCAL;
703 	} else {
704 		conf_reg &= ~MEN_Z135_MCR_RCFC;
705 		uart->automode = false;
706 	}
707 
708 	termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
709 
710 	conf_reg |= lcr << MEN_Z135_LCR_SHIFT;
711 	iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG);
712 
713 	uart_freq = ioread32(port->membase + MEN_Z135_UART_FREQ);
714 	if (uart_freq == 0)
715 		uart_freq = MEN_Z135_BASECLK;
716 
717 	baud = uart_get_baud_rate(port, termios, old, 0, uart_freq / 16);
718 
719 	spin_lock_irq(&port->lock);
720 	if (tty_termios_baud_rate(termios))
721 		tty_termios_encode_baud_rate(termios, baud, baud);
722 
723 	bd_reg = uart_freq / (4 * baud);
724 	iowrite32(bd_reg, port->membase + MEN_Z135_BAUD_REG);
725 
726 	uart_update_timeout(port, termios->c_cflag, baud);
727 	spin_unlock_irq(&port->lock);
728 }
729 
730 static const char *men_z135_type(struct uart_port *port)
731 {
732 	return KBUILD_MODNAME;
733 }
734 
735 static void men_z135_release_port(struct uart_port *port)
736 {
737 	iounmap(port->membase);
738 	port->membase = NULL;
739 
740 	release_mem_region(port->mapbase, MEN_Z135_MEM_SIZE);
741 }
742 
743 static int men_z135_request_port(struct uart_port *port)
744 {
745 	int size = MEN_Z135_MEM_SIZE;
746 
747 	if (!request_mem_region(port->mapbase, size, "men_z135_port"))
748 		return -EBUSY;
749 
750 	port->membase = ioremap(port->mapbase, MEN_Z135_MEM_SIZE);
751 	if (port->membase == NULL) {
752 		release_mem_region(port->mapbase, MEN_Z135_MEM_SIZE);
753 		return -ENOMEM;
754 	}
755 
756 	return 0;
757 }
758 
759 static void men_z135_config_port(struct uart_port *port, int type)
760 {
761 	port->type = PORT_MEN_Z135;
762 	men_z135_request_port(port);
763 }
764 
765 static int men_z135_verify_port(struct uart_port *port,
766 				struct serial_struct *serinfo)
767 {
768 	return -EINVAL;
769 }
770 
771 static struct uart_ops men_z135_ops = {
772 	.tx_empty = men_z135_tx_empty,
773 	.set_mctrl = men_z135_set_mctrl,
774 	.get_mctrl = men_z135_get_mctrl,
775 	.stop_tx = men_z135_stop_tx,
776 	.start_tx = men_z135_start_tx,
777 	.stop_rx = men_z135_stop_rx,
778 	.enable_ms = men_z135_enable_ms,
779 	.startup = men_z135_startup,
780 	.shutdown = men_z135_shutdown,
781 	.set_termios = men_z135_set_termios,
782 	.type = men_z135_type,
783 	.release_port = men_z135_release_port,
784 	.request_port = men_z135_request_port,
785 	.config_port = men_z135_config_port,
786 	.verify_port = men_z135_verify_port,
787 };
788 
789 static struct uart_driver men_z135_driver = {
790 	.owner = THIS_MODULE,
791 	.driver_name = KBUILD_MODNAME,
792 	.dev_name = "ttyHSU",
793 	.major = 0,
794 	.minor = 0,
795 	.nr = MEN_Z135_MAX_PORTS,
796 };
797 
798 /**
799  * men_z135_probe() - Probe a z135 instance
800  * @mdev: The MCB device
801  * @id: The MCB device ID
802  *
803  * men_z135_probe does the basic setup of hardware resources and registers the
804  * new uart port to the tty layer.
805  */
806 static int men_z135_probe(struct mcb_device *mdev,
807 			const struct mcb_device_id *id)
808 {
809 	struct men_z135_port *uart;
810 	struct resource *mem;
811 	struct device *dev;
812 	int err;
813 
814 	dev = &mdev->dev;
815 
816 	uart = devm_kzalloc(dev, sizeof(struct men_z135_port), GFP_KERNEL);
817 	if (!uart)
818 		return -ENOMEM;
819 
820 	uart->rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
821 	if (!uart->rxbuf)
822 		return -ENOMEM;
823 
824 	mem = &mdev->mem;
825 
826 	mcb_set_drvdata(mdev, uart);
827 
828 	uart->port.uartclk = MEN_Z135_BASECLK * 16;
829 	uart->port.fifosize = MEN_Z135_FIFO_SIZE;
830 	uart->port.iotype = UPIO_MEM;
831 	uart->port.ops = &men_z135_ops;
832 	uart->port.irq = mcb_get_irq(mdev);
833 	uart->port.iotype = UPIO_MEM;
834 	uart->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
835 	uart->port.line = line++;
836 	uart->port.dev = dev;
837 	uart->port.type = PORT_MEN_Z135;
838 	uart->port.mapbase = mem->start;
839 	uart->port.membase = NULL;
840 	uart->mdev = mdev;
841 
842 	spin_lock_init(&uart->lock);
843 
844 	err = uart_add_one_port(&men_z135_driver, &uart->port);
845 	if (err)
846 		goto err;
847 
848 	return 0;
849 
850 err:
851 	free_page((unsigned long) uart->rxbuf);
852 	dev_err(dev, "Failed to add UART: %d\n", err);
853 
854 	return err;
855 }
856 
857 /**
858  * men_z135_remove() - Remove a z135 instance from the system
859  *
860  * @mdev: The MCB device
861  */
862 static void men_z135_remove(struct mcb_device *mdev)
863 {
864 	struct men_z135_port *uart = mcb_get_drvdata(mdev);
865 
866 	line--;
867 	uart_remove_one_port(&men_z135_driver, &uart->port);
868 	free_page((unsigned long) uart->rxbuf);
869 }
870 
871 static const struct mcb_device_id men_z135_ids[] = {
872 	{ .device = 0x87 },
873 	{ }
874 };
875 MODULE_DEVICE_TABLE(mcb, men_z135_ids);
876 
877 static struct mcb_driver mcb_driver = {
878 	.driver = {
879 		.name = "z135-uart",
880 		.owner = THIS_MODULE,
881 	},
882 	.probe = men_z135_probe,
883 	.remove = men_z135_remove,
884 	.id_table = men_z135_ids,
885 };
886 
887 /**
888  * men_z135_init() - Driver Registration Routine
889  *
890  * men_z135_init is the first routine called when the driver is loaded. All it
891  * does is register with the legacy MEN Chameleon subsystem.
892  */
893 static int __init men_z135_init(void)
894 {
895 	int err;
896 
897 	err = uart_register_driver(&men_z135_driver);
898 	if (err) {
899 		pr_err("Failed to register UART: %d\n", err);
900 		return err;
901 	}
902 
903 	err = mcb_register_driver(&mcb_driver);
904 	if  (err) {
905 		pr_err("Failed to register MCB driver: %d\n", err);
906 		uart_unregister_driver(&men_z135_driver);
907 		return err;
908 	}
909 
910 	return 0;
911 }
912 module_init(men_z135_init);
913 
914 /**
915  * men_z135_exit() - Driver Exit Routine
916  *
917  * men_z135_exit is called just before the driver is removed from memory.
918  */
919 static void __exit men_z135_exit(void)
920 {
921 	mcb_unregister_driver(&mcb_driver);
922 	uart_unregister_driver(&men_z135_driver);
923 }
924 module_exit(men_z135_exit);
925 
926 MODULE_AUTHOR("Johannes Thumshirn <johannes.thumshirn@men.de>");
927 MODULE_LICENSE("GPL v2");
928 MODULE_DESCRIPTION("MEN 16z135 High Speed UART");
929 MODULE_ALIAS("mcb:16z135");
930