xref: /linux/drivers/tty/serial/men_z135_uart.c (revision 36ec807b627b4c0a0a382f0ae48eac7187d14b2b) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * MEN 16z135 High Speed UART
4  *
5  * Copyright (C) 2014 MEN Mikroelektronik GmbH (www.men.de)
6  * Author: Johannes Thumshirn <johannes.thumshirn@men.de>
7  */
8 #define pr_fmt(fmt) KBUILD_MODNAME ":" fmt
9 
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/interrupt.h>
13 #include <linux/serial_core.h>
14 #include <linux/ioport.h>
15 #include <linux/io.h>
16 #include <linux/tty_flip.h>
17 #include <linux/bitops.h>
18 #include <linux/mcb.h>
19 
20 #define MEN_Z135_MAX_PORTS		12
21 #define MEN_Z135_BASECLK		29491200
22 #define MEN_Z135_FIFO_SIZE		1024
23 #define MEN_Z135_FIFO_WATERMARK		1020
24 
25 #define MEN_Z135_STAT_REG		0x0
26 #define MEN_Z135_RX_RAM			0x4
27 #define MEN_Z135_TX_RAM			0x400
28 #define MEN_Z135_RX_CTRL		0x800
29 #define MEN_Z135_TX_CTRL		0x804
30 #define MEN_Z135_CONF_REG		0x808
31 #define MEN_Z135_UART_FREQ		0x80c
32 #define MEN_Z135_BAUD_REG		0x810
33 #define MEN_Z135_TIMEOUT		0x814
34 
35 #define IRQ_ID(x) ((x) & 0x1f)
36 
37 #define MEN_Z135_IER_RXCIEN BIT(0)		/* RX Space IRQ */
38 #define MEN_Z135_IER_TXCIEN BIT(1)		/* TX Space IRQ */
39 #define MEN_Z135_IER_RLSIEN BIT(2)		/* Receiver Line Status IRQ */
40 #define MEN_Z135_IER_MSIEN  BIT(3)		/* Modem Status IRQ */
41 #define MEN_Z135_ALL_IRQS (MEN_Z135_IER_RXCIEN		\
42 				| MEN_Z135_IER_RLSIEN	\
43 				| MEN_Z135_IER_MSIEN	\
44 				| MEN_Z135_IER_TXCIEN)
45 
46 #define MEN_Z135_MCR_DTR	BIT(24)
47 #define MEN_Z135_MCR_RTS	BIT(25)
48 #define MEN_Z135_MCR_OUT1	BIT(26)
49 #define MEN_Z135_MCR_OUT2	BIT(27)
50 #define MEN_Z135_MCR_LOOP	BIT(28)
51 #define MEN_Z135_MCR_RCFC	BIT(29)
52 
53 #define MEN_Z135_MSR_DCTS	BIT(0)
54 #define MEN_Z135_MSR_DDSR	BIT(1)
55 #define MEN_Z135_MSR_DRI	BIT(2)
56 #define MEN_Z135_MSR_DDCD	BIT(3)
57 #define MEN_Z135_MSR_CTS	BIT(4)
58 #define MEN_Z135_MSR_DSR	BIT(5)
59 #define MEN_Z135_MSR_RI		BIT(6)
60 #define MEN_Z135_MSR_DCD	BIT(7)
61 
62 #define MEN_Z135_LCR_SHIFT 8	/* LCR shift mask */
63 
64 #define MEN_Z135_WL5 0		/* CS5 */
65 #define MEN_Z135_WL6 1		/* CS6 */
66 #define MEN_Z135_WL7 2		/* CS7 */
67 #define MEN_Z135_WL8 3		/* CS8 */
68 
69 #define MEN_Z135_STB_SHIFT 2	/* Stopbits */
70 #define MEN_Z135_NSTB1 0
71 #define MEN_Z135_NSTB2 1
72 
73 #define MEN_Z135_PEN_SHIFT 3	/* Parity enable */
74 #define MEN_Z135_PAR_DIS 0
75 #define MEN_Z135_PAR_ENA 1
76 
77 #define MEN_Z135_PTY_SHIFT 4	/* Parity type */
78 #define MEN_Z135_PTY_ODD 0
79 #define MEN_Z135_PTY_EVN 1
80 
81 #define MEN_Z135_LSR_DR BIT(0)
82 #define MEN_Z135_LSR_OE BIT(1)
83 #define MEN_Z135_LSR_PE BIT(2)
84 #define MEN_Z135_LSR_FE BIT(3)
85 #define MEN_Z135_LSR_BI BIT(4)
86 #define MEN_Z135_LSR_THEP BIT(5)
87 #define MEN_Z135_LSR_TEXP BIT(6)
88 #define MEN_Z135_LSR_RXFIFOERR BIT(7)
89 
90 #define MEN_Z135_IRQ_ID_RLS BIT(0)
91 #define MEN_Z135_IRQ_ID_RDA BIT(1)
92 #define MEN_Z135_IRQ_ID_CTI BIT(2)
93 #define MEN_Z135_IRQ_ID_TSA BIT(3)
94 #define MEN_Z135_IRQ_ID_MST BIT(4)
95 
96 #define LCR(x) (((x) >> MEN_Z135_LCR_SHIFT) & 0xff)
97 
98 #define BYTES_TO_ALIGN(x) ((x) & 0x3)
99 
100 static int line;
101 
102 static int txlvl = 5;
103 module_param(txlvl, int, S_IRUGO);
104 MODULE_PARM_DESC(txlvl, "TX IRQ trigger level 0-7, default 5 (128 byte)");
105 
106 static int rxlvl = 6;
107 module_param(rxlvl, int, S_IRUGO);
108 MODULE_PARM_DESC(rxlvl, "RX IRQ trigger level 0-7, default 6 (256 byte)");
109 
110 static int align;
111 module_param(align, int, S_IRUGO);
112 MODULE_PARM_DESC(align, "Keep hardware FIFO write pointer aligned, default 0");
113 
114 static uint rx_timeout;
115 module_param(rx_timeout, uint, S_IRUGO);
116 MODULE_PARM_DESC(rx_timeout, "RX timeout. "
117 		"Timeout in seconds = (timeout_reg * baud_reg * 4) / freq_reg");
118 
119 struct men_z135_port {
120 	struct uart_port port;
121 	struct mcb_device *mdev;
122 	struct resource *mem;
123 	unsigned char *rxbuf;
124 	u32 stat_reg;
125 	spinlock_t lock;
126 	bool automode;
127 };
128 #define to_men_z135(port) container_of((port), struct men_z135_port, port)
129 
130 /**
131  * men_z135_reg_set() - Set value in register
132  * @uart: The UART port
133  * @addr: Register address
134  * @val: value to set
135  */
136 static inline void men_z135_reg_set(struct men_z135_port *uart,
137 				u32 addr, u32 val)
138 {
139 	struct uart_port *port = &uart->port;
140 	unsigned long flags;
141 	u32 reg;
142 
143 	spin_lock_irqsave(&uart->lock, flags);
144 
145 	reg = ioread32(port->membase + addr);
146 	reg |= val;
147 	iowrite32(reg, port->membase + addr);
148 
149 	spin_unlock_irqrestore(&uart->lock, flags);
150 }
151 
152 /**
153  * men_z135_reg_clr() - Unset value in register
154  * @uart: The UART port
155  * @addr: Register address
156  * @val: value to clear
157  */
158 static void men_z135_reg_clr(struct men_z135_port *uart,
159 				u32 addr, u32 val)
160 {
161 	struct uart_port *port = &uart->port;
162 	unsigned long flags;
163 	u32 reg;
164 
165 	spin_lock_irqsave(&uart->lock, flags);
166 
167 	reg = ioread32(port->membase + addr);
168 	reg &= ~val;
169 	iowrite32(reg, port->membase + addr);
170 
171 	spin_unlock_irqrestore(&uart->lock, flags);
172 }
173 
174 /**
175  * men_z135_handle_modem_status() - Handle change of modem status
176  * @uart: The UART port
177  *
178  * Handle change of modem status register. This is done by reading the "delta"
179  * versions of DCD (Data Carrier Detect) and CTS (Clear To Send).
180  */
181 static void men_z135_handle_modem_status(struct men_z135_port *uart)
182 {
183 	u8 msr;
184 
185 	msr = (uart->stat_reg >> 8) & 0xff;
186 
187 	if (msr & MEN_Z135_MSR_DDCD)
188 		uart_handle_dcd_change(&uart->port,
189 				msr & MEN_Z135_MSR_DCD);
190 	if (msr & MEN_Z135_MSR_DCTS)
191 		uart_handle_cts_change(&uart->port,
192 				msr & MEN_Z135_MSR_CTS);
193 }
194 
195 static void men_z135_handle_lsr(struct men_z135_port *uart)
196 {
197 	struct uart_port *port = &uart->port;
198 	u8 lsr;
199 
200 	lsr = (uart->stat_reg >> 16) & 0xff;
201 
202 	if (lsr & MEN_Z135_LSR_OE)
203 		port->icount.overrun++;
204 	if (lsr & MEN_Z135_LSR_PE)
205 		port->icount.parity++;
206 	if (lsr & MEN_Z135_LSR_FE)
207 		port->icount.frame++;
208 	if (lsr & MEN_Z135_LSR_BI) {
209 		port->icount.brk++;
210 		uart_handle_break(port);
211 	}
212 }
213 
214 /**
215  * get_rx_fifo_content() - Get the number of bytes in RX FIFO
216  * @uart: The UART port
217  *
218  * Read RXC register from hardware and return current FIFO fill size.
219  */
220 static u16 get_rx_fifo_content(struct men_z135_port *uart)
221 {
222 	struct uart_port *port = &uart->port;
223 	u32 stat_reg;
224 	u16 rxc;
225 	u8 rxc_lo;
226 	u8 rxc_hi;
227 
228 	stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG);
229 	rxc_lo = stat_reg >> 24;
230 	rxc_hi = (stat_reg & 0xC0) >> 6;
231 
232 	rxc = rxc_lo | (rxc_hi << 8);
233 
234 	return rxc;
235 }
236 
237 /**
238  * men_z135_handle_rx() - RX tasklet routine
239  * @uart: Pointer to struct men_z135_port
240  *
241  * Copy from RX FIFO and acknowledge number of bytes copied.
242  */
243 static void men_z135_handle_rx(struct men_z135_port *uart)
244 {
245 	struct uart_port *port = &uart->port;
246 	struct tty_port *tport = &port->state->port;
247 	int copied;
248 	u16 size;
249 	int room;
250 
251 	size = get_rx_fifo_content(uart);
252 
253 	if (size == 0)
254 		return;
255 
256 	/* Avoid accidently accessing TX FIFO instead of RX FIFO. Last
257 	 * longword in RX FIFO cannot be read.(0x004-0x3FF)
258 	 */
259 	if (size > MEN_Z135_FIFO_WATERMARK)
260 		size = MEN_Z135_FIFO_WATERMARK;
261 
262 	room = tty_buffer_request_room(tport, size);
263 	if (room != size)
264 		dev_warn(&uart->mdev->dev,
265 			"Not enough room in flip buffer, truncating to %d\n",
266 			room);
267 
268 	if (room == 0)
269 		return;
270 
271 	memcpy_fromio(uart->rxbuf, port->membase + MEN_Z135_RX_RAM, room);
272 	/* Be sure to first copy all data and then acknowledge it */
273 	mb();
274 	iowrite32(room, port->membase +  MEN_Z135_RX_CTRL);
275 
276 	copied = tty_insert_flip_string(tport, uart->rxbuf, room);
277 	if (copied != room)
278 		dev_warn(&uart->mdev->dev,
279 			"Only copied %d instead of %d bytes\n",
280 			copied, room);
281 
282 	port->icount.rx += copied;
283 
284 	tty_flip_buffer_push(tport);
285 
286 }
287 
288 /**
289  * men_z135_handle_tx() - TX tasklet routine
290  * @uart: Pointer to struct men_z135_port
291  *
292  */
293 static void men_z135_handle_tx(struct men_z135_port *uart)
294 {
295 	struct uart_port *port = &uart->port;
296 	struct tty_port *tport = &port->state->port;
297 	unsigned char *tail;
298 	unsigned int n, txfree;
299 	u32 txc;
300 	u32 wptr;
301 	int qlen;
302 
303 	if (kfifo_is_empty(&tport->xmit_fifo))
304 		goto out;
305 
306 	if (uart_tx_stopped(port))
307 		goto out;
308 
309 	if (port->x_char)
310 		goto out;
311 
312 	/* calculate bytes to copy */
313 	qlen = kfifo_len(&tport->xmit_fifo);
314 	if (qlen <= 0)
315 		goto out;
316 
317 	wptr = ioread32(port->membase + MEN_Z135_TX_CTRL);
318 	txc = (wptr >> 16) & 0x3ff;
319 	wptr &= 0x3ff;
320 
321 	if (txc > MEN_Z135_FIFO_WATERMARK)
322 		txc = MEN_Z135_FIFO_WATERMARK;
323 
324 	txfree = MEN_Z135_FIFO_WATERMARK - txc;
325 	if (txfree <= 0) {
326 		dev_err(&uart->mdev->dev,
327 			"Not enough room in TX FIFO have %d, need %d\n",
328 			txfree, qlen);
329 		goto irq_en;
330 	}
331 
332 	/* if we're not aligned, it's better to copy only 1 or 2 bytes and
333 	 * then the rest.
334 	 */
335 	if (align && qlen >= 3 && BYTES_TO_ALIGN(wptr))
336 		n = 4 - BYTES_TO_ALIGN(wptr);
337 	else if (qlen > txfree)
338 		n = txfree;
339 	else
340 		n = qlen;
341 
342 	if (n <= 0)
343 		goto irq_en;
344 
345 	n = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail,
346 			min_t(unsigned int, UART_XMIT_SIZE, n));
347 	memcpy_toio(port->membase + MEN_Z135_TX_RAM, tail, n);
348 
349 	iowrite32(n & 0x3ff, port->membase + MEN_Z135_TX_CTRL);
350 	uart_xmit_advance(port, n);
351 
352 	if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
353 		uart_write_wakeup(port);
354 
355 irq_en:
356 	if (!kfifo_is_empty(&tport->xmit_fifo))
357 		men_z135_reg_set(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
358 	else
359 		men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
360 
361 out:
362 	return;
363 
364 }
365 
366 /**
367  * men_z135_intr() - Handle legacy IRQs
368  * @irq: The IRQ number
369  * @data: Pointer to UART port
370  *
371  * Check IIR register to find the cause of the interrupt and handle it.
372  * It is possible that multiple interrupts reason bits are set and reading
373  * the IIR is a destructive read, so we always need to check for all possible
374  * interrupts and handle them.
375  */
376 static irqreturn_t men_z135_intr(int irq, void *data)
377 {
378 	struct men_z135_port *uart = (struct men_z135_port *)data;
379 	struct uart_port *port = &uart->port;
380 	bool handled = false;
381 	int irq_id;
382 
383 	uart->stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG);
384 	irq_id = IRQ_ID(uart->stat_reg);
385 
386 	if (!irq_id)
387 		goto out;
388 
389 	uart_port_lock(port);
390 	/* It's save to write to IIR[7:6] RXC[9:8] */
391 	iowrite8(irq_id, port->membase + MEN_Z135_STAT_REG);
392 
393 	if (irq_id & MEN_Z135_IRQ_ID_RLS) {
394 		men_z135_handle_lsr(uart);
395 		handled = true;
396 	}
397 
398 	if (irq_id & (MEN_Z135_IRQ_ID_RDA | MEN_Z135_IRQ_ID_CTI)) {
399 		if (irq_id & MEN_Z135_IRQ_ID_CTI)
400 			dev_dbg(&uart->mdev->dev, "Character Timeout Indication\n");
401 		men_z135_handle_rx(uart);
402 		handled = true;
403 	}
404 
405 	if (irq_id & MEN_Z135_IRQ_ID_TSA) {
406 		men_z135_handle_tx(uart);
407 		handled = true;
408 	}
409 
410 	if (irq_id & MEN_Z135_IRQ_ID_MST) {
411 		men_z135_handle_modem_status(uart);
412 		handled = true;
413 	}
414 
415 	uart_port_unlock(port);
416 out:
417 	return IRQ_RETVAL(handled);
418 }
419 
420 /**
421  * men_z135_request_irq() - Request IRQ for 16z135 core
422  * @uart: z135 private uart port structure
423  *
424  * Request an IRQ for 16z135 to use. First try using MSI, if it fails
425  * fall back to using legacy interrupts.
426  */
427 static int men_z135_request_irq(struct men_z135_port *uart)
428 {
429 	struct device *dev = &uart->mdev->dev;
430 	struct uart_port *port = &uart->port;
431 	int err = 0;
432 
433 	err = request_irq(port->irq, men_z135_intr, IRQF_SHARED,
434 			"men_z135_intr", uart);
435 	if (err)
436 		dev_err(dev, "Error %d getting interrupt\n", err);
437 
438 	return err;
439 }
440 
441 /**
442  * men_z135_tx_empty() - Handle tx_empty call
443  * @port: The UART port
444  *
445  * This function tests whether the TX FIFO and shifter for the port
446  * described by @port is empty.
447  */
448 static unsigned int men_z135_tx_empty(struct uart_port *port)
449 {
450 	u32 wptr;
451 	u16 txc;
452 
453 	wptr = ioread32(port->membase + MEN_Z135_TX_CTRL);
454 	txc = (wptr >> 16) & 0x3ff;
455 
456 	if (txc == 0)
457 		return TIOCSER_TEMT;
458 	else
459 		return 0;
460 }
461 
462 /**
463  * men_z135_set_mctrl() - Set modem control lines
464  * @port: The UART port
465  * @mctrl: The modem control lines
466  *
467  * This function sets the modem control lines for a port described by @port
468  * to the state described by @mctrl
469  */
470 static void men_z135_set_mctrl(struct uart_port *port, unsigned int mctrl)
471 {
472 	u32 old;
473 	u32 conf_reg;
474 
475 	conf_reg = old = ioread32(port->membase + MEN_Z135_CONF_REG);
476 	if (mctrl & TIOCM_RTS)
477 		conf_reg |= MEN_Z135_MCR_RTS;
478 	else
479 		conf_reg &= ~MEN_Z135_MCR_RTS;
480 
481 	if (mctrl & TIOCM_DTR)
482 		conf_reg |= MEN_Z135_MCR_DTR;
483 	else
484 		conf_reg &= ~MEN_Z135_MCR_DTR;
485 
486 	if (mctrl & TIOCM_OUT1)
487 		conf_reg |= MEN_Z135_MCR_OUT1;
488 	else
489 		conf_reg &= ~MEN_Z135_MCR_OUT1;
490 
491 	if (mctrl & TIOCM_OUT2)
492 		conf_reg |= MEN_Z135_MCR_OUT2;
493 	else
494 		conf_reg &= ~MEN_Z135_MCR_OUT2;
495 
496 	if (mctrl & TIOCM_LOOP)
497 		conf_reg |= MEN_Z135_MCR_LOOP;
498 	else
499 		conf_reg &= ~MEN_Z135_MCR_LOOP;
500 
501 	if (conf_reg != old)
502 		iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG);
503 }
504 
505 /**
506  * men_z135_get_mctrl() - Get modem control lines
507  * @port: The UART port
508  *
509  * Retruns the current state of modem control inputs.
510  */
511 static unsigned int men_z135_get_mctrl(struct uart_port *port)
512 {
513 	unsigned int mctrl = 0;
514 	u8 msr;
515 
516 	msr = ioread8(port->membase + MEN_Z135_STAT_REG + 1);
517 
518 	if (msr & MEN_Z135_MSR_CTS)
519 		mctrl |= TIOCM_CTS;
520 	if (msr & MEN_Z135_MSR_DSR)
521 		mctrl |= TIOCM_DSR;
522 	if (msr & MEN_Z135_MSR_RI)
523 		mctrl |= TIOCM_RI;
524 	if (msr & MEN_Z135_MSR_DCD)
525 		mctrl |= TIOCM_CAR;
526 
527 	return mctrl;
528 }
529 
530 /**
531  * men_z135_stop_tx() - Stop transmitting characters
532  * @port: The UART port
533  *
534  * Stop transmitting characters. This might be due to CTS line becomming
535  * inactive or the tty layer indicating we want to stop transmission due to
536  * an XOFF character.
537  */
538 static void men_z135_stop_tx(struct uart_port *port)
539 {
540 	struct men_z135_port *uart = to_men_z135(port);
541 
542 	men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
543 }
544 
545 /*
546  * men_z135_disable_ms() - Disable Modem Status
547  * port: The UART port
548  *
549  * Enable Modem Status IRQ.
550  */
551 static void men_z135_disable_ms(struct uart_port *port)
552 {
553 	struct men_z135_port *uart = to_men_z135(port);
554 
555 	men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_MSIEN);
556 }
557 
558 /**
559  * men_z135_start_tx() - Start transmitting characters
560  * @port: The UART port
561  *
562  * Start transmitting character. This actually doesn't transmit anything, but
563  * fires off the TX tasklet.
564  */
565 static void men_z135_start_tx(struct uart_port *port)
566 {
567 	struct men_z135_port *uart = to_men_z135(port);
568 
569 	if (uart->automode)
570 		men_z135_disable_ms(port);
571 
572 	men_z135_handle_tx(uart);
573 }
574 
575 /**
576  * men_z135_stop_rx() - Stop receiving characters
577  * @port: The UART port
578  *
579  * Stop receiving characters; the port is in the process of being closed.
580  */
581 static void men_z135_stop_rx(struct uart_port *port)
582 {
583 	struct men_z135_port *uart = to_men_z135(port);
584 
585 	men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_RXCIEN);
586 }
587 
588 /**
589  * men_z135_enable_ms() - Enable Modem Status
590  * @port: the port
591  *
592  * Enable Modem Status IRQ.
593  */
594 static void men_z135_enable_ms(struct uart_port *port)
595 {
596 	struct men_z135_port *uart = to_men_z135(port);
597 
598 	men_z135_reg_set(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_MSIEN);
599 }
600 
601 static int men_z135_startup(struct uart_port *port)
602 {
603 	struct men_z135_port *uart = to_men_z135(port);
604 	int err;
605 	u32 conf_reg = 0;
606 
607 	err = men_z135_request_irq(uart);
608 	if (err)
609 		return -ENODEV;
610 
611 	conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG);
612 
613 	/* Activate all but TX space available IRQ */
614 	conf_reg |= MEN_Z135_ALL_IRQS & ~MEN_Z135_IER_TXCIEN;
615 	conf_reg &= ~(0xff << 16);
616 	conf_reg |= (txlvl << 16);
617 	conf_reg |= (rxlvl << 20);
618 
619 	iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG);
620 
621 	if (rx_timeout)
622 		iowrite32(rx_timeout, port->membase + MEN_Z135_TIMEOUT);
623 
624 	return 0;
625 }
626 
627 static void men_z135_shutdown(struct uart_port *port)
628 {
629 	struct men_z135_port *uart = to_men_z135(port);
630 	u32 conf_reg = 0;
631 
632 	conf_reg |= MEN_Z135_ALL_IRQS;
633 
634 	men_z135_reg_clr(uart, MEN_Z135_CONF_REG, conf_reg);
635 
636 	free_irq(uart->port.irq, uart);
637 }
638 
639 static void men_z135_set_termios(struct uart_port *port,
640 				 struct ktermios *termios,
641 				 const struct ktermios *old)
642 {
643 	struct men_z135_port *uart = to_men_z135(port);
644 	unsigned int baud;
645 	u32 conf_reg;
646 	u32 bd_reg;
647 	u32 uart_freq;
648 	u8 lcr;
649 
650 	conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG);
651 	lcr = LCR(conf_reg);
652 
653 	/* byte size */
654 	switch (termios->c_cflag & CSIZE) {
655 	case CS5:
656 		lcr |= MEN_Z135_WL5;
657 		break;
658 	case CS6:
659 		lcr |= MEN_Z135_WL6;
660 		break;
661 	case CS7:
662 		lcr |= MEN_Z135_WL7;
663 		break;
664 	case CS8:
665 		lcr |= MEN_Z135_WL8;
666 		break;
667 	}
668 
669 	/* stop bits */
670 	if (termios->c_cflag & CSTOPB)
671 		lcr |= MEN_Z135_NSTB2 << MEN_Z135_STB_SHIFT;
672 
673 	/* parity */
674 	if (termios->c_cflag & PARENB) {
675 		lcr |= MEN_Z135_PAR_ENA << MEN_Z135_PEN_SHIFT;
676 
677 		if (termios->c_cflag & PARODD)
678 			lcr |= MEN_Z135_PTY_ODD << MEN_Z135_PTY_SHIFT;
679 		else
680 			lcr |= MEN_Z135_PTY_EVN << MEN_Z135_PTY_SHIFT;
681 	} else
682 		lcr |= MEN_Z135_PAR_DIS << MEN_Z135_PEN_SHIFT;
683 
684 	conf_reg |= MEN_Z135_IER_MSIEN;
685 	if (termios->c_cflag & CRTSCTS) {
686 		conf_reg |= MEN_Z135_MCR_RCFC;
687 		uart->automode = true;
688 		termios->c_cflag &= ~CLOCAL;
689 	} else {
690 		conf_reg &= ~MEN_Z135_MCR_RCFC;
691 		uart->automode = false;
692 	}
693 
694 	termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
695 
696 	conf_reg |= lcr << MEN_Z135_LCR_SHIFT;
697 	iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG);
698 
699 	uart_freq = ioread32(port->membase + MEN_Z135_UART_FREQ);
700 	if (uart_freq == 0)
701 		uart_freq = MEN_Z135_BASECLK;
702 
703 	baud = uart_get_baud_rate(port, termios, old, 0, uart_freq / 16);
704 
705 	uart_port_lock_irq(port);
706 	if (tty_termios_baud_rate(termios))
707 		tty_termios_encode_baud_rate(termios, baud, baud);
708 
709 	bd_reg = uart_freq / (4 * baud);
710 	iowrite32(bd_reg, port->membase + MEN_Z135_BAUD_REG);
711 
712 	uart_update_timeout(port, termios->c_cflag, baud);
713 	uart_port_unlock_irq(port);
714 }
715 
716 static const char *men_z135_type(struct uart_port *port)
717 {
718 	return KBUILD_MODNAME;
719 }
720 
721 static void men_z135_release_port(struct uart_port *port)
722 {
723 	struct men_z135_port *uart = to_men_z135(port);
724 
725 	iounmap(port->membase);
726 	port->membase = NULL;
727 
728 	mcb_release_mem(uart->mem);
729 }
730 
731 static int men_z135_request_port(struct uart_port *port)
732 {
733 	struct men_z135_port *uart = to_men_z135(port);
734 	struct mcb_device *mdev = uart->mdev;
735 	struct resource *mem;
736 
737 	mem = mcb_request_mem(uart->mdev, dev_name(&mdev->dev));
738 	if (IS_ERR(mem))
739 		return PTR_ERR(mem);
740 
741 	port->mapbase = mem->start;
742 	uart->mem = mem;
743 
744 	port->membase = ioremap(mem->start, resource_size(mem));
745 	if (port->membase == NULL) {
746 		mcb_release_mem(mem);
747 		return -ENOMEM;
748 	}
749 
750 	return 0;
751 }
752 
753 static void men_z135_config_port(struct uart_port *port, int type)
754 {
755 	port->type = PORT_MEN_Z135;
756 	men_z135_request_port(port);
757 }
758 
759 static int men_z135_verify_port(struct uart_port *port,
760 				struct serial_struct *serinfo)
761 {
762 	return -EINVAL;
763 }
764 
765 static const struct uart_ops men_z135_ops = {
766 	.tx_empty = men_z135_tx_empty,
767 	.set_mctrl = men_z135_set_mctrl,
768 	.get_mctrl = men_z135_get_mctrl,
769 	.stop_tx = men_z135_stop_tx,
770 	.start_tx = men_z135_start_tx,
771 	.stop_rx = men_z135_stop_rx,
772 	.enable_ms = men_z135_enable_ms,
773 	.startup = men_z135_startup,
774 	.shutdown = men_z135_shutdown,
775 	.set_termios = men_z135_set_termios,
776 	.type = men_z135_type,
777 	.release_port = men_z135_release_port,
778 	.request_port = men_z135_request_port,
779 	.config_port = men_z135_config_port,
780 	.verify_port = men_z135_verify_port,
781 };
782 
783 static struct uart_driver men_z135_driver = {
784 	.owner = THIS_MODULE,
785 	.driver_name = KBUILD_MODNAME,
786 	.dev_name = "ttyHSU",
787 	.major = 0,
788 	.minor = 0,
789 	.nr = MEN_Z135_MAX_PORTS,
790 };
791 
792 /**
793  * men_z135_probe() - Probe a z135 instance
794  * @mdev: The MCB device
795  * @id: The MCB device ID
796  *
797  * men_z135_probe does the basic setup of hardware resources and registers the
798  * new uart port to the tty layer.
799  */
800 static int men_z135_probe(struct mcb_device *mdev,
801 			const struct mcb_device_id *id)
802 {
803 	struct men_z135_port *uart;
804 	struct resource *mem;
805 	struct device *dev;
806 	int err;
807 
808 	dev = &mdev->dev;
809 
810 	uart = devm_kzalloc(dev, sizeof(struct men_z135_port), GFP_KERNEL);
811 	if (!uart)
812 		return -ENOMEM;
813 
814 	uart->rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
815 	if (!uart->rxbuf)
816 		return -ENOMEM;
817 
818 	mem = &mdev->mem;
819 
820 	mcb_set_drvdata(mdev, uart);
821 
822 	uart->port.uartclk = MEN_Z135_BASECLK * 16;
823 	uart->port.fifosize = MEN_Z135_FIFO_SIZE;
824 	uart->port.iotype = UPIO_MEM;
825 	uart->port.ops = &men_z135_ops;
826 	uart->port.irq = mcb_get_irq(mdev);
827 	uart->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
828 	uart->port.line = line++;
829 	uart->port.dev = dev;
830 	uart->port.type = PORT_MEN_Z135;
831 	uart->port.mapbase = mem->start;
832 	uart->port.membase = NULL;
833 	uart->mdev = mdev;
834 
835 	spin_lock_init(&uart->lock);
836 
837 	err = uart_add_one_port(&men_z135_driver, &uart->port);
838 	if (err)
839 		goto err;
840 
841 	return 0;
842 
843 err:
844 	free_page((unsigned long) uart->rxbuf);
845 	dev_err(dev, "Failed to add UART: %d\n", err);
846 
847 	return err;
848 }
849 
850 /**
851  * men_z135_remove() - Remove a z135 instance from the system
852  *
853  * @mdev: The MCB device
854  */
855 static void men_z135_remove(struct mcb_device *mdev)
856 {
857 	struct men_z135_port *uart = mcb_get_drvdata(mdev);
858 
859 	line--;
860 	uart_remove_one_port(&men_z135_driver, &uart->port);
861 	free_page((unsigned long) uart->rxbuf);
862 }
863 
864 static const struct mcb_device_id men_z135_ids[] = {
865 	{ .device = 0x87 },
866 	{ }
867 };
868 MODULE_DEVICE_TABLE(mcb, men_z135_ids);
869 
870 static struct mcb_driver mcb_driver = {
871 	.driver = {
872 		.name = "z135-uart",
873 		.owner = THIS_MODULE,
874 	},
875 	.probe = men_z135_probe,
876 	.remove = men_z135_remove,
877 	.id_table = men_z135_ids,
878 };
879 
880 /**
881  * men_z135_init() - Driver Registration Routine
882  *
883  * men_z135_init is the first routine called when the driver is loaded. All it
884  * does is register with the legacy MEN Chameleon subsystem.
885  */
886 static int __init men_z135_init(void)
887 {
888 	int err;
889 
890 	err = uart_register_driver(&men_z135_driver);
891 	if (err) {
892 		pr_err("Failed to register UART: %d\n", err);
893 		return err;
894 	}
895 
896 	err = mcb_register_driver(&mcb_driver);
897 	if  (err) {
898 		pr_err("Failed to register MCB driver: %d\n", err);
899 		uart_unregister_driver(&men_z135_driver);
900 		return err;
901 	}
902 
903 	return 0;
904 }
905 module_init(men_z135_init);
906 
907 /**
908  * men_z135_exit() - Driver Exit Routine
909  *
910  * men_z135_exit is called just before the driver is removed from memory.
911  */
912 static void __exit men_z135_exit(void)
913 {
914 	mcb_unregister_driver(&mcb_driver);
915 	uart_unregister_driver(&men_z135_driver);
916 }
917 module_exit(men_z135_exit);
918 
919 MODULE_AUTHOR("Johannes Thumshirn <johannes.thumshirn@men.de>");
920 MODULE_LICENSE("GPL v2");
921 MODULE_DESCRIPTION("MEN 16z135 High Speed UART");
922 MODULE_ALIAS("mcb:16z135");
923 MODULE_IMPORT_NS(MCB);
924