xref: /linux/drivers/tty/serial/men_z135_uart.c (revision 0d3b051adbb72ed81956447d0d1e54d5943ee6f5) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * MEN 16z135 High Speed UART
4  *
5  * Copyright (C) 2014 MEN Mikroelektronik GmbH (www.men.de)
6  * Author: Johannes Thumshirn <johannes.thumshirn@men.de>
7  */
8 #define pr_fmt(fmt) KBUILD_MODNAME ":" fmt
9 
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/interrupt.h>
13 #include <linux/serial_core.h>
14 #include <linux/ioport.h>
15 #include <linux/io.h>
16 #include <linux/tty_flip.h>
17 #include <linux/bitops.h>
18 #include <linux/mcb.h>
19 
20 #define MEN_Z135_MAX_PORTS		12
21 #define MEN_Z135_BASECLK		29491200
22 #define MEN_Z135_FIFO_SIZE		1024
23 #define MEN_Z135_FIFO_WATERMARK		1020
24 
25 #define MEN_Z135_STAT_REG		0x0
26 #define MEN_Z135_RX_RAM			0x4
27 #define MEN_Z135_TX_RAM			0x400
28 #define MEN_Z135_RX_CTRL		0x800
29 #define MEN_Z135_TX_CTRL		0x804
30 #define MEN_Z135_CONF_REG		0x808
31 #define MEN_Z135_UART_FREQ		0x80c
32 #define MEN_Z135_BAUD_REG		0x810
33 #define MEN_Z135_TIMEOUT		0x814
34 
35 #define IRQ_ID(x) ((x) & 0x1f)
36 
37 #define MEN_Z135_IER_RXCIEN BIT(0)		/* RX Space IRQ */
38 #define MEN_Z135_IER_TXCIEN BIT(1)		/* TX Space IRQ */
39 #define MEN_Z135_IER_RLSIEN BIT(2)		/* Receiver Line Status IRQ */
40 #define MEN_Z135_IER_MSIEN  BIT(3)		/* Modem Status IRQ */
41 #define MEN_Z135_ALL_IRQS (MEN_Z135_IER_RXCIEN		\
42 				| MEN_Z135_IER_RLSIEN	\
43 				| MEN_Z135_IER_MSIEN	\
44 				| MEN_Z135_IER_TXCIEN)
45 
46 #define MEN_Z135_MCR_DTR	BIT(24)
47 #define MEN_Z135_MCR_RTS	BIT(25)
48 #define MEN_Z135_MCR_OUT1	BIT(26)
49 #define MEN_Z135_MCR_OUT2	BIT(27)
50 #define MEN_Z135_MCR_LOOP	BIT(28)
51 #define MEN_Z135_MCR_RCFC	BIT(29)
52 
53 #define MEN_Z135_MSR_DCTS	BIT(0)
54 #define MEN_Z135_MSR_DDSR	BIT(1)
55 #define MEN_Z135_MSR_DRI	BIT(2)
56 #define MEN_Z135_MSR_DDCD	BIT(3)
57 #define MEN_Z135_MSR_CTS	BIT(4)
58 #define MEN_Z135_MSR_DSR	BIT(5)
59 #define MEN_Z135_MSR_RI		BIT(6)
60 #define MEN_Z135_MSR_DCD	BIT(7)
61 
62 #define MEN_Z135_LCR_SHIFT 8	/* LCR shift mask */
63 
64 #define MEN_Z135_WL5 0		/* CS5 */
65 #define MEN_Z135_WL6 1		/* CS6 */
66 #define MEN_Z135_WL7 2		/* CS7 */
67 #define MEN_Z135_WL8 3		/* CS8 */
68 
69 #define MEN_Z135_STB_SHIFT 2	/* Stopbits */
70 #define MEN_Z135_NSTB1 0
71 #define MEN_Z135_NSTB2 1
72 
73 #define MEN_Z135_PEN_SHIFT 3	/* Parity enable */
74 #define MEN_Z135_PAR_DIS 0
75 #define MEN_Z135_PAR_ENA 1
76 
77 #define MEN_Z135_PTY_SHIFT 4	/* Parity type */
78 #define MEN_Z135_PTY_ODD 0
79 #define MEN_Z135_PTY_EVN 1
80 
81 #define MEN_Z135_LSR_DR BIT(0)
82 #define MEN_Z135_LSR_OE BIT(1)
83 #define MEN_Z135_LSR_PE BIT(2)
84 #define MEN_Z135_LSR_FE BIT(3)
85 #define MEN_Z135_LSR_BI BIT(4)
86 #define MEN_Z135_LSR_THEP BIT(5)
87 #define MEN_Z135_LSR_TEXP BIT(6)
88 #define MEN_Z135_LSR_RXFIFOERR BIT(7)
89 
90 #define MEN_Z135_IRQ_ID_RLS BIT(0)
91 #define MEN_Z135_IRQ_ID_RDA BIT(1)
92 #define MEN_Z135_IRQ_ID_CTI BIT(2)
93 #define MEN_Z135_IRQ_ID_TSA BIT(3)
94 #define MEN_Z135_IRQ_ID_MST BIT(4)
95 
96 #define LCR(x) (((x) >> MEN_Z135_LCR_SHIFT) & 0xff)
97 
98 #define BYTES_TO_ALIGN(x) ((x) & 0x3)
99 
100 static int line;
101 
102 static int txlvl = 5;
103 module_param(txlvl, int, S_IRUGO);
104 MODULE_PARM_DESC(txlvl, "TX IRQ trigger level 0-7, default 5 (128 byte)");
105 
106 static int rxlvl = 6;
107 module_param(rxlvl, int, S_IRUGO);
108 MODULE_PARM_DESC(rxlvl, "RX IRQ trigger level 0-7, default 6 (256 byte)");
109 
110 static int align;
111 module_param(align, int, S_IRUGO);
112 MODULE_PARM_DESC(align, "Keep hardware FIFO write pointer aligned, default 0");
113 
114 static uint rx_timeout;
115 module_param(rx_timeout, uint, S_IRUGO);
116 MODULE_PARM_DESC(rx_timeout, "RX timeout. "
117 		"Timeout in seconds = (timeout_reg * baud_reg * 4) / freq_reg");
118 
119 struct men_z135_port {
120 	struct uart_port port;
121 	struct mcb_device *mdev;
122 	struct resource *mem;
123 	unsigned char *rxbuf;
124 	u32 stat_reg;
125 	spinlock_t lock;
126 	bool automode;
127 };
128 #define to_men_z135(port) container_of((port), struct men_z135_port, port)
129 
130 /**
131  * men_z135_reg_set() - Set value in register
132  * @uart: The UART port
133  * @addr: Register address
134  * @val: value to set
135  */
136 static inline void men_z135_reg_set(struct men_z135_port *uart,
137 				u32 addr, u32 val)
138 {
139 	struct uart_port *port = &uart->port;
140 	unsigned long flags;
141 	u32 reg;
142 
143 	spin_lock_irqsave(&uart->lock, flags);
144 
145 	reg = ioread32(port->membase + addr);
146 	reg |= val;
147 	iowrite32(reg, port->membase + addr);
148 
149 	spin_unlock_irqrestore(&uart->lock, flags);
150 }
151 
152 /**
153  * men_z135_reg_clr() - Unset value in register
154  * @uart: The UART port
155  * @addr: Register address
156  * @val: value to clear
157  */
158 static void men_z135_reg_clr(struct men_z135_port *uart,
159 				u32 addr, u32 val)
160 {
161 	struct uart_port *port = &uart->port;
162 	unsigned long flags;
163 	u32 reg;
164 
165 	spin_lock_irqsave(&uart->lock, flags);
166 
167 	reg = ioread32(port->membase + addr);
168 	reg &= ~val;
169 	iowrite32(reg, port->membase + addr);
170 
171 	spin_unlock_irqrestore(&uart->lock, flags);
172 }
173 
174 /**
175  * men_z135_handle_modem_status() - Handle change of modem status
176  * @uart: The UART port
177  *
178  * Handle change of modem status register. This is done by reading the "delta"
179  * versions of DCD (Data Carrier Detect) and CTS (Clear To Send).
180  */
181 static void men_z135_handle_modem_status(struct men_z135_port *uart)
182 {
183 	u8 msr;
184 
185 	msr = (uart->stat_reg >> 8) & 0xff;
186 
187 	if (msr & MEN_Z135_MSR_DDCD)
188 		uart_handle_dcd_change(&uart->port,
189 				msr & MEN_Z135_MSR_DCD);
190 	if (msr & MEN_Z135_MSR_DCTS)
191 		uart_handle_cts_change(&uart->port,
192 				msr & MEN_Z135_MSR_CTS);
193 }
194 
195 static void men_z135_handle_lsr(struct men_z135_port *uart)
196 {
197 	struct uart_port *port = &uart->port;
198 	u8 lsr;
199 
200 	lsr = (uart->stat_reg >> 16) & 0xff;
201 
202 	if (lsr & MEN_Z135_LSR_OE)
203 		port->icount.overrun++;
204 	if (lsr & MEN_Z135_LSR_PE)
205 		port->icount.parity++;
206 	if (lsr & MEN_Z135_LSR_FE)
207 		port->icount.frame++;
208 	if (lsr & MEN_Z135_LSR_BI) {
209 		port->icount.brk++;
210 		uart_handle_break(port);
211 	}
212 }
213 
214 /**
215  * get_rx_fifo_content() - Get the number of bytes in RX FIFO
216  * @uart: The UART port
217  *
218  * Read RXC register from hardware and return current FIFO fill size.
219  */
220 static u16 get_rx_fifo_content(struct men_z135_port *uart)
221 {
222 	struct uart_port *port = &uart->port;
223 	u32 stat_reg;
224 	u16 rxc;
225 	u8 rxc_lo;
226 	u8 rxc_hi;
227 
228 	stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG);
229 	rxc_lo = stat_reg >> 24;
230 	rxc_hi = (stat_reg & 0xC0) >> 6;
231 
232 	rxc = rxc_lo | (rxc_hi << 8);
233 
234 	return rxc;
235 }
236 
237 /**
238  * men_z135_handle_rx() - RX tasklet routine
239  * @uart: Pointer to struct men_z135_port
240  *
241  * Copy from RX FIFO and acknowledge number of bytes copied.
242  */
243 static void men_z135_handle_rx(struct men_z135_port *uart)
244 {
245 	struct uart_port *port = &uart->port;
246 	struct tty_port *tport = &port->state->port;
247 	int copied;
248 	u16 size;
249 	int room;
250 
251 	size = get_rx_fifo_content(uart);
252 
253 	if (size == 0)
254 		return;
255 
256 	/* Avoid accidently accessing TX FIFO instead of RX FIFO. Last
257 	 * longword in RX FIFO cannot be read.(0x004-0x3FF)
258 	 */
259 	if (size > MEN_Z135_FIFO_WATERMARK)
260 		size = MEN_Z135_FIFO_WATERMARK;
261 
262 	room = tty_buffer_request_room(tport, size);
263 	if (room != size)
264 		dev_warn(&uart->mdev->dev,
265 			"Not enough room in flip buffer, truncating to %d\n",
266 			room);
267 
268 	if (room == 0)
269 		return;
270 
271 	memcpy_fromio(uart->rxbuf, port->membase + MEN_Z135_RX_RAM, room);
272 	/* Be sure to first copy all data and then acknowledge it */
273 	mb();
274 	iowrite32(room, port->membase +  MEN_Z135_RX_CTRL);
275 
276 	copied = tty_insert_flip_string(tport, uart->rxbuf, room);
277 	if (copied != room)
278 		dev_warn(&uart->mdev->dev,
279 			"Only copied %d instead of %d bytes\n",
280 			copied, room);
281 
282 	port->icount.rx += copied;
283 
284 	tty_flip_buffer_push(tport);
285 
286 }
287 
288 /**
289  * men_z135_handle_tx() - TX tasklet routine
290  * @uart: Pointer to struct men_z135_port
291  *
292  */
293 static void men_z135_handle_tx(struct men_z135_port *uart)
294 {
295 	struct uart_port *port = &uart->port;
296 	struct circ_buf *xmit = &port->state->xmit;
297 	u32 txc;
298 	u32 wptr;
299 	int qlen;
300 	int n;
301 	int txfree;
302 	int head;
303 	int tail;
304 	int s;
305 
306 	if (uart_circ_empty(xmit))
307 		goto out;
308 
309 	if (uart_tx_stopped(port))
310 		goto out;
311 
312 	if (port->x_char)
313 		goto out;
314 
315 	/* calculate bytes to copy */
316 	qlen = uart_circ_chars_pending(xmit);
317 	if (qlen <= 0)
318 		goto out;
319 
320 	wptr = ioread32(port->membase + MEN_Z135_TX_CTRL);
321 	txc = (wptr >> 16) & 0x3ff;
322 	wptr &= 0x3ff;
323 
324 	if (txc > MEN_Z135_FIFO_WATERMARK)
325 		txc = MEN_Z135_FIFO_WATERMARK;
326 
327 	txfree = MEN_Z135_FIFO_WATERMARK - txc;
328 	if (txfree <= 0) {
329 		dev_err(&uart->mdev->dev,
330 			"Not enough room in TX FIFO have %d, need %d\n",
331 			txfree, qlen);
332 		goto irq_en;
333 	}
334 
335 	/* if we're not aligned, it's better to copy only 1 or 2 bytes and
336 	 * then the rest.
337 	 */
338 	if (align && qlen >= 3 && BYTES_TO_ALIGN(wptr))
339 		n = 4 - BYTES_TO_ALIGN(wptr);
340 	else if (qlen > txfree)
341 		n = txfree;
342 	else
343 		n = qlen;
344 
345 	if (n <= 0)
346 		goto irq_en;
347 
348 	head = xmit->head & (UART_XMIT_SIZE - 1);
349 	tail = xmit->tail & (UART_XMIT_SIZE - 1);
350 
351 	s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail;
352 	n = min(n, s);
353 
354 	memcpy_toio(port->membase + MEN_Z135_TX_RAM, &xmit->buf[xmit->tail], n);
355 	xmit->tail = (xmit->tail + n) & (UART_XMIT_SIZE - 1);
356 
357 	iowrite32(n & 0x3ff, port->membase + MEN_Z135_TX_CTRL);
358 
359 	port->icount.tx += n;
360 
361 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
362 		uart_write_wakeup(port);
363 
364 irq_en:
365 	if (!uart_circ_empty(xmit))
366 		men_z135_reg_set(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
367 	else
368 		men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
369 
370 out:
371 	return;
372 
373 }
374 
375 /**
376  * men_z135_intr() - Handle legacy IRQs
377  * @irq: The IRQ number
378  * @data: Pointer to UART port
379  *
380  * Check IIR register to find the cause of the interrupt and handle it.
381  * It is possible that multiple interrupts reason bits are set and reading
382  * the IIR is a destructive read, so we always need to check for all possible
383  * interrupts and handle them.
384  */
385 static irqreturn_t men_z135_intr(int irq, void *data)
386 {
387 	struct men_z135_port *uart = (struct men_z135_port *)data;
388 	struct uart_port *port = &uart->port;
389 	bool handled = false;
390 	int irq_id;
391 
392 	uart->stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG);
393 	irq_id = IRQ_ID(uart->stat_reg);
394 
395 	if (!irq_id)
396 		goto out;
397 
398 	spin_lock(&port->lock);
399 	/* It's save to write to IIR[7:6] RXC[9:8] */
400 	iowrite8(irq_id, port->membase + MEN_Z135_STAT_REG);
401 
402 	if (irq_id & MEN_Z135_IRQ_ID_RLS) {
403 		men_z135_handle_lsr(uart);
404 		handled = true;
405 	}
406 
407 	if (irq_id & (MEN_Z135_IRQ_ID_RDA | MEN_Z135_IRQ_ID_CTI)) {
408 		if (irq_id & MEN_Z135_IRQ_ID_CTI)
409 			dev_dbg(&uart->mdev->dev, "Character Timeout Indication\n");
410 		men_z135_handle_rx(uart);
411 		handled = true;
412 	}
413 
414 	if (irq_id & MEN_Z135_IRQ_ID_TSA) {
415 		men_z135_handle_tx(uart);
416 		handled = true;
417 	}
418 
419 	if (irq_id & MEN_Z135_IRQ_ID_MST) {
420 		men_z135_handle_modem_status(uart);
421 		handled = true;
422 	}
423 
424 	spin_unlock(&port->lock);
425 out:
426 	return IRQ_RETVAL(handled);
427 }
428 
429 /**
430  * men_z135_request_irq() - Request IRQ for 16z135 core
431  * @uart: z135 private uart port structure
432  *
433  * Request an IRQ for 16z135 to use. First try using MSI, if it fails
434  * fall back to using legacy interrupts.
435  */
436 static int men_z135_request_irq(struct men_z135_port *uart)
437 {
438 	struct device *dev = &uart->mdev->dev;
439 	struct uart_port *port = &uart->port;
440 	int err = 0;
441 
442 	err = request_irq(port->irq, men_z135_intr, IRQF_SHARED,
443 			"men_z135_intr", uart);
444 	if (err)
445 		dev_err(dev, "Error %d getting interrupt\n", err);
446 
447 	return err;
448 }
449 
450 /**
451  * men_z135_tx_empty() - Handle tx_empty call
452  * @port: The UART port
453  *
454  * This function tests whether the TX FIFO and shifter for the port
455  * described by @port is empty.
456  */
457 static unsigned int men_z135_tx_empty(struct uart_port *port)
458 {
459 	u32 wptr;
460 	u16 txc;
461 
462 	wptr = ioread32(port->membase + MEN_Z135_TX_CTRL);
463 	txc = (wptr >> 16) & 0x3ff;
464 
465 	if (txc == 0)
466 		return TIOCSER_TEMT;
467 	else
468 		return 0;
469 }
470 
471 /**
472  * men_z135_set_mctrl() - Set modem control lines
473  * @port: The UART port
474  * @mctrl: The modem control lines
475  *
476  * This function sets the modem control lines for a port described by @port
477  * to the state described by @mctrl
478  */
479 static void men_z135_set_mctrl(struct uart_port *port, unsigned int mctrl)
480 {
481 	u32 old;
482 	u32 conf_reg;
483 
484 	conf_reg = old = ioread32(port->membase + MEN_Z135_CONF_REG);
485 	if (mctrl & TIOCM_RTS)
486 		conf_reg |= MEN_Z135_MCR_RTS;
487 	else
488 		conf_reg &= ~MEN_Z135_MCR_RTS;
489 
490 	if (mctrl & TIOCM_DTR)
491 		conf_reg |= MEN_Z135_MCR_DTR;
492 	else
493 		conf_reg &= ~MEN_Z135_MCR_DTR;
494 
495 	if (mctrl & TIOCM_OUT1)
496 		conf_reg |= MEN_Z135_MCR_OUT1;
497 	else
498 		conf_reg &= ~MEN_Z135_MCR_OUT1;
499 
500 	if (mctrl & TIOCM_OUT2)
501 		conf_reg |= MEN_Z135_MCR_OUT2;
502 	else
503 		conf_reg &= ~MEN_Z135_MCR_OUT2;
504 
505 	if (mctrl & TIOCM_LOOP)
506 		conf_reg |= MEN_Z135_MCR_LOOP;
507 	else
508 		conf_reg &= ~MEN_Z135_MCR_LOOP;
509 
510 	if (conf_reg != old)
511 		iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG);
512 }
513 
514 /**
515  * men_z135_get_mctrl() - Get modem control lines
516  * @port: The UART port
517  *
518  * Retruns the current state of modem control inputs.
519  */
520 static unsigned int men_z135_get_mctrl(struct uart_port *port)
521 {
522 	unsigned int mctrl = 0;
523 	u8 msr;
524 
525 	msr = ioread8(port->membase + MEN_Z135_STAT_REG + 1);
526 
527 	if (msr & MEN_Z135_MSR_CTS)
528 		mctrl |= TIOCM_CTS;
529 	if (msr & MEN_Z135_MSR_DSR)
530 		mctrl |= TIOCM_DSR;
531 	if (msr & MEN_Z135_MSR_RI)
532 		mctrl |= TIOCM_RI;
533 	if (msr & MEN_Z135_MSR_DCD)
534 		mctrl |= TIOCM_CAR;
535 
536 	return mctrl;
537 }
538 
539 /**
540  * men_z135_stop_tx() - Stop transmitting characters
541  * @port: The UART port
542  *
543  * Stop transmitting characters. This might be due to CTS line becomming
544  * inactive or the tty layer indicating we want to stop transmission due to
545  * an XOFF character.
546  */
547 static void men_z135_stop_tx(struct uart_port *port)
548 {
549 	struct men_z135_port *uart = to_men_z135(port);
550 
551 	men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
552 }
553 
554 /*
555  * men_z135_disable_ms() - Disable Modem Status
556  * port: The UART port
557  *
558  * Enable Modem Status IRQ.
559  */
560 static void men_z135_disable_ms(struct uart_port *port)
561 {
562 	struct men_z135_port *uart = to_men_z135(port);
563 
564 	men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_MSIEN);
565 }
566 
567 /**
568  * men_z135_start_tx() - Start transmitting characters
569  * @port: The UART port
570  *
571  * Start transmitting character. This actually doesn't transmit anything, but
572  * fires off the TX tasklet.
573  */
574 static void men_z135_start_tx(struct uart_port *port)
575 {
576 	struct men_z135_port *uart = to_men_z135(port);
577 
578 	if (uart->automode)
579 		men_z135_disable_ms(port);
580 
581 	men_z135_handle_tx(uart);
582 }
583 
584 /**
585  * men_z135_stop_rx() - Stop receiving characters
586  * @port: The UART port
587  *
588  * Stop receiving characters; the port is in the process of being closed.
589  */
590 static void men_z135_stop_rx(struct uart_port *port)
591 {
592 	struct men_z135_port *uart = to_men_z135(port);
593 
594 	men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_RXCIEN);
595 }
596 
597 /**
598  * men_z135_enable_ms() - Enable Modem Status
599  * @port: the port
600  *
601  * Enable Modem Status IRQ.
602  */
603 static void men_z135_enable_ms(struct uart_port *port)
604 {
605 	struct men_z135_port *uart = to_men_z135(port);
606 
607 	men_z135_reg_set(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_MSIEN);
608 }
609 
610 static int men_z135_startup(struct uart_port *port)
611 {
612 	struct men_z135_port *uart = to_men_z135(port);
613 	int err;
614 	u32 conf_reg = 0;
615 
616 	err = men_z135_request_irq(uart);
617 	if (err)
618 		return -ENODEV;
619 
620 	conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG);
621 
622 	/* Activate all but TX space available IRQ */
623 	conf_reg |= MEN_Z135_ALL_IRQS & ~MEN_Z135_IER_TXCIEN;
624 	conf_reg &= ~(0xff << 16);
625 	conf_reg |= (txlvl << 16);
626 	conf_reg |= (rxlvl << 20);
627 
628 	iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG);
629 
630 	if (rx_timeout)
631 		iowrite32(rx_timeout, port->membase + MEN_Z135_TIMEOUT);
632 
633 	return 0;
634 }
635 
636 static void men_z135_shutdown(struct uart_port *port)
637 {
638 	struct men_z135_port *uart = to_men_z135(port);
639 	u32 conf_reg = 0;
640 
641 	conf_reg |= MEN_Z135_ALL_IRQS;
642 
643 	men_z135_reg_clr(uart, MEN_Z135_CONF_REG, conf_reg);
644 
645 	free_irq(uart->port.irq, uart);
646 }
647 
648 static void men_z135_set_termios(struct uart_port *port,
649 				struct ktermios *termios,
650 				struct ktermios *old)
651 {
652 	struct men_z135_port *uart = to_men_z135(port);
653 	unsigned int baud;
654 	u32 conf_reg;
655 	u32 bd_reg;
656 	u32 uart_freq;
657 	u8 lcr;
658 
659 	conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG);
660 	lcr = LCR(conf_reg);
661 
662 	/* byte size */
663 	switch (termios->c_cflag & CSIZE) {
664 	case CS5:
665 		lcr |= MEN_Z135_WL5;
666 		break;
667 	case CS6:
668 		lcr |= MEN_Z135_WL6;
669 		break;
670 	case CS7:
671 		lcr |= MEN_Z135_WL7;
672 		break;
673 	case CS8:
674 		lcr |= MEN_Z135_WL8;
675 		break;
676 	}
677 
678 	/* stop bits */
679 	if (termios->c_cflag & CSTOPB)
680 		lcr |= MEN_Z135_NSTB2 << MEN_Z135_STB_SHIFT;
681 
682 	/* parity */
683 	if (termios->c_cflag & PARENB) {
684 		lcr |= MEN_Z135_PAR_ENA << MEN_Z135_PEN_SHIFT;
685 
686 		if (termios->c_cflag & PARODD)
687 			lcr |= MEN_Z135_PTY_ODD << MEN_Z135_PTY_SHIFT;
688 		else
689 			lcr |= MEN_Z135_PTY_EVN << MEN_Z135_PTY_SHIFT;
690 	} else
691 		lcr |= MEN_Z135_PAR_DIS << MEN_Z135_PEN_SHIFT;
692 
693 	conf_reg |= MEN_Z135_IER_MSIEN;
694 	if (termios->c_cflag & CRTSCTS) {
695 		conf_reg |= MEN_Z135_MCR_RCFC;
696 		uart->automode = true;
697 		termios->c_cflag &= ~CLOCAL;
698 	} else {
699 		conf_reg &= ~MEN_Z135_MCR_RCFC;
700 		uart->automode = false;
701 	}
702 
703 	termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
704 
705 	conf_reg |= lcr << MEN_Z135_LCR_SHIFT;
706 	iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG);
707 
708 	uart_freq = ioread32(port->membase + MEN_Z135_UART_FREQ);
709 	if (uart_freq == 0)
710 		uart_freq = MEN_Z135_BASECLK;
711 
712 	baud = uart_get_baud_rate(port, termios, old, 0, uart_freq / 16);
713 
714 	spin_lock_irq(&port->lock);
715 	if (tty_termios_baud_rate(termios))
716 		tty_termios_encode_baud_rate(termios, baud, baud);
717 
718 	bd_reg = uart_freq / (4 * baud);
719 	iowrite32(bd_reg, port->membase + MEN_Z135_BAUD_REG);
720 
721 	uart_update_timeout(port, termios->c_cflag, baud);
722 	spin_unlock_irq(&port->lock);
723 }
724 
725 static const char *men_z135_type(struct uart_port *port)
726 {
727 	return KBUILD_MODNAME;
728 }
729 
730 static void men_z135_release_port(struct uart_port *port)
731 {
732 	struct men_z135_port *uart = to_men_z135(port);
733 
734 	iounmap(port->membase);
735 	port->membase = NULL;
736 
737 	mcb_release_mem(uart->mem);
738 }
739 
740 static int men_z135_request_port(struct uart_port *port)
741 {
742 	struct men_z135_port *uart = to_men_z135(port);
743 	struct mcb_device *mdev = uart->mdev;
744 	struct resource *mem;
745 
746 	mem = mcb_request_mem(uart->mdev, dev_name(&mdev->dev));
747 	if (IS_ERR(mem))
748 		return PTR_ERR(mem);
749 
750 	port->mapbase = mem->start;
751 	uart->mem = mem;
752 
753 	port->membase = ioremap(mem->start, resource_size(mem));
754 	if (port->membase == NULL) {
755 		mcb_release_mem(mem);
756 		return -ENOMEM;
757 	}
758 
759 	return 0;
760 }
761 
762 static void men_z135_config_port(struct uart_port *port, int type)
763 {
764 	port->type = PORT_MEN_Z135;
765 	men_z135_request_port(port);
766 }
767 
768 static int men_z135_verify_port(struct uart_port *port,
769 				struct serial_struct *serinfo)
770 {
771 	return -EINVAL;
772 }
773 
774 static const struct uart_ops men_z135_ops = {
775 	.tx_empty = men_z135_tx_empty,
776 	.set_mctrl = men_z135_set_mctrl,
777 	.get_mctrl = men_z135_get_mctrl,
778 	.stop_tx = men_z135_stop_tx,
779 	.start_tx = men_z135_start_tx,
780 	.stop_rx = men_z135_stop_rx,
781 	.enable_ms = men_z135_enable_ms,
782 	.startup = men_z135_startup,
783 	.shutdown = men_z135_shutdown,
784 	.set_termios = men_z135_set_termios,
785 	.type = men_z135_type,
786 	.release_port = men_z135_release_port,
787 	.request_port = men_z135_request_port,
788 	.config_port = men_z135_config_port,
789 	.verify_port = men_z135_verify_port,
790 };
791 
792 static struct uart_driver men_z135_driver = {
793 	.owner = THIS_MODULE,
794 	.driver_name = KBUILD_MODNAME,
795 	.dev_name = "ttyHSU",
796 	.major = 0,
797 	.minor = 0,
798 	.nr = MEN_Z135_MAX_PORTS,
799 };
800 
801 /**
802  * men_z135_probe() - Probe a z135 instance
803  * @mdev: The MCB device
804  * @id: The MCB device ID
805  *
806  * men_z135_probe does the basic setup of hardware resources and registers the
807  * new uart port to the tty layer.
808  */
809 static int men_z135_probe(struct mcb_device *mdev,
810 			const struct mcb_device_id *id)
811 {
812 	struct men_z135_port *uart;
813 	struct resource *mem;
814 	struct device *dev;
815 	int err;
816 
817 	dev = &mdev->dev;
818 
819 	uart = devm_kzalloc(dev, sizeof(struct men_z135_port), GFP_KERNEL);
820 	if (!uart)
821 		return -ENOMEM;
822 
823 	uart->rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
824 	if (!uart->rxbuf)
825 		return -ENOMEM;
826 
827 	mem = &mdev->mem;
828 
829 	mcb_set_drvdata(mdev, uart);
830 
831 	uart->port.uartclk = MEN_Z135_BASECLK * 16;
832 	uart->port.fifosize = MEN_Z135_FIFO_SIZE;
833 	uart->port.iotype = UPIO_MEM;
834 	uart->port.ops = &men_z135_ops;
835 	uart->port.irq = mcb_get_irq(mdev);
836 	uart->port.iotype = UPIO_MEM;
837 	uart->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
838 	uart->port.line = line++;
839 	uart->port.dev = dev;
840 	uart->port.type = PORT_MEN_Z135;
841 	uart->port.mapbase = mem->start;
842 	uart->port.membase = NULL;
843 	uart->mdev = mdev;
844 
845 	spin_lock_init(&uart->lock);
846 
847 	err = uart_add_one_port(&men_z135_driver, &uart->port);
848 	if (err)
849 		goto err;
850 
851 	return 0;
852 
853 err:
854 	free_page((unsigned long) uart->rxbuf);
855 	dev_err(dev, "Failed to add UART: %d\n", err);
856 
857 	return err;
858 }
859 
860 /**
861  * men_z135_remove() - Remove a z135 instance from the system
862  *
863  * @mdev: The MCB device
864  */
865 static void men_z135_remove(struct mcb_device *mdev)
866 {
867 	struct men_z135_port *uart = mcb_get_drvdata(mdev);
868 
869 	line--;
870 	uart_remove_one_port(&men_z135_driver, &uart->port);
871 	free_page((unsigned long) uart->rxbuf);
872 }
873 
874 static const struct mcb_device_id men_z135_ids[] = {
875 	{ .device = 0x87 },
876 	{ }
877 };
878 MODULE_DEVICE_TABLE(mcb, men_z135_ids);
879 
880 static struct mcb_driver mcb_driver = {
881 	.driver = {
882 		.name = "z135-uart",
883 		.owner = THIS_MODULE,
884 	},
885 	.probe = men_z135_probe,
886 	.remove = men_z135_remove,
887 	.id_table = men_z135_ids,
888 };
889 
890 /**
891  * men_z135_init() - Driver Registration Routine
892  *
893  * men_z135_init is the first routine called when the driver is loaded. All it
894  * does is register with the legacy MEN Chameleon subsystem.
895  */
896 static int __init men_z135_init(void)
897 {
898 	int err;
899 
900 	err = uart_register_driver(&men_z135_driver);
901 	if (err) {
902 		pr_err("Failed to register UART: %d\n", err);
903 		return err;
904 	}
905 
906 	err = mcb_register_driver(&mcb_driver);
907 	if  (err) {
908 		pr_err("Failed to register MCB driver: %d\n", err);
909 		uart_unregister_driver(&men_z135_driver);
910 		return err;
911 	}
912 
913 	return 0;
914 }
915 module_init(men_z135_init);
916 
917 /**
918  * men_z135_exit() - Driver Exit Routine
919  *
920  * men_z135_exit is called just before the driver is removed from memory.
921  */
922 static void __exit men_z135_exit(void)
923 {
924 	mcb_unregister_driver(&mcb_driver);
925 	uart_unregister_driver(&men_z135_driver);
926 }
927 module_exit(men_z135_exit);
928 
929 MODULE_AUTHOR("Johannes Thumshirn <johannes.thumshirn@men.de>");
930 MODULE_LICENSE("GPL v2");
931 MODULE_DESCRIPTION("MEN 16z135 High Speed UART");
932 MODULE_ALIAS("mcb:16z135");
933 MODULE_IMPORT_NS(MCB);
934